2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licenced under the GPL.
16 #include "qemu-timer.h"
17 #include "qemu-char.h"
20 target_phys_addr_t io_base
;
23 { 0x40100000, PXA2XX_PIC_FFUART
},
24 { 0x40200000, PXA2XX_PIC_BTUART
},
25 { 0x40700000, PXA2XX_PIC_STUART
},
26 { 0x41600000, PXA25X_PIC_HWUART
},
28 }, pxa270_serial
[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART
},
30 { 0x40200000, PXA2XX_PIC_BTUART
},
31 { 0x40700000, PXA2XX_PIC_STUART
},
35 typedef struct PXASSPDef
{
36 target_phys_addr_t io_base
;
41 static PXASSPDef pxa250_ssp
[] = {
42 { 0x41000000, PXA2XX_PIC_SSP
},
47 static PXASSPDef pxa255_ssp
[] = {
48 { 0x41000000, PXA2XX_PIC_SSP
},
49 { 0x41400000, PXA25X_PIC_NSSP
},
54 static PXASSPDef pxa26x_ssp
[] = {
55 { 0x41000000, PXA2XX_PIC_SSP
},
56 { 0x41400000, PXA25X_PIC_NSSP
},
57 { 0x41500000, PXA26X_PIC_ASSP
},
62 static PXASSPDef pxa27x_ssp
[] = {
63 { 0x41000000, PXA2XX_PIC_SSP
},
64 { 0x41700000, PXA27X_PIC_SSP2
},
65 { 0x41900000, PXA2XX_PIC_SSP3
},
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
91 static uint32_t pxa2xx_pm_read(void *opaque
, target_phys_addr_t addr
)
93 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
100 return s
->pm_regs
[addr
>> 2];
103 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
109 static void pxa2xx_pm_write(void *opaque
, target_phys_addr_t addr
,
112 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
116 s
->pm_regs
[addr
>> 2] &= 0x15 & ~(value
& 0x2a);
117 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
120 case PSSR
: /* Read-clean registers */
123 s
->pm_regs
[addr
>> 2] &= ~value
;
126 default: /* Read-write registers */
127 if (addr
>= PMCR
&& addr
<= PCMD31
&& !(addr
& 3)) {
128 s
->pm_regs
[addr
>> 2] = value
;
132 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
137 static CPUReadMemoryFunc
* const pxa2xx_pm_readfn
[] = {
143 static CPUWriteMemoryFunc
* const pxa2xx_pm_writefn
[] = {
149 static void pxa2xx_pm_save(QEMUFile
*f
, void *opaque
)
151 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
154 for (i
= 0; i
< 0x40; i
++)
155 qemu_put_be32s(f
, &s
->pm_regs
[i
]);
158 static int pxa2xx_pm_load(QEMUFile
*f
, void *opaque
, int version_id
)
160 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
163 for (i
= 0; i
< 0x40; i
++)
164 qemu_get_be32s(f
, &s
->pm_regs
[i
]);
169 #define CCCR 0x00 /* Core Clock Configuration register */
170 #define CKEN 0x04 /* Clock Enable register */
171 #define OSCC 0x08 /* Oscillator Configuration register */
172 #define CCSR 0x0c /* Core Clock Status register */
174 static uint32_t pxa2xx_cm_read(void *opaque
, target_phys_addr_t addr
)
176 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
182 return s
->cm_regs
[addr
>> 2];
185 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
188 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
194 static void pxa2xx_cm_write(void *opaque
, target_phys_addr_t addr
,
197 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
202 s
->cm_regs
[addr
>> 2] = value
;
206 s
->cm_regs
[addr
>> 2] &= ~0x6c;
207 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
208 if ((value
>> 1) & 1) /* OON */
209 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
213 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
218 static CPUReadMemoryFunc
* const pxa2xx_cm_readfn
[] = {
224 static CPUWriteMemoryFunc
* const pxa2xx_cm_writefn
[] = {
230 static void pxa2xx_cm_save(QEMUFile
*f
, void *opaque
)
232 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
235 for (i
= 0; i
< 4; i
++)
236 qemu_put_be32s(f
, &s
->cm_regs
[i
]);
237 qemu_put_be32s(f
, &s
->clkcfg
);
238 qemu_put_be32s(f
, &s
->pmnc
);
241 static int pxa2xx_cm_load(QEMUFile
*f
, void *opaque
, int version_id
)
243 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
246 for (i
= 0; i
< 4; i
++)
247 qemu_get_be32s(f
, &s
->cm_regs
[i
]);
248 qemu_get_be32s(f
, &s
->clkcfg
);
249 qemu_get_be32s(f
, &s
->pmnc
);
254 static uint32_t pxa2xx_clkpwr_read(void *opaque
, int op2
, int reg
, int crm
)
256 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
259 case 6: /* Clock Configuration register */
262 case 7: /* Power Mode register */
266 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
272 static void pxa2xx_clkpwr_write(void *opaque
, int op2
, int reg
, int crm
,
275 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
276 static const char *pwrmode
[8] = {
277 "Normal", "Idle", "Deep-idle", "Standby",
278 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
282 case 6: /* Clock Configuration register */
283 s
->clkcfg
= value
& 0xf;
285 printf("%s: CPU frequency change attempt\n", __FUNCTION__
);
288 case 7: /* Power Mode register */
290 printf("%s: CPU voltage change attempt\n", __FUNCTION__
);
298 if (!(s
->cm_regs
[CCCR
>> 2] & (1 << 31))) { /* CPDIS */
299 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
306 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
307 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
311 s
->env
->uncached_cpsr
=
312 ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
313 s
->env
->cp15
.c1_sys
= 0;
314 s
->env
->cp15
.c1_coproc
= 0;
315 s
->env
->cp15
.c2_base0
= 0;
317 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
318 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
321 * The scratch-pad register is almost universally used
322 * for storing the return address on suspend. For the
323 * lack of a resuming bootloader, perform a jump
324 * directly to that address.
326 memset(s
->env
->regs
, 0, 4 * 15);
327 s
->env
->regs
[15] = s
->pm_regs
[PSPR
>> 2];
330 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
331 cpu_physical_memory_write(0, &buffer
, 4);
332 buffer
= s
->pm_regs
[PSPR
>> 2];
333 cpu_physical_memory_write(8, &buffer
, 4);
337 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
343 printf("%s: machine entered %s mode\n", __FUNCTION__
,
349 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
354 /* Performace Monitoring Registers */
355 #define CPPMNC 0 /* Performance Monitor Control register */
356 #define CPCCNT 1 /* Clock Counter register */
357 #define CPINTEN 4 /* Interrupt Enable register */
358 #define CPFLAG 5 /* Overflow Flag register */
359 #define CPEVTSEL 8 /* Event Selection register */
361 #define CPPMN0 0 /* Performance Count register 0 */
362 #define CPPMN1 1 /* Performance Count register 1 */
363 #define CPPMN2 2 /* Performance Count register 2 */
364 #define CPPMN3 3 /* Performance Count register 3 */
366 static uint32_t pxa2xx_perf_read(void *opaque
, int op2
, int reg
, int crm
)
368 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
375 return qemu_get_clock(vm_clock
);
384 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
390 static void pxa2xx_perf_write(void *opaque
, int op2
, int reg
, int crm
,
393 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
407 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
412 static uint32_t pxa2xx_cp14_read(void *opaque
, int op2
, int reg
, int crm
)
416 return pxa2xx_clkpwr_read(opaque
, op2
, reg
, crm
);
418 return pxa2xx_perf_read(opaque
, op2
, reg
, crm
);
429 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
435 static void pxa2xx_cp14_write(void *opaque
, int op2
, int reg
, int crm
,
440 pxa2xx_clkpwr_write(opaque
, op2
, reg
, crm
, value
);
443 pxa2xx_perf_write(opaque
, op2
, reg
, crm
, value
);
455 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
460 #define MDCNFG 0x00 /* SDRAM Configuration register */
461 #define MDREFR 0x04 /* SDRAM Refresh Control register */
462 #define MSC0 0x08 /* Static Memory Control register 0 */
463 #define MSC1 0x0c /* Static Memory Control register 1 */
464 #define MSC2 0x10 /* Static Memory Control register 2 */
465 #define MECR 0x14 /* Expansion Memory Bus Config register */
466 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
467 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
468 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
469 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
470 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
471 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
472 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
473 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
474 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
475 #define ARB_CNTL 0x48 /* Arbiter Control register */
476 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
477 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
478 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
479 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
480 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
481 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
482 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
484 static uint32_t pxa2xx_mm_read(void *opaque
, target_phys_addr_t addr
)
486 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
489 case MDCNFG
... SA1110
:
491 return s
->mm_regs
[addr
>> 2];
494 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
500 static void pxa2xx_mm_write(void *opaque
, target_phys_addr_t addr
,
503 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
506 case MDCNFG
... SA1110
:
507 if ((addr
& 3) == 0) {
508 s
->mm_regs
[addr
>> 2] = value
;
513 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
518 static CPUReadMemoryFunc
* const pxa2xx_mm_readfn
[] = {
524 static CPUWriteMemoryFunc
* const pxa2xx_mm_writefn
[] = {
530 static void pxa2xx_mm_save(QEMUFile
*f
, void *opaque
)
532 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
535 for (i
= 0; i
< 0x1a; i
++)
536 qemu_put_be32s(f
, &s
->mm_regs
[i
]);
539 static int pxa2xx_mm_load(QEMUFile
*f
, void *opaque
, int version_id
)
541 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
544 for (i
= 0; i
< 0x1a; i
++)
545 qemu_get_be32s(f
, &s
->mm_regs
[i
]);
550 /* Synchronous Serial Ports */
566 uint32_t rx_fifo
[16];
571 #define SSCR0 0x00 /* SSP Control register 0 */
572 #define SSCR1 0x04 /* SSP Control register 1 */
573 #define SSSR 0x08 /* SSP Status register */
574 #define SSITR 0x0c /* SSP Interrupt Test register */
575 #define SSDR 0x10 /* SSP Data register */
576 #define SSTO 0x28 /* SSP Time-Out register */
577 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
578 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
579 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
580 #define SSTSS 0x38 /* SSP Time Slot Status register */
581 #define SSACD 0x3c /* SSP Audio Clock Divider register */
583 /* Bitfields for above registers */
584 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
585 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
586 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
587 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
588 #define SSCR0_SSE (1 << 7)
589 #define SSCR0_RIM (1 << 22)
590 #define SSCR0_TIM (1 << 23)
591 #define SSCR0_MOD (1 << 31)
592 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
593 #define SSCR1_RIE (1 << 0)
594 #define SSCR1_TIE (1 << 1)
595 #define SSCR1_LBM (1 << 2)
596 #define SSCR1_MWDS (1 << 5)
597 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
598 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
599 #define SSCR1_EFWR (1 << 14)
600 #define SSCR1_PINTE (1 << 18)
601 #define SSCR1_TINTE (1 << 19)
602 #define SSCR1_RSRE (1 << 20)
603 #define SSCR1_TSRE (1 << 21)
604 #define SSCR1_EBCEI (1 << 29)
605 #define SSITR_INT (7 << 5)
606 #define SSSR_TNF (1 << 2)
607 #define SSSR_RNE (1 << 3)
608 #define SSSR_TFS (1 << 5)
609 #define SSSR_RFS (1 << 6)
610 #define SSSR_ROR (1 << 7)
611 #define SSSR_PINT (1 << 18)
612 #define SSSR_TINT (1 << 19)
613 #define SSSR_EOC (1 << 20)
614 #define SSSR_TUR (1 << 21)
615 #define SSSR_BCE (1 << 23)
616 #define SSSR_RW 0x00bc0080
618 static void pxa2xx_ssp_int_update(PXA2xxSSPState
*s
)
622 level
|= s
->ssitr
& SSITR_INT
;
623 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
624 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
625 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
626 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
627 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
628 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
629 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
630 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
631 qemu_set_irq(s
->irq
, !!level
);
634 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState
*s
)
636 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
637 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
638 s
->sssr
&= ~SSSR_TNF
;
640 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
641 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
644 s
->sssr
&= ~SSSR_RFS
;
645 if (0 <= SSCR1_TFT(s
->sscr
[1]))
648 s
->sssr
&= ~SSSR_TFS
;
652 s
->sssr
&= ~SSSR_RNE
;
656 pxa2xx_ssp_int_update(s
);
659 static uint32_t pxa2xx_ssp_read(void *opaque
, target_phys_addr_t addr
)
661 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
676 return s
->sssr
| s
->ssitr
;
680 if (s
->rx_level
< 1) {
681 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
685 retval
= s
->rx_fifo
[s
->rx_start
++];
687 pxa2xx_ssp_fifo_update(s
);
698 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
704 static void pxa2xx_ssp_write(void *opaque
, target_phys_addr_t addr
,
707 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
711 s
->sscr
[0] = value
& 0xc7ffffff;
712 s
->enable
= value
& SSCR0_SSE
;
713 if (value
& SSCR0_MOD
)
714 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
715 if (s
->enable
&& SSCR0_DSS(value
) < 4)
716 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
718 if (!(value
& SSCR0_SSE
)) {
723 pxa2xx_ssp_fifo_update(s
);
728 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
729 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
730 pxa2xx_ssp_fifo_update(s
);
742 s
->ssitr
= value
& SSITR_INT
;
743 pxa2xx_ssp_int_update(s
);
747 s
->sssr
&= ~(value
& SSSR_RW
);
748 pxa2xx_ssp_int_update(s
);
752 if (SSCR0_UWIRE(s
->sscr
[0])) {
753 if (s
->sscr
[1] & SSCR1_MWDS
)
758 /* Note how 32bits overflow does no harm here */
759 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
761 /* Data goes from here to the Tx FIFO and is shifted out from
762 * there directly to the slave, no need to buffer it.
766 readval
= ssi_transfer(s
->bus
, value
);
767 if (s
->rx_level
< 0x10) {
768 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = readval
;
773 pxa2xx_ssp_fifo_update(s
);
789 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
794 static CPUReadMemoryFunc
* const pxa2xx_ssp_readfn
[] = {
800 static CPUWriteMemoryFunc
* const pxa2xx_ssp_writefn
[] = {
806 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
808 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
811 qemu_put_be32(f
, s
->enable
);
813 qemu_put_be32s(f
, &s
->sscr
[0]);
814 qemu_put_be32s(f
, &s
->sscr
[1]);
815 qemu_put_be32s(f
, &s
->sspsp
);
816 qemu_put_be32s(f
, &s
->ssto
);
817 qemu_put_be32s(f
, &s
->ssitr
);
818 qemu_put_be32s(f
, &s
->sssr
);
819 qemu_put_8s(f
, &s
->sstsa
);
820 qemu_put_8s(f
, &s
->ssrsa
);
821 qemu_put_8s(f
, &s
->ssacd
);
823 qemu_put_byte(f
, s
->rx_level
);
824 for (i
= 0; i
< s
->rx_level
; i
++)
825 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
828 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
830 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
833 s
->enable
= qemu_get_be32(f
);
835 qemu_get_be32s(f
, &s
->sscr
[0]);
836 qemu_get_be32s(f
, &s
->sscr
[1]);
837 qemu_get_be32s(f
, &s
->sspsp
);
838 qemu_get_be32s(f
, &s
->ssto
);
839 qemu_get_be32s(f
, &s
->ssitr
);
840 qemu_get_be32s(f
, &s
->sssr
);
841 qemu_get_8s(f
, &s
->sstsa
);
842 qemu_get_8s(f
, &s
->ssrsa
);
843 qemu_get_8s(f
, &s
->ssacd
);
845 s
->rx_level
= qemu_get_byte(f
);
847 for (i
= 0; i
< s
->rx_level
; i
++)
848 s
->rx_fifo
[i
] = qemu_get_byte(f
);
853 static void pxa2xx_ssp_init(SysBusDevice
*dev
)
856 PXA2xxSSPState
*s
= FROM_SYSBUS(PXA2xxSSPState
, dev
);
858 sysbus_init_irq(dev
, &s
->irq
);
860 iomemtype
= cpu_register_io_memory(pxa2xx_ssp_readfn
,
861 pxa2xx_ssp_writefn
, s
);
862 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
863 register_savevm("pxa2xx_ssp", -1, 0,
864 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
866 s
->bus
= ssi_create_bus(&dev
->qdev
, "ssi");
869 /* Real-Time Clock */
870 #define RCNR 0x00 /* RTC Counter register */
871 #define RTAR 0x04 /* RTC Alarm register */
872 #define RTSR 0x08 /* RTC Status register */
873 #define RTTR 0x0c /* RTC Timer Trim register */
874 #define RDCR 0x10 /* RTC Day Counter register */
875 #define RYCR 0x14 /* RTC Year Counter register */
876 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
877 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
878 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
879 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
880 #define SWCR 0x28 /* RTC Stopwatch Counter register */
881 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
882 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
883 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
884 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
886 static inline void pxa2xx_rtc_int_update(PXA2xxState
*s
)
888 qemu_set_irq(s
->pic
[PXA2XX_PIC_RTCALARM
], !!(s
->rtsr
& 0x2553));
891 static void pxa2xx_rtc_hzupdate(PXA2xxState
*s
)
893 int64_t rt
= qemu_get_clock(rt_clock
);
894 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
895 (1000 * ((s
->rttr
& 0xffff) + 1));
896 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
897 (1000 * ((s
->rttr
& 0xffff) + 1));
901 static void pxa2xx_rtc_swupdate(PXA2xxState
*s
)
903 int64_t rt
= qemu_get_clock(rt_clock
);
904 if (s
->rtsr
& (1 << 12))
905 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
909 static void pxa2xx_rtc_piupdate(PXA2xxState
*s
)
911 int64_t rt
= qemu_get_clock(rt_clock
);
912 if (s
->rtsr
& (1 << 15))
913 s
->last_swcr
+= rt
- s
->last_pi
;
917 static inline void pxa2xx_rtc_alarm_update(PXA2xxState
*s
,
920 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
921 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+
922 (((s
->rtar
- s
->last_rcnr
) * 1000 *
923 ((s
->rttr
& 0xffff) + 1)) >> 15));
925 qemu_del_timer(s
->rtc_hz
);
927 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
928 qemu_mod_timer(s
->rtc_rdal1
, s
->last_hz
+
929 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
930 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
932 qemu_del_timer(s
->rtc_rdal1
);
934 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
935 qemu_mod_timer(s
->rtc_rdal2
, s
->last_hz
+
936 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
937 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
939 qemu_del_timer(s
->rtc_rdal2
);
941 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
942 qemu_mod_timer(s
->rtc_swal1
, s
->last_sw
+
943 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
945 qemu_del_timer(s
->rtc_swal1
);
947 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
948 qemu_mod_timer(s
->rtc_swal2
, s
->last_sw
+
949 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
951 qemu_del_timer(s
->rtc_swal2
);
953 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
954 qemu_mod_timer(s
->rtc_pi
, s
->last_pi
+
955 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
957 qemu_del_timer(s
->rtc_pi
);
960 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
962 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
964 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
965 pxa2xx_rtc_int_update(s
);
968 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
970 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
972 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
973 pxa2xx_rtc_int_update(s
);
976 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
978 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
980 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
981 pxa2xx_rtc_int_update(s
);
984 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
986 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
988 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
989 pxa2xx_rtc_int_update(s
);
992 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
994 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
995 s
->rtsr
|= (1 << 10);
996 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
997 pxa2xx_rtc_int_update(s
);
1000 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
1002 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
1003 s
->rtsr
|= (1 << 13);
1004 pxa2xx_rtc_piupdate(s
);
1005 s
->last_rtcpicr
= 0;
1006 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1007 pxa2xx_rtc_int_update(s
);
1010 static uint32_t pxa2xx_rtc_read(void *opaque
, target_phys_addr_t addr
)
1012 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
1036 return s
->last_rcnr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1037 (1000 * ((s
->rttr
& 0xffff) + 1));
1039 return s
->last_rdcr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1040 (1000 * ((s
->rttr
& 0xffff) + 1));
1042 return s
->last_rycr
;
1044 if (s
->rtsr
& (1 << 12))
1045 return s
->last_swcr
+ (qemu_get_clock(rt_clock
) - s
->last_sw
) / 10;
1047 return s
->last_swcr
;
1049 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1055 static void pxa2xx_rtc_write(void *opaque
, target_phys_addr_t addr
,
1058 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
1062 if (!(s
->rttr
& (1 << 31))) {
1063 pxa2xx_rtc_hzupdate(s
);
1065 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1070 if ((s
->rtsr
^ value
) & (1 << 15))
1071 pxa2xx_rtc_piupdate(s
);
1073 if ((s
->rtsr
^ value
) & (1 << 12))
1074 pxa2xx_rtc_swupdate(s
);
1076 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1077 pxa2xx_rtc_alarm_update(s
, value
);
1079 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1080 pxa2xx_rtc_int_update(s
);
1085 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1090 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1095 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1100 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1105 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1109 pxa2xx_rtc_swupdate(s
);
1112 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1117 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1122 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1126 pxa2xx_rtc_hzupdate(s
);
1127 s
->last_rcnr
= value
;
1128 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1132 pxa2xx_rtc_hzupdate(s
);
1133 s
->last_rdcr
= value
;
1134 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1138 s
->last_rycr
= value
;
1142 pxa2xx_rtc_swupdate(s
);
1143 s
->last_swcr
= value
;
1144 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1148 pxa2xx_rtc_piupdate(s
);
1149 s
->last_rtcpicr
= value
& 0xffff;
1150 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1154 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1158 static CPUReadMemoryFunc
* const pxa2xx_rtc_readfn
[] = {
1164 static CPUWriteMemoryFunc
* const pxa2xx_rtc_writefn
[] = {
1170 static void pxa2xx_rtc_init(PXA2xxState
*s
)
1178 qemu_get_timedate(&tm
, 0);
1179 wom
= ((tm
.tm_mday
- 1) / 7) + 1;
1181 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
1182 s
->last_rdcr
= (wom
<< 20) | ((tm
.tm_wday
+ 1) << 17) |
1183 (tm
.tm_hour
<< 12) | (tm
.tm_min
<< 6) | tm
.tm_sec
;
1184 s
->last_rycr
= ((tm
.tm_year
+ 1900) << 9) |
1185 ((tm
.tm_mon
+ 1) << 5) | tm
.tm_mday
;
1186 s
->last_swcr
= (tm
.tm_hour
<< 19) |
1187 (tm
.tm_min
<< 13) | (tm
.tm_sec
<< 7);
1188 s
->last_rtcpicr
= 0;
1189 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_get_clock(rt_clock
);
1191 s
->rtc_hz
= qemu_new_timer(rt_clock
, pxa2xx_rtc_hz_tick
, s
);
1192 s
->rtc_rdal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1193 s
->rtc_rdal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1194 s
->rtc_swal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal1_tick
, s
);
1195 s
->rtc_swal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal2_tick
, s
);
1196 s
->rtc_pi
= qemu_new_timer(rt_clock
, pxa2xx_rtc_pi_tick
, s
);
1199 static void pxa2xx_rtc_save(QEMUFile
*f
, void *opaque
)
1201 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
1203 pxa2xx_rtc_hzupdate(s
);
1204 pxa2xx_rtc_piupdate(s
);
1205 pxa2xx_rtc_swupdate(s
);
1207 qemu_put_be32s(f
, &s
->rttr
);
1208 qemu_put_be32s(f
, &s
->rtsr
);
1209 qemu_put_be32s(f
, &s
->rtar
);
1210 qemu_put_be32s(f
, &s
->rdar1
);
1211 qemu_put_be32s(f
, &s
->rdar2
);
1212 qemu_put_be32s(f
, &s
->ryar1
);
1213 qemu_put_be32s(f
, &s
->ryar2
);
1214 qemu_put_be32s(f
, &s
->swar1
);
1215 qemu_put_be32s(f
, &s
->swar2
);
1216 qemu_put_be32s(f
, &s
->piar
);
1217 qemu_put_be32s(f
, &s
->last_rcnr
);
1218 qemu_put_be32s(f
, &s
->last_rdcr
);
1219 qemu_put_be32s(f
, &s
->last_rycr
);
1220 qemu_put_be32s(f
, &s
->last_swcr
);
1221 qemu_put_be32s(f
, &s
->last_rtcpicr
);
1222 qemu_put_sbe64s(f
, &s
->last_hz
);
1223 qemu_put_sbe64s(f
, &s
->last_sw
);
1224 qemu_put_sbe64s(f
, &s
->last_pi
);
1227 static int pxa2xx_rtc_load(QEMUFile
*f
, void *opaque
, int version_id
)
1229 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
1231 qemu_get_be32s(f
, &s
->rttr
);
1232 qemu_get_be32s(f
, &s
->rtsr
);
1233 qemu_get_be32s(f
, &s
->rtar
);
1234 qemu_get_be32s(f
, &s
->rdar1
);
1235 qemu_get_be32s(f
, &s
->rdar2
);
1236 qemu_get_be32s(f
, &s
->ryar1
);
1237 qemu_get_be32s(f
, &s
->ryar2
);
1238 qemu_get_be32s(f
, &s
->swar1
);
1239 qemu_get_be32s(f
, &s
->swar2
);
1240 qemu_get_be32s(f
, &s
->piar
);
1241 qemu_get_be32s(f
, &s
->last_rcnr
);
1242 qemu_get_be32s(f
, &s
->last_rdcr
);
1243 qemu_get_be32s(f
, &s
->last_rycr
);
1244 qemu_get_be32s(f
, &s
->last_swcr
);
1245 qemu_get_be32s(f
, &s
->last_rtcpicr
);
1246 qemu_get_sbe64s(f
, &s
->last_hz
);
1247 qemu_get_sbe64s(f
, &s
->last_sw
);
1248 qemu_get_sbe64s(f
, &s
->last_pi
);
1250 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1258 PXA2xxI2CState
*host
;
1259 } PXA2xxI2CSlaveState
;
1261 struct PXA2xxI2CState
{
1262 PXA2xxI2CSlaveState
*slave
;
1265 target_phys_addr_t offset
;
1273 #define IBMR 0x80 /* I2C Bus Monitor register */
1274 #define IDBR 0x88 /* I2C Data Buffer register */
1275 #define ICR 0x90 /* I2C Control register */
1276 #define ISR 0x98 /* I2C Status register */
1277 #define ISAR 0xa0 /* I2C Slave Address register */
1279 static void pxa2xx_i2c_update(PXA2xxI2CState
*s
)
1282 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1283 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1284 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1285 level
|= s
->status
& (1 << 9); /* SAD */
1286 qemu_set_irq(s
->irq
, !!level
);
1289 /* These are only stubs now. */
1290 static void pxa2xx_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
1292 PXA2xxI2CSlaveState
*slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, i2c
);
1293 PXA2xxI2CState
*s
= slave
->host
;
1296 case I2C_START_SEND
:
1297 s
->status
|= (1 << 9); /* set SAD */
1298 s
->status
&= ~(1 << 0); /* clear RWM */
1300 case I2C_START_RECV
:
1301 s
->status
|= (1 << 9); /* set SAD */
1302 s
->status
|= 1 << 0; /* set RWM */
1305 s
->status
|= (1 << 4); /* set SSD */
1308 s
->status
|= 1 << 1; /* set ACKNAK */
1311 pxa2xx_i2c_update(s
);
1314 static int pxa2xx_i2c_rx(i2c_slave
*i2c
)
1316 PXA2xxI2CSlaveState
*slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, i2c
);
1317 PXA2xxI2CState
*s
= slave
->host
;
1318 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1321 if (s
->status
& (1 << 0)) { /* RWM */
1322 s
->status
|= 1 << 6; /* set ITE */
1324 pxa2xx_i2c_update(s
);
1329 static int pxa2xx_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
1331 PXA2xxI2CSlaveState
*slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, i2c
);
1332 PXA2xxI2CState
*s
= slave
->host
;
1333 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1336 if (!(s
->status
& (1 << 0))) { /* RWM */
1337 s
->status
|= 1 << 7; /* set IRF */
1340 pxa2xx_i2c_update(s
);
1345 static uint32_t pxa2xx_i2c_read(void *opaque
, target_phys_addr_t addr
)
1347 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1354 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1356 return s
->slave
->i2c
.address
;
1360 if (s
->status
& (1 << 2))
1361 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1366 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1372 static void pxa2xx_i2c_write(void *opaque
, target_phys_addr_t addr
,
1375 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1381 s
->control
= value
& 0xfff7;
1382 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1383 /* TODO: slave mode */
1384 if (value
& (1 << 0)) { /* START condition */
1386 s
->status
|= 1 << 0; /* set RWM */
1388 s
->status
&= ~(1 << 0); /* clear RWM */
1389 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1391 if (s
->status
& (1 << 0)) { /* RWM */
1392 s
->data
= i2c_recv(s
->bus
);
1393 if (value
& (1 << 2)) /* ACKNAK */
1397 ack
= !i2c_send(s
->bus
, s
->data
);
1400 if (value
& (1 << 1)) /* STOP condition */
1401 i2c_end_transfer(s
->bus
);
1404 if (value
& (1 << 0)) /* START condition */
1405 s
->status
|= 1 << 6; /* set ITE */
1407 if (s
->status
& (1 << 0)) /* RWM */
1408 s
->status
|= 1 << 7; /* set IRF */
1410 s
->status
|= 1 << 6; /* set ITE */
1411 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1413 s
->status
|= 1 << 6; /* set ITE */
1414 s
->status
|= 1 << 10; /* set BED */
1415 s
->status
|= 1 << 1; /* set ACKNAK */
1418 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1419 if (value
& (1 << 4)) /* MA */
1420 i2c_end_transfer(s
->bus
);
1421 pxa2xx_i2c_update(s
);
1425 s
->status
&= ~(value
& 0x07f0);
1426 pxa2xx_i2c_update(s
);
1430 i2c_set_slave_address(&s
->slave
->i2c
, value
& 0x7f);
1434 s
->data
= value
& 0xff;
1438 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1442 static CPUReadMemoryFunc
* const pxa2xx_i2c_readfn
[] = {
1448 static CPUWriteMemoryFunc
* const pxa2xx_i2c_writefn
[] = {
1454 static void pxa2xx_i2c_save(QEMUFile
*f
, void *opaque
)
1456 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1458 qemu_put_be16s(f
, &s
->control
);
1459 qemu_put_be16s(f
, &s
->status
);
1460 qemu_put_8s(f
, &s
->ibmr
);
1461 qemu_put_8s(f
, &s
->data
);
1463 i2c_slave_save(f
, &s
->slave
->i2c
);
1466 static int pxa2xx_i2c_load(QEMUFile
*f
, void *opaque
, int version_id
)
1468 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1470 if (version_id
!= 1)
1473 qemu_get_be16s(f
, &s
->control
);
1474 qemu_get_be16s(f
, &s
->status
);
1475 qemu_get_8s(f
, &s
->ibmr
);
1476 qemu_get_8s(f
, &s
->data
);
1478 i2c_slave_load(f
, &s
->slave
->i2c
);
1482 static void pxa2xx_i2c_slave_init(i2c_slave
*i2c
)
1484 /* Nothing to do. */
1487 static I2CSlaveInfo pxa2xx_i2c_slave_info
= {
1488 .qdev
.name
= "pxa2xx-i2c-slave",
1489 .qdev
.size
= sizeof(PXA2xxI2CSlaveState
),
1490 .init
= pxa2xx_i2c_slave_init
,
1491 .event
= pxa2xx_i2c_event
,
1492 .recv
= pxa2xx_i2c_rx
,
1493 .send
= pxa2xx_i2c_tx
1496 PXA2xxI2CState
*pxa2xx_i2c_init(target_phys_addr_t base
,
1497 qemu_irq irq
, uint32_t region_size
)
1501 PXA2xxI2CState
*s
= qemu_mallocz(sizeof(PXA2xxI2CState
));
1503 /* FIXME: Should the slave device really be on a separate bus? */
1504 dev
= i2c_create_slave(i2c_init_bus(NULL
, "dummy"), "pxa2xx-i2c-slave", 0);
1505 s
->slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, I2C_SLAVE_FROM_QDEV(dev
));
1509 s
->bus
= i2c_init_bus(NULL
, "i2c");
1510 s
->offset
= base
- (base
& (~region_size
) & TARGET_PAGE_MASK
);
1512 iomemtype
= cpu_register_io_memory(pxa2xx_i2c_readfn
,
1513 pxa2xx_i2c_writefn
, s
);
1514 cpu_register_physical_memory(base
& ~region_size
,
1515 region_size
+ 1, iomemtype
);
1517 register_savevm("pxa2xx_i2c", base
, 1,
1518 pxa2xx_i2c_save
, pxa2xx_i2c_load
, s
);
1523 i2c_bus
*pxa2xx_i2c_bus(PXA2xxI2CState
*s
)
1528 /* PXA Inter-IC Sound Controller */
1529 static void pxa2xx_i2s_reset(PXA2xxI2SState
*i2s
)
1535 i2s
->control
[0] = 0x00;
1536 i2s
->control
[1] = 0x00;
1541 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1542 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1543 #define SACR_DREC(val) (val & (1 << 3))
1544 #define SACR_DPRL(val) (val & (1 << 4))
1546 static inline void pxa2xx_i2s_update(PXA2xxI2SState
*i2s
)
1549 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1550 !SACR_DREC(i2s
->control
[1]);
1551 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1552 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1554 pxa2xx_dma_request(i2s
->dma
, PXA2XX_RX_RQ_I2S
, rfs
);
1555 pxa2xx_dma_request(i2s
->dma
, PXA2XX_TX_RQ_I2S
, tfs
);
1557 i2s
->status
&= 0xe0;
1558 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1559 i2s
->status
|= 1 << 0; /* TNF */
1561 i2s
->status
|= 1 << 1; /* RNE */
1563 i2s
->status
|= 1 << 2; /* BSY */
1565 i2s
->status
|= 1 << 3; /* TFS */
1567 i2s
->status
|= 1 << 4; /* RFS */
1568 if (!(i2s
->tx_len
&& i2s
->enable
))
1569 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1570 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1572 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1575 #define SACR0 0x00 /* Serial Audio Global Control register */
1576 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1577 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1578 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1579 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1580 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1581 #define SADR 0x80 /* Serial Audio Data register */
1583 static uint32_t pxa2xx_i2s_read(void *opaque
, target_phys_addr_t addr
)
1585 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1589 return s
->control
[0];
1591 return s
->control
[1];
1601 if (s
->rx_len
> 0) {
1603 pxa2xx_i2s_update(s
);
1604 return s
->codec_in(s
->opaque
);
1608 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1614 static void pxa2xx_i2s_write(void *opaque
, target_phys_addr_t addr
,
1617 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1622 if (value
& (1 << 3)) /* RST */
1623 pxa2xx_i2s_reset(s
);
1624 s
->control
[0] = value
& 0xff3d;
1625 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1626 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1627 s
->codec_out(s
->opaque
, *sample
);
1628 s
->status
&= ~(1 << 7); /* I2SOFF */
1630 if (value
& (1 << 4)) /* EFWR */
1631 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1632 s
->enable
= ((value
^ 4) & 5) == 5; /* ENB && !RST*/
1633 pxa2xx_i2s_update(s
);
1636 s
->control
[1] = value
& 0x0039;
1637 if (value
& (1 << 5)) /* ENLBF */
1638 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1639 if (value
& (1 << 4)) /* DPRL */
1641 pxa2xx_i2s_update(s
);
1644 s
->mask
= value
& 0x0078;
1645 pxa2xx_i2s_update(s
);
1648 s
->status
&= ~(value
& (3 << 5));
1649 pxa2xx_i2s_update(s
);
1652 s
->clk
= value
& 0x007f;
1655 if (s
->tx_len
&& s
->enable
) {
1657 pxa2xx_i2s_update(s
);
1658 s
->codec_out(s
->opaque
, value
);
1659 } else if (s
->fifo_len
< 16) {
1660 s
->fifo
[s
->fifo_len
++] = value
;
1661 pxa2xx_i2s_update(s
);
1665 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1669 static CPUReadMemoryFunc
* const pxa2xx_i2s_readfn
[] = {
1675 static CPUWriteMemoryFunc
* const pxa2xx_i2s_writefn
[] = {
1681 static void pxa2xx_i2s_save(QEMUFile
*f
, void *opaque
)
1683 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1685 qemu_put_be32s(f
, &s
->control
[0]);
1686 qemu_put_be32s(f
, &s
->control
[1]);
1687 qemu_put_be32s(f
, &s
->status
);
1688 qemu_put_be32s(f
, &s
->mask
);
1689 qemu_put_be32s(f
, &s
->clk
);
1691 qemu_put_be32(f
, s
->enable
);
1692 qemu_put_be32(f
, s
->rx_len
);
1693 qemu_put_be32(f
, s
->tx_len
);
1694 qemu_put_be32(f
, s
->fifo_len
);
1697 static int pxa2xx_i2s_load(QEMUFile
*f
, void *opaque
, int version_id
)
1699 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1701 qemu_get_be32s(f
, &s
->control
[0]);
1702 qemu_get_be32s(f
, &s
->control
[1]);
1703 qemu_get_be32s(f
, &s
->status
);
1704 qemu_get_be32s(f
, &s
->mask
);
1705 qemu_get_be32s(f
, &s
->clk
);
1707 s
->enable
= qemu_get_be32(f
);
1708 s
->rx_len
= qemu_get_be32(f
);
1709 s
->tx_len
= qemu_get_be32(f
);
1710 s
->fifo_len
= qemu_get_be32(f
);
1715 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1717 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1720 /* Signal FIFO errors */
1721 if (s
->enable
&& s
->tx_len
)
1722 s
->status
|= 1 << 5; /* TUR */
1723 if (s
->enable
&& s
->rx_len
)
1724 s
->status
|= 1 << 6; /* ROR */
1726 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1727 * handle the cases where it makes a difference. */
1728 s
->tx_len
= tx
- s
->fifo_len
;
1730 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1732 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1733 s
->codec_out(s
->opaque
, *sample
);
1734 pxa2xx_i2s_update(s
);
1737 static PXA2xxI2SState
*pxa2xx_i2s_init(target_phys_addr_t base
,
1738 qemu_irq irq
, PXA2xxDMAState
*dma
)
1741 PXA2xxI2SState
*s
= (PXA2xxI2SState
*)
1742 qemu_mallocz(sizeof(PXA2xxI2SState
));
1746 s
->data_req
= pxa2xx_i2s_data_req
;
1748 pxa2xx_i2s_reset(s
);
1750 iomemtype
= cpu_register_io_memory(pxa2xx_i2s_readfn
,
1751 pxa2xx_i2s_writefn
, s
);
1752 cpu_register_physical_memory(base
, 0x100000, iomemtype
);
1754 register_savevm("pxa2xx_i2s", base
, 0,
1755 pxa2xx_i2s_save
, pxa2xx_i2s_load
, s
);
1760 /* PXA Fast Infra-red Communications Port */
1761 struct PXA2xxFIrState
{
1763 PXA2xxDMAState
*dma
;
1765 CharDriverState
*chr
;
1772 uint8_t rx_fifo
[64];
1775 static void pxa2xx_fir_reset(PXA2xxFIrState
*s
)
1777 s
->control
[0] = 0x00;
1778 s
->control
[1] = 0x00;
1779 s
->control
[2] = 0x00;
1780 s
->status
[0] = 0x00;
1781 s
->status
[1] = 0x00;
1785 static inline void pxa2xx_fir_update(PXA2xxFIrState
*s
)
1787 static const int tresh
[4] = { 8, 16, 32, 0 };
1789 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1790 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1791 s
->status
[0] |= 1 << 4; /* RFS */
1793 s
->status
[0] &= ~(1 << 4); /* RFS */
1794 if (s
->control
[0] & (1 << 3)) /* TXE */
1795 s
->status
[0] |= 1 << 3; /* TFS */
1797 s
->status
[0] &= ~(1 << 3); /* TFS */
1799 s
->status
[1] |= 1 << 2; /* RNE */
1801 s
->status
[1] &= ~(1 << 2); /* RNE */
1802 if (s
->control
[0] & (1 << 4)) /* RXE */
1803 s
->status
[1] |= 1 << 0; /* RSY */
1805 s
->status
[1] &= ~(1 << 0); /* RSY */
1807 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1808 (s
->status
[0] & (1 << 4)); /* RFS */
1809 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1810 (s
->status
[0] & (1 << 3)); /* TFS */
1811 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1812 (s
->status
[0] & (1 << 6)); /* EOC */
1813 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1814 (s
->status
[0] & (1 << 1)); /* TUR */
1815 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1817 pxa2xx_dma_request(s
->dma
, PXA2XX_RX_RQ_ICP
, (s
->status
[0] >> 4) & 1);
1818 pxa2xx_dma_request(s
->dma
, PXA2XX_TX_RQ_ICP
, (s
->status
[0] >> 3) & 1);
1820 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1823 #define ICCR0 0x00 /* FICP Control register 0 */
1824 #define ICCR1 0x04 /* FICP Control register 1 */
1825 #define ICCR2 0x08 /* FICP Control register 2 */
1826 #define ICDR 0x0c /* FICP Data register */
1827 #define ICSR0 0x14 /* FICP Status register 0 */
1828 #define ICSR1 0x18 /* FICP Status register 1 */
1829 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1831 static uint32_t pxa2xx_fir_read(void *opaque
, target_phys_addr_t addr
)
1833 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1838 return s
->control
[0];
1840 return s
->control
[1];
1842 return s
->control
[2];
1844 s
->status
[0] &= ~0x01;
1845 s
->status
[1] &= ~0x72;
1848 ret
= s
->rx_fifo
[s
->rx_start
++];
1850 pxa2xx_fir_update(s
);
1853 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1856 return s
->status
[0];
1858 return s
->status
[1] | (1 << 3); /* TNF */
1862 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1868 static void pxa2xx_fir_write(void *opaque
, target_phys_addr_t addr
,
1871 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1876 s
->control
[0] = value
;
1877 if (!(value
& (1 << 4))) /* RXE */
1878 s
->rx_len
= s
->rx_start
= 0;
1879 if (!(value
& (1 << 3))) /* TXE */
1881 s
->enable
= value
& 1; /* ITR */
1884 pxa2xx_fir_update(s
);
1887 s
->control
[1] = value
;
1890 s
->control
[2] = value
& 0x3f;
1891 pxa2xx_fir_update(s
);
1894 if (s
->control
[2] & (1 << 2)) /* TXP */
1898 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1899 qemu_chr_write(s
->chr
, &ch
, 1);
1902 s
->status
[0] &= ~(value
& 0x66);
1903 pxa2xx_fir_update(s
);
1908 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1912 static CPUReadMemoryFunc
* const pxa2xx_fir_readfn
[] = {
1918 static CPUWriteMemoryFunc
* const pxa2xx_fir_writefn
[] = {
1924 static int pxa2xx_fir_is_empty(void *opaque
)
1926 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1927 return (s
->rx_len
< 64);
1930 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1932 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1933 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1937 s
->status
[1] |= 1 << 4; /* EOF */
1938 if (s
->rx_len
>= 64) {
1939 s
->status
[1] |= 1 << 6; /* ROR */
1943 if (s
->control
[2] & (1 << 3)) /* RXP */
1944 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1946 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1949 pxa2xx_fir_update(s
);
1952 static void pxa2xx_fir_event(void *opaque
, int event
)
1956 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1958 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1961 qemu_put_be32(f
, s
->enable
);
1963 qemu_put_8s(f
, &s
->control
[0]);
1964 qemu_put_8s(f
, &s
->control
[1]);
1965 qemu_put_8s(f
, &s
->control
[2]);
1966 qemu_put_8s(f
, &s
->status
[0]);
1967 qemu_put_8s(f
, &s
->status
[1]);
1969 qemu_put_byte(f
, s
->rx_len
);
1970 for (i
= 0; i
< s
->rx_len
; i
++)
1971 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
1974 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
1976 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1979 s
->enable
= qemu_get_be32(f
);
1981 qemu_get_8s(f
, &s
->control
[0]);
1982 qemu_get_8s(f
, &s
->control
[1]);
1983 qemu_get_8s(f
, &s
->control
[2]);
1984 qemu_get_8s(f
, &s
->status
[0]);
1985 qemu_get_8s(f
, &s
->status
[1]);
1987 s
->rx_len
= qemu_get_byte(f
);
1989 for (i
= 0; i
< s
->rx_len
; i
++)
1990 s
->rx_fifo
[i
] = qemu_get_byte(f
);
1995 static PXA2xxFIrState
*pxa2xx_fir_init(target_phys_addr_t base
,
1996 qemu_irq irq
, PXA2xxDMAState
*dma
,
1997 CharDriverState
*chr
)
2000 PXA2xxFIrState
*s
= (PXA2xxFIrState
*)
2001 qemu_mallocz(sizeof(PXA2xxFIrState
));
2007 pxa2xx_fir_reset(s
);
2009 iomemtype
= cpu_register_io_memory(pxa2xx_fir_readfn
,
2010 pxa2xx_fir_writefn
, s
);
2011 cpu_register_physical_memory(base
, 0x1000, iomemtype
);
2014 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
2015 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
2017 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save
, pxa2xx_fir_load
, s
);
2022 static void pxa2xx_reset(void *opaque
, int line
, int level
)
2024 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
2026 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2028 /* TODO: reset peripherals */
2032 /* Initialise a PXA270 integrated chip (ARM based core). */
2033 PXA2xxState
*pxa270_init(unsigned int sdram_size
, const char *revision
)
2038 s
= (PXA2xxState
*) qemu_mallocz(sizeof(PXA2xxState
));
2040 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2041 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2045 revision
= "pxa270";
2047 s
->env
= cpu_init(revision
);
2049 fprintf(stderr
, "Unable to find CPU definition\n");
2052 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2054 /* SDRAM & Internal Memory Storage */
2055 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
,
2056 sdram_size
, qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2057 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
,
2058 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM
);
2060 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2062 s
->dma
= pxa27x_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2064 pxa27x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
],
2065 s
->pic
[PXA27X_PIC_OST_4_11
]);
2067 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
2069 dinfo
= drive_get(IF_SD
, 0, 0);
2071 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2074 s
->mmc
= pxa2xx_mmci_init(0x41100000, dinfo
->bdrv
,
2075 s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2077 for (i
= 0; pxa270_serial
[i
].io_base
; i
++)
2079 serial_mm_init(pxa270_serial
[i
].io_base
, 2,
2080 s
->pic
[pxa270_serial
[i
].irqn
], 14857000/16,
2085 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2086 s
->dma
, serial_hds
[i
]);
2088 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
]);
2090 s
->cm_base
= 0x41300000;
2091 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2092 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2093 iomemtype
= cpu_register_io_memory(pxa2xx_cm_readfn
,
2094 pxa2xx_cm_writefn
, s
);
2095 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2096 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2098 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2100 s
->mm_base
= 0x48000000;
2101 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2102 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2103 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2104 iomemtype
= cpu_register_io_memory(pxa2xx_mm_readfn
,
2105 pxa2xx_mm_writefn
, s
);
2106 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2107 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2109 s
->pm_base
= 0x40f00000;
2110 iomemtype
= cpu_register_io_memory(pxa2xx_pm_readfn
,
2111 pxa2xx_pm_writefn
, s
);
2112 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2113 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2115 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2116 s
->ssp
= (SSIBus
**)qemu_mallocz(sizeof(SSIBus
*) * i
);
2117 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2119 dev
= sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp
[i
].io_base
,
2120 s
->pic
[pxa27x_ssp
[i
].irqn
]);
2121 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2125 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2128 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2129 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2131 s
->rtc_base
= 0x40900000;
2132 iomemtype
= cpu_register_io_memory(pxa2xx_rtc_readfn
,
2133 pxa2xx_rtc_writefn
, s
);
2134 cpu_register_physical_memory(s
->rtc_base
, 0x1000, iomemtype
);
2136 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2138 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 0xffff);
2139 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0xff);
2141 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2143 s
->kp
= pxa27x_keypad_init(0x41500000, s
->pic
[PXA2XX_PIC_KEYPAD
]);
2145 /* GPIO1 resets the processor */
2146 /* The handler can be overridden by board-specific code */
2147 pxa2xx_gpio_out_set(s
->gpio
, 1, s
->reset
);
2151 /* Initialise a PXA255 integrated chip (ARM based core). */
2152 PXA2xxState
*pxa255_init(unsigned int sdram_size
)
2158 s
= (PXA2xxState
*) qemu_mallocz(sizeof(PXA2xxState
));
2160 s
->env
= cpu_init("pxa255");
2162 fprintf(stderr
, "Unable to find CPU definition\n");
2165 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2167 /* SDRAM & Internal Memory Storage */
2168 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
, sdram_size
,
2169 qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2170 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
, PXA2XX_INTERNAL_SIZE
,
2171 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE
) | IO_MEM_RAM
);
2173 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2175 s
->dma
= pxa255_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2177 pxa25x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
]);
2179 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 85);
2181 dinfo
= drive_get(IF_SD
, 0, 0);
2183 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2186 s
->mmc
= pxa2xx_mmci_init(0x41100000, dinfo
->bdrv
,
2187 s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2189 for (i
= 0; pxa255_serial
[i
].io_base
; i
++)
2191 serial_mm_init(pxa255_serial
[i
].io_base
, 2,
2192 s
->pic
[pxa255_serial
[i
].irqn
], 14745600/16,
2197 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2198 s
->dma
, serial_hds
[i
]);
2200 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
]);
2202 s
->cm_base
= 0x41300000;
2203 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2204 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2205 iomemtype
= cpu_register_io_memory(pxa2xx_cm_readfn
,
2206 pxa2xx_cm_writefn
, s
);
2207 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2208 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2210 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2212 s
->mm_base
= 0x48000000;
2213 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2214 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2215 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2216 iomemtype
= cpu_register_io_memory(pxa2xx_mm_readfn
,
2217 pxa2xx_mm_writefn
, s
);
2218 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2219 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2221 s
->pm_base
= 0x40f00000;
2222 iomemtype
= cpu_register_io_memory(pxa2xx_pm_readfn
,
2223 pxa2xx_pm_writefn
, s
);
2224 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2225 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2227 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2228 s
->ssp
= (SSIBus
**)qemu_mallocz(sizeof(SSIBus
*) * i
);
2229 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2231 dev
= sysbus_create_simple("pxa2xx-ssp", pxa255_ssp
[i
].io_base
,
2232 s
->pic
[pxa255_ssp
[i
].irqn
]);
2233 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2237 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2240 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2241 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2243 s
->rtc_base
= 0x40900000;
2244 iomemtype
= cpu_register_io_memory(pxa2xx_rtc_readfn
,
2245 pxa2xx_rtc_writefn
, s
);
2246 cpu_register_physical_memory(s
->rtc_base
, 0x1000, iomemtype
);
2248 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2250 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 0xffff);
2251 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0xff);
2253 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2255 /* GPIO1 resets the processor */
2256 /* The handler can be overridden by board-specific code */
2257 pxa2xx_gpio_out_set(s
->gpio
, 1, s
->reset
);
2261 static void pxa2xx_register_devices(void)
2263 i2c_register_slave(&pxa2xx_i2c_slave_info
);
2264 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState
), pxa2xx_ssp_init
);
2267 device_init(pxa2xx_register_devices
)