2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "hw/spapr_pci.h"
30 #include "exec-memory.h"
33 #include "hw/pci_internals.h"
35 static PCIDevice
*find_dev(sPAPREnvironment
*spapr
,
36 uint64_t buid
, uint32_t config_addr
)
39 int devfn
= (config_addr
>> 8) & 0xFF;
42 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
43 if (phb
->buid
!= buid
) {
47 QTAILQ_FOREACH(qdev
, &phb
->host_state
.bus
->qbus
.children
, sibling
) {
48 PCIDevice
*dev
= (PCIDevice
*)qdev
;
49 if (dev
->devfn
== devfn
) {
58 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
60 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
63 static uint32_t rtas_read_pci_config_do(PCIDevice
*pci_dev
, uint32_t addr
,
64 uint32_t limit
, uint32_t len
)
66 if ((addr
+ len
) <= limit
) {
67 return pci_host_config_read_common(pci_dev
, addr
, limit
, len
);
73 static void rtas_write_pci_config_do(PCIDevice
*pci_dev
, uint32_t addr
,
74 uint32_t limit
, uint32_t val
,
77 if ((addr
+ len
) <= limit
) {
78 pci_host_config_write_common(pci_dev
, addr
, limit
, val
, len
);
82 static void rtas_ibm_read_pci_config(sPAPREnvironment
*spapr
,
83 uint32_t token
, uint32_t nargs
,
85 uint32_t nret
, target_ulong rets
)
87 uint32_t val
, size
, addr
;
88 uint64_t buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
89 PCIDevice
*dev
= find_dev(spapr
, buid
, rtas_ld(args
, 0));
95 size
= rtas_ld(args
, 3);
96 addr
= rtas_pci_cfgaddr(rtas_ld(args
, 0));
97 val
= rtas_read_pci_config_do(dev
, addr
, pci_config_size(dev
), size
);
99 rtas_st(rets
, 1, val
);
102 static void rtas_read_pci_config(sPAPREnvironment
*spapr
,
103 uint32_t token
, uint32_t nargs
,
105 uint32_t nret
, target_ulong rets
)
107 uint32_t val
, size
, addr
;
108 PCIDevice
*dev
= find_dev(spapr
, 0, rtas_ld(args
, 0));
111 rtas_st(rets
, 0, -1);
114 size
= rtas_ld(args
, 1);
115 addr
= rtas_pci_cfgaddr(rtas_ld(args
, 0));
116 val
= rtas_read_pci_config_do(dev
, addr
, pci_config_size(dev
), size
);
118 rtas_st(rets
, 1, val
);
121 static void rtas_ibm_write_pci_config(sPAPREnvironment
*spapr
,
122 uint32_t token
, uint32_t nargs
,
124 uint32_t nret
, target_ulong rets
)
126 uint32_t val
, size
, addr
;
127 uint64_t buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
128 PCIDevice
*dev
= find_dev(spapr
, buid
, rtas_ld(args
, 0));
131 rtas_st(rets
, 0, -1);
134 val
= rtas_ld(args
, 4);
135 size
= rtas_ld(args
, 3);
136 addr
= rtas_pci_cfgaddr(rtas_ld(args
, 0));
137 rtas_write_pci_config_do(dev
, addr
, pci_config_size(dev
), val
, size
);
141 static void rtas_write_pci_config(sPAPREnvironment
*spapr
,
142 uint32_t token
, uint32_t nargs
,
144 uint32_t nret
, target_ulong rets
)
146 uint32_t val
, size
, addr
;
147 PCIDevice
*dev
= find_dev(spapr
, 0, rtas_ld(args
, 0));
150 rtas_st(rets
, 0, -1);
153 val
= rtas_ld(args
, 2);
154 size
= rtas_ld(args
, 1);
155 addr
= rtas_pci_cfgaddr(rtas_ld(args
, 0));
156 rtas_write_pci_config_do(dev
, addr
, pci_config_size(dev
), val
, size
);
160 static int pci_spapr_map_irq(PCIDevice
*pci_dev
, int irq_num
)
163 * Here we need to convert pci_dev + irq_num to some unique value
164 * which is less than number of IRQs on the specific bus (now it
165 * is 16). At the moment irq_num == device_id (number of the
167 * FIXME: we should swizzle in fn and irq_num
169 return (pci_dev
->devfn
>> 3) % SPAPR_PCI_NUM_LSI
;
172 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
175 * Here we use the number returned by pci_spapr_map_irq to find a
176 * corresponding qemu_irq.
178 sPAPRPHBState
*phb
= opaque
;
180 qemu_set_irq(phb
->lsi_table
[irq_num
].qirq
, level
);
183 static uint64_t spapr_io_read(void *opaque
, target_phys_addr_t addr
,
188 return cpu_inb(addr
);
190 return cpu_inw(addr
);
192 return cpu_inl(addr
);
197 static void spapr_io_write(void *opaque
, target_phys_addr_t addr
,
198 uint64_t data
, unsigned size
)
202 cpu_outb(addr
, data
);
205 cpu_outw(addr
, data
);
208 cpu_outl(addr
, data
);
214 static const MemoryRegionOps spapr_io_ops
= {
215 .endianness
= DEVICE_LITTLE_ENDIAN
,
216 .read
= spapr_io_read
,
217 .write
= spapr_io_write
223 static int spapr_phb_init(SysBusDevice
*s
)
225 sPAPRPHBState
*phb
= FROM_SYSBUS(sPAPRPHBState
, s
);
230 phb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, phb
->buid
);
231 namebuf
= alloca(strlen(phb
->dtbusname
) + 32);
233 /* Initialize memory regions */
234 sprintf(namebuf
, "%s.mmio", phb
->dtbusname
);
235 memory_region_init(&phb
->memspace
, namebuf
, INT64_MAX
);
237 sprintf(namebuf
, "%s.mmio-alias", phb
->dtbusname
);
238 memory_region_init_alias(&phb
->memwindow
, namebuf
, &phb
->memspace
,
239 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, phb
->mem_win_size
);
240 memory_region_add_subregion(get_system_memory(), phb
->mem_win_addr
,
243 /* On ppc, we only have MMIO no specific IO space from the CPU
244 * perspective. In theory we ought to be able to embed the PCI IO
245 * memory region direction in the system memory space. However,
246 * if any of the IO BAR subregions use the old_portio mechanism,
247 * that won't be processed properly unless accessed from the
248 * system io address space. This hack to bounce things via
249 * system_io works around the problem until all the users of
250 * old_portion are updated */
251 sprintf(namebuf
, "%s.io", phb
->dtbusname
);
252 memory_region_init(&phb
->iospace
, namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
253 /* FIXME: fix to support multiple PHBs */
254 memory_region_add_subregion(get_system_io(), 0, &phb
->iospace
);
256 sprintf(namebuf
, "%s.io-alias", phb
->dtbusname
);
257 memory_region_init_io(&phb
->iowindow
, &spapr_io_ops
, phb
,
258 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
259 memory_region_add_subregion(get_system_memory(), phb
->io_win_addr
,
262 bus
= pci_register_bus(&phb
->busdev
.qdev
,
263 phb
->busname
? phb
->busname
: phb
->dtbusname
,
264 pci_spapr_set_irq
, pci_spapr_map_irq
, phb
,
265 &phb
->memspace
, &phb
->iospace
,
266 PCI_DEVFN(0, 0), SPAPR_PCI_NUM_LSI
);
267 phb
->host_state
.bus
= bus
;
269 QLIST_INSERT_HEAD(&spapr
->phbs
, phb
, list
);
271 /* Initialize the LSI table */
272 for (i
= 0; i
< SPAPR_PCI_NUM_LSI
; i
++) {
276 qirq
= spapr_allocate_lsi(0, &num
);
281 phb
->lsi_table
[i
].dt_irq
= num
;
282 phb
->lsi_table
[i
].qirq
= qirq
;
288 static Property spapr_phb_properties
[] = {
289 DEFINE_PROP_HEX64("buid", sPAPRPHBState
, buid
, 0),
290 DEFINE_PROP_STRING("busname", sPAPRPHBState
, busname
),
291 DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState
, mem_win_addr
, 0),
292 DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState
, mem_win_size
, 0x20000000),
293 DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState
, io_win_addr
, 0),
294 DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState
, io_win_size
, 0x10000),
295 DEFINE_PROP_END_OF_LIST(),
298 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
300 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
301 DeviceClass
*dc
= DEVICE_CLASS(klass
);
303 sdc
->init
= spapr_phb_init
;
304 dc
->props
= spapr_phb_properties
;
306 spapr_rtas_register("read-pci-config", rtas_read_pci_config
);
307 spapr_rtas_register("write-pci-config", rtas_write_pci_config
);
308 spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config
);
309 spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config
);
312 static TypeInfo spapr_phb_info
= {
313 .name
= "spapr-pci-host-bridge",
314 .parent
= TYPE_SYS_BUS_DEVICE
,
315 .instance_size
= sizeof(sPAPRPHBState
),
316 .class_init
= spapr_phb_class_init
,
319 void spapr_create_phb(sPAPREnvironment
*spapr
,
320 const char *busname
, uint64_t buid
,
321 uint64_t mem_win_addr
, uint64_t mem_win_size
,
322 uint64_t io_win_addr
)
326 dev
= qdev_create(NULL
, spapr_phb_info
.name
);
329 qdev_prop_set_string(dev
, "busname", g_strdup(busname
));
331 qdev_prop_set_uint64(dev
, "buid", buid
);
332 qdev_prop_set_uint64(dev
, "mem_win_addr", mem_win_addr
);
333 qdev_prop_set_uint64(dev
, "mem_win_size", mem_win_size
);
334 qdev_prop_set_uint64(dev
, "io_win_addr", io_win_addr
);
336 qdev_init_nofail(dev
);
339 /* Macros to operate with address in OF binding to PCI */
340 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
341 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
342 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
343 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
344 #define b_ss(x) b_x((x), 24, 2) /* the space code */
345 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
346 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
347 #define b_fff(x) b_x((x), 8, 3) /* function number */
348 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
350 int spapr_populate_pci_devices(sPAPRPHBState
*phb
,
351 uint32_t xics_phandle
,
354 PCIBus
*bus
= phb
->host_state
.bus
;
357 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
363 } __attribute__((packed
)) ranges
[] = {
365 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
366 cpu_to_be64(phb
->io_win_addr
),
367 cpu_to_be64(memory_region_size(&phb
->iospace
)),
370 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
371 cpu_to_be64(phb
->mem_win_addr
),
372 cpu_to_be64(memory_region_size(&phb
->memwindow
)),
375 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
376 uint32_t interrupt_map_mask
[] = {
377 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0};
378 uint32_t interrupt_map
[bus
->nirq
][7];
380 /* Start populating the FDT */
381 sprintf(nodename
, "pci@%" PRIx64
, phb
->buid
);
382 bus_off
= fdt_add_subnode(fdt
, 0, nodename
);
395 /* Write PHB properties */
396 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
397 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
398 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#address-cells", 0x3));
399 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#size-cells", 0x2));
400 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
401 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
402 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
403 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof(ranges
)));
404 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
405 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
407 /* Build the interrupt-map, this must matches what is done
408 * in pci_spapr_map_irq
410 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
411 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
412 for (i
= 0; i
< 7; i
++) {
413 uint32_t *irqmap
= interrupt_map
[i
];
414 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
418 irqmap
[4] = cpu_to_be32(xics_phandle
);
419 irqmap
[5] = cpu_to_be32(phb
->lsi_table
[i
% SPAPR_PCI_NUM_LSI
].dt_irq
);
420 irqmap
[6] = cpu_to_be32(0x8);
422 /* Write interrupt map */
423 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
424 7 * sizeof(interrupt_map
[0])));
429 static void register_types(void)
431 type_register_static(&spapr_phb_info
);
433 type_init(register_types
)