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target/ppc: Implemented xvf16ger*
[qemu.git] / target / ppc / cpu.h
blob6d78078f379d038d6d6e64e617f3e0c383dbecb5
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu/int128.h"
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-defs.h"
26 #include "cpu-qom.h"
27 #include "qom/object.h"
28 #include "hw/registerfields.h"
29
30 #define TCG_GUEST_DEFAULT_MO 0
31
32 #define TARGET_PAGE_BITS_64K 16
33 #define TARGET_PAGE_BITS_16M 24
34
35 #if defined(TARGET_PPC64)
36 #define PPC_ELF_MACHINE EM_PPC64
37 #else
38 #define PPC_ELF_MACHINE EM_PPC
39 #endif
40
41 #define PPC_BIT_NR(bit) (63 - (bit))
42 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
43 #define PPC_BIT32(bit) (0x80000000 >> (bit))
44 #define PPC_BIT8(bit) (0x80 >> (bit))
45 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
46 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
47 PPC_BIT32(bs))
48 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
49
50 /*****************************************************************************/
51 /* Exception vectors definitions */
52 enum {
53 POWERPC_EXCP_NONE = -1,
54 /* The 64 first entries are used by the PowerPC embedded specification */
55 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
56 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
57 POWERPC_EXCP_DSI = 2, /* Data storage exception */
58 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
59 POWERPC_EXCP_EXTERNAL = 4, /* External input */
60 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
61 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
62 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
63 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
64 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
65 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
66 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
67 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
68 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
69 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
70 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
71 /* Vectors 16 to 31 are reserved */
72 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
73 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
74 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
75 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
76 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
77 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
78 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
79 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
80 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
81 /* Vectors 42 to 63 are reserved */
82 /* Exceptions defined in the PowerPC server specification */
83 POWERPC_EXCP_RESET = 64, /* System reset exception */
84 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
85 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
86 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
87 POWERPC_EXCP_TRACE = 68, /* Trace exception */
88 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
89 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
90 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
91 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
92 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
93 /* 40x specific exceptions */
94 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
95 /* Vectors 75-76 are 601 specific exceptions */
96 /* 602 specific exceptions */
97 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
98 /* 602/603 specific exceptions */
99 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
100 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
101 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
102 /* Exceptions available on most PowerPC */
103 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
104 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
105 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
106 POWERPC_EXCP_SMI = 84, /* System management interrupt */
107 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
108 /* 7xx/74xx specific exceptions */
109 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
110 /* 74xx specific exceptions */
111 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
112 /* 970FX specific exceptions */
113 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
114 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
115 /* Freescale embedded cores specific exceptions */
116 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
117 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
118 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
119 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
120 /* VSX Unavailable (Power ISA 2.06 and later) */
121 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
122 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
123 /* Additional ISA 2.06 and later server exceptions */
124 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
125 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
126 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
127 /* Server doorbell variants */
128 POWERPC_EXCP_SDOOR = 99,
129 POWERPC_EXCP_SDOOR_HV = 100,
130 /* ISA 3.00 additions */
131 POWERPC_EXCP_HVIRT = 101,
132 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
133 POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
134 POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
135 /* EOL */
136 POWERPC_EXCP_NB = 105,
137 /* QEMU exceptions: special cases we want to stop translation */
138 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
139 };
140
141 /* Exceptions error codes */
142 enum {
143 /* Exception subtypes for POWERPC_EXCP_ALIGN */
144 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
145 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
146 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
147 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
148 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
149 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
150 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
151 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
152 /* FP exceptions */
153 POWERPC_EXCP_FP = 0x10,
154 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
155 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
156 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
157 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
158 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
159 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
160 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
161 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
162 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
163 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
164 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
165 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
166 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
167 /* Invalid instruction */
168 POWERPC_EXCP_INVAL = 0x20,
169 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
170 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
171 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
172 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
173 /* Privileged instruction */
174 POWERPC_EXCP_PRIV = 0x30,
175 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
176 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
177 /* Trap */
178 POWERPC_EXCP_TRAP = 0x40,
179 };
180
181 #define PPC_INPUT(env) ((env)->bus_model)
182
183 /*****************************************************************************/
184 typedef struct opc_handler_t opc_handler_t;
185
186 /*****************************************************************************/
187 /* Types used to describe some PowerPC registers etc. */
188 typedef struct DisasContext DisasContext;
189 typedef struct ppc_spr_t ppc_spr_t;
190 typedef union ppc_tlb_t ppc_tlb_t;
191 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
192
193 /* SPR access micro-ops generations callbacks */
194 struct ppc_spr_t {
195 const char *name;
196 target_ulong default_value;
197 #ifndef CONFIG_USER_ONLY
198 unsigned int gdb_id;
199 #endif
200 #ifdef CONFIG_TCG
201 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
202 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
203 # ifndef CONFIG_USER_ONLY
204 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
205 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
206 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
207 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
208 # endif
209 #endif
210 #ifdef CONFIG_KVM
211 /*
212 * We (ab)use the fact that all the SPRs will have ids for the
213 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
214 * don't sync this
215 */
216 uint64_t one_reg_id;
217 #endif
218 };
219
220 /* VSX/Altivec registers (128 bits) */
221 typedef union _ppc_vsr_t {
222 uint8_t u8[16];
223 uint16_t u16[8];
224 uint32_t u32[4];
225 uint64_t u64[2];
226 int8_t s8[16];
227 int16_t s16[8];
228 int32_t s32[4];
229 int64_t s64[2];
230 float16 f16[8];
231 float32 f32[4];
232 float64 f64[2];
233 float128 f128;
234 #ifdef CONFIG_INT128
235 __uint128_t u128;
236 #endif
237 Int128 s128;
238 } ppc_vsr_t;
239
240 typedef ppc_vsr_t ppc_avr_t;
241 typedef ppc_vsr_t ppc_fprp_t;
242 typedef ppc_vsr_t ppc_acc_t;
243
244 #if !defined(CONFIG_USER_ONLY)
245 /* Software TLB cache */
246 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
247 struct ppc6xx_tlb_t {
248 target_ulong pte0;
249 target_ulong pte1;
250 target_ulong EPN;
251 };
252
253 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
254 struct ppcemb_tlb_t {
255 uint64_t RPN;
256 target_ulong EPN;
257 target_ulong PID;
258 target_ulong size;
259 uint32_t prot;
260 uint32_t attr; /* Storage attributes */
261 };
262
263 typedef struct ppcmas_tlb_t {
264 uint32_t mas8;
265 uint32_t mas1;
266 uint64_t mas2;
267 uint64_t mas7_3;
268 } ppcmas_tlb_t;
269
270 union ppc_tlb_t {
271 ppc6xx_tlb_t *tlb6;
272 ppcemb_tlb_t *tlbe;
273 ppcmas_tlb_t *tlbm;
274 };
275
276 /* possible TLB variants */
277 #define TLB_NONE 0
278 #define TLB_6XX 1
279 #define TLB_EMB 2
280 #define TLB_MAS 3
281 #endif
282
283 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
284
285 typedef struct ppc_slb_t ppc_slb_t;
286 struct ppc_slb_t {
287 uint64_t esid;
288 uint64_t vsid;
289 const PPCHash64SegmentPageSizes *sps;
290 };
291
292 #define MAX_SLB_ENTRIES 64
293 #define SEGMENT_SHIFT_256M 28
294 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
295
296 #define SEGMENT_SHIFT_1T 40
297 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
298
299 typedef struct ppc_v3_pate_t {
300 uint64_t dw0;
301 uint64_t dw1;
302 } ppc_v3_pate_t;
303
304 /* PMU related structs and defines */
305 #define PMU_COUNTERS_NUM 6
306 typedef enum {
307 PMU_EVENT_INVALID = 0,
308 PMU_EVENT_INACTIVE,
309 PMU_EVENT_CYCLES,
310 PMU_EVENT_INSTRUCTIONS,
311 PMU_EVENT_INSN_RUN_LATCH,
312 } PMUEventType;
313
314 /*****************************************************************************/
315 /* Machine state register bits definition */
316 #define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
317 #define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
318 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
319 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
320 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
321 #define MSR_TS1 PPC_BIT_NR(30)
322 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
323 #define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
324 #define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
325 #define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
326 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
327 #define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
328 #define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
329 #define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
330 #define MSR_S PPC_BIT_NR(41) /* Secure state */
331 #define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
332 #define MSR_POW PPC_BIT_NR(45) /* Power management */
333 #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
334 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
335 #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
336 #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
337 #define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
338 #define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
339 #define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
340 #define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
341 #define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
342 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
343 #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
344 #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
345 #define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
346 #define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
347 #define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
348 #define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
349 #define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
350 #define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
351 #define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
352 #define MSR_DR PPC_BIT_NR(59) /* Data relocate */
353 #define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
354 #define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
355 #define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
356 #define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
357 #define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
358 #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
359
360 FIELD(MSR, SF, MSR_SF, 1)
361 FIELD(MSR, TAG, MSR_TAG, 1)
362 FIELD(MSR, ISF, MSR_ISF, 1)
363 #if defined(TARGET_PPC64)
364 FIELD(MSR, HV, MSR_HV, 1)
365 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
366 #else
367 #define FIELD_EX64_HV(storage) 0
368 #endif
369 FIELD(MSR, TS0, MSR_TS0, 1)
370 FIELD(MSR, TS1, MSR_TS1, 1)
371 FIELD(MSR, TS, MSR_TS0, 2)
372 FIELD(MSR, TM, MSR_TM, 1)
373 FIELD(MSR, CM, MSR_CM, 1)
374 FIELD(MSR, ICM, MSR_ICM, 1)
375 FIELD(MSR, GS, MSR_GS, 1)
376 FIELD(MSR, UCLE, MSR_UCLE, 1)
377 FIELD(MSR, VR, MSR_VR, 1)
378 FIELD(MSR, SPE, MSR_SPE, 1)
379 FIELD(MSR, VSX, MSR_VSX, 1)
380 FIELD(MSR, S, MSR_S, 1)
381 FIELD(MSR, KEY, MSR_KEY, 1)
382 FIELD(MSR, POW, MSR_POW, 1)
383 FIELD(MSR, WE, MSR_WE, 1)
384 FIELD(MSR, TGPR, MSR_TGPR, 1)
385 FIELD(MSR, CE, MSR_CE, 1)
386 FIELD(MSR, ILE, MSR_ILE, 1)
387 FIELD(MSR, EE, MSR_EE, 1)
388 FIELD(MSR, PR, MSR_PR, 1)
389 FIELD(MSR, FP, MSR_FP, 1)
390 FIELD(MSR, ME, MSR_ME, 1)
391 FIELD(MSR, FE0, MSR_FE0, 1)
392 FIELD(MSR, SE, MSR_SE, 1)
393 FIELD(MSR, DWE, MSR_DWE, 1)
394 FIELD(MSR, UBLE, MSR_UBLE, 1)
395 FIELD(MSR, BE, MSR_BE, 1)
396 FIELD(MSR, DE, MSR_DE, 1)
397 FIELD(MSR, FE1, MSR_FE1, 1)
398 FIELD(MSR, AL, MSR_AL, 1)
399 FIELD(MSR, EP, MSR_EP, 1)
400 FIELD(MSR, IR, MSR_IR, 1)
401 FIELD(MSR, DR, MSR_DR, 1)
402 FIELD(MSR, IS, MSR_IS, 1)
403 FIELD(MSR, DS, MSR_DS, 1)
404 FIELD(MSR, PE, MSR_PE, 1)
405 FIELD(MSR, PX, MSR_PX, 1)
406 FIELD(MSR, PMM, MSR_PMM, 1)
407 FIELD(MSR, RI, MSR_RI, 1)
408 FIELD(MSR, LE, MSR_LE, 1)
409
410 /*
411 * FE0 and FE1 bits are not side-by-side
412 * so we can't combine them using FIELD()
413 */
414 #define FIELD_EX64_FE(msr) \
415 ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
416
417 /* PMU bits */
418 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
419 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
420 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
421 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
422 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
423 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
424 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
425 #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
426 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
427 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
428 #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
429 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
430 /* MMCR0 userspace r/w mask */
431 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
432 /* MMCR2 userspace r/w mask */
433 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
434 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
435 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
436 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
437 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
438 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
439 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
440 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
441
442 #define MMCR1_EVT_SIZE 8
443 /* extract64() does a right shift before extracting */
444 #define MMCR1_PMC1SEL_START 32
445 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
446 #define MMCR1_PMC2SEL_START 40
447 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
448 #define MMCR1_PMC3SEL_START 48
449 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
450 #define MMCR1_PMC4SEL_START 56
451 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
452
453 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
454 #define CTRL_RUN PPC_BIT(63)
455
456 /* EBB/BESCR bits */
457 /* Global Enable */
458 #define BESCR_GE PPC_BIT(0)
459 /* External Event-based Exception Enable */
460 #define BESCR_EE PPC_BIT(30)
461 /* Performance Monitor Event-based Exception Enable */
462 #define BESCR_PME PPC_BIT(31)
463 /* External Event-based Exception Occurred */
464 #define BESCR_EEO PPC_BIT(62)
465 /* Performance Monitor Event-based Exception Occurred */
466 #define BESCR_PMEO PPC_BIT(63)
467 #define BESCR_INVALID PPC_BITMASK(32, 33)
468
469 /* LPCR bits */
470 #define LPCR_VPM0 PPC_BIT(0)
471 #define LPCR_VPM1 PPC_BIT(1)
472 #define LPCR_ISL PPC_BIT(2)
473 #define LPCR_KBV PPC_BIT(3)
474 #define LPCR_DPFD_SHIFT (63 - 11)
475 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
476 #define LPCR_VRMASD_SHIFT (63 - 16)
477 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
478 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
479 #define LPCR_PECE_U_SHIFT (63 - 19)
480 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
481 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
482 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
483 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
484 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
485 #define LPCR_ILE PPC_BIT(38)
486 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
487 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
488 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
489 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
490 #define LPCR_HR PPC_BIT(43) /* Host Radix */
491 #define LPCR_ONL PPC_BIT(45)
492 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
493 #define LPCR_P7_PECE0 PPC_BIT(49)
494 #define LPCR_P7_PECE1 PPC_BIT(50)
495 #define LPCR_P7_PECE2 PPC_BIT(51)
496 #define LPCR_P8_PECE0 PPC_BIT(47)
497 #define LPCR_P8_PECE1 PPC_BIT(48)
498 #define LPCR_P8_PECE2 PPC_BIT(49)
499 #define LPCR_P8_PECE3 PPC_BIT(50)
500 #define LPCR_P8_PECE4 PPC_BIT(51)
501 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
502 #define LPCR_PECE_L_SHIFT (63 - 51)
503 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
504 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
505 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
506 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
507 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
508 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
509 #define LPCR_MER PPC_BIT(52)
510 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
511 #define LPCR_TC PPC_BIT(54)
512 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
513 #define LPCR_LPES0 PPC_BIT(60)
514 #define LPCR_LPES1 PPC_BIT(61)
515 #define LPCR_RMI PPC_BIT(62)
516 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
517 #define LPCR_HDICE PPC_BIT(63)
518
519 /* PSSCR bits */
520 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
521 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
522
523 /* HFSCR bits */
524 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
525 #define HFSCR_IC_MSGP 0xA
526
527 #define DBCR0_ICMP (1 << 27)
528 #define DBCR0_BRT (1 << 26)
529 #define DBSR_ICMP (1 << 27)
530 #define DBSR_BRT (1 << 26)
531
532 /* Hypervisor bit is more specific */
533 #if defined(TARGET_PPC64)
534 #define MSR_HVB (1ULL << MSR_HV)
535 #else
536 #define MSR_HVB (0ULL)
537 #endif
538
539 /* DSISR */
540 #define DSISR_NOPTE 0x40000000
541 /* Not permitted by access authority of encoded access authority */
542 #define DSISR_PROTFAULT 0x08000000
543 #define DSISR_ISSTORE 0x02000000
544 /* Not permitted by virtual page class key protection */
545 #define DSISR_AMR 0x00200000
546 /* Unsupported Radix Tree Configuration */
547 #define DSISR_R_BADCONFIG 0x00080000
548 #define DSISR_ATOMIC_RC 0x00040000
549 /* Unable to translate address of (guest) pde or process/page table entry */
550 #define DSISR_PRTABLE_FAULT 0x00020000
551
552 /* SRR1 error code fields */
553
554 #define SRR1_NOPTE DSISR_NOPTE
555 /* Not permitted due to no-execute or guard bit set */
556 #define SRR1_NOEXEC_GUARD 0x10000000
557 #define SRR1_PROTFAULT DSISR_PROTFAULT
558 #define SRR1_IAMR DSISR_AMR
559
560 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
561
562 #define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
563
564 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
565 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
566 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
567 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
568 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
569 #define SRR1_WAKERESET 0x00100000 /* System reset */
570 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
571 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
572
573 /* SRR1[46:47] power-saving exit mode */
574
575 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
576
577 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
578 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
579 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
580
581 /* Facility Status and Control (FSCR) bits */
582 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
583 #define FSCR_TAR (63 - 55) /* Target Address Register */
584 #define FSCR_SCV (63 - 51) /* System call vectored */
585 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
586 #define FSCR_IC_MASK (0xFFULL)
587 #define FSCR_IC_POS (63 - 7)
588 #define FSCR_IC_DSCR_SPR3 2
589 #define FSCR_IC_PMU 3
590 #define FSCR_IC_BHRB 4
591 #define FSCR_IC_TM 5
592 #define FSCR_IC_EBB 7
593 #define FSCR_IC_TAR 8
594 #define FSCR_IC_SCV 12
595
596 /* Exception state register bits definition */
597 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
598 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
599 #define ESR_PTR PPC_BIT(38) /* Trap */
600 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
601 #define ESR_ST PPC_BIT(40) /* Store Operation */
602 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
603 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
604 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
605 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
606 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
607 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
608 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
609 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
610 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
611 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
612 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
613
614 /* Transaction EXception And Summary Register bits */
615 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
616 #define TEXASR_DISALLOWED (63 - 8)
617 #define TEXASR_NESTING_OVERFLOW (63 - 9)
618 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
619 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
620 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
621 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
622 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
623 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
624 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
625 #define TEXASR_ABORT (63 - 31)
626 #define TEXASR_SUSPENDED (63 - 32)
627 #define TEXASR_PRIVILEGE_HV (63 - 34)
628 #define TEXASR_PRIVILEGE_PR (63 - 35)
629 #define TEXASR_FAILURE_SUMMARY (63 - 36)
630 #define TEXASR_TFIAR_EXACT (63 - 37)
631 #define TEXASR_ROT (63 - 38)
632 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
633
634 enum {
635 POWERPC_FLAG_NONE = 0x00000000,
636 /* Flag for MSR bit 25 signification (VRE/SPE) */
637 POWERPC_FLAG_SPE = 0x00000001,
638 POWERPC_FLAG_VRE = 0x00000002,
639 /* Flag for MSR bit 17 signification (TGPR/CE) */
640 POWERPC_FLAG_TGPR = 0x00000004,
641 POWERPC_FLAG_CE = 0x00000008,
642 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
643 POWERPC_FLAG_SE = 0x00000010,
644 POWERPC_FLAG_DWE = 0x00000020,
645 POWERPC_FLAG_UBLE = 0x00000040,
646 /* Flag for MSR bit 9 signification (BE/DE) */
647 POWERPC_FLAG_BE = 0x00000080,
648 POWERPC_FLAG_DE = 0x00000100,
649 /* Flag for MSR bit 2 signification (PX/PMM) */
650 POWERPC_FLAG_PX = 0x00000200,
651 POWERPC_FLAG_PMM = 0x00000400,
652 /* Flag for special features */
653 /* Decrementer clock */
654 POWERPC_FLAG_BUS_CLK = 0x00020000,
655 /* Has CFAR */
656 POWERPC_FLAG_CFAR = 0x00040000,
657 /* Has VSX */
658 POWERPC_FLAG_VSX = 0x00080000,
659 /* Has Transaction Memory (ISA 2.07) */
660 POWERPC_FLAG_TM = 0x00100000,
661 /* Has SCV (ISA 3.00) */
662 POWERPC_FLAG_SCV = 0x00200000,
663 };
664
665 /*
666 * Bits for env->hflags.
667 *
668 * Most of these bits overlap with corresponding bits in MSR,
669 * but some come from other sources. Those that do come from
670 * the MSR are validated in hreg_compute_hflags.
671 */
672 enum {
673 HFLAGS_LE = 0, /* MSR_LE */
674 HFLAGS_HV = 1, /* computed from MSR_HV and other state */
675 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
676 HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
677 HFLAGS_DR = 4, /* MSR_DR */
678 HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
679 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
680 HFLAGS_TM = 8, /* computed from MSR_TM */
681 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
682 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
683 HFLAGS_FP = 13, /* MSR_FP */
684 HFLAGS_PR = 14, /* MSR_PR */
685 HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
686 HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
687 HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */
688 HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
689 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
690
691 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
692 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
693 };
694
695 /*****************************************************************************/
696 /* Floating point status and control register */
697 #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
698 #define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
699 #define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
700 #define FPSCR_FX 31 /* Floating-point exception summary */
701 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
702 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
703 #define FPSCR_OX 28 /* Floating-point overflow exception */
704 #define FPSCR_UX 27 /* Floating-point underflow exception */
705 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
706 #define FPSCR_XX 25 /* Floating-point inexact exception */
707 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
708 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
709 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
710 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
711 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
712 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
713 #define FPSCR_FR 18 /* Floating-point fraction rounded */
714 #define FPSCR_FI 17 /* Floating-point fraction inexact */
715 #define FPSCR_C 16 /* Floating-point result class descriptor */
716 #define FPSCR_FL 15 /* Floating-point less than or negative */
717 #define FPSCR_FG 14 /* Floating-point greater than or negative */
718 #define FPSCR_FE 13 /* Floating-point equal or zero */
719 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
720 #define FPSCR_FPCC 12 /* Floating-point condition code */
721 #define FPSCR_FPRF 12 /* Floating-point result flags */
722 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
723 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
724 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
725 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
726 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
727 #define FPSCR_UE 5 /* Floating-point underflow exception enable */
728 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
729 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
730 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
731 #define FPSCR_RN1 1
732 #define FPSCR_RN0 0 /* Floating-point rounding control */
733 /* Invalid operation exception summary */
734 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
735 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
736 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
737 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
738 (1 << FPSCR_VXCVI))
739
740 FIELD(FPSCR, FI, FPSCR_FI, 1)
741
742 #define FP_DRN2 (1ull << FPSCR_DRN2)
743 #define FP_DRN1 (1ull << FPSCR_DRN1)
744 #define FP_DRN0 (1ull << FPSCR_DRN0)
745 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
746 #define FP_FX (1ull << FPSCR_FX)
747 #define FP_FEX (1ull << FPSCR_FEX)
748 #define FP_VX (1ull << FPSCR_VX)
749 #define FP_OX (1ull << FPSCR_OX)
750 #define FP_UX (1ull << FPSCR_UX)
751 #define FP_ZX (1ull << FPSCR_ZX)
752 #define FP_XX (1ull << FPSCR_XX)
753 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
754 #define FP_VXISI (1ull << FPSCR_VXISI)
755 #define FP_VXIDI (1ull << FPSCR_VXIDI)
756 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
757 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
758 #define FP_VXVC (1ull << FPSCR_VXVC)
759 #define FP_FR (1ull << FPSCR_FR)
760 #define FP_FI (1ull << FPSCR_FI)
761 #define FP_C (1ull << FPSCR_C)
762 #define FP_FL (1ull << FPSCR_FL)
763 #define FP_FG (1ull << FPSCR_FG)
764 #define FP_FE (1ull << FPSCR_FE)
765 #define FP_FU (1ull << FPSCR_FU)
766 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
767 #define FP_FPRF (FP_C | FP_FPCC)
768 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
769 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
770 #define FP_VXCVI (1ull << FPSCR_VXCVI)
771 #define FP_VE (1ull << FPSCR_VE)
772 #define FP_OE (1ull << FPSCR_OE)
773 #define FP_UE (1ull << FPSCR_UE)
774 #define FP_ZE (1ull << FPSCR_ZE)
775 #define FP_XE (1ull << FPSCR_XE)
776 #define FP_NI (1ull << FPSCR_NI)
777 #define FP_RN1 (1ull << FPSCR_RN1)
778 #define FP_RN0 (1ull << FPSCR_RN0)
779 #define FP_RN (FP_RN1 | FP_RN0)
780
781 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
782 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
783
784 /* the exception bits which can be cleared by mcrfs - includes FX */
785 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
786 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
787 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
788 FP_VXSQRT | FP_VXCVI)
789
790 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
791 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
792 FP_FEX | FP_VX | PPC_BIT(52)))
793
794 /*****************************************************************************/
795 /* Vector status and control register */
796 #define VSCR_NJ 16 /* Vector non-java */
797 #define VSCR_SAT 0 /* Vector saturation */
798
799 /*****************************************************************************/
800 /* BookE e500 MMU registers */
801
802 #define MAS0_NV_SHIFT 0
803 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
804
805 #define MAS0_WQ_SHIFT 12
806 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
807 /* Write TLB entry regardless of reservation */
808 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
809 /* Write TLB entry only already in use */
810 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
811 /* Clear TLB entry */
812 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
813
814 #define MAS0_HES_SHIFT 14
815 #define MAS0_HES (1 << MAS0_HES_SHIFT)
816
817 #define MAS0_ESEL_SHIFT 16
818 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
819
820 #define MAS0_TLBSEL_SHIFT 28
821 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
822 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
823 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
824 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
825 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
826
827 #define MAS0_ATSEL_SHIFT 31
828 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
829 #define MAS0_ATSEL_TLB 0
830 #define MAS0_ATSEL_LRAT MAS0_ATSEL
831
832 #define MAS1_TSIZE_SHIFT 7
833 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
834
835 #define MAS1_TS_SHIFT 12
836 #define MAS1_TS (1 << MAS1_TS_SHIFT)
837
838 #define MAS1_IND_SHIFT 13
839 #define MAS1_IND (1 << MAS1_IND_SHIFT)
840
841 #define MAS1_TID_SHIFT 16
842 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
843
844 #define MAS1_IPROT_SHIFT 30
845 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
846
847 #define MAS1_VALID_SHIFT 31
848 #define MAS1_VALID 0x80000000
849
850 #define MAS2_EPN_SHIFT 12
851 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
852
853 #define MAS2_ACM_SHIFT 6
854 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
855
856 #define MAS2_VLE_SHIFT 5
857 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
858
859 #define MAS2_W_SHIFT 4
860 #define MAS2_W (1 << MAS2_W_SHIFT)
861
862 #define MAS2_I_SHIFT 3
863 #define MAS2_I (1 << MAS2_I_SHIFT)
864
865 #define MAS2_M_SHIFT 2
866 #define MAS2_M (1 << MAS2_M_SHIFT)
867
868 #define MAS2_G_SHIFT 1
869 #define MAS2_G (1 << MAS2_G_SHIFT)
870
871 #define MAS2_E_SHIFT 0
872 #define MAS2_E (1 << MAS2_E_SHIFT)
873
874 #define MAS3_RPN_SHIFT 12
875 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
876
877 #define MAS3_U0 0x00000200
878 #define MAS3_U1 0x00000100
879 #define MAS3_U2 0x00000080
880 #define MAS3_U3 0x00000040
881 #define MAS3_UX 0x00000020
882 #define MAS3_SX 0x00000010
883 #define MAS3_UW 0x00000008
884 #define MAS3_SW 0x00000004
885 #define MAS3_UR 0x00000002
886 #define MAS3_SR 0x00000001
887 #define MAS3_SPSIZE_SHIFT 1
888 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
889
890 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
891 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
892 #define MAS4_TIDSELD_MASK 0x00030000
893 #define MAS4_TIDSELD_PID0 0x00000000
894 #define MAS4_TIDSELD_PID1 0x00010000
895 #define MAS4_TIDSELD_PID2 0x00020000
896 #define MAS4_TIDSELD_PIDZ 0x00030000
897 #define MAS4_INDD 0x00008000 /* Default IND */
898 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
899 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
900 #define MAS4_ACMD 0x00000040
901 #define MAS4_VLED 0x00000020
902 #define MAS4_WD 0x00000010
903 #define MAS4_ID 0x00000008
904 #define MAS4_MD 0x00000004
905 #define MAS4_GD 0x00000002
906 #define MAS4_ED 0x00000001
907 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
908 #define MAS4_WIMGED_SHIFT 0
909
910 #define MAS5_SGS 0x80000000
911 #define MAS5_SLPID_MASK 0x00000fff
912
913 #define MAS6_SPID0 0x3fff0000
914 #define MAS6_SPID1 0x00007ffe
915 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
916 #define MAS6_SAS 0x00000001
917 #define MAS6_SPID MAS6_SPID0
918 #define MAS6_SIND 0x00000002 /* Indirect page */
919 #define MAS6_SIND_SHIFT 1
920 #define MAS6_SPID_MASK 0x3fff0000
921 #define MAS6_SPID_SHIFT 16
922 #define MAS6_ISIZE_MASK 0x00000f80
923 #define MAS6_ISIZE_SHIFT 7
924
925 #define MAS7_RPN 0xffffffff
926
927 #define MAS8_TGS 0x80000000
928 #define MAS8_VF 0x40000000
929 #define MAS8_TLBPID 0x00000fff
930
931 /* Bit definitions for MMUCFG */
932 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
933 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
934 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
935 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
936 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
937 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
938 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
939 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
940 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
941
942 /* Bit definitions for MMUCSR0 */
943 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
944 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
945 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
946 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
947 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
948 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
949 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
950 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
951 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
952 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
953
954 /* TLBnCFG encoding */
955 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
956 #define TLBnCFG_HES 0x00002000 /* HW select supported */
957 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
958 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
959 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
960 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
961 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
962 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
963 #define TLBnCFG_MINSIZE_SHIFT 20
964 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
965 #define TLBnCFG_MAXSIZE_SHIFT 16
966 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
967 #define TLBnCFG_ASSOC_SHIFT 24
968
969 /* TLBnPS encoding */
970 #define TLBnPS_4K 0x00000004
971 #define TLBnPS_8K 0x00000008
972 #define TLBnPS_16K 0x00000010
973 #define TLBnPS_32K 0x00000020
974 #define TLBnPS_64K 0x00000040
975 #define TLBnPS_128K 0x00000080
976 #define TLBnPS_256K 0x00000100
977 #define TLBnPS_512K 0x00000200
978 #define TLBnPS_1M 0x00000400
979 #define TLBnPS_2M 0x00000800
980 #define TLBnPS_4M 0x00001000
981 #define TLBnPS_8M 0x00002000
982 #define TLBnPS_16M 0x00004000
983 #define TLBnPS_32M 0x00008000
984 #define TLBnPS_64M 0x00010000
985 #define TLBnPS_128M 0x00020000
986 #define TLBnPS_256M 0x00040000
987 #define TLBnPS_512M 0x00080000
988 #define TLBnPS_1G 0x00100000
989 #define TLBnPS_2G 0x00200000
990 #define TLBnPS_4G 0x00400000
991 #define TLBnPS_8G 0x00800000
992 #define TLBnPS_16G 0x01000000
993 #define TLBnPS_32G 0x02000000
994 #define TLBnPS_64G 0x04000000
995 #define TLBnPS_128G 0x08000000
996 #define TLBnPS_256G 0x10000000
997
998 /* tlbilx action encoding */
999 #define TLBILX_T_ALL 0
1000 #define TLBILX_T_TID 1
1001 #define TLBILX_T_FULLMATCH 3
1002 #define TLBILX_T_CLASS0 4
1003 #define TLBILX_T_CLASS1 5
1004 #define TLBILX_T_CLASS2 6
1005 #define TLBILX_T_CLASS3 7
1006
1007 /* BookE 2.06 helper defines */
1008
1009 #define BOOKE206_FLUSH_TLB0 (1 << 0)
1010 #define BOOKE206_FLUSH_TLB1 (1 << 1)
1011 #define BOOKE206_FLUSH_TLB2 (1 << 2)
1012 #define BOOKE206_FLUSH_TLB3 (1 << 3)
1013
1014 /* number of possible TLBs */
1015 #define BOOKE206_MAX_TLBN 4
1016
1017 #define EPID_EPID_SHIFT 0x0
1018 #define EPID_EPID 0xFF
1019 #define EPID_ELPID_SHIFT 0x10
1020 #define EPID_ELPID 0x3F0000
1021 #define EPID_EGS 0x20000000
1022 #define EPID_EGS_SHIFT 29
1023 #define EPID_EAS 0x40000000
1024 #define EPID_EAS_SHIFT 30
1025 #define EPID_EPR 0x80000000
1026 #define EPID_EPR_SHIFT 31
1027 /* We don't support EGS and ELPID */
1028 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1029
1030 /*****************************************************************************/
1031 /* Server and Embedded Processor Control */
1032
1033 #define DBELL_TYPE_SHIFT 27
1034 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1035 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1036 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1037 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1038 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1039 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1040
1041 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1042
1043 #define DBELL_BRDCAST PPC_BIT(37)
1044 #define DBELL_LPIDTAG_SHIFT 14
1045 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1046 #define DBELL_PIRTAG_MASK 0x3fff
1047
1048 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1049
1050 #define PPC_PAGE_SIZES_MAX_SZ 8
1051
1052 struct ppc_radix_page_info {
1053 uint32_t count;
1054 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1055 };
1056
1057 /*****************************************************************************/
1058 /* The whole PowerPC CPU context */
1059
1060 /*
1061 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1062 * + real/paged mode combinations. The other two modes are for
1063 * external PID load/store.
1064 */
1065 #define PPC_TLB_EPID_LOAD 8
1066 #define PPC_TLB_EPID_STORE 9
1067
1068 #define PPC_CPU_OPCODES_LEN 0x40
1069 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1070
1071 struct CPUArchState {
1072 /* Most commonly used resources during translated code execution first */
1073 target_ulong gpr[32]; /* general purpose registers */
1074 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1075 target_ulong lr;
1076 target_ulong ctr;
1077 uint32_t crf[8]; /* condition register */
1078 #if defined(TARGET_PPC64)
1079 target_ulong cfar;
1080 #endif
1081 target_ulong xer; /* XER (with SO, OV, CA split out) */
1082 target_ulong so;
1083 target_ulong ov;
1084 target_ulong ca;
1085 target_ulong ov32;
1086 target_ulong ca32;
1087
1088 target_ulong reserve_addr; /* Reservation address */
1089 target_ulong reserve_val; /* Reservation value */
1090 target_ulong reserve_val2;
1091
1092 /* These are used in supervisor mode only */
1093 target_ulong msr; /* machine state register */
1094 target_ulong tgpr[4]; /* temporary general purpose registers, */
1095 /* used to speed-up TLB assist handlers */
1096
1097 target_ulong nip; /* next instruction pointer */
1098 uint64_t retxh; /* high part of 128-bit helper return */
1099
1100 /* when a memory exception occurs, the access type is stored here */
1101 int access_type;
1102
1103 #if !defined(CONFIG_USER_ONLY)
1104 /* MMU context, only relevant for full system emulation */
1105 #if defined(TARGET_PPC64)
1106 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1107 #endif
1108 target_ulong sr[32]; /* segment registers */
1109 uint32_t nb_BATs; /* number of BATs */
1110 target_ulong DBAT[2][8];
1111 target_ulong IBAT[2][8];
1112 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1113 int32_t nb_tlb; /* Total number of TLB */
1114 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1115 int nb_ways; /* Number of ways in the TLB set */
1116 int last_way; /* Last used way used to allocate TLB in a LRU way */
1117 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1118 int nb_pids; /* Number of available PID registers */
1119 int tlb_type; /* Type of TLB we're dealing with */
1120 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1121 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1122 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1123 uint32_t tlb_need_flush; /* Delayed flush needed */
1124 #define TLB_NEED_LOCAL_FLUSH 0x1
1125 #define TLB_NEED_GLOBAL_FLUSH 0x2
1126 #endif
1127
1128 /* Other registers */
1129 target_ulong spr[1024]; /* special purpose registers */
1130 ppc_spr_t spr_cb[1024];
1131 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1132 uint8_t pmc_ins_cnt;
1133 uint8_t pmc_cyc_cnt;
1134 /* Vector status and control register, minus VSCR_SAT */
1135 uint32_t vscr;
1136 /* VSX registers (including FP and AVR) */
1137 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1138 /* Non-zero if and only if VSCR_SAT should be set */
1139 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1140 /* SPE registers */
1141 uint64_t spe_acc;
1142 uint32_t spe_fscr;
1143 /* SPE and Altivec share status as they'll never be used simultaneously */
1144 float_status vec_status;
1145 float_status fp_status; /* Floating point execution context */
1146 target_ulong fpscr; /* Floating point status and control register */
1147
1148 /* Internal devices resources */
1149 ppc_tb_t *tb_env; /* Time base and decrementer */
1150 ppc_dcr_t *dcr_env; /* Device control registers */
1151
1152 int dcache_line_size;
1153 int icache_line_size;
1154
1155 /* These resources are used during exception processing */
1156 /* CPU model definition */
1157 target_ulong msr_mask;
1158 powerpc_mmu_t mmu_model;
1159 powerpc_excp_t excp_model;
1160 powerpc_input_t bus_model;
1161 int bfd_mach;
1162 uint32_t flags;
1163 uint64_t insns_flags;
1164 uint64_t insns_flags2;
1165
1166 int error_code;
1167 uint32_t pending_interrupts;
1168 #if !defined(CONFIG_USER_ONLY)
1169 /*
1170 * This is the IRQ controller, which is implementation dependent and only
1171 * relevant when emulating a complete machine. Note that this isn't used
1172 * by recent Book3s compatible CPUs (POWER7 and newer).
1173 */
1174 uint32_t irq_input_state;
1175 void **irq_inputs;
1176
1177 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1178 target_ulong excp_prefix;
1179 target_ulong ivor_mask;
1180 target_ulong ivpr_mask;
1181 target_ulong hreset_vector;
1182 hwaddr mpic_iack;
1183 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1184 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1185 /* instructions and SPRs are diallowed if MSR:HV is 0 */
1186 /*
1187 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1188 * special way (such as routing some resume causes to 0x100, i.e. sreset).
1189 */
1190 bool resume_as_sreset;
1191 #endif
1192
1193 /* These resources are used only in TCG */
1194 uint32_t hflags;
1195 target_ulong hflags_compat_nmsr; /* for migration compatibility */
1196
1197 /* Power management */
1198 int (*check_pow)(CPUPPCState *env);
1199
1200 #if !defined(CONFIG_USER_ONLY)
1201 void *load_info; /* holds boot loading state */
1202 #endif
1203
1204 /* booke timers */
1205
1206 /*
1207 * Specifies bit locations of the Time Base used to signal a fixed timer
1208 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1209 *
1210 * 0 selects the least significant bit, 63 selects the most significant bit
1211 */
1212 uint8_t fit_period[4];
1213 uint8_t wdt_period[4];
1214
1215 /* Transactional memory state */
1216 target_ulong tm_gpr[32];
1217 ppc_avr_t tm_vsr[64];
1218 uint64_t tm_cr;
1219 uint64_t tm_lr;
1220 uint64_t tm_ctr;
1221 uint64_t tm_fpscr;
1222 uint64_t tm_amr;
1223 uint64_t tm_ppr;
1224 uint64_t tm_vrsave;
1225 uint32_t tm_vscr;
1226 uint64_t tm_dscr;
1227 uint64_t tm_tar;
1228
1229 /*
1230 * Timers used to fire performance monitor alerts
1231 * when counting cycles.
1232 */
1233 QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1234
1235 /*
1236 * PMU base time value used by the PMU to calculate
1237 * running cycles.
1238 */
1239 uint64_t pmu_base_time;
1240 };
1241
1242 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1243 do { \
1244 env->fit_period[0] = (a_); \
1245 env->fit_period[1] = (b_); \
1246 env->fit_period[2] = (c_); \
1247 env->fit_period[3] = (d_); \
1248 } while (0)
1249
1250 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1251 do { \
1252 env->wdt_period[0] = (a_); \
1253 env->wdt_period[1] = (b_); \
1254 env->wdt_period[2] = (c_); \
1255 env->wdt_period[3] = (d_); \
1256 } while (0)
1257
1258 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1259 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1260
1261 /**
1262 * PowerPCCPU:
1263 * @env: #CPUPPCState
1264 * @vcpu_id: vCPU identifier given to KVM
1265 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1266 *
1267 * A PowerPC CPU.
1268 */
1269 struct ArchCPU {
1270 /*< private >*/
1271 CPUState parent_obj;
1272 /*< public >*/
1273
1274 CPUNegativeOffsetState neg;
1275 CPUPPCState env;
1276
1277 int vcpu_id;
1278 uint32_t compat_pvr;
1279 PPCVirtualHypervisor *vhyp;
1280 void *machine_data;
1281 int32_t node_id; /* NUMA node this CPU belongs to */
1282 PPCHash64Options *hash64_opts;
1283
1284 /* Those resources are used only during code translation */
1285 /* opcode handlers */
1286 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1287
1288 /* Fields related to migration compatibility hacks */
1289 bool pre_2_8_migration;
1290 target_ulong mig_msr_mask;
1291 uint64_t mig_insns_flags;
1292 uint64_t mig_insns_flags2;
1293 uint32_t mig_nb_BATs;
1294 bool pre_2_10_migration;
1295 bool pre_3_0_migration;
1296 int32_t mig_slb_nr;
1297 };
1298
1299
1300 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1301 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1302 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1303
1304 #ifndef CONFIG_USER_ONLY
1305 struct PPCVirtualHypervisorClass {
1306 InterfaceClass parent;
1307 bool (*cpu_in_nested)(PowerPCCPU *cpu);
1308 void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1309 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1310 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1311 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1312 hwaddr ptex, int n);
1313 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1314 const ppc_hash_pte64_t *hptes,
1315 hwaddr ptex, int n);
1316 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1317 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1318 bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1319 target_ulong lpid, ppc_v3_pate_t *entry);
1320 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1321 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1322 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1323 };
1324
1325 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1326 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1327 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1328
1329 static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1330 {
1331 return PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp)->cpu_in_nested(cpu);
1332 }
1333 #endif /* CONFIG_USER_ONLY */
1334
1335 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1336 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1337 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1338 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1339 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1340 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1341 #ifndef CONFIG_USER_ONLY
1342 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1343 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1344 #endif
1345 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1346 int cpuid, void *opaque);
1347 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1348 int cpuid, void *opaque);
1349 #ifndef CONFIG_USER_ONLY
1350 void ppc_cpu_do_interrupt(CPUState *cpu);
1351 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1352 void ppc_cpu_do_system_reset(CPUState *cs);
1353 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1354 extern const VMStateDescription vmstate_ppc_cpu;
1355 #endif
1356
1357 /*****************************************************************************/
1358 void ppc_translate_init(void);
1359
1360 #if !defined(CONFIG_USER_ONLY)
1361 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1362 #endif /* !defined(CONFIG_USER_ONLY) */
1363 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1364 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1365
1366 void ppc_cpu_list(void);
1367
1368 /* Time-base and decrementer management */
1369 #ifndef NO_CPU_IO_DEFS
1370 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1371 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1372 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1373 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1374 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1375 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1376 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1377 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1378 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1379 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1380 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1381 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1382 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1383 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1384 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1385 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1386 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1387 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1388 #if !defined(CONFIG_USER_ONLY)
1389 target_ulong load_40x_pit(CPUPPCState *env);
1390 void store_40x_pit(CPUPPCState *env, target_ulong val);
1391 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1392 void store_40x_sler(CPUPPCState *env, uint32_t val);
1393 void store_40x_tcr(CPUPPCState *env, target_ulong val);
1394 void store_40x_tsr(CPUPPCState *env, target_ulong val);
1395 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1396 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1397 void ppc_tlb_invalidate_all(CPUPPCState *env);
1398 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1399 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1400 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1401 hwaddr *raddrp, target_ulong address,
1402 uint32_t pid);
1403 int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
1404 hwaddr *raddrp,
1405 target_ulong address, uint32_t pid, int ext,
1406 int i);
1407 hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
1408 ppcmas_tlb_t *tlb);
1409 #endif
1410 #endif
1411
1412 void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1413 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1414 const char *caller, uint32_t cause);
1415
1416 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1417 {
1418 uint64_t gprv;
1419
1420 gprv = env->gpr[gprn];
1421 if (env->flags & POWERPC_FLAG_SPE) {
1422 /*
1423 * If the CPU implements the SPE extension, we have to get the
1424 * high bits of the GPR from the gprh storage area
1425 */
1426 gprv &= 0xFFFFFFFFULL;
1427 gprv |= (uint64_t)env->gprh[gprn] << 32;
1428 }
1429
1430 return gprv;
1431 }
1432
1433 /* Device control registers */
1434 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1435 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1436
1437 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1438 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1439 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1440
1441 #define cpu_list ppc_cpu_list
1442
1443 /* MMU modes definitions */
1444 #define MMU_USER_IDX 0
1445 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1446 {
1447 #ifdef CONFIG_USER_ONLY
1448 return MMU_USER_IDX;
1449 #else
1450 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1451 #endif
1452 }
1453
1454 /* Compatibility modes */
1455 #if defined(TARGET_PPC64)
1456 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1457 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1458 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1459 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1460
1461 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1462
1463 #if !defined(CONFIG_USER_ONLY)
1464 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1465 #endif
1466 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1467 void ppc_compat_add_property(Object *obj, const char *name,
1468 uint32_t *compat_pvr, const char *basedesc);
1469 #endif /* defined(TARGET_PPC64) */
1470
1471 #include "exec/cpu-all.h"
1472
1473 /*****************************************************************************/
1474 /* CRF definitions */
1475 #define CRF_LT_BIT 3
1476 #define CRF_GT_BIT 2
1477 #define CRF_EQ_BIT 1
1478 #define CRF_SO_BIT 0
1479 #define CRF_LT (1 << CRF_LT_BIT)
1480 #define CRF_GT (1 << CRF_GT_BIT)
1481 #define CRF_EQ (1 << CRF_EQ_BIT)
1482 #define CRF_SO (1 << CRF_SO_BIT)
1483 /* For SPE extensions */
1484 #define CRF_CH (1 << CRF_LT_BIT)
1485 #define CRF_CL (1 << CRF_GT_BIT)
1486 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1487 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1488
1489 /* XER definitions */
1490 #define XER_SO 31
1491 #define XER_OV 30
1492 #define XER_CA 29
1493 #define XER_OV32 19
1494 #define XER_CA32 18
1495 #define XER_CMP 8
1496 #define XER_BC 0
1497 #define xer_so (env->so)
1498 #define xer_ov (env->ov)
1499 #define xer_ca (env->ca)
1500 #define xer_ov32 (env->ov)
1501 #define xer_ca32 (env->ca)
1502 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1503 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1504
1505 /* SPR definitions */
1506 #define SPR_MQ (0x000)
1507 #define SPR_XER (0x001)
1508 #define SPR_LR (0x008)
1509 #define SPR_CTR (0x009)
1510 #define SPR_UAMR (0x00D)
1511 #define SPR_DSCR (0x011)
1512 #define SPR_DSISR (0x012)
1513 #define SPR_DAR (0x013)
1514 #define SPR_DECR (0x016)
1515 #define SPR_SDR1 (0x019)
1516 #define SPR_SRR0 (0x01A)
1517 #define SPR_SRR1 (0x01B)
1518 #define SPR_CFAR (0x01C)
1519 #define SPR_AMR (0x01D)
1520 #define SPR_ACOP (0x01F)
1521 #define SPR_BOOKE_PID (0x030)
1522 #define SPR_BOOKS_PID (0x030)
1523 #define SPR_BOOKE_DECAR (0x036)
1524 #define SPR_BOOKE_CSRR0 (0x03A)
1525 #define SPR_BOOKE_CSRR1 (0x03B)
1526 #define SPR_BOOKE_DEAR (0x03D)
1527 #define SPR_IAMR (0x03D)
1528 #define SPR_BOOKE_ESR (0x03E)
1529 #define SPR_BOOKE_IVPR (0x03F)
1530 #define SPR_MPC_EIE (0x050)
1531 #define SPR_MPC_EID (0x051)
1532 #define SPR_MPC_NRI (0x052)
1533 #define SPR_TFHAR (0x080)
1534 #define SPR_TFIAR (0x081)
1535 #define SPR_TEXASR (0x082)
1536 #define SPR_TEXASRU (0x083)
1537 #define SPR_UCTRL (0x088)
1538 #define SPR_TIDR (0x090)
1539 #define SPR_MPC_CMPA (0x090)
1540 #define SPR_MPC_CMPB (0x091)
1541 #define SPR_MPC_CMPC (0x092)
1542 #define SPR_MPC_CMPD (0x093)
1543 #define SPR_MPC_ECR (0x094)
1544 #define SPR_MPC_DER (0x095)
1545 #define SPR_MPC_COUNTA (0x096)
1546 #define SPR_MPC_COUNTB (0x097)
1547 #define SPR_CTRL (0x098)
1548 #define SPR_MPC_CMPE (0x098)
1549 #define SPR_MPC_CMPF (0x099)
1550 #define SPR_FSCR (0x099)
1551 #define SPR_MPC_CMPG (0x09A)
1552 #define SPR_MPC_CMPH (0x09B)
1553 #define SPR_MPC_LCTRL1 (0x09C)
1554 #define SPR_MPC_LCTRL2 (0x09D)
1555 #define SPR_UAMOR (0x09D)
1556 #define SPR_MPC_ICTRL (0x09E)
1557 #define SPR_MPC_BAR (0x09F)
1558 #define SPR_PSPB (0x09F)
1559 #define SPR_DPDES (0x0B0)
1560 #define SPR_DAWR0 (0x0B4)
1561 #define SPR_RPR (0x0BA)
1562 #define SPR_CIABR (0x0BB)
1563 #define SPR_DAWRX0 (0x0BC)
1564 #define SPR_HFSCR (0x0BE)
1565 #define SPR_VRSAVE (0x100)
1566 #define SPR_USPRG0 (0x100)
1567 #define SPR_USPRG1 (0x101)
1568 #define SPR_USPRG2 (0x102)
1569 #define SPR_USPRG3 (0x103)
1570 #define SPR_USPRG4 (0x104)
1571 #define SPR_USPRG5 (0x105)
1572 #define SPR_USPRG6 (0x106)
1573 #define SPR_USPRG7 (0x107)
1574 #define SPR_VTBL (0x10C)
1575 #define SPR_VTBU (0x10D)
1576 #define SPR_SPRG0 (0x110)
1577 #define SPR_SPRG1 (0x111)
1578 #define SPR_SPRG2 (0x112)
1579 #define SPR_SPRG3 (0x113)
1580 #define SPR_SPRG4 (0x114)
1581 #define SPR_SCOMC (0x114)
1582 #define SPR_SPRG5 (0x115)
1583 #define SPR_SCOMD (0x115)
1584 #define SPR_SPRG6 (0x116)
1585 #define SPR_SPRG7 (0x117)
1586 #define SPR_ASR (0x118)
1587 #define SPR_EAR (0x11A)
1588 #define SPR_TBL (0x11C)
1589 #define SPR_TBU (0x11D)
1590 #define SPR_TBU40 (0x11E)
1591 #define SPR_SVR (0x11E)
1592 #define SPR_BOOKE_PIR (0x11E)
1593 #define SPR_PVR (0x11F)
1594 #define SPR_HSPRG0 (0x130)
1595 #define SPR_BOOKE_DBSR (0x130)
1596 #define SPR_HSPRG1 (0x131)
1597 #define SPR_HDSISR (0x132)
1598 #define SPR_HDAR (0x133)
1599 #define SPR_BOOKE_EPCR (0x133)
1600 #define SPR_SPURR (0x134)
1601 #define SPR_BOOKE_DBCR0 (0x134)
1602 #define SPR_IBCR (0x135)
1603 #define SPR_PURR (0x135)
1604 #define SPR_BOOKE_DBCR1 (0x135)
1605 #define SPR_DBCR (0x136)
1606 #define SPR_HDEC (0x136)
1607 #define SPR_BOOKE_DBCR2 (0x136)
1608 #define SPR_HIOR (0x137)
1609 #define SPR_MBAR (0x137)
1610 #define SPR_RMOR (0x138)
1611 #define SPR_BOOKE_IAC1 (0x138)
1612 #define SPR_HRMOR (0x139)
1613 #define SPR_BOOKE_IAC2 (0x139)
1614 #define SPR_HSRR0 (0x13A)
1615 #define SPR_BOOKE_IAC3 (0x13A)
1616 #define SPR_HSRR1 (0x13B)
1617 #define SPR_BOOKE_IAC4 (0x13B)
1618 #define SPR_BOOKE_DAC1 (0x13C)
1619 #define SPR_MMCRH (0x13C)
1620 #define SPR_DABR2 (0x13D)
1621 #define SPR_BOOKE_DAC2 (0x13D)
1622 #define SPR_TFMR (0x13D)
1623 #define SPR_BOOKE_DVC1 (0x13E)
1624 #define SPR_LPCR (0x13E)
1625 #define SPR_BOOKE_DVC2 (0x13F)
1626 #define SPR_LPIDR (0x13F)
1627 #define SPR_BOOKE_TSR (0x150)
1628 #define SPR_HMER (0x150)
1629 #define SPR_HMEER (0x151)
1630 #define SPR_PCR (0x152)
1631 #define SPR_BOOKE_LPIDR (0x152)
1632 #define SPR_BOOKE_TCR (0x154)
1633 #define SPR_BOOKE_TLB0PS (0x158)
1634 #define SPR_BOOKE_TLB1PS (0x159)
1635 #define SPR_BOOKE_TLB2PS (0x15A)
1636 #define SPR_BOOKE_TLB3PS (0x15B)
1637 #define SPR_AMOR (0x15D)
1638 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1639 #define SPR_BOOKE_IVOR0 (0x190)
1640 #define SPR_BOOKE_IVOR1 (0x191)
1641 #define SPR_BOOKE_IVOR2 (0x192)
1642 #define SPR_BOOKE_IVOR3 (0x193)
1643 #define SPR_BOOKE_IVOR4 (0x194)
1644 #define SPR_BOOKE_IVOR5 (0x195)
1645 #define SPR_BOOKE_IVOR6 (0x196)
1646 #define SPR_BOOKE_IVOR7 (0x197)
1647 #define SPR_BOOKE_IVOR8 (0x198)
1648 #define SPR_BOOKE_IVOR9 (0x199)
1649 #define SPR_BOOKE_IVOR10 (0x19A)
1650 #define SPR_BOOKE_IVOR11 (0x19B)
1651 #define SPR_BOOKE_IVOR12 (0x19C)
1652 #define SPR_BOOKE_IVOR13 (0x19D)
1653 #define SPR_BOOKE_IVOR14 (0x19E)
1654 #define SPR_BOOKE_IVOR15 (0x19F)
1655 #define SPR_BOOKE_IVOR38 (0x1B0)
1656 #define SPR_BOOKE_IVOR39 (0x1B1)
1657 #define SPR_BOOKE_IVOR40 (0x1B2)
1658 #define SPR_BOOKE_IVOR41 (0x1B3)
1659 #define SPR_BOOKE_IVOR42 (0x1B4)
1660 #define SPR_BOOKE_GIVOR2 (0x1B8)
1661 #define SPR_BOOKE_GIVOR3 (0x1B9)
1662 #define SPR_BOOKE_GIVOR4 (0x1BA)
1663 #define SPR_BOOKE_GIVOR8 (0x1BB)
1664 #define SPR_BOOKE_GIVOR13 (0x1BC)
1665 #define SPR_BOOKE_GIVOR14 (0x1BD)
1666 #define SPR_TIR (0x1BE)
1667 #define SPR_PTCR (0x1D0)
1668 #define SPR_BOOKE_SPEFSCR (0x200)
1669 #define SPR_Exxx_BBEAR (0x201)
1670 #define SPR_Exxx_BBTAR (0x202)
1671 #define SPR_Exxx_L1CFG0 (0x203)
1672 #define SPR_Exxx_L1CFG1 (0x204)
1673 #define SPR_Exxx_NPIDR (0x205)
1674 #define SPR_ATBL (0x20E)
1675 #define SPR_ATBU (0x20F)
1676 #define SPR_IBAT0U (0x210)
1677 #define SPR_BOOKE_IVOR32 (0x210)
1678 #define SPR_RCPU_MI_GRA (0x210)
1679 #define SPR_IBAT0L (0x211)
1680 #define SPR_BOOKE_IVOR33 (0x211)
1681 #define SPR_IBAT1U (0x212)
1682 #define SPR_BOOKE_IVOR34 (0x212)
1683 #define SPR_IBAT1L (0x213)
1684 #define SPR_BOOKE_IVOR35 (0x213)
1685 #define SPR_IBAT2U (0x214)
1686 #define SPR_BOOKE_IVOR36 (0x214)
1687 #define SPR_IBAT2L (0x215)
1688 #define SPR_BOOKE_IVOR37 (0x215)
1689 #define SPR_IBAT3U (0x216)
1690 #define SPR_IBAT3L (0x217)
1691 #define SPR_DBAT0U (0x218)
1692 #define SPR_RCPU_L2U_GRA (0x218)
1693 #define SPR_DBAT0L (0x219)
1694 #define SPR_DBAT1U (0x21A)
1695 #define SPR_DBAT1L (0x21B)
1696 #define SPR_DBAT2U (0x21C)
1697 #define SPR_DBAT2L (0x21D)
1698 #define SPR_DBAT3U (0x21E)
1699 #define SPR_DBAT3L (0x21F)
1700 #define SPR_IBAT4U (0x230)
1701 #define SPR_RPCU_BBCMCR (0x230)
1702 #define SPR_MPC_IC_CST (0x230)
1703 #define SPR_Exxx_CTXCR (0x230)
1704 #define SPR_IBAT4L (0x231)
1705 #define SPR_MPC_IC_ADR (0x231)
1706 #define SPR_Exxx_DBCR3 (0x231)
1707 #define SPR_IBAT5U (0x232)
1708 #define SPR_MPC_IC_DAT (0x232)
1709 #define SPR_Exxx_DBCNT (0x232)
1710 #define SPR_IBAT5L (0x233)
1711 #define SPR_IBAT6U (0x234)
1712 #define SPR_IBAT6L (0x235)
1713 #define SPR_IBAT7U (0x236)
1714 #define SPR_IBAT7L (0x237)
1715 #define SPR_DBAT4U (0x238)
1716 #define SPR_RCPU_L2U_MCR (0x238)
1717 #define SPR_MPC_DC_CST (0x238)
1718 #define SPR_Exxx_ALTCTXCR (0x238)
1719 #define SPR_DBAT4L (0x239)
1720 #define SPR_MPC_DC_ADR (0x239)
1721 #define SPR_DBAT5U (0x23A)
1722 #define SPR_BOOKE_MCSRR0 (0x23A)
1723 #define SPR_MPC_DC_DAT (0x23A)
1724 #define SPR_DBAT5L (0x23B)
1725 #define SPR_BOOKE_MCSRR1 (0x23B)
1726 #define SPR_DBAT6U (0x23C)
1727 #define SPR_BOOKE_MCSR (0x23C)
1728 #define SPR_DBAT6L (0x23D)
1729 #define SPR_Exxx_MCAR (0x23D)
1730 #define SPR_DBAT7U (0x23E)
1731 #define SPR_BOOKE_DSRR0 (0x23E)
1732 #define SPR_DBAT7L (0x23F)
1733 #define SPR_BOOKE_DSRR1 (0x23F)
1734 #define SPR_BOOKE_SPRG8 (0x25C)
1735 #define SPR_BOOKE_SPRG9 (0x25D)
1736 #define SPR_BOOKE_MAS0 (0x270)
1737 #define SPR_BOOKE_MAS1 (0x271)
1738 #define SPR_BOOKE_MAS2 (0x272)
1739 #define SPR_BOOKE_MAS3 (0x273)
1740 #define SPR_BOOKE_MAS4 (0x274)
1741 #define SPR_BOOKE_MAS5 (0x275)
1742 #define SPR_BOOKE_MAS6 (0x276)
1743 #define SPR_BOOKE_PID1 (0x279)
1744 #define SPR_BOOKE_PID2 (0x27A)
1745 #define SPR_MPC_DPDR (0x280)
1746 #define SPR_MPC_IMMR (0x288)
1747 #define SPR_BOOKE_TLB0CFG (0x2B0)
1748 #define SPR_BOOKE_TLB1CFG (0x2B1)
1749 #define SPR_BOOKE_TLB2CFG (0x2B2)
1750 #define SPR_BOOKE_TLB3CFG (0x2B3)
1751 #define SPR_BOOKE_EPR (0x2BE)
1752 #define SPR_PERF0 (0x300)
1753 #define SPR_RCPU_MI_RBA0 (0x300)
1754 #define SPR_MPC_MI_CTR (0x300)
1755 #define SPR_POWER_USIER (0x300)
1756 #define SPR_PERF1 (0x301)
1757 #define SPR_RCPU_MI_RBA1 (0x301)
1758 #define SPR_POWER_UMMCR2 (0x301)
1759 #define SPR_PERF2 (0x302)
1760 #define SPR_RCPU_MI_RBA2 (0x302)
1761 #define SPR_MPC_MI_AP (0x302)
1762 #define SPR_POWER_UMMCRA (0x302)
1763 #define SPR_PERF3 (0x303)
1764 #define SPR_RCPU_MI_RBA3 (0x303)
1765 #define SPR_MPC_MI_EPN (0x303)
1766 #define SPR_POWER_UPMC1 (0x303)
1767 #define SPR_PERF4 (0x304)
1768 #define SPR_POWER_UPMC2 (0x304)
1769 #define SPR_PERF5 (0x305)
1770 #define SPR_MPC_MI_TWC (0x305)
1771 #define SPR_POWER_UPMC3 (0x305)
1772 #define SPR_PERF6 (0x306)
1773 #define SPR_MPC_MI_RPN (0x306)
1774 #define SPR_POWER_UPMC4 (0x306)
1775 #define SPR_PERF7 (0x307)
1776 #define SPR_POWER_UPMC5 (0x307)
1777 #define SPR_PERF8 (0x308)
1778 #define SPR_RCPU_L2U_RBA0 (0x308)
1779 #define SPR_MPC_MD_CTR (0x308)
1780 #define SPR_POWER_UPMC6 (0x308)
1781 #define SPR_PERF9 (0x309)
1782 #define SPR_RCPU_L2U_RBA1 (0x309)
1783 #define SPR_MPC_MD_CASID (0x309)
1784 #define SPR_970_UPMC7 (0X309)
1785 #define SPR_PERFA (0x30A)
1786 #define SPR_RCPU_L2U_RBA2 (0x30A)
1787 #define SPR_MPC_MD_AP (0x30A)
1788 #define SPR_970_UPMC8 (0X30A)
1789 #define SPR_PERFB (0x30B)
1790 #define SPR_RCPU_L2U_RBA3 (0x30B)
1791 #define SPR_MPC_MD_EPN (0x30B)
1792 #define SPR_POWER_UMMCR0 (0X30B)
1793 #define SPR_PERFC (0x30C)
1794 #define SPR_MPC_MD_TWB (0x30C)
1795 #define SPR_POWER_USIAR (0X30C)
1796 #define SPR_PERFD (0x30D)
1797 #define SPR_MPC_MD_TWC (0x30D)
1798 #define SPR_POWER_USDAR (0X30D)
1799 #define SPR_PERFE (0x30E)
1800 #define SPR_MPC_MD_RPN (0x30E)
1801 #define SPR_POWER_UMMCR1 (0X30E)
1802 #define SPR_PERFF (0x30F)
1803 #define SPR_MPC_MD_TW (0x30F)
1804 #define SPR_UPERF0 (0x310)
1805 #define SPR_POWER_SIER (0x310)
1806 #define SPR_UPERF1 (0x311)
1807 #define SPR_POWER_MMCR2 (0x311)
1808 #define SPR_UPERF2 (0x312)
1809 #define SPR_POWER_MMCRA (0X312)
1810 #define SPR_UPERF3 (0x313)
1811 #define SPR_POWER_PMC1 (0X313)
1812 #define SPR_UPERF4 (0x314)
1813 #define SPR_POWER_PMC2 (0X314)
1814 #define SPR_UPERF5 (0x315)
1815 #define SPR_POWER_PMC3 (0X315)
1816 #define SPR_UPERF6 (0x316)
1817 #define SPR_POWER_PMC4 (0X316)
1818 #define SPR_UPERF7 (0x317)
1819 #define SPR_POWER_PMC5 (0X317)
1820 #define SPR_UPERF8 (0x318)
1821 #define SPR_POWER_PMC6 (0X318)
1822 #define SPR_UPERF9 (0x319)
1823 #define SPR_970_PMC7 (0X319)
1824 #define SPR_UPERFA (0x31A)
1825 #define SPR_970_PMC8 (0X31A)
1826 #define SPR_UPERFB (0x31B)
1827 #define SPR_POWER_MMCR0 (0X31B)
1828 #define SPR_UPERFC (0x31C)
1829 #define SPR_POWER_SIAR (0X31C)
1830 #define SPR_UPERFD (0x31D)
1831 #define SPR_POWER_SDAR (0X31D)
1832 #define SPR_UPERFE (0x31E)
1833 #define SPR_POWER_MMCR1 (0X31E)
1834 #define SPR_UPERFF (0x31F)
1835 #define SPR_RCPU_MI_RA0 (0x320)
1836 #define SPR_MPC_MI_DBCAM (0x320)
1837 #define SPR_BESCRS (0x320)
1838 #define SPR_RCPU_MI_RA1 (0x321)
1839 #define SPR_MPC_MI_DBRAM0 (0x321)
1840 #define SPR_BESCRSU (0x321)
1841 #define SPR_RCPU_MI_RA2 (0x322)
1842 #define SPR_MPC_MI_DBRAM1 (0x322)
1843 #define SPR_BESCRR (0x322)
1844 #define SPR_RCPU_MI_RA3 (0x323)
1845 #define SPR_BESCRRU (0x323)
1846 #define SPR_EBBHR (0x324)
1847 #define SPR_EBBRR (0x325)
1848 #define SPR_BESCR (0x326)
1849 #define SPR_RCPU_L2U_RA0 (0x328)
1850 #define SPR_MPC_MD_DBCAM (0x328)
1851 #define SPR_RCPU_L2U_RA1 (0x329)
1852 #define SPR_MPC_MD_DBRAM0 (0x329)
1853 #define SPR_RCPU_L2U_RA2 (0x32A)
1854 #define SPR_MPC_MD_DBRAM1 (0x32A)
1855 #define SPR_RCPU_L2U_RA3 (0x32B)
1856 #define SPR_TAR (0x32F)
1857 #define SPR_ASDR (0x330)
1858 #define SPR_IC (0x350)
1859 #define SPR_VTB (0x351)
1860 #define SPR_MMCRC (0x353)
1861 #define SPR_PSSCR (0x357)
1862 #define SPR_440_INV0 (0x370)
1863 #define SPR_440_INV1 (0x371)
1864 #define SPR_440_INV2 (0x372)
1865 #define SPR_440_INV3 (0x373)
1866 #define SPR_440_ITV0 (0x374)
1867 #define SPR_440_ITV1 (0x375)
1868 #define SPR_440_ITV2 (0x376)
1869 #define SPR_440_ITV3 (0x377)
1870 #define SPR_440_CCR1 (0x378)
1871 #define SPR_TACR (0x378)
1872 #define SPR_TCSCR (0x379)
1873 #define SPR_CSIGR (0x37a)
1874 #define SPR_DCRIPR (0x37B)
1875 #define SPR_POWER_SPMC1 (0x37C)
1876 #define SPR_POWER_SPMC2 (0x37D)
1877 #define SPR_POWER_MMCRS (0x37E)
1878 #define SPR_WORT (0x37F)
1879 #define SPR_PPR (0x380)
1880 #define SPR_750_GQR0 (0x390)
1881 #define SPR_440_DNV0 (0x390)
1882 #define SPR_750_GQR1 (0x391)
1883 #define SPR_440_DNV1 (0x391)
1884 #define SPR_750_GQR2 (0x392)
1885 #define SPR_440_DNV2 (0x392)
1886 #define SPR_750_GQR3 (0x393)
1887 #define SPR_440_DNV3 (0x393)
1888 #define SPR_750_GQR4 (0x394)
1889 #define SPR_440_DTV0 (0x394)
1890 #define SPR_750_GQR5 (0x395)
1891 #define SPR_440_DTV1 (0x395)
1892 #define SPR_750_GQR6 (0x396)
1893 #define SPR_440_DTV2 (0x396)
1894 #define SPR_750_GQR7 (0x397)
1895 #define SPR_440_DTV3 (0x397)
1896 #define SPR_750_THRM4 (0x398)
1897 #define SPR_750CL_HID2 (0x398)
1898 #define SPR_440_DVLIM (0x398)
1899 #define SPR_750_WPAR (0x399)
1900 #define SPR_440_IVLIM (0x399)
1901 #define SPR_TSCR (0x399)
1902 #define SPR_750_DMAU (0x39A)
1903 #define SPR_750_DMAL (0x39B)
1904 #define SPR_440_RSTCFG (0x39B)
1905 #define SPR_BOOKE_DCDBTRL (0x39C)
1906 #define SPR_BOOKE_DCDBTRH (0x39D)
1907 #define SPR_BOOKE_ICDBTRL (0x39E)
1908 #define SPR_BOOKE_ICDBTRH (0x39F)
1909 #define SPR_74XX_UMMCR2 (0x3A0)
1910 #define SPR_7XX_UPMC5 (0x3A1)
1911 #define SPR_7XX_UPMC6 (0x3A2)
1912 #define SPR_UBAMR (0x3A7)
1913 #define SPR_7XX_UMMCR0 (0x3A8)
1914 #define SPR_7XX_UPMC1 (0x3A9)
1915 #define SPR_7XX_UPMC2 (0x3AA)
1916 #define SPR_7XX_USIAR (0x3AB)
1917 #define SPR_7XX_UMMCR1 (0x3AC)
1918 #define SPR_7XX_UPMC3 (0x3AD)
1919 #define SPR_7XX_UPMC4 (0x3AE)
1920 #define SPR_USDA (0x3AF)
1921 #define SPR_40x_ZPR (0x3B0)
1922 #define SPR_BOOKE_MAS7 (0x3B0)
1923 #define SPR_74XX_MMCR2 (0x3B0)
1924 #define SPR_7XX_PMC5 (0x3B1)
1925 #define SPR_40x_PID (0x3B1)
1926 #define SPR_7XX_PMC6 (0x3B2)
1927 #define SPR_440_MMUCR (0x3B2)
1928 #define SPR_4xx_CCR0 (0x3B3)
1929 #define SPR_BOOKE_EPLC (0x3B3)
1930 #define SPR_405_IAC3 (0x3B4)
1931 #define SPR_BOOKE_EPSC (0x3B4)
1932 #define SPR_405_IAC4 (0x3B5)
1933 #define SPR_405_DVC1 (0x3B6)
1934 #define SPR_405_DVC2 (0x3B7)
1935 #define SPR_BAMR (0x3B7)
1936 #define SPR_7XX_MMCR0 (0x3B8)
1937 #define SPR_7XX_PMC1 (0x3B9)
1938 #define SPR_40x_SGR (0x3B9)
1939 #define SPR_7XX_PMC2 (0x3BA)
1940 #define SPR_40x_DCWR (0x3BA)
1941 #define SPR_7XX_SIAR (0x3BB)
1942 #define SPR_405_SLER (0x3BB)
1943 #define SPR_7XX_MMCR1 (0x3BC)
1944 #define SPR_405_SU0R (0x3BC)
1945 #define SPR_401_SKR (0x3BC)
1946 #define SPR_7XX_PMC3 (0x3BD)
1947 #define SPR_405_DBCR1 (0x3BD)
1948 #define SPR_7XX_PMC4 (0x3BE)
1949 #define SPR_SDA (0x3BF)
1950 #define SPR_403_VTBL (0x3CC)
1951 #define SPR_403_VTBU (0x3CD)
1952 #define SPR_DMISS (0x3D0)
1953 #define SPR_DCMP (0x3D1)
1954 #define SPR_HASH1 (0x3D2)
1955 #define SPR_HASH2 (0x3D3)
1956 #define SPR_BOOKE_ICDBDR (0x3D3)
1957 #define SPR_TLBMISS (0x3D4)
1958 #define SPR_IMISS (0x3D4)
1959 #define SPR_40x_ESR (0x3D4)
1960 #define SPR_PTEHI (0x3D5)
1961 #define SPR_ICMP (0x3D5)
1962 #define SPR_40x_DEAR (0x3D5)
1963 #define SPR_PTELO (0x3D6)
1964 #define SPR_RPA (0x3D6)
1965 #define SPR_40x_EVPR (0x3D6)
1966 #define SPR_L3PM (0x3D7)
1967 #define SPR_403_CDBCR (0x3D7)
1968 #define SPR_L3ITCR0 (0x3D8)
1969 #define SPR_TCR (0x3D8)
1970 #define SPR_40x_TSR (0x3D8)
1971 #define SPR_IBR (0x3DA)
1972 #define SPR_40x_TCR (0x3DA)
1973 #define SPR_ESASRR (0x3DB)
1974 #define SPR_40x_PIT (0x3DB)
1975 #define SPR_403_TBL (0x3DC)
1976 #define SPR_403_TBU (0x3DD)
1977 #define SPR_SEBR (0x3DE)
1978 #define SPR_40x_SRR2 (0x3DE)
1979 #define SPR_SER (0x3DF)
1980 #define SPR_40x_SRR3 (0x3DF)
1981 #define SPR_L3OHCR (0x3E8)
1982 #define SPR_L3ITCR1 (0x3E9)
1983 #define SPR_L3ITCR2 (0x3EA)
1984 #define SPR_L3ITCR3 (0x3EB)
1985 #define SPR_HID0 (0x3F0)
1986 #define SPR_40x_DBSR (0x3F0)
1987 #define SPR_HID1 (0x3F1)
1988 #define SPR_IABR (0x3F2)
1989 #define SPR_40x_DBCR0 (0x3F2)
1990 #define SPR_Exxx_L1CSR0 (0x3F2)
1991 #define SPR_ICTRL (0x3F3)
1992 #define SPR_HID2 (0x3F3)
1993 #define SPR_750CL_HID4 (0x3F3)
1994 #define SPR_Exxx_L1CSR1 (0x3F3)
1995 #define SPR_440_DBDR (0x3F3)
1996 #define SPR_LDSTDB (0x3F4)
1997 #define SPR_750_TDCL (0x3F4)
1998 #define SPR_40x_IAC1 (0x3F4)
1999 #define SPR_MMUCSR0 (0x3F4)
2000 #define SPR_970_HID4 (0x3F4)
2001 #define SPR_DABR (0x3F5)
2002 #define DABR_MASK (~(target_ulong)0x7)
2003 #define SPR_Exxx_BUCSR (0x3F5)
2004 #define SPR_40x_IAC2 (0x3F5)
2005 #define SPR_40x_DAC1 (0x3F6)
2006 #define SPR_MSSCR0 (0x3F6)
2007 #define SPR_970_HID5 (0x3F6)
2008 #define SPR_MSSSR0 (0x3F7)
2009 #define SPR_MSSCR1 (0x3F7)
2010 #define SPR_DABRX (0x3F7)
2011 #define SPR_40x_DAC2 (0x3F7)
2012 #define SPR_MMUCFG (0x3F7)
2013 #define SPR_LDSTCR (0x3F8)
2014 #define SPR_L2PMCR (0x3F8)
2015 #define SPR_750FX_HID2 (0x3F8)
2016 #define SPR_Exxx_L1FINV0 (0x3F8)
2017 #define SPR_L2CR (0x3F9)
2018 #define SPR_Exxx_L2CSR0 (0x3F9)
2019 #define SPR_L3CR (0x3FA)
2020 #define SPR_750_TDCH (0x3FA)
2021 #define SPR_IABR2 (0x3FA)
2022 #define SPR_40x_DCCR (0x3FA)
2023 #define SPR_ICTC (0x3FB)
2024 #define SPR_40x_ICCR (0x3FB)
2025 #define SPR_THRM1 (0x3FC)
2026 #define SPR_403_PBL1 (0x3FC)
2027 #define SPR_SP (0x3FD)
2028 #define SPR_THRM2 (0x3FD)
2029 #define SPR_403_PBU1 (0x3FD)
2030 #define SPR_604_HID13 (0x3FD)
2031 #define SPR_LT (0x3FE)
2032 #define SPR_THRM3 (0x3FE)
2033 #define SPR_RCPU_FPECR (0x3FE)
2034 #define SPR_403_PBL2 (0x3FE)
2035 #define SPR_PIR (0x3FF)
2036 #define SPR_403_PBU2 (0x3FF)
2037 #define SPR_604_HID15 (0x3FF)
2038 #define SPR_E500_SVR (0x3FF)
2039
2040 /* Disable MAS Interrupt Updates for Hypervisor */
2041 #define EPCR_DMIUH (1 << 22)
2042 /* Disable Guest TLB Management Instructions */
2043 #define EPCR_DGTMI (1 << 23)
2044 /* Guest Interrupt Computation Mode */
2045 #define EPCR_GICM (1 << 24)
2046 /* Interrupt Computation Mode */
2047 #define EPCR_ICM (1 << 25)
2048 /* Disable Embedded Hypervisor Debug */
2049 #define EPCR_DUVD (1 << 26)
2050 /* Instruction Storage Interrupt Directed to Guest State */
2051 #define EPCR_ISIGS (1 << 27)
2052 /* Data Storage Interrupt Directed to Guest State */
2053 #define EPCR_DSIGS (1 << 28)
2054 /* Instruction TLB Error Interrupt Directed to Guest State */
2055 #define EPCR_ITLBGS (1 << 29)
2056 /* Data TLB Error Interrupt Directed to Guest State */
2057 #define EPCR_DTLBGS (1 << 30)
2058 /* External Input Interrupt Directed to Guest State */
2059 #define EPCR_EXTGS (1 << 31)
2060
2061 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2062 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2063 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2064 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2065 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2066
2067 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2068 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2069 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2070 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2071 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2072
2073 /* E500 L2CSR0 */
2074 #define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2075 #define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2076 #define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2077
2078 /* HID0 bits */
2079 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2080 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2081 #define HID0_NAP (1 << 22) /* pre-2.06 */
2082 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2083 #define HID0_POWER9_HILE PPC_BIT(4)
2084
2085 /*****************************************************************************/
2086 /* PowerPC Instructions types definitions */
2087 enum {
2088 PPC_NONE = 0x0000000000000000ULL,
2089 /* PowerPC base instructions set */
2090 PPC_INSNS_BASE = 0x0000000000000001ULL,
2091 /* integer operations instructions */
2092 #define PPC_INTEGER PPC_INSNS_BASE
2093 /* flow control instructions */
2094 #define PPC_FLOW PPC_INSNS_BASE
2095 /* virtual memory instructions */
2096 #define PPC_MEM PPC_INSNS_BASE
2097 /* ld/st with reservation instructions */
2098 #define PPC_RES PPC_INSNS_BASE
2099 /* spr/msr access instructions */
2100 #define PPC_MISC PPC_INSNS_BASE
2101 /* 64 bits PowerPC instruction set */
2102 PPC_64B = 0x0000000000000020ULL,
2103 /* New 64 bits extensions (PowerPC 2.0x) */
2104 PPC_64BX = 0x0000000000000040ULL,
2105 /* 64 bits hypervisor extensions */
2106 PPC_64H = 0x0000000000000080ULL,
2107 /* New wait instruction (PowerPC 2.0x) */
2108 PPC_WAIT = 0x0000000000000100ULL,
2109 /* Time base mftb instruction */
2110 PPC_MFTB = 0x0000000000000200ULL,
2111
2112 /* Fixed-point unit extensions */
2113 /* isel instruction */
2114 PPC_ISEL = 0x0000000000000800ULL,
2115 /* popcntb instruction */
2116 PPC_POPCNTB = 0x0000000000001000ULL,
2117 /* string load / store */
2118 PPC_STRING = 0x0000000000002000ULL,
2119 /* real mode cache inhibited load / store */
2120 PPC_CILDST = 0x0000000000004000ULL,
2121
2122 /* Floating-point unit extensions */
2123 /* Optional floating point instructions */
2124 PPC_FLOAT = 0x0000000000010000ULL,
2125 /* New floating-point extensions (PowerPC 2.0x) */
2126 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2127 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2128 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2129 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2130 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2131 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2132 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2133
2134 /* Vector/SIMD extensions */
2135 /* Altivec support */
2136 PPC_ALTIVEC = 0x0000000001000000ULL,
2137 /* PowerPC 2.03 SPE extension */
2138 PPC_SPE = 0x0000000002000000ULL,
2139 /* PowerPC 2.03 SPE single-precision floating-point extension */
2140 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2141 /* PowerPC 2.03 SPE double-precision floating-point extension */
2142 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2143
2144 /* Optional memory control instructions */
2145 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2146 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2147 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2148 /* sync instruction */
2149 PPC_MEM_SYNC = 0x0000000080000000ULL,
2150 /* eieio instruction */
2151 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2152
2153 /* Cache control instructions */
2154 PPC_CACHE = 0x0000000200000000ULL,
2155 /* icbi instruction */
2156 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2157 /* dcbz instruction */
2158 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2159 /* dcba instruction */
2160 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2161 /* Freescale cache locking instructions */
2162 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2163
2164 /* MMU related extensions */
2165 /* external control instructions */
2166 PPC_EXTERN = 0x0000010000000000ULL,
2167 /* segment register access instructions */
2168 PPC_SEGMENT = 0x0000020000000000ULL,
2169 /* PowerPC 6xx TLB management instructions */
2170 PPC_6xx_TLB = 0x0000040000000000ULL,
2171 /* PowerPC 40x TLB management instructions */
2172 PPC_40x_TLB = 0x0000100000000000ULL,
2173 /* segment register access instructions for PowerPC 64 "bridge" */
2174 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2175 /* SLB management */
2176 PPC_SLBI = 0x0000400000000000ULL,
2177
2178 /* Embedded PowerPC dedicated instructions */
2179 PPC_WRTEE = 0x0001000000000000ULL,
2180 /* PowerPC 40x exception model */
2181 PPC_40x_EXCP = 0x0002000000000000ULL,
2182 /* PowerPC 405 Mac instructions */
2183 PPC_405_MAC = 0x0004000000000000ULL,
2184 /* PowerPC 440 specific instructions */
2185 PPC_440_SPEC = 0x0008000000000000ULL,
2186 /* BookE (embedded) PowerPC specification */
2187 PPC_BOOKE = 0x0010000000000000ULL,
2188 /* mfapidi instruction */
2189 PPC_MFAPIDI = 0x0020000000000000ULL,
2190 /* tlbiva instruction */
2191 PPC_TLBIVA = 0x0040000000000000ULL,
2192 /* tlbivax instruction */
2193 PPC_TLBIVAX = 0x0080000000000000ULL,
2194 /* PowerPC 4xx dedicated instructions */
2195 PPC_4xx_COMMON = 0x0100000000000000ULL,
2196 /* PowerPC 40x ibct instructions */
2197 PPC_40x_ICBT = 0x0200000000000000ULL,
2198 /* rfmci is not implemented in all BookE PowerPC */
2199 PPC_RFMCI = 0x0400000000000000ULL,
2200 /* rfdi instruction */
2201 PPC_RFDI = 0x0800000000000000ULL,
2202 /* DCR accesses */
2203 PPC_DCR = 0x1000000000000000ULL,
2204 /* DCR extended accesse */
2205 PPC_DCRX = 0x2000000000000000ULL,
2206 /* user-mode DCR access, implemented in PowerPC 460 */
2207 PPC_DCRUX = 0x4000000000000000ULL,
2208 /* popcntw and popcntd instructions */
2209 PPC_POPCNTWD = 0x8000000000000000ULL,
2210
2211 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_64B \
2212 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2213 | PPC_ISEL | PPC_POPCNTB \
2214 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2215 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2216 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2217 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2218 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2219 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2220 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2221 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2222 | PPC_CACHE | PPC_CACHE_ICBI \
2223 | PPC_CACHE_DCBZ \
2224 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2225 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2226 | PPC_40x_TLB | PPC_SEGMENT_64B \
2227 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2228 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2229 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2230 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2231 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2232 | PPC_POPCNTWD | PPC_CILDST)
2233
2234 /* extended type values */
2235
2236 /* BookE 2.06 PowerPC specification */
2237 PPC2_BOOKE206 = 0x0000000000000001ULL,
2238 /* VSX (extensions to Altivec / VMX) */
2239 PPC2_VSX = 0x0000000000000002ULL,
2240 /* Decimal Floating Point (DFP) */
2241 PPC2_DFP = 0x0000000000000004ULL,
2242 /* Embedded.Processor Control */
2243 PPC2_PRCNTL = 0x0000000000000008ULL,
2244 /* Byte-reversed, indexed, double-word load and store */
2245 PPC2_DBRX = 0x0000000000000010ULL,
2246 /* Book I 2.05 PowerPC specification */
2247 PPC2_ISA205 = 0x0000000000000020ULL,
2248 /* VSX additions in ISA 2.07 */
2249 PPC2_VSX207 = 0x0000000000000040ULL,
2250 /* ISA 2.06B bpermd */
2251 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2252 /* ISA 2.06B divide extended variants */
2253 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2254 /* ISA 2.06B larx/stcx. instructions */
2255 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2256 /* ISA 2.06B floating point integer conversion */
2257 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2258 /* ISA 2.06B floating point test instructions */
2259 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2260 /* ISA 2.07 bctar instruction */
2261 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2262 /* ISA 2.07 load/store quadword */
2263 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2264 /* ISA 2.07 Altivec */
2265 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2266 /* PowerISA 2.07 Book3s specification */
2267 PPC2_ISA207S = 0x0000000000008000ULL,
2268 /* Double precision floating point conversion for signed integer 64 */
2269 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2270 /* Transactional Memory (ISA 2.07, Book II) */
2271 PPC2_TM = 0x0000000000020000ULL,
2272 /* Server PM instructgions (ISA 2.06, Book III) */
2273 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2274 /* POWER ISA 3.0 */
2275 PPC2_ISA300 = 0x0000000000080000ULL,
2276 /* POWER ISA 3.1 */
2277 PPC2_ISA310 = 0x0000000000100000ULL,
2278 /* lwsync instruction */
2279 PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
2280
2281 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2282 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2283 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2284 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2285 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2286 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2287 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2288 PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC)
2289 };
2290
2291 /*****************************************************************************/
2292 /*
2293 * Memory access type :
2294 * may be needed for precise access rights control and precise exceptions.
2295 */
2296 enum {
2297 /* Type of instruction that generated the access */
2298 ACCESS_CODE = 0x10, /* Code fetch access */
2299 ACCESS_INT = 0x20, /* Integer load/store access */
2300 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2301 ACCESS_RES = 0x40, /* load/store with reservation */
2302 ACCESS_EXT = 0x50, /* external access */
2303 ACCESS_CACHE = 0x60, /* Cache manipulation */
2304 };
2305
2306 /*
2307 * Hardware interrupt sources:
2308 * all those exception can be raised simulteaneously
2309 */
2310 /* Input pins definitions */
2311 enum {
2312 /* 6xx bus input pins */
2313 PPC6xx_INPUT_HRESET = 0,
2314 PPC6xx_INPUT_SRESET = 1,
2315 PPC6xx_INPUT_CKSTP_IN = 2,
2316 PPC6xx_INPUT_MCP = 3,
2317 PPC6xx_INPUT_SMI = 4,
2318 PPC6xx_INPUT_INT = 5,
2319 PPC6xx_INPUT_TBEN = 6,
2320 PPC6xx_INPUT_WAKEUP = 7,
2321 PPC6xx_INPUT_NB,
2322 };
2323
2324 enum {
2325 /* Embedded PowerPC input pins */
2326 PPCBookE_INPUT_HRESET = 0,
2327 PPCBookE_INPUT_SRESET = 1,
2328 PPCBookE_INPUT_CKSTP_IN = 2,
2329 PPCBookE_INPUT_MCP = 3,
2330 PPCBookE_INPUT_SMI = 4,
2331 PPCBookE_INPUT_INT = 5,
2332 PPCBookE_INPUT_CINT = 6,
2333 PPCBookE_INPUT_NB,
2334 };
2335
2336 enum {
2337 /* PowerPC E500 input pins */
2338 PPCE500_INPUT_RESET_CORE = 0,
2339 PPCE500_INPUT_MCK = 1,
2340 PPCE500_INPUT_CINT = 3,
2341 PPCE500_INPUT_INT = 4,
2342 PPCE500_INPUT_DEBUG = 6,
2343 PPCE500_INPUT_NB,
2344 };
2345
2346 enum {
2347 /* PowerPC 40x input pins */
2348 PPC40x_INPUT_RESET_CORE = 0,
2349 PPC40x_INPUT_RESET_CHIP = 1,
2350 PPC40x_INPUT_RESET_SYS = 2,
2351 PPC40x_INPUT_CINT = 3,
2352 PPC40x_INPUT_INT = 4,
2353 PPC40x_INPUT_HALT = 5,
2354 PPC40x_INPUT_DEBUG = 6,
2355 PPC40x_INPUT_NB,
2356 };
2357
2358 enum {
2359 /* RCPU input pins */
2360 PPCRCPU_INPUT_PORESET = 0,
2361 PPCRCPU_INPUT_HRESET = 1,
2362 PPCRCPU_INPUT_SRESET = 2,
2363 PPCRCPU_INPUT_IRQ0 = 3,
2364 PPCRCPU_INPUT_IRQ1 = 4,
2365 PPCRCPU_INPUT_IRQ2 = 5,
2366 PPCRCPU_INPUT_IRQ3 = 6,
2367 PPCRCPU_INPUT_IRQ4 = 7,
2368 PPCRCPU_INPUT_IRQ5 = 8,
2369 PPCRCPU_INPUT_IRQ6 = 9,
2370 PPCRCPU_INPUT_IRQ7 = 10,
2371 PPCRCPU_INPUT_NB,
2372 };
2373
2374 #if defined(TARGET_PPC64)
2375 enum {
2376 /* PowerPC 970 input pins */
2377 PPC970_INPUT_HRESET = 0,
2378 PPC970_INPUT_SRESET = 1,
2379 PPC970_INPUT_CKSTP = 2,
2380 PPC970_INPUT_TBEN = 3,
2381 PPC970_INPUT_MCP = 4,
2382 PPC970_INPUT_INT = 5,
2383 PPC970_INPUT_THINT = 6,
2384 PPC970_INPUT_NB,
2385 };
2386
2387 enum {
2388 /* POWER7 input pins */
2389 POWER7_INPUT_INT = 0,
2390 /*
2391 * POWER7 probably has other inputs, but we don't care about them
2392 * for any existing machine. We can wire these up when we need
2393 * them
2394 */
2395 POWER7_INPUT_NB,
2396 };
2397
2398 enum {
2399 /* POWER9 input pins */
2400 POWER9_INPUT_INT = 0,
2401 POWER9_INPUT_HINT = 1,
2402 POWER9_INPUT_NB,
2403 };
2404 #endif
2405
2406 /* Hardware exceptions definitions */
2407 enum {
2408 /* External hardware exception sources */
2409 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2410 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2411 PPC_INTERRUPT_MCK, /* Machine check exception */
2412 PPC_INTERRUPT_EXT, /* External interrupt */
2413 PPC_INTERRUPT_SMI, /* System management interrupt */
2414 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2415 PPC_INTERRUPT_DEBUG, /* External debug exception */
2416 PPC_INTERRUPT_THERM, /* Thermal exception */
2417 /* Internal hardware exception sources */
2418 PPC_INTERRUPT_DECR, /* Decrementer exception */
2419 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2420 PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt */
2421 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2422 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2423 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2424 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2425 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2426 PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
2427 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
2428 PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
2429 PPC_INTERRUPT_EBB, /* Event-based Branch exception */
2430 };
2431
2432 /* Processor Compatibility mask (PCR) */
2433 enum {
2434 PCR_COMPAT_2_05 = PPC_BIT(62),
2435 PCR_COMPAT_2_06 = PPC_BIT(61),
2436 PCR_COMPAT_2_07 = PPC_BIT(60),
2437 PCR_COMPAT_3_00 = PPC_BIT(59),
2438 PCR_COMPAT_3_10 = PPC_BIT(58),
2439 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2440 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2441 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2442 };
2443
2444 /* HMER/HMEER */
2445 enum {
2446 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2447 HMER_PROC_RECV_DONE = PPC_BIT(2),
2448 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2449 HMER_TFAC_ERROR = PPC_BIT(4),
2450 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2451 HMER_XSCOM_FAIL = PPC_BIT(8),
2452 HMER_XSCOM_DONE = PPC_BIT(9),
2453 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2454 HMER_WARN_RISE = PPC_BIT(14),
2455 HMER_WARN_FALL = PPC_BIT(15),
2456 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2457 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2458 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2459 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2460 };
2461
2462 /*****************************************************************************/
2463
2464 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2465 target_ulong cpu_read_xer(const CPUPPCState *env);
2466 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2467
2468 /*
2469 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2470 * have PPC_SEGMENT_64B.
2471 */
2472 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2473
2474 #ifdef CONFIG_DEBUG_TCG
2475 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2476 target_ulong *cs_base, uint32_t *flags);
2477 #else
2478 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2479 target_ulong *cs_base, uint32_t *flags)
2480 {
2481 *pc = env->nip;
2482 *cs_base = 0;
2483 *flags = env->hflags;
2484 }
2485 #endif
2486
2487 G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2488 G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2489 uintptr_t raddr);
2490 G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2491 uint32_t error_code);
2492 G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2493 uint32_t error_code, uintptr_t raddr);
2494
2495 /* PERFM EBB helper*/
2496 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2497 void raise_ebb_perfm_exception(CPUPPCState *env);
2498 #endif
2499
2500 #if !defined(CONFIG_USER_ONLY)
2501 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2502 {
2503 uintptr_t tlbml = (uintptr_t)tlbm;
2504 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2505
2506 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2507 }
2508
2509 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2510 {
2511 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2512 int r = tlbncfg & TLBnCFG_N_ENTRY;
2513 return r;
2514 }
2515
2516 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2517 {
2518 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2519 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2520 return r;
2521 }
2522
2523 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2524 {
2525 int id = booke206_tlbm_id(env, tlbm);
2526 int end = 0;
2527 int i;
2528
2529 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2530 end += booke206_tlb_size(env, i);
2531 if (id < end) {
2532 return i;
2533 }
2534 }
2535
2536 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2537 return 0;
2538 }
2539
2540 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2541 {
2542 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2543 int tlbid = booke206_tlbm_id(env, tlb);
2544 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2545 }
2546
2547 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2548 target_ulong ea, int way)
2549 {
2550 int r;
2551 uint32_t ways = booke206_tlb_ways(env, tlbn);
2552 int ways_bits = ctz32(ways);
2553 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2554 int i;
2555
2556 way &= ways - 1;
2557 ea >>= MAS2_EPN_SHIFT;
2558 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2559 r = (ea << ways_bits) | way;
2560
2561 if (r >= booke206_tlb_size(env, tlbn)) {
2562 return NULL;
2563 }
2564
2565 /* bump up to tlbn index */
2566 for (i = 0; i < tlbn; i++) {
2567 r += booke206_tlb_size(env, i);
2568 }
2569
2570 return &env->tlb.tlbm[r];
2571 }
2572
2573 /* returns bitmap of supported page sizes for a given TLB */
2574 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2575 {
2576 uint32_t ret = 0;
2577
2578 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2579 /* MAV2 */
2580 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2581 } else {
2582 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2583 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2584 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2585 int i;
2586 for (i = min; i <= max; i++) {
2587 ret |= (1 << (i << 1));
2588 }
2589 }
2590
2591 return ret;
2592 }
2593
2594 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2595 ppcmas_tlb_t *tlb)
2596 {
2597 uint8_t i;
2598 int32_t tsize = -1;
2599
2600 for (i = 0; i < 32; i++) {
2601 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2602 if (tsize == -1) {
2603 tsize = i;
2604 } else {
2605 return;
2606 }
2607 }
2608 }
2609
2610 /* TLBnPS unimplemented? Odd.. */
2611 assert(tsize != -1);
2612 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2613 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2614 }
2615
2616 #endif
2617
2618 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2619 {
2620 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2621 return msr & (1ULL << MSR_CM);
2622 }
2623
2624 return msr & (1ULL << MSR_SF);
2625 }
2626
2627 /**
2628 * Check whether register rx is in the range between start and
2629 * start + nregs (as needed by the LSWX and LSWI instructions)
2630 */
2631 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2632 {
2633 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2634 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2635 }
2636
2637 /* Accessors for FP, VMX and VSX registers */
2638 #if HOST_BIG_ENDIAN
2639 #define VsrB(i) u8[i]
2640 #define VsrSB(i) s8[i]
2641 #define VsrH(i) u16[i]
2642 #define VsrSH(i) s16[i]
2643 #define VsrW(i) u32[i]
2644 #define VsrSW(i) s32[i]
2645 #define VsrD(i) u64[i]
2646 #define VsrSD(i) s64[i]
2647 #define VsrHF(i) f16[i]
2648 #define VsrSF(i) f32[i]
2649 #define VsrDF(i) f64[i]
2650 #else
2651 #define VsrB(i) u8[15 - (i)]
2652 #define VsrSB(i) s8[15 - (i)]
2653 #define VsrH(i) u16[7 - (i)]
2654 #define VsrSH(i) s16[7 - (i)]
2655 #define VsrW(i) u32[3 - (i)]
2656 #define VsrSW(i) s32[3 - (i)]
2657 #define VsrD(i) u64[1 - (i)]
2658 #define VsrSD(i) s64[1 - (i)]
2659 #define VsrHF(i) f16[7 - (i)]
2660 #define VsrSF(i) f32[3 - (i)]
2661 #define VsrDF(i) f64[1 - (i)]
2662 #endif
2663
2664 static inline int vsr64_offset(int i, bool high)
2665 {
2666 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2667 }
2668
2669 static inline int vsr_full_offset(int i)
2670 {
2671 return offsetof(CPUPPCState, vsr[i].u64[0]);
2672 }
2673
2674 static inline int acc_full_offset(int i)
2675 {
2676 return vsr_full_offset(i * 4);
2677 }
2678
2679 static inline int fpr_offset(int i)
2680 {
2681 return vsr64_offset(i, true);
2682 }
2683
2684 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2685 {
2686 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2687 }
2688
2689 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2690 {
2691 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2692 }
2693
2694 static inline long avr64_offset(int i, bool high)
2695 {
2696 return vsr64_offset(i + 32, high);
2697 }
2698
2699 static inline int avr_full_offset(int i)
2700 {
2701 return vsr_full_offset(i + 32);
2702 }
2703
2704 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2705 {
2706 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2707 }
2708
2709 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2710 {
2711 /* We can test whether the SPR is defined by checking for a valid name */
2712 return cpu->env.spr_cb[spr].name != NULL;
2713 }
2714
2715 #if !defined(CONFIG_USER_ONLY)
2716 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2717 {
2718 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2719 CPUPPCState *env = &cpu->env;
2720 bool ile;
2721
2722 if (hv && env->has_hv_mode) {
2723 if (is_isa300(pcc)) {
2724 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2725 } else {
2726 ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2727 }
2728
2729 } else if (pcc->lpcr_mask & LPCR_ILE) {
2730 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2731 } else {
2732 ile = FIELD_EX64(env->msr, MSR, ILE);
2733 }
2734
2735 return ile;
2736 }
2737 #endif
2738
2739 void dump_mmu(CPUPPCState *env);
2740
2741 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2742 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2743 uint32_t ppc_get_vscr(CPUPPCState *env);
2744
2745 /*****************************************************************************/
2746 /* Power management enable checks */
2747 static inline int check_pow_none(CPUPPCState *env)
2748 {
2749 return 0;
2750 }
2751
2752 static inline int check_pow_nocheck(CPUPPCState *env)
2753 {
2754 return 1;
2755 }
2756
2757 /*****************************************************************************/
2758 /* PowerPC implementations definitions */
2759
2760 #define POWERPC_FAMILY(_name) \
2761 static void \
2762 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2763 \
2764 static const TypeInfo \
2765 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2766 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2767 .parent = TYPE_POWERPC_CPU, \
2768 .abstract = true, \
2769 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2770 }; \
2771 \
2772 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2773 { \
2774 type_register_static( \
2775 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2776 } \
2777 \
2778 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2779 \
2780 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2781
2782
2783 #endif /* PPC_CPU_H */
QEmu