include/hw/ppc/ppc4xx.h

   1 /*
   2  * QEMU PowerPC 4xx emulation shared definitions
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef PPC4XX_H
  26 #define PPC4XX_H
  27
  28 #include "hw/ppc/ppc.h"
  29 #include "exec/memory.h"
  30 #include "hw/sysbus.h"
  31
  32 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
  33                         MemoryRegion ram_memories[],
  34                         hwaddr ram_bases[], hwaddr ram_sizes[],
  35                         const ram_addr_t sdram_bank_sizes[]);
  36
  37 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
  38                         MemoryRegion ram_memories[],
  39                         hwaddr *ram_bases,
  40                         hwaddr *ram_sizes,
  41                         int do_init);
  42
  43 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
  44
  45 /*
  46  * Generic DCR device
  47  */
  48 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
  49 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
  50 struct Ppc4xxDcrDeviceState {
  51     SysBusDevice parent_obj;
  52
  53     PowerPCCPU *cpu;
  54 };
  55
  56 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
  57                          dcr_read_cb dcr_read, dcr_write_cb dcr_write);
  58 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
  59                         Error **errp);
  60
  61 /* Memory Access Layer (MAL) */
  62 #define TYPE_PPC4xx_MAL "ppc4xx-mal"
  63 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
  64 struct Ppc4xxMalState {
  65     Ppc4xxDcrDeviceState parent_obj;
  66
  67     qemu_irq irqs[4];
  68     uint32_t cfg;
  69     uint32_t esr;
  70     uint32_t ier;
  71     uint32_t txcasr;
  72     uint32_t txcarr;
  73     uint32_t txeobisr;
  74     uint32_t txdeir;
  75     uint32_t rxcasr;
  76     uint32_t rxcarr;
  77     uint32_t rxeobisr;
  78     uint32_t rxdeir;
  79     uint32_t *txctpr;
  80     uint32_t *rxctpr;
  81     uint32_t *rcbs;
  82     uint8_t  txcnum;
  83     uint8_t  rxcnum;
  84 };
  85
  86 /* Peripheral local bus arbitrer */
  87 #define TYPE_PPC405_PLB "ppc405-plb"
  88 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
  89 struct Ppc405PlbState {
  90     Ppc4xxDcrDeviceState parent_obj;
  91
  92     uint32_t acr;
  93     uint32_t bear;
  94     uint32_t besr;
  95 };
  96
  97 #endif /* PPC4XX_H */