2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 # define hw_omap_h "omap.h"
22 # define OMAP_EMIFS_BASE 0x00000000
23 # define OMAP2_Q0_BASE 0x00000000
24 # define OMAP_CS0_BASE 0x00000000
25 # define OMAP_CS1_BASE 0x04000000
26 # define OMAP_CS2_BASE 0x08000000
27 # define OMAP_CS3_BASE 0x0c000000
28 # define OMAP_EMIFF_BASE 0x10000000
29 # define OMAP_IMIF_BASE 0x20000000
30 # define OMAP_LOCALBUS_BASE 0x30000000
31 # define OMAP2_Q1_BASE 0x40000000
32 # define OMAP2_L4_BASE 0x48000000
33 # define OMAP2_SRAM_BASE 0x40200000
34 # define OMAP2_L3_BASE 0x68000000
35 # define OMAP2_Q2_BASE 0x80000000
36 # define OMAP2_Q3_BASE 0xc0000000
37 # define OMAP_MPUI_BASE 0xe1000000
39 # define OMAP730_SRAM_SIZE 0x00032000
40 # define OMAP15XX_SRAM_SIZE 0x00030000
41 # define OMAP16XX_SRAM_SIZE 0x00004000
42 # define OMAP1611_SRAM_SIZE 0x0003e800
43 # define OMAP242X_SRAM_SIZE 0x000a0000
44 # define OMAP243X_SRAM_SIZE 0x00010000
45 # define OMAP_CS0_SIZE 0x04000000
46 # define OMAP_CS1_SIZE 0x04000000
47 # define OMAP_CS2_SIZE 0x04000000
48 # define OMAP_CS3_SIZE 0x04000000
51 struct omap_mpu_state_s
;
52 typedef struct clk
*omap_clk
;
53 omap_clk
omap_findclk(struct omap_mpu_state_s
*mpu
, const char *name
);
54 void omap_clk_init(struct omap_mpu_state_s
*mpu
);
55 void omap_clk_adduser(struct clk
*clk
, qemu_irq user
);
56 void omap_clk_get(omap_clk clk
);
57 void omap_clk_put(omap_clk clk
);
58 void omap_clk_onoff(omap_clk clk
, int on
);
59 void omap_clk_canidle(omap_clk clk
, int can
);
60 void omap_clk_setrate(omap_clk clk
, int divide
, int multiply
);
61 int64_t omap_clk_getrate(omap_clk clk
);
62 void omap_clk_reparent(omap_clk clk
, omap_clk parent
);
66 struct omap_l4_s
*omap_l4_init(target_phys_addr_t base
, int ta_num
);
68 struct omap_target_agent_s
;
69 struct omap_target_agent_s
*omap_l4ta_get(struct omap_l4_s
*bus
, int cs
);
70 target_phys_addr_t
omap_l4_attach(struct omap_target_agent_s
*ta
, int region
,
72 # define l4_register_io_memory cpu_register_io_memory
74 /* OMAP interrupt controller */
75 struct omap_intr_handler_s
;
76 struct omap_intr_handler_s
*omap_inth_init(target_phys_addr_t base
,
77 unsigned long size
, unsigned char nbanks
, qemu_irq
**pins
,
78 qemu_irq parent_irq
, qemu_irq parent_fiq
, omap_clk clk
);
79 struct omap_intr_handler_s
*omap2_inth_init(target_phys_addr_t base
,
80 int size
, int nbanks
, qemu_irq
**pins
,
81 qemu_irq parent_irq
, qemu_irq parent_fiq
,
82 omap_clk fclk
, omap_clk iclk
);
83 void omap_inth_reset(struct omap_intr_handler_s
*s
);
84 qemu_irq
omap_inth_get_pin(struct omap_intr_handler_s
*s
, int n
);
87 struct omap_prcm_s
*omap_prcm_init(struct omap_target_agent_s
*ta
,
88 qemu_irq mpu_int
, qemu_irq dsp_int
, qemu_irq iva_int
,
89 struct omap_mpu_state_s
*mpu
);
92 struct omap_sysctl_s
*omap_sysctl_init(struct omap_target_agent_s
*ta
,
93 omap_clk iclk
, struct omap_mpu_state_s
*mpu
);
95 /* OMAP2 SDRAM controller */
97 struct omap_sdrc_s
*omap_sdrc_init(target_phys_addr_t base
);
98 void omap_sdrc_reset(struct omap_sdrc_s
*s
);
100 /* OMAP2 general purpose memory controller */
102 struct omap_gpmc_s
*omap_gpmc_init(target_phys_addr_t base
, qemu_irq irq
);
103 void omap_gpmc_reset(struct omap_gpmc_s
*s
);
104 void omap_gpmc_attach(struct omap_gpmc_s
*s
, int cs
, int iomemtype
,
105 void (*base_upd
)(void *opaque
, target_phys_addr_t
new),
106 void (*unmap
)(void *opaque
), void *opaque
);
109 * Common IRQ numbers for level 1 interrupt handler
110 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
112 # define OMAP_INT_CAMERA 1
113 # define OMAP_INT_FIQ 3
114 # define OMAP_INT_RTDX 6
115 # define OMAP_INT_DSP_MMU_ABORT 7
116 # define OMAP_INT_HOST 8
117 # define OMAP_INT_ABORT 9
118 # define OMAP_INT_BRIDGE_PRIV 13
119 # define OMAP_INT_GPIO_BANK1 14
120 # define OMAP_INT_UART3 15
121 # define OMAP_INT_TIMER3 16
122 # define OMAP_INT_DMA_CH0_6 19
123 # define OMAP_INT_DMA_CH1_7 20
124 # define OMAP_INT_DMA_CH2_8 21
125 # define OMAP_INT_DMA_CH3 22
126 # define OMAP_INT_DMA_CH4 23
127 # define OMAP_INT_DMA_CH5 24
128 # define OMAP_INT_DMA_LCD 25
129 # define OMAP_INT_TIMER1 26
130 # define OMAP_INT_WD_TIMER 27
131 # define OMAP_INT_BRIDGE_PUB 28
132 # define OMAP_INT_TIMER2 30
133 # define OMAP_INT_LCD_CTRL 31
136 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
138 # define OMAP_INT_15XX_IH2_IRQ 0
139 # define OMAP_INT_15XX_LB_MMU 17
140 # define OMAP_INT_15XX_LOCAL_BUS 29
143 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
145 # define OMAP_INT_1510_SPI_TX 4
146 # define OMAP_INT_1510_SPI_RX 5
147 # define OMAP_INT_1510_DSP_MAILBOX1 10
148 # define OMAP_INT_1510_DSP_MAILBOX2 11
151 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
153 # define OMAP_INT_310_McBSP2_TX 4
154 # define OMAP_INT_310_McBSP2_RX 5
155 # define OMAP_INT_310_HSB_MAILBOX1 12
156 # define OMAP_INT_310_HSAB_MMU 18
159 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
161 # define OMAP_INT_1610_IH2_IRQ 0
162 # define OMAP_INT_1610_IH2_FIQ 2
163 # define OMAP_INT_1610_McBSP2_TX 4
164 # define OMAP_INT_1610_McBSP2_RX 5
165 # define OMAP_INT_1610_DSP_MAILBOX1 10
166 # define OMAP_INT_1610_DSP_MAILBOX2 11
167 # define OMAP_INT_1610_LCD_LINE 12
168 # define OMAP_INT_1610_GPTIMER1 17
169 # define OMAP_INT_1610_GPTIMER2 18
170 # define OMAP_INT_1610_SSR_FIFO_0 29
173 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
175 # define OMAP_INT_730_IH2_FIQ 0
176 # define OMAP_INT_730_IH2_IRQ 1
177 # define OMAP_INT_730_USB_NON_ISO 2
178 # define OMAP_INT_730_USB_ISO 3
179 # define OMAP_INT_730_ICR 4
180 # define OMAP_INT_730_EAC 5
181 # define OMAP_INT_730_GPIO_BANK1 6
182 # define OMAP_INT_730_GPIO_BANK2 7
183 # define OMAP_INT_730_GPIO_BANK3 8
184 # define OMAP_INT_730_McBSP2TX 10
185 # define OMAP_INT_730_McBSP2RX 11
186 # define OMAP_INT_730_McBSP2RX_OVF 12
187 # define OMAP_INT_730_LCD_LINE 14
188 # define OMAP_INT_730_GSM_PROTECT 15
189 # define OMAP_INT_730_TIMER3 16
190 # define OMAP_INT_730_GPIO_BANK5 17
191 # define OMAP_INT_730_GPIO_BANK6 18
192 # define OMAP_INT_730_SPGIO_WR 29
195 * Common IRQ numbers for level 2 interrupt handler
197 # define OMAP_INT_KEYBOARD 1
198 # define OMAP_INT_uWireTX 2
199 # define OMAP_INT_uWireRX 3
200 # define OMAP_INT_I2C 4
201 # define OMAP_INT_MPUIO 5
202 # define OMAP_INT_USB_HHC_1 6
203 # define OMAP_INT_McBSP3TX 10
204 # define OMAP_INT_McBSP3RX 11
205 # define OMAP_INT_McBSP1TX 12
206 # define OMAP_INT_McBSP1RX 13
207 # define OMAP_INT_UART1 14
208 # define OMAP_INT_UART2 15
209 # define OMAP_INT_USB_W2FC 20
210 # define OMAP_INT_1WIRE 21
211 # define OMAP_INT_OS_TIMER 22
212 # define OMAP_INT_OQN 23
213 # define OMAP_INT_GAUGE_32K 24
214 # define OMAP_INT_RTC_TIMER 25
215 # define OMAP_INT_RTC_ALARM 26
216 # define OMAP_INT_DSP_MMU 28
219 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
221 # define OMAP_INT_1510_BT_MCSI1TX 16
222 # define OMAP_INT_1510_BT_MCSI1RX 17
223 # define OMAP_INT_1510_SoSSI_MATCH 19
224 # define OMAP_INT_1510_MEM_STICK 27
225 # define OMAP_INT_1510_COM_SPI_RO 31
228 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
230 # define OMAP_INT_310_FAC 0
231 # define OMAP_INT_310_USB_HHC_2 7
232 # define OMAP_INT_310_MCSI1_FE 16
233 # define OMAP_INT_310_MCSI2_FE 17
234 # define OMAP_INT_310_USB_W2FC_ISO 29
235 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
236 # define OMAP_INT_310_McBSP2RX_OF 31
239 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
241 # define OMAP_INT_1610_FAC 0
242 # define OMAP_INT_1610_USB_HHC_2 7
243 # define OMAP_INT_1610_USB_OTG 8
244 # define OMAP_INT_1610_SoSSI 9
245 # define OMAP_INT_1610_BT_MCSI1TX 16
246 # define OMAP_INT_1610_BT_MCSI1RX 17
247 # define OMAP_INT_1610_SoSSI_MATCH 19
248 # define OMAP_INT_1610_MEM_STICK 27
249 # define OMAP_INT_1610_McBSP2RX_OF 31
250 # define OMAP_INT_1610_STI 32
251 # define OMAP_INT_1610_STI_WAKEUP 33
252 # define OMAP_INT_1610_GPTIMER3 34
253 # define OMAP_INT_1610_GPTIMER4 35
254 # define OMAP_INT_1610_GPTIMER5 36
255 # define OMAP_INT_1610_GPTIMER6 37
256 # define OMAP_INT_1610_GPTIMER7 38
257 # define OMAP_INT_1610_GPTIMER8 39
258 # define OMAP_INT_1610_GPIO_BANK2 40
259 # define OMAP_INT_1610_GPIO_BANK3 41
260 # define OMAP_INT_1610_MMC2 42
261 # define OMAP_INT_1610_CF 43
262 # define OMAP_INT_1610_WAKE_UP_REQ 46
263 # define OMAP_INT_1610_GPIO_BANK4 48
264 # define OMAP_INT_1610_SPI 49
265 # define OMAP_INT_1610_DMA_CH6 53
266 # define OMAP_INT_1610_DMA_CH7 54
267 # define OMAP_INT_1610_DMA_CH8 55
268 # define OMAP_INT_1610_DMA_CH9 56
269 # define OMAP_INT_1610_DMA_CH10 57
270 # define OMAP_INT_1610_DMA_CH11 58
271 # define OMAP_INT_1610_DMA_CH12 59
272 # define OMAP_INT_1610_DMA_CH13 60
273 # define OMAP_INT_1610_DMA_CH14 61
274 # define OMAP_INT_1610_DMA_CH15 62
275 # define OMAP_INT_1610_NAND 63
278 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
280 # define OMAP_INT_730_HW_ERRORS 0
281 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
282 # define OMAP_INT_730_CFCD 2
283 # define OMAP_INT_730_CFIREQ 3
284 # define OMAP_INT_730_I2C 4
285 # define OMAP_INT_730_PCC 5
286 # define OMAP_INT_730_MPU_EXT_NIRQ 6
287 # define OMAP_INT_730_SPI_100K_1 7
288 # define OMAP_INT_730_SYREN_SPI 8
289 # define OMAP_INT_730_VLYNQ 9
290 # define OMAP_INT_730_GPIO_BANK4 10
291 # define OMAP_INT_730_McBSP1TX 11
292 # define OMAP_INT_730_McBSP1RX 12
293 # define OMAP_INT_730_McBSP1RX_OF 13
294 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
295 # define OMAP_INT_730_UART_MODEM_1 15
296 # define OMAP_INT_730_MCSI 16
297 # define OMAP_INT_730_uWireTX 17
298 # define OMAP_INT_730_uWireRX 18
299 # define OMAP_INT_730_SMC_CD 19
300 # define OMAP_INT_730_SMC_IREQ 20
301 # define OMAP_INT_730_HDQ_1WIRE 21
302 # define OMAP_INT_730_TIMER32K 22
303 # define OMAP_INT_730_MMC_SDIO 23
304 # define OMAP_INT_730_UPLD 24
305 # define OMAP_INT_730_USB_HHC_1 27
306 # define OMAP_INT_730_USB_HHC_2 28
307 # define OMAP_INT_730_USB_GENI 29
308 # define OMAP_INT_730_USB_OTG 30
309 # define OMAP_INT_730_CAMERA_IF 31
310 # define OMAP_INT_730_RNG 32
311 # define OMAP_INT_730_DUAL_MODE_TIMER 33
312 # define OMAP_INT_730_DBB_RF_EN 34
313 # define OMAP_INT_730_MPUIO_KEYPAD 35
314 # define OMAP_INT_730_SHA1_MD5 36
315 # define OMAP_INT_730_SPI_100K_2 37
316 # define OMAP_INT_730_RNG_IDLE 38
317 # define OMAP_INT_730_MPUIO 39
318 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
319 # define OMAP_INT_730_LLPC_OE_FALLING 41
320 # define OMAP_INT_730_LLPC_OE_RISING 42
321 # define OMAP_INT_730_LLPC_VSYNC 43
322 # define OMAP_INT_730_WAKE_UP_REQ 46
323 # define OMAP_INT_730_DMA_CH6 53
324 # define OMAP_INT_730_DMA_CH7 54
325 # define OMAP_INT_730_DMA_CH8 55
326 # define OMAP_INT_730_DMA_CH9 56
327 # define OMAP_INT_730_DMA_CH10 57
328 # define OMAP_INT_730_DMA_CH11 58
329 # define OMAP_INT_730_DMA_CH12 59
330 # define OMAP_INT_730_DMA_CH13 60
331 # define OMAP_INT_730_DMA_CH14 61
332 # define OMAP_INT_730_DMA_CH15 62
333 # define OMAP_INT_730_NAND 63
336 * OMAP-24xx common IRQ numbers
338 # define OMAP_INT_24XX_STI 4
339 # define OMAP_INT_24XX_SYS_NIRQ 7
340 # define OMAP_INT_24XX_L3_IRQ 10
341 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
342 # define OMAP_INT_24XX_SDMA_IRQ0 12
343 # define OMAP_INT_24XX_SDMA_IRQ1 13
344 # define OMAP_INT_24XX_SDMA_IRQ2 14
345 # define OMAP_INT_24XX_SDMA_IRQ3 15
346 # define OMAP_INT_243X_MCBSP2_IRQ 16
347 # define OMAP_INT_243X_MCBSP3_IRQ 17
348 # define OMAP_INT_243X_MCBSP4_IRQ 18
349 # define OMAP_INT_243X_MCBSP5_IRQ 19
350 # define OMAP_INT_24XX_GPMC_IRQ 20
351 # define OMAP_INT_24XX_GUFFAW_IRQ 21
352 # define OMAP_INT_24XX_IVA_IRQ 22
353 # define OMAP_INT_24XX_EAC_IRQ 23
354 # define OMAP_INT_24XX_CAM_IRQ 24
355 # define OMAP_INT_24XX_DSS_IRQ 25
356 # define OMAP_INT_24XX_MAIL_U0_MPU 26
357 # define OMAP_INT_24XX_DSP_UMA 27
358 # define OMAP_INT_24XX_DSP_MMU 28
359 # define OMAP_INT_24XX_GPIO_BANK1 29
360 # define OMAP_INT_24XX_GPIO_BANK2 30
361 # define OMAP_INT_24XX_GPIO_BANK3 31
362 # define OMAP_INT_24XX_GPIO_BANK4 32
363 # define OMAP_INT_243X_GPIO_BANK5 33
364 # define OMAP_INT_24XX_MAIL_U3_MPU 34
365 # define OMAP_INT_24XX_WDT3 35
366 # define OMAP_INT_24XX_WDT4 36
367 # define OMAP_INT_24XX_GPTIMER1 37
368 # define OMAP_INT_24XX_GPTIMER2 38
369 # define OMAP_INT_24XX_GPTIMER3 39
370 # define OMAP_INT_24XX_GPTIMER4 40
371 # define OMAP_INT_24XX_GPTIMER5 41
372 # define OMAP_INT_24XX_GPTIMER6 42
373 # define OMAP_INT_24XX_GPTIMER7 43
374 # define OMAP_INT_24XX_GPTIMER8 44
375 # define OMAP_INT_24XX_GPTIMER9 45
376 # define OMAP_INT_24XX_GPTIMER10 46
377 # define OMAP_INT_24XX_GPTIMER11 47
378 # define OMAP_INT_24XX_GPTIMER12 48
379 # define OMAP_INT_24XX_PKA_IRQ 50
380 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
381 # define OMAP_INT_24XX_RNG_IRQ 52
382 # define OMAP_INT_24XX_MG_IRQ 53
383 # define OMAP_INT_24XX_I2C1_IRQ 56
384 # define OMAP_INT_24XX_I2C2_IRQ 57
385 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
386 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
387 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
388 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
389 # define OMAP_INT_243X_MCBSP1_IRQ 64
390 # define OMAP_INT_24XX_MCSPI1_IRQ 65
391 # define OMAP_INT_24XX_MCSPI2_IRQ 66
392 # define OMAP_INT_24XX_SSI1_IRQ0 67
393 # define OMAP_INT_24XX_SSI1_IRQ1 68
394 # define OMAP_INT_24XX_SSI2_IRQ0 69
395 # define OMAP_INT_24XX_SSI2_IRQ1 70
396 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
397 # define OMAP_INT_24XX_UART1_IRQ 72
398 # define OMAP_INT_24XX_UART2_IRQ 73
399 # define OMAP_INT_24XX_UART3_IRQ 74
400 # define OMAP_INT_24XX_USB_IRQ_GEN 75
401 # define OMAP_INT_24XX_USB_IRQ_NISO 76
402 # define OMAP_INT_24XX_USB_IRQ_ISO 77
403 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
404 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
405 # define OMAP_INT_24XX_USB_IRQ_OTG 80
406 # define OMAP_INT_24XX_VLYNQ_IRQ 81
407 # define OMAP_INT_24XX_MMC_IRQ 83
408 # define OMAP_INT_24XX_MS_IRQ 84
409 # define OMAP_INT_24XX_FAC_IRQ 85
410 # define OMAP_INT_24XX_MCSPI3_IRQ 91
411 # define OMAP_INT_243X_HS_USB_MC 92
412 # define OMAP_INT_243X_HS_USB_DMA 93
413 # define OMAP_INT_243X_CARKIT 94
414 # define OMAP_INT_34XX_GPTIMER12 95
417 enum omap_dma_model
{
425 struct soc_dma_s
*omap_dma_init(target_phys_addr_t base
, qemu_irq
*irqs
,
426 qemu_irq lcd_irq
, struct omap_mpu_state_s
*mpu
, omap_clk clk
,
427 enum omap_dma_model model
);
428 struct soc_dma_s
*omap_dma4_init(target_phys_addr_t base
, qemu_irq
*irqs
,
429 struct omap_mpu_state_s
*mpu
, int fifo
,
430 int chans
, omap_clk iclk
, omap_clk fclk
);
431 void omap_dma_reset(struct soc_dma_s
*s
);
438 /* Only used in OMAP DMA 3.x gigacells */
442 imif
, /* omap16xx: ocp_t1 */
444 local
, /* omap16xx: ocp_t2 */
446 __omap_dma_port_last
,
454 } omap_dma_addressing_t
;
456 /* Only used in OMAP DMA 3.x gigacells */
457 struct omap_dma_lcd_channel_s
{
458 enum omap_dma_port src
;
459 target_phys_addr_t src_f1_top
;
460 target_phys_addr_t src_f1_bottom
;
461 target_phys_addr_t src_f2_top
;
462 target_phys_addr_t src_f2_bottom
;
464 /* Used in OMAP DMA 3.2 gigacell */
465 unsigned char brust_f1
;
466 unsigned char pack_f1
;
467 unsigned char data_type_f1
;
468 unsigned char brust_f2
;
469 unsigned char pack_f2
;
470 unsigned char data_type_f2
;
471 unsigned char end_prog
;
472 unsigned char repeat
;
473 unsigned char auto_init
;
474 unsigned char priority
;
476 unsigned char running
;
478 unsigned char omap_3_1_compatible_disable
;
480 unsigned char lch_type
;
481 int16_t element_index_f1
;
482 int16_t element_index_f2
;
483 int32_t frame_index_f1
;
484 int32_t frame_index_f2
;
485 uint16_t elements_f1
;
487 uint16_t elements_f2
;
489 omap_dma_addressing_t mode_f1
;
490 omap_dma_addressing_t mode_f2
;
492 /* Destination port is fixed. */
498 target_phys_addr_t phys_framebuffer
[2];
500 struct omap_mpu_state_s
*mpu
;
501 } *omap_dma_get_lcdch(struct soc_dma_s
*s
);
504 * DMA request numbers for OMAP1
505 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
507 # define OMAP_DMA_NO_DEVICE 0
508 # define OMAP_DMA_MCSI1_TX 1
509 # define OMAP_DMA_MCSI1_RX 2
510 # define OMAP_DMA_I2C_RX 3
511 # define OMAP_DMA_I2C_TX 4
512 # define OMAP_DMA_EXT_NDMA_REQ0 5
513 # define OMAP_DMA_EXT_NDMA_REQ1 6
514 # define OMAP_DMA_UWIRE_TX 7
515 # define OMAP_DMA_MCBSP1_TX 8
516 # define OMAP_DMA_MCBSP1_RX 9
517 # define OMAP_DMA_MCBSP3_TX 10
518 # define OMAP_DMA_MCBSP3_RX 11
519 # define OMAP_DMA_UART1_TX 12
520 # define OMAP_DMA_UART1_RX 13
521 # define OMAP_DMA_UART2_TX 14
522 # define OMAP_DMA_UART2_RX 15
523 # define OMAP_DMA_MCBSP2_TX 16
524 # define OMAP_DMA_MCBSP2_RX 17
525 # define OMAP_DMA_UART3_TX 18
526 # define OMAP_DMA_UART3_RX 19
527 # define OMAP_DMA_CAMERA_IF_RX 20
528 # define OMAP_DMA_MMC_TX 21
529 # define OMAP_DMA_MMC_RX 22
530 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
531 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
532 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
533 # define OMAP_DMA_USB_W2FC_RX0 26
534 # define OMAP_DMA_USB_W2FC_RX1 27
535 # define OMAP_DMA_USB_W2FC_RX2 28
536 # define OMAP_DMA_USB_W2FC_TX0 29
537 # define OMAP_DMA_USB_W2FC_TX1 30
538 # define OMAP_DMA_USB_W2FC_TX2 31
540 /* These are only for 1610 */
541 # define OMAP_DMA_CRYPTO_DES_IN 32
542 # define OMAP_DMA_SPI_TX 33
543 # define OMAP_DMA_SPI_RX 34
544 # define OMAP_DMA_CRYPTO_HASH 35
545 # define OMAP_DMA_CCP_ATTN 36
546 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
547 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
548 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
549 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
550 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
551 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
552 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
553 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
554 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
555 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
556 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
557 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
558 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
559 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
560 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
561 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
562 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
563 # define OMAP_DMA_MMC2_TX 54
564 # define OMAP_DMA_MMC2_RX 55
565 # define OMAP_DMA_CRYPTO_DES_OUT 56
568 * DMA request numbers for the OMAP2
570 # define OMAP24XX_DMA_NO_DEVICE 0
571 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
572 # define OMAP24XX_DMA_EXT_DMAREQ0 2
573 # define OMAP24XX_DMA_EXT_DMAREQ1 3
574 # define OMAP24XX_DMA_GPMC 4
575 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
576 # define OMAP24XX_DMA_DSS 6
577 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
578 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
579 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
580 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
581 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
582 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
583 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
584 # define OMAP24XX_DMA_EXT_DMAREQ2 14
585 # define OMAP24XX_DMA_EXT_DMAREQ3 15
586 # define OMAP24XX_DMA_EXT_DMAREQ4 16
587 # define OMAP24XX_DMA_EAC_AC_RD 17
588 # define OMAP24XX_DMA_EAC_AC_WR 18
589 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
590 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
591 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
592 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
593 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
594 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
595 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
596 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
597 # define OMAP24XX_DMA_I2C1_TX 27
598 # define OMAP24XX_DMA_I2C1_RX 28
599 # define OMAP24XX_DMA_I2C2_TX 29
600 # define OMAP24XX_DMA_I2C2_RX 30
601 # define OMAP24XX_DMA_MCBSP1_TX 31
602 # define OMAP24XX_DMA_MCBSP1_RX 32
603 # define OMAP24XX_DMA_MCBSP2_TX 33
604 # define OMAP24XX_DMA_MCBSP2_RX 34
605 # define OMAP24XX_DMA_SPI1_TX0 35
606 # define OMAP24XX_DMA_SPI1_RX0 36
607 # define OMAP24XX_DMA_SPI1_TX1 37
608 # define OMAP24XX_DMA_SPI1_RX1 38
609 # define OMAP24XX_DMA_SPI1_TX2 39
610 # define OMAP24XX_DMA_SPI1_RX2 40
611 # define OMAP24XX_DMA_SPI1_TX3 41
612 # define OMAP24XX_DMA_SPI1_RX3 42
613 # define OMAP24XX_DMA_SPI2_TX0 43
614 # define OMAP24XX_DMA_SPI2_RX0 44
615 # define OMAP24XX_DMA_SPI2_TX1 45
616 # define OMAP24XX_DMA_SPI2_RX1 46
618 # define OMAP24XX_DMA_UART1_TX 49
619 # define OMAP24XX_DMA_UART1_RX 50
620 # define OMAP24XX_DMA_UART2_TX 51
621 # define OMAP24XX_DMA_UART2_RX 52
622 # define OMAP24XX_DMA_UART3_TX 53
623 # define OMAP24XX_DMA_UART3_RX 54
624 # define OMAP24XX_DMA_USB_W2FC_TX0 55
625 # define OMAP24XX_DMA_USB_W2FC_RX0 56
626 # define OMAP24XX_DMA_USB_W2FC_TX1 57
627 # define OMAP24XX_DMA_USB_W2FC_RX1 58
628 # define OMAP24XX_DMA_USB_W2FC_TX2 59
629 # define OMAP24XX_DMA_USB_W2FC_RX2 60
630 # define OMAP24XX_DMA_MMC1_TX 61
631 # define OMAP24XX_DMA_MMC1_RX 62
632 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
633 # define OMAP24XX_DMA_EXT_DMAREQ5 64
636 struct omap_mpu_timer_s
;
637 struct omap_mpu_timer_s
*omap_mpu_timer_init(target_phys_addr_t base
,
638 qemu_irq irq
, omap_clk clk
);
641 struct omap_gp_timer_s
;
642 struct omap_gp_timer_s
*omap_gp_timer_init(struct omap_target_agent_s
*ta
,
643 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
);
644 void omap_gp_timer_reset(struct omap_gp_timer_s
*s
);
646 struct omap_watchdog_timer_s
;
647 struct omap_watchdog_timer_s
*omap_wd_timer_init(target_phys_addr_t base
,
648 qemu_irq irq
, omap_clk clk
);
650 struct omap_32khz_timer_s
;
651 struct omap_32khz_timer_s
*omap_os_timer_init(target_phys_addr_t base
,
652 qemu_irq irq
, omap_clk clk
);
654 /* OMAP2 sysctimer */
655 struct omap_synctimer_s
;
656 struct omap_synctimer_s
*omap_synctimer_init(struct omap_target_agent_s
*ta
,
657 struct omap_mpu_state_s
*mpu
, omap_clk fclk
, omap_clk iclk
);
658 void omap_synctimer_reset(struct omap_synctimer_s
*s
);
660 struct omap_tipb_bridge_s
;
661 struct omap_tipb_bridge_s
*omap_tipb_bridge_init(target_phys_addr_t base
,
662 qemu_irq abort_irq
, omap_clk clk
);
665 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
666 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
667 qemu_irq txdma
, qemu_irq rxdma
, CharDriverState
*chr
);
668 struct omap_uart_s
*omap2_uart_init(struct omap_target_agent_s
*ta
,
669 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
670 qemu_irq txdma
, qemu_irq rxdma
, CharDriverState
*chr
);
671 void omap_uart_reset(struct omap_uart_s
*s
);
672 void omap_uart_attach(struct omap_uart_s
*s
, CharDriverState
*chr
);
675 struct omap_mpuio_s
*omap_mpuio_init(target_phys_addr_t base
,
676 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
678 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
);
679 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
);
680 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
);
682 /* omap1 gpio module interface */
684 struct omap_gpio_s
*omap_gpio_init(target_phys_addr_t base
,
685 qemu_irq irq
, omap_clk clk
);
686 void omap_gpio_reset(struct omap_gpio_s
*s
);
687 qemu_irq
*omap_gpio_in_get(struct omap_gpio_s
*s
);
688 void omap_gpio_out_set(struct omap_gpio_s
*s
, int line
, qemu_irq handler
);
690 /* omap2 gpio interface */
692 struct omap_gpif_s
*omap2_gpio_init(struct omap_target_agent_s
*ta
,
693 qemu_irq
*irq
, omap_clk
*fclk
, omap_clk iclk
, int modules
);
694 void omap_gpif_reset(struct omap_gpif_s
*s
);
695 qemu_irq
*omap2_gpio_in_get(struct omap_gpif_s
*s
, int start
);
696 void omap2_gpio_out_set(struct omap_gpif_s
*s
, int line
, qemu_irq handler
);
699 uint16_t (*receive
)(void *opaque
);
700 void (*send
)(void *opaque
, uint16_t data
);
704 struct omap_uwire_s
*omap_uwire_init(target_phys_addr_t base
,
705 qemu_irq
*irq
, qemu_irq dma
, omap_clk clk
);
706 void omap_uwire_attach(struct omap_uwire_s
*s
,
707 uWireSlave
*slave
, int chipselect
);
711 struct omap_mcspi_s
*omap_mcspi_init(struct omap_target_agent_s
*ta
, int chnum
,
712 qemu_irq irq
, qemu_irq
*drq
, omap_clk fclk
, omap_clk iclk
);
713 void omap_mcspi_attach(struct omap_mcspi_s
*s
,
714 uint32_t (*txrx
)(void *opaque
, uint32_t, int), void *opaque
,
716 void omap_mcspi_reset(struct omap_mcspi_s
*s
);
719 struct omap_rtc_s
*omap_rtc_init(target_phys_addr_t base
,
720 qemu_irq
*irq
, omap_clk clk
);
725 /* The CPU can call this if it is generating the clock signal on the
726 * i2s port. The CODEC can ignore it if it is set up as a clock
727 * master and generates its own clock. */
728 void (*set_rate
)(void *opaque
, int in
, int out
);
730 void (*tx_swallow
)(void *opaque
);
747 struct omap_mcbsp_s
*omap_mcbsp_init(target_phys_addr_t base
,
748 qemu_irq
*irq
, qemu_irq
*dma
, omap_clk clk
);
749 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, I2SCodec
*slave
);
752 struct omap_lpg_s
*omap_lpg_init(target_phys_addr_t base
, omap_clk clk
);
754 void omap_tap_init(struct omap_target_agent_s
*ta
,
755 struct omap_mpu_state_s
*mpu
);
758 struct omap_eac_s
*omap_eac_init(struct omap_target_agent_s
*ta
,
759 qemu_irq irq
, qemu_irq
*drq
, omap_clk fclk
, omap_clk iclk
);
762 struct omap_lcd_panel_s
;
763 void omap_lcdc_reset(struct omap_lcd_panel_s
*s
);
764 struct omap_lcd_panel_s
*omap_lcdc_init(target_phys_addr_t base
, qemu_irq irq
,
765 struct omap_dma_lcd_channel_s
*dma
,
766 ram_addr_t imif_base
, ram_addr_t emiff_base
, omap_clk clk
);
771 void (*write
)(void *opaque
, int dc
, uint16_t value
);
772 void (*block
)(void *opaque
, int dc
, void *buf
, size_t len
, int pitch
);
773 uint16_t (*read
)(void *opaque
, int dc
);
776 void omap_dss_reset(struct omap_dss_s
*s
);
777 struct omap_dss_s
*omap_dss_init(struct omap_target_agent_s
*ta
,
778 target_phys_addr_t l3_base
,
779 qemu_irq irq
, qemu_irq drq
,
780 omap_clk fck1
, omap_clk fck2
, omap_clk ck54m
,
781 omap_clk ick1
, omap_clk ick2
);
782 void omap_rfbi_attach(struct omap_dss_s
*s
, int cs
, struct rfbi_chip_s
*chip
);
786 struct omap_mmc_s
*omap_mmc_init(target_phys_addr_t base
,
787 BlockDriverState
*bd
,
788 qemu_irq irq
, qemu_irq dma
[], omap_clk clk
);
789 struct omap_mmc_s
*omap2_mmc_init(struct omap_target_agent_s
*ta
,
790 BlockDriverState
*bd
, qemu_irq irq
, qemu_irq dma
[],
791 omap_clk fclk
, omap_clk iclk
);
792 void omap_mmc_reset(struct omap_mmc_s
*s
);
793 void omap_mmc_handlers(struct omap_mmc_s
*s
, qemu_irq ro
, qemu_irq cover
);
794 void omap_mmc_enable(struct omap_mmc_s
*s
, int enable
);
798 struct omap_i2c_s
*omap_i2c_init(target_phys_addr_t base
,
799 qemu_irq irq
, qemu_irq
*dma
, omap_clk clk
);
800 struct omap_i2c_s
*omap2_i2c_init(struct omap_target_agent_s
*ta
,
801 qemu_irq irq
, qemu_irq
*dma
, omap_clk fclk
, omap_clk iclk
);
802 void omap_i2c_reset(struct omap_i2c_s
*s
);
803 i2c_bus
*omap_i2c_bus(struct omap_i2c_s
*s
);
805 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
806 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
807 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
808 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
809 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
810 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
811 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
812 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
814 # define cpu_is_omap15xx(cpu) \
815 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
816 # define cpu_is_omap16xx(cpu) \
817 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
818 # define cpu_is_omap24xx(cpu) \
819 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
821 # define cpu_class_omap1(cpu) \
822 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
823 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
824 # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
826 struct omap_mpu_state_s
{
827 enum omap_mpu_model
{
847 struct omap_dma_port_if_s
{
848 uint32_t (*read
[3])(struct omap_mpu_state_s
*s
,
849 target_phys_addr_t offset
);
850 void (*write
[3])(struct omap_mpu_state_s
*s
,
851 target_phys_addr_t offset
, uint32_t value
);
852 int (*addr_valid
)(struct omap_mpu_state_s
*s
,
853 target_phys_addr_t addr
);
854 } port
[__omap_dma_port_last
];
856 unsigned long sdram_size
;
857 unsigned long sram_size
;
859 /* MPUI-TIPB peripherals */
860 struct omap_uart_s
*uart
[3];
862 struct omap_gpio_s
*gpio
;
864 struct omap_mcbsp_s
*mcbsp1
;
865 struct omap_mcbsp_s
*mcbsp3
;
867 /* MPU public TIPB peripherals */
868 struct omap_32khz_timer_s
*os_timer
;
870 struct omap_mmc_s
*mmc
;
872 struct omap_mpuio_s
*mpuio
;
874 struct omap_uwire_s
*microwire
;
890 struct omap_i2c_s
*i2c
[2];
892 struct omap_rtc_s
*rtc
;
894 struct omap_mcbsp_s
*mcbsp2
;
896 struct omap_lpg_s
*led
[2];
898 /* MPU private TIPB peripherals */
899 struct omap_intr_handler_s
*ih
[2];
901 struct soc_dma_s
*dma
;
903 struct omap_mpu_timer_s
*timer
[3];
904 struct omap_watchdog_timer_s
*wdt
;
906 struct omap_lcd_panel_s
*lcd
;
908 uint32_t ulpd_pm_regs
[21];
909 int64_t ulpd_gauge_start
;
911 uint32_t func_mux_ctrl
[14];
912 uint32_t comp_mode_ctrl
[1];
913 uint32_t pull_dwn_ctrl
[4];
914 uint32_t gate_inh_ctrl
[1];
915 uint32_t voltage_ctrl
[1];
916 uint32_t test_dbg_ctrl
[1];
917 uint32_t mod_conf_ctrl
[1];
922 struct omap_tipb_bridge_s
*private_tipb
;
923 struct omap_tipb_bridge_s
*public_tipb
;
925 uint32_t tcmi_regs
[17];
937 uint16_t arm_idlect1
;
938 uint16_t arm_idlect2
;
944 uint16_t dsp_idlect1
;
945 uint16_t dsp_idlect2
;
949 /* OMAP2-only peripherals */
950 struct omap_l4_s
*l4
;
952 struct omap_gp_timer_s
*gptimer
[12];
953 struct omap_synctimer_s
*synctimer
;
955 struct omap_prcm_s
*prcm
;
956 struct omap_sdrc_s
*sdrc
;
957 struct omap_gpmc_s
*gpmc
;
958 struct omap_sysctl_s
*sysc
;
960 struct omap_gpif_s
*gpif
;
962 struct omap_mcspi_s
*mcspi
[2];
964 struct omap_dss_s
*dss
;
966 struct omap_eac_s
*eac
;
970 struct omap_mpu_state_s
*omap310_mpu_init(unsigned long sdram_size
,
974 struct omap_mpu_state_s
*omap2420_mpu_init(unsigned long sdram_size
,
977 # if TARGET_PHYS_ADDR_BITS == 32
978 # define OMAP_FMT_plx "%#08x"
979 # elif TARGET_PHYS_ADDR_BITS == 64
980 # define OMAP_FMT_plx "%#08" PRIx64
982 # error TARGET_PHYS_ADDR_BITS undefined
985 uint32_t omap_badwidth_read8(void *opaque
, target_phys_addr_t addr
);
986 void omap_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
988 uint32_t omap_badwidth_read16(void *opaque
, target_phys_addr_t addr
);
989 void omap_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
991 uint32_t omap_badwidth_read32(void *opaque
, target_phys_addr_t addr
);
992 void omap_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
995 void omap_mpu_wakeup(void *opaque
, int irq
, int req
);
997 # define OMAP_BAD_REG(paddr) \
998 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1000 # define OMAP_RO_REG(paddr) \
1001 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1002 __FUNCTION__, paddr)
1004 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1005 (Board-specifc tags are not here) */
1006 #define OMAP_TAG_CLOCK 0x4f01
1007 #define OMAP_TAG_MMC 0x4f02
1008 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1009 #define OMAP_TAG_USB 0x4f04
1010 #define OMAP_TAG_LCD 0x4f05
1011 #define OMAP_TAG_GPIO_SWITCH 0x4f06
1012 #define OMAP_TAG_UART 0x4f07
1013 #define OMAP_TAG_FBMEM 0x4f08
1014 #define OMAP_TAG_STI_CONSOLE 0x4f09
1015 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1016 #define OMAP_TAG_PARTITION 0x4f0b
1017 #define OMAP_TAG_TEA5761 0x4f10
1018 #define OMAP_TAG_TMP105 0x4f11
1019 #define OMAP_TAG_BOOT_REASON 0x4f80
1020 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1021 #define OMAP_TAG_VERSION_STR 0x4f82
1024 OMAP_GPIOSW_TYPE_COVER
= 0 << 4,
1025 OMAP_GPIOSW_TYPE_CONNECTION
= 1 << 4,
1026 OMAP_GPIOSW_TYPE_ACTIVITY
= 2 << 4,
1029 #define OMAP_GPIOSW_INVERTED 0x0001
1030 #define OMAP_GPIOSW_OUTPUT 0x0002
1032 # define TCMI_VERBOSE 1
1033 //# define MEM_VERBOSE 1
1035 # ifdef TCMI_VERBOSE
1036 # define OMAP_8B_REG(paddr) \
1037 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1038 __FUNCTION__, paddr)
1039 # define OMAP_16B_REG(paddr) \
1040 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1041 __FUNCTION__, paddr)
1042 # define OMAP_32B_REG(paddr) \
1043 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1044 __FUNCTION__, paddr)
1046 # define OMAP_8B_REG(paddr)
1047 # define OMAP_16B_REG(paddr)
1048 # define OMAP_32B_REG(paddr)
1051 # define OMAP_MPUI_REG_MASK 0x000007ff
1055 CPUReadMemoryFunc
* const *mem_read
;
1056 CPUWriteMemoryFunc
* const *mem_write
;
1061 static uint32_t io_readb(void *opaque
, target_phys_addr_t addr
)
1063 struct io_fn
*s
= opaque
;
1067 ret
= s
->mem_read
[0](s
->opaque
, addr
);
1070 fprintf(stderr
, "%08x ---> %02x\n", (uint32_t) addr
, ret
);
1073 static uint32_t io_readh(void *opaque
, target_phys_addr_t addr
)
1075 struct io_fn
*s
= opaque
;
1079 ret
= s
->mem_read
[1](s
->opaque
, addr
);
1082 fprintf(stderr
, "%08x ---> %04x\n", (uint32_t) addr
, ret
);
1085 static uint32_t io_readw(void *opaque
, target_phys_addr_t addr
)
1087 struct io_fn
*s
= opaque
;
1091 ret
= s
->mem_read
[2](s
->opaque
, addr
);
1094 fprintf(stderr
, "%08x ---> %08x\n", (uint32_t) addr
, ret
);
1097 static void io_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1099 struct io_fn
*s
= opaque
;
1102 fprintf(stderr
, "%08x <--- %02x\n", (uint32_t) addr
, value
);
1104 s
->mem_write
[0](s
->opaque
, addr
, value
);
1107 static void io_writeh(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1109 struct io_fn
*s
= opaque
;
1112 fprintf(stderr
, "%08x <--- %04x\n", (uint32_t) addr
, value
);
1114 s
->mem_write
[1](s
->opaque
, addr
, value
);
1117 static void io_writew(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1119 struct io_fn
*s
= opaque
;
1122 fprintf(stderr
, "%08x <--- %08x\n", (uint32_t) addr
, value
);
1124 s
->mem_write
[2](s
->opaque
, addr
, value
);
1128 static CPUReadMemoryFunc
* const io_readfn
[] = { io_readb
, io_readh
, io_readw
, };
1129 static CPUWriteMemoryFunc
* const io_writefn
[] = { io_writeb
, io_writeh
, io_writew
, };
1131 inline static int debug_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
1132 CPUWriteMemoryFunc
* const *mem_write
,
1135 struct io_fn
*s
= qemu_malloc(sizeof(struct io_fn
));
1137 s
->mem_read
= mem_read
;
1138 s
->mem_write
= mem_write
;
1141 return cpu_register_io_memory(io_readfn
, io_writefn
, s
);
1143 # define cpu_register_io_memory debug_register_io_memory
1146 /* Define when we want to reduce the number of IO regions registered. */
1147 /*# define L4_MUX_HACK*/
1150 # undef l4_register_io_memory
1151 int l4_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
1152 CPUWriteMemoryFunc
* const *mem_write
, void *opaque
);
1155 #endif /* hw_omap_h */