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usb:xhci: no DMA on HC reset
[qemu.git] / hw / ppc / ppc.c
blob38ff2e1596ca9d070b91ec20e0ebb78c696e55b2
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu-common.h"
26 #include "cpu.h"
27 #include "hw/hw.h"
28 #include "hw/ppc/ppc.h"
29 #include "hw/ppc/ppc_e500.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/cpus.h"
33 #include "hw/timer/m48t59.h"
34 #include "qemu/log.h"
35 #include "qemu/error-report.h"
36 #include "hw/loader.h"
37 #include "sysemu/kvm.h"
38 #include "kvm_ppc.h"
39 #include "trace.h"
40
41 //#define PPC_DEBUG_IRQ
42 //#define PPC_DEBUG_TB
43
44 #ifdef PPC_DEBUG_IRQ
45 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
46 #else
47 # define LOG_IRQ(...) do { } while (0)
48 #endif
49
50
51 #ifdef PPC_DEBUG_TB
52 # define LOG_TB(...) qemu_log(__VA_ARGS__)
53 #else
54 # define LOG_TB(...) do { } while (0)
55 #endif
56
57 static void cpu_ppc_tb_stop (CPUPPCState *env);
58 static void cpu_ppc_tb_start (CPUPPCState *env);
59
60 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
61 {
62 CPUState *cs = CPU(cpu);
63 CPUPPCState *env = &cpu->env;
64 unsigned int old_pending = env->pending_interrupts;
65
66 if (level) {
67 env->pending_interrupts |= 1 << n_IRQ;
68 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
69 } else {
70 env->pending_interrupts &= ~(1 << n_IRQ);
71 if (env->pending_interrupts == 0) {
72 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
73 }
74 }
75
76 if (old_pending != env->pending_interrupts) {
77 #ifdef CONFIG_KVM
78 kvmppc_set_interrupt(cpu, n_IRQ, level);
79 #endif
80 }
81
82 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
83 "req %08x\n", __func__, env, n_IRQ, level,
84 env->pending_interrupts, CPU(cpu)->interrupt_request);
85 }
86
87 /* PowerPC 6xx / 7xx internal IRQ controller */
88 static void ppc6xx_set_irq(void *opaque, int pin, int level)
89 {
90 PowerPCCPU *cpu = opaque;
91 CPUPPCState *env = &cpu->env;
92 int cur_level;
93
94 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
95 env, pin, level);
96 cur_level = (env->irq_input_state >> pin) & 1;
97 /* Don't generate spurious events */
98 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
99 CPUState *cs = CPU(cpu);
100
101 switch (pin) {
102 case PPC6xx_INPUT_TBEN:
103 /* Level sensitive - active high */
104 LOG_IRQ("%s: %s the time base\n",
105 __func__, level ? "start" : "stop");
106 if (level) {
107 cpu_ppc_tb_start(env);
108 } else {
109 cpu_ppc_tb_stop(env);
110 }
111 case PPC6xx_INPUT_INT:
112 /* Level sensitive - active high */
113 LOG_IRQ("%s: set the external IRQ state to %d\n",
114 __func__, level);
115 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
116 break;
117 case PPC6xx_INPUT_SMI:
118 /* Level sensitive - active high */
119 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
120 __func__, level);
121 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
122 break;
123 case PPC6xx_INPUT_MCP:
124 /* Negative edge sensitive */
125 /* XXX: TODO: actual reaction may depends on HID0 status
126 * 603/604/740/750: check HID0[EMCP]
127 */
128 if (cur_level == 1 && level == 0) {
129 LOG_IRQ("%s: raise machine check state\n",
130 __func__);
131 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
132 }
133 break;
134 case PPC6xx_INPUT_CKSTP_IN:
135 /* Level sensitive - active low */
136 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
137 /* XXX: Note that the only way to restart the CPU is to reset it */
138 if (level) {
139 LOG_IRQ("%s: stop the CPU\n", __func__);
140 cs->halted = 1;
141 }
142 break;
143 case PPC6xx_INPUT_HRESET:
144 /* Level sensitive - active low */
145 if (level) {
146 LOG_IRQ("%s: reset the CPU\n", __func__);
147 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
148 }
149 break;
150 case PPC6xx_INPUT_SRESET:
151 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
152 __func__, level);
153 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
154 break;
155 default:
156 /* Unknown pin - do nothing */
157 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
158 return;
159 }
160 if (level)
161 env->irq_input_state |= 1 << pin;
162 else
163 env->irq_input_state &= ~(1 << pin);
164 }
165 }
166
167 void ppc6xx_irq_init(CPUPPCState *env)
168 {
169 PowerPCCPU *cpu = ppc_env_get_cpu(env);
170
171 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
172 PPC6xx_INPUT_NB);
173 }
174
175 #if defined(TARGET_PPC64)
176 /* PowerPC 970 internal IRQ controller */
177 static void ppc970_set_irq(void *opaque, int pin, int level)
178 {
179 PowerPCCPU *cpu = opaque;
180 CPUPPCState *env = &cpu->env;
181 int cur_level;
182
183 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
184 env, pin, level);
185 cur_level = (env->irq_input_state >> pin) & 1;
186 /* Don't generate spurious events */
187 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
188 CPUState *cs = CPU(cpu);
189
190 switch (pin) {
191 case PPC970_INPUT_INT:
192 /* Level sensitive - active high */
193 LOG_IRQ("%s: set the external IRQ state to %d\n",
194 __func__, level);
195 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
196 break;
197 case PPC970_INPUT_THINT:
198 /* Level sensitive - active high */
199 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
200 level);
201 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
202 break;
203 case PPC970_INPUT_MCP:
204 /* Negative edge sensitive */
205 /* XXX: TODO: actual reaction may depends on HID0 status
206 * 603/604/740/750: check HID0[EMCP]
207 */
208 if (cur_level == 1 && level == 0) {
209 LOG_IRQ("%s: raise machine check state\n",
210 __func__);
211 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
212 }
213 break;
214 case PPC970_INPUT_CKSTP:
215 /* Level sensitive - active low */
216 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
217 if (level) {
218 LOG_IRQ("%s: stop the CPU\n", __func__);
219 cs->halted = 1;
220 } else {
221 LOG_IRQ("%s: restart the CPU\n", __func__);
222 cs->halted = 0;
223 qemu_cpu_kick(cs);
224 }
225 break;
226 case PPC970_INPUT_HRESET:
227 /* Level sensitive - active low */
228 if (level) {
229 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
230 }
231 break;
232 case PPC970_INPUT_SRESET:
233 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
234 __func__, level);
235 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
236 break;
237 case PPC970_INPUT_TBEN:
238 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
239 level);
240 /* XXX: TODO */
241 break;
242 default:
243 /* Unknown pin - do nothing */
244 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
245 return;
246 }
247 if (level)
248 env->irq_input_state |= 1 << pin;
249 else
250 env->irq_input_state &= ~(1 << pin);
251 }
252 }
253
254 void ppc970_irq_init(CPUPPCState *env)
255 {
256 PowerPCCPU *cpu = ppc_env_get_cpu(env);
257
258 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
259 PPC970_INPUT_NB);
260 }
261
262 /* POWER7 internal IRQ controller */
263 static void power7_set_irq(void *opaque, int pin, int level)
264 {
265 PowerPCCPU *cpu = opaque;
266 CPUPPCState *env = &cpu->env;
267
268 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
269 env, pin, level);
270
271 switch (pin) {
272 case POWER7_INPUT_INT:
273 /* Level sensitive - active high */
274 LOG_IRQ("%s: set the external IRQ state to %d\n",
275 __func__, level);
276 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
277 break;
278 default:
279 /* Unknown pin - do nothing */
280 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
281 return;
282 }
283 if (level) {
284 env->irq_input_state |= 1 << pin;
285 } else {
286 env->irq_input_state &= ~(1 << pin);
287 }
288 }
289
290 void ppcPOWER7_irq_init(CPUPPCState *env)
291 {
292 PowerPCCPU *cpu = ppc_env_get_cpu(env);
293
294 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
295 POWER7_INPUT_NB);
296 }
297 #endif /* defined(TARGET_PPC64) */
298
299 /* PowerPC 40x internal IRQ controller */
300 static void ppc40x_set_irq(void *opaque, int pin, int level)
301 {
302 PowerPCCPU *cpu = opaque;
303 CPUPPCState *env = &cpu->env;
304 int cur_level;
305
306 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
307 env, pin, level);
308 cur_level = (env->irq_input_state >> pin) & 1;
309 /* Don't generate spurious events */
310 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
311 CPUState *cs = CPU(cpu);
312
313 switch (pin) {
314 case PPC40x_INPUT_RESET_SYS:
315 if (level) {
316 LOG_IRQ("%s: reset the PowerPC system\n",
317 __func__);
318 ppc40x_system_reset(cpu);
319 }
320 break;
321 case PPC40x_INPUT_RESET_CHIP:
322 if (level) {
323 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
324 ppc40x_chip_reset(cpu);
325 }
326 break;
327 case PPC40x_INPUT_RESET_CORE:
328 /* XXX: TODO: update DBSR[MRR] */
329 if (level) {
330 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
331 ppc40x_core_reset(cpu);
332 }
333 break;
334 case PPC40x_INPUT_CINT:
335 /* Level sensitive - active high */
336 LOG_IRQ("%s: set the critical IRQ state to %d\n",
337 __func__, level);
338 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
339 break;
340 case PPC40x_INPUT_INT:
341 /* Level sensitive - active high */
342 LOG_IRQ("%s: set the external IRQ state to %d\n",
343 __func__, level);
344 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
345 break;
346 case PPC40x_INPUT_HALT:
347 /* Level sensitive - active low */
348 if (level) {
349 LOG_IRQ("%s: stop the CPU\n", __func__);
350 cs->halted = 1;
351 } else {
352 LOG_IRQ("%s: restart the CPU\n", __func__);
353 cs->halted = 0;
354 qemu_cpu_kick(cs);
355 }
356 break;
357 case PPC40x_INPUT_DEBUG:
358 /* Level sensitive - active high */
359 LOG_IRQ("%s: set the debug pin state to %d\n",
360 __func__, level);
361 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
362 break;
363 default:
364 /* Unknown pin - do nothing */
365 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
366 return;
367 }
368 if (level)
369 env->irq_input_state |= 1 << pin;
370 else
371 env->irq_input_state &= ~(1 << pin);
372 }
373 }
374
375 void ppc40x_irq_init(CPUPPCState *env)
376 {
377 PowerPCCPU *cpu = ppc_env_get_cpu(env);
378
379 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
380 cpu, PPC40x_INPUT_NB);
381 }
382
383 /* PowerPC E500 internal IRQ controller */
384 static void ppce500_set_irq(void *opaque, int pin, int level)
385 {
386 PowerPCCPU *cpu = opaque;
387 CPUPPCState *env = &cpu->env;
388 int cur_level;
389
390 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
391 env, pin, level);
392 cur_level = (env->irq_input_state >> pin) & 1;
393 /* Don't generate spurious events */
394 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
395 switch (pin) {
396 case PPCE500_INPUT_MCK:
397 if (level) {
398 LOG_IRQ("%s: reset the PowerPC system\n",
399 __func__);
400 qemu_system_reset_request();
401 }
402 break;
403 case PPCE500_INPUT_RESET_CORE:
404 if (level) {
405 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
406 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
407 }
408 break;
409 case PPCE500_INPUT_CINT:
410 /* Level sensitive - active high */
411 LOG_IRQ("%s: set the critical IRQ state to %d\n",
412 __func__, level);
413 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
414 break;
415 case PPCE500_INPUT_INT:
416 /* Level sensitive - active high */
417 LOG_IRQ("%s: set the core IRQ state to %d\n",
418 __func__, level);
419 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
420 break;
421 case PPCE500_INPUT_DEBUG:
422 /* Level sensitive - active high */
423 LOG_IRQ("%s: set the debug pin state to %d\n",
424 __func__, level);
425 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
426 break;
427 default:
428 /* Unknown pin - do nothing */
429 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
430 return;
431 }
432 if (level)
433 env->irq_input_state |= 1 << pin;
434 else
435 env->irq_input_state &= ~(1 << pin);
436 }
437 }
438
439 void ppce500_irq_init(CPUPPCState *env)
440 {
441 PowerPCCPU *cpu = ppc_env_get_cpu(env);
442
443 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
444 cpu, PPCE500_INPUT_NB);
445 }
446
447 /* Enable or Disable the E500 EPR capability */
448 void ppce500_set_mpic_proxy(bool enabled)
449 {
450 CPUState *cs;
451
452 CPU_FOREACH(cs) {
453 PowerPCCPU *cpu = POWERPC_CPU(cs);
454
455 cpu->env.mpic_proxy = enabled;
456 if (kvm_enabled()) {
457 kvmppc_set_mpic_proxy(cpu, enabled);
458 }
459 }
460 }
461
462 /*****************************************************************************/
463 /* PowerPC time base and decrementer emulation */
464
465 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
466 {
467 /* TB time in tb periods */
468 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset;
469 }
470
471 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
472 {
473 ppc_tb_t *tb_env = env->tb_env;
474 uint64_t tb;
475
476 if (kvm_enabled()) {
477 return env->spr[SPR_TBL];
478 }
479
480 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
481 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
482
483 return tb;
484 }
485
486 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
487 {
488 ppc_tb_t *tb_env = env->tb_env;
489 uint64_t tb;
490
491 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
492 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
493
494 return tb >> 32;
495 }
496
497 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
498 {
499 if (kvm_enabled()) {
500 return env->spr[SPR_TBU];
501 }
502
503 return _cpu_ppc_load_tbu(env);
504 }
505
506 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
507 int64_t *tb_offsetp, uint64_t value)
508 {
509 *tb_offsetp = value -
510 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
511
512 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
513 __func__, value, *tb_offsetp);
514 }
515
516 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
517 {
518 ppc_tb_t *tb_env = env->tb_env;
519 uint64_t tb;
520
521 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
522 tb &= 0xFFFFFFFF00000000ULL;
523 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
524 &tb_env->tb_offset, tb | (uint64_t)value);
525 }
526
527 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
528 {
529 ppc_tb_t *tb_env = env->tb_env;
530 uint64_t tb;
531
532 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
533 tb &= 0x00000000FFFFFFFFULL;
534 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
535 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
536 }
537
538 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
539 {
540 _cpu_ppc_store_tbu(env, value);
541 }
542
543 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
544 {
545 ppc_tb_t *tb_env = env->tb_env;
546 uint64_t tb;
547
548 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
549 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
550
551 return tb;
552 }
553
554 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
555 {
556 ppc_tb_t *tb_env = env->tb_env;
557 uint64_t tb;
558
559 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
560 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
561
562 return tb >> 32;
563 }
564
565 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
566 {
567 ppc_tb_t *tb_env = env->tb_env;
568 uint64_t tb;
569
570 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
571 tb &= 0xFFFFFFFF00000000ULL;
572 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
573 &tb_env->atb_offset, tb | (uint64_t)value);
574 }
575
576 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
577 {
578 ppc_tb_t *tb_env = env->tb_env;
579 uint64_t tb;
580
581 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
582 tb &= 0x00000000FFFFFFFFULL;
583 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
584 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
585 }
586
587 static void cpu_ppc_tb_stop (CPUPPCState *env)
588 {
589 ppc_tb_t *tb_env = env->tb_env;
590 uint64_t tb, atb, vmclk;
591
592 /* If the time base is already frozen, do nothing */
593 if (tb_env->tb_freq != 0) {
594 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
595 /* Get the time base */
596 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
597 /* Get the alternate time base */
598 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
599 /* Store the time base value (ie compute the current offset) */
600 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
601 /* Store the alternate time base value (compute the current offset) */
602 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
603 /* Set the time base frequency to zero */
604 tb_env->tb_freq = 0;
605 /* Now, the time bases are frozen to tb_offset / atb_offset value */
606 }
607 }
608
609 static void cpu_ppc_tb_start (CPUPPCState *env)
610 {
611 ppc_tb_t *tb_env = env->tb_env;
612 uint64_t tb, atb, vmclk;
613
614 /* If the time base is not frozen, do nothing */
615 if (tb_env->tb_freq == 0) {
616 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
617 /* Get the time base from tb_offset */
618 tb = tb_env->tb_offset;
619 /* Get the alternate time base from atb_offset */
620 atb = tb_env->atb_offset;
621 /* Restore the tb frequency from the decrementer frequency */
622 tb_env->tb_freq = tb_env->decr_freq;
623 /* Store the time base value */
624 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
625 /* Store the alternate time base value */
626 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
627 }
628 }
629
630 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
631 {
632 ppc_tb_t *tb_env = env->tb_env;
633 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
634 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
635 }
636
637 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
638 {
639 ppc_tb_t *tb_env = env->tb_env;
640 uint32_t decr;
641 int64_t diff;
642
643 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
644 if (diff >= 0) {
645 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
646 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
647 decr = 0;
648 } else {
649 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
650 }
651 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
652
653 return decr;
654 }
655
656 uint32_t cpu_ppc_load_decr (CPUPPCState *env)
657 {
658 ppc_tb_t *tb_env = env->tb_env;
659
660 if (kvm_enabled()) {
661 return env->spr[SPR_DECR];
662 }
663
664 return _cpu_ppc_load_decr(env, tb_env->decr_next);
665 }
666
667 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
668 {
669 ppc_tb_t *tb_env = env->tb_env;
670
671 return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
672 }
673
674 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
675 {
676 ppc_tb_t *tb_env = env->tb_env;
677 uint64_t diff;
678
679 diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start;
680
681 return tb_env->purr_load +
682 muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
683 }
684
685 /* When decrementer expires,
686 * all we need to do is generate or queue a CPU exception
687 */
688 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
689 {
690 /* Raise it */
691 LOG_TB("raise decrementer exception\n");
692 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
693 }
694
695 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
696 {
697 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
698 }
699
700 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
701 {
702 /* Raise it */
703 LOG_TB("raise decrementer exception\n");
704 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
705 }
706
707 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
708 {
709 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
710 }
711
712 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
713 QEMUTimer *timer,
714 void (*raise_excp)(void *),
715 void (*lower_excp)(PowerPCCPU *),
716 uint32_t decr, uint32_t value)
717 {
718 CPUPPCState *env = &cpu->env;
719 ppc_tb_t *tb_env = env->tb_env;
720 uint64_t now, next;
721
722 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
723 decr, value);
724
725 if (kvm_enabled()) {
726 /* KVM handles decrementer exceptions, we don't need our own timer */
727 return;
728 }
729
730 /*
731 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
732 * interrupt.
733 *
734 * If we get a really small DEC value, we can assume that by the time we
735 * handled it we should inject an interrupt already.
736 *
737 * On MSB level based DEC implementations the MSB always means the interrupt
738 * is pending, so raise it on those.
739 *
740 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
741 * an edge interrupt, so raise it here too.
742 */
743 if ((value < 3) ||
744 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & 0x80000000)) ||
745 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & 0x80000000)
746 && !(decr & 0x80000000))) {
747 (*raise_excp)(cpu);
748 return;
749 }
750
751 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
752 if (!(value & 0x80000000) && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) {
753 (*lower_excp)(cpu);
754 }
755
756 /* Calculate the next timer event */
757 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
758 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
759 *nextp = next;
760
761 /* Adjust timer */
762 timer_mod(timer, next);
763 }
764
765 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
766 uint32_t value)
767 {
768 ppc_tb_t *tb_env = cpu->env.tb_env;
769
770 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
771 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr,
772 value);
773 }
774
775 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
776 {
777 PowerPCCPU *cpu = ppc_env_get_cpu(env);
778
779 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value);
780 }
781
782 static void cpu_ppc_decr_cb(void *opaque)
783 {
784 PowerPCCPU *cpu = opaque;
785
786 cpu_ppc_decr_excp(cpu);
787 }
788
789 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
790 uint32_t value)
791 {
792 ppc_tb_t *tb_env = cpu->env.tb_env;
793
794 if (tb_env->hdecr_timer != NULL) {
795 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
796 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
797 hdecr, value);
798 }
799 }
800
801 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
802 {
803 PowerPCCPU *cpu = ppc_env_get_cpu(env);
804
805 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value);
806 }
807
808 static void cpu_ppc_hdecr_cb(void *opaque)
809 {
810 PowerPCCPU *cpu = opaque;
811
812 cpu_ppc_hdecr_excp(cpu);
813 }
814
815 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
816 {
817 ppc_tb_t *tb_env = cpu->env.tb_env;
818
819 tb_env->purr_load = value;
820 tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
821 }
822
823 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
824 {
825 CPUPPCState *env = opaque;
826 PowerPCCPU *cpu = ppc_env_get_cpu(env);
827 ppc_tb_t *tb_env = env->tb_env;
828
829 tb_env->tb_freq = freq;
830 tb_env->decr_freq = freq;
831 /* There is a bug in Linux 2.4 kernels:
832 * if a decrementer exception is pending when it enables msr_ee at startup,
833 * it's not ready to handle it...
834 */
835 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
836 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
837 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
838 }
839
840 static void timebase_pre_save(void *opaque)
841 {
842 PPCTimebase *tb = opaque;
843 uint64_t ticks = cpu_get_host_ticks();
844 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
845
846 if (!first_ppc_cpu->env.tb_env) {
847 error_report("No timebase object");
848 return;
849 }
850
851 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
852 /*
853 * tb_offset is only expected to be changed by migration so
854 * there is no need to update it from KVM here
855 */
856 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
857 }
858
859 static int timebase_post_load(void *opaque, int version_id)
860 {
861 PPCTimebase *tb_remote = opaque;
862 CPUState *cpu;
863 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
864 int64_t tb_off_adj, tb_off, ns_diff;
865 int64_t migration_duration_ns, migration_duration_tb, guest_tb, host_ns;
866 unsigned long freq;
867
868 if (!first_ppc_cpu->env.tb_env) {
869 error_report("No timebase object");
870 return -1;
871 }
872
873 freq = first_ppc_cpu->env.tb_env->tb_freq;
874 /*
875 * Calculate timebase on the destination side of migration.
876 * The destination timebase must be not less than the source timebase.
877 * We try to adjust timebase by downtime if host clocks are not
878 * too much out of sync (1 second for now).
879 */
880 host_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
881 ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns);
882 migration_duration_ns = MIN(NANOSECONDS_PER_SECOND, ns_diff);
883 migration_duration_tb = muldiv64(migration_duration_ns, freq,
884 NANOSECONDS_PER_SECOND);
885 guest_tb = tb_remote->guest_timebase + MIN(0, migration_duration_tb);
886
887 tb_off_adj = guest_tb - cpu_get_host_ticks();
888
889 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
890 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
891 (tb_off_adj - tb_off) / freq);
892
893 /* Set new offset to all CPUs */
894 CPU_FOREACH(cpu) {
895 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
896 pcpu->env.tb_env->tb_offset = tb_off_adj;
897 }
898
899 return 0;
900 }
901
902 const VMStateDescription vmstate_ppc_timebase = {
903 .name = "timebase",
904 .version_id = 1,
905 .minimum_version_id = 1,
906 .minimum_version_id_old = 1,
907 .pre_save = timebase_pre_save,
908 .post_load = timebase_post_load,
909 .fields = (VMStateField []) {
910 VMSTATE_UINT64(guest_timebase, PPCTimebase),
911 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
912 VMSTATE_END_OF_LIST()
913 },
914 };
915
916 /* Set up (once) timebase frequency (in Hz) */
917 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
918 {
919 PowerPCCPU *cpu = ppc_env_get_cpu(env);
920 ppc_tb_t *tb_env;
921
922 tb_env = g_malloc0(sizeof(ppc_tb_t));
923 env->tb_env = tb_env;
924 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
925 if (env->insns_flags & PPC_SEGMENT_64B) {
926 /* All Book3S 64bit CPUs implement level based DEC logic */
927 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
928 }
929 /* Create new timer */
930 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
931 if (0) {
932 /* XXX: find a suitable condition to enable the hypervisor decrementer
933 */
934 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
935 cpu);
936 } else {
937 tb_env->hdecr_timer = NULL;
938 }
939 cpu_ppc_set_tb_clk(env, freq);
940
941 return &cpu_ppc_set_tb_clk;
942 }
943
944 /* Specific helpers for POWER & PowerPC 601 RTC */
945 #if 0
946 static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
947 {
948 return cpu_ppc_tb_init(env, 7812500);
949 }
950 #endif
951
952 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
953 {
954 _cpu_ppc_store_tbu(env, value);
955 }
956
957 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
958 {
959 return _cpu_ppc_load_tbu(env);
960 }
961
962 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
963 {
964 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
965 }
966
967 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
968 {
969 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
970 }
971
972 /*****************************************************************************/
973 /* PowerPC 40x timers */
974
975 /* PIT, FIT & WDT */
976 typedef struct ppc40x_timer_t ppc40x_timer_t;
977 struct ppc40x_timer_t {
978 uint64_t pit_reload; /* PIT auto-reload value */
979 uint64_t fit_next; /* Tick for next FIT interrupt */
980 QEMUTimer *fit_timer;
981 uint64_t wdt_next; /* Tick for next WDT interrupt */
982 QEMUTimer *wdt_timer;
983
984 /* 405 have the PIT, 440 have a DECR. */
985 unsigned int decr_excp;
986 };
987
988 /* Fixed interval timer */
989 static void cpu_4xx_fit_cb (void *opaque)
990 {
991 PowerPCCPU *cpu;
992 CPUPPCState *env;
993 ppc_tb_t *tb_env;
994 ppc40x_timer_t *ppc40x_timer;
995 uint64_t now, next;
996
997 env = opaque;
998 cpu = ppc_env_get_cpu(env);
999 tb_env = env->tb_env;
1000 ppc40x_timer = tb_env->opaque;
1001 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1002 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1003 case 0:
1004 next = 1 << 9;
1005 break;
1006 case 1:
1007 next = 1 << 13;
1008 break;
1009 case 2:
1010 next = 1 << 17;
1011 break;
1012 case 3:
1013 next = 1 << 21;
1014 break;
1015 default:
1016 /* Cannot occur, but makes gcc happy */
1017 return;
1018 }
1019 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
1020 if (next == now)
1021 next++;
1022 timer_mod(ppc40x_timer->fit_timer, next);
1023 env->spr[SPR_40x_TSR] |= 1 << 26;
1024 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1025 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1026 }
1027 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
1028 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1029 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1030 }
1031
1032 /* Programmable interval timer */
1033 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1034 {
1035 ppc40x_timer_t *ppc40x_timer;
1036 uint64_t now, next;
1037
1038 ppc40x_timer = tb_env->opaque;
1039 if (ppc40x_timer->pit_reload <= 1 ||
1040 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1041 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1042 /* Stop PIT */
1043 LOG_TB("%s: stop PIT\n", __func__);
1044 timer_del(tb_env->decr_timer);
1045 } else {
1046 LOG_TB("%s: start PIT %016" PRIx64 "\n",
1047 __func__, ppc40x_timer->pit_reload);
1048 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1049 next = now + muldiv64(ppc40x_timer->pit_reload,
1050 NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1051 if (is_excp)
1052 next += tb_env->decr_next - now;
1053 if (next == now)
1054 next++;
1055 timer_mod(tb_env->decr_timer, next);
1056 tb_env->decr_next = next;
1057 }
1058 }
1059
1060 static void cpu_4xx_pit_cb (void *opaque)
1061 {
1062 PowerPCCPU *cpu;
1063 CPUPPCState *env;
1064 ppc_tb_t *tb_env;
1065 ppc40x_timer_t *ppc40x_timer;
1066
1067 env = opaque;
1068 cpu = ppc_env_get_cpu(env);
1069 tb_env = env->tb_env;
1070 ppc40x_timer = tb_env->opaque;
1071 env->spr[SPR_40x_TSR] |= 1 << 27;
1072 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1073 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1074 }
1075 start_stop_pit(env, tb_env, 1);
1076 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
1077 "%016" PRIx64 "\n", __func__,
1078 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1079 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1080 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1081 ppc40x_timer->pit_reload);
1082 }
1083
1084 /* Watchdog timer */
1085 static void cpu_4xx_wdt_cb (void *opaque)
1086 {
1087 PowerPCCPU *cpu;
1088 CPUPPCState *env;
1089 ppc_tb_t *tb_env;
1090 ppc40x_timer_t *ppc40x_timer;
1091 uint64_t now, next;
1092
1093 env = opaque;
1094 cpu = ppc_env_get_cpu(env);
1095 tb_env = env->tb_env;
1096 ppc40x_timer = tb_env->opaque;
1097 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1098 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1099 case 0:
1100 next = 1 << 17;
1101 break;
1102 case 1:
1103 next = 1 << 21;
1104 break;
1105 case 2:
1106 next = 1 << 25;
1107 break;
1108 case 3:
1109 next = 1 << 29;
1110 break;
1111 default:
1112 /* Cannot occur, but makes gcc happy */
1113 return;
1114 }
1115 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1116 if (next == now)
1117 next++;
1118 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
1119 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1120 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1121 case 0x0:
1122 case 0x1:
1123 timer_mod(ppc40x_timer->wdt_timer, next);
1124 ppc40x_timer->wdt_next = next;
1125 env->spr[SPR_40x_TSR] |= 1U << 31;
1126 break;
1127 case 0x2:
1128 timer_mod(ppc40x_timer->wdt_timer, next);
1129 ppc40x_timer->wdt_next = next;
1130 env->spr[SPR_40x_TSR] |= 1 << 30;
1131 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1132 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1133 }
1134 break;
1135 case 0x3:
1136 env->spr[SPR_40x_TSR] &= ~0x30000000;
1137 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1138 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1139 case 0x0:
1140 /* No reset */
1141 break;
1142 case 0x1: /* Core reset */
1143 ppc40x_core_reset(cpu);
1144 break;
1145 case 0x2: /* Chip reset */
1146 ppc40x_chip_reset(cpu);
1147 break;
1148 case 0x3: /* System reset */
1149 ppc40x_system_reset(cpu);
1150 break;
1151 }
1152 }
1153 }
1154
1155 void store_40x_pit (CPUPPCState *env, target_ulong val)
1156 {
1157 ppc_tb_t *tb_env;
1158 ppc40x_timer_t *ppc40x_timer;
1159
1160 tb_env = env->tb_env;
1161 ppc40x_timer = tb_env->opaque;
1162 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1163 ppc40x_timer->pit_reload = val;
1164 start_stop_pit(env, tb_env, 0);
1165 }
1166
1167 target_ulong load_40x_pit (CPUPPCState *env)
1168 {
1169 return cpu_ppc_load_decr(env);
1170 }
1171
1172 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1173 {
1174 CPUPPCState *env = opaque;
1175 ppc_tb_t *tb_env = env->tb_env;
1176
1177 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1178 freq);
1179 tb_env->tb_freq = freq;
1180 tb_env->decr_freq = freq;
1181 /* XXX: we should also update all timers */
1182 }
1183
1184 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1185 unsigned int decr_excp)
1186 {
1187 ppc_tb_t *tb_env;
1188 ppc40x_timer_t *ppc40x_timer;
1189
1190 tb_env = g_malloc0(sizeof(ppc_tb_t));
1191 env->tb_env = tb_env;
1192 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1193 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1194 tb_env->tb_freq = freq;
1195 tb_env->decr_freq = freq;
1196 tb_env->opaque = ppc40x_timer;
1197 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1198 if (ppc40x_timer != NULL) {
1199 /* We use decr timer for PIT */
1200 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env);
1201 ppc40x_timer->fit_timer =
1202 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env);
1203 ppc40x_timer->wdt_timer =
1204 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env);
1205 ppc40x_timer->decr_excp = decr_excp;
1206 }
1207
1208 return &ppc_40x_set_tb_clk;
1209 }
1210
1211 /*****************************************************************************/
1212 /* Embedded PowerPC Device Control Registers */
1213 typedef struct ppc_dcrn_t ppc_dcrn_t;
1214 struct ppc_dcrn_t {
1215 dcr_read_cb dcr_read;
1216 dcr_write_cb dcr_write;
1217 void *opaque;
1218 };
1219
1220 /* XXX: on 460, DCR addresses are 32 bits wide,
1221 * using DCRIPR to get the 22 upper bits of the DCR address
1222 */
1223 #define DCRN_NB 1024
1224 struct ppc_dcr_t {
1225 ppc_dcrn_t dcrn[DCRN_NB];
1226 int (*read_error)(int dcrn);
1227 int (*write_error)(int dcrn);
1228 };
1229
1230 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1231 {
1232 ppc_dcrn_t *dcr;
1233
1234 if (dcrn < 0 || dcrn >= DCRN_NB)
1235 goto error;
1236 dcr = &dcr_env->dcrn[dcrn];
1237 if (dcr->dcr_read == NULL)
1238 goto error;
1239 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1240
1241 return 0;
1242
1243 error:
1244 if (dcr_env->read_error != NULL)
1245 return (*dcr_env->read_error)(dcrn);
1246
1247 return -1;
1248 }
1249
1250 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1251 {
1252 ppc_dcrn_t *dcr;
1253
1254 if (dcrn < 0 || dcrn >= DCRN_NB)
1255 goto error;
1256 dcr = &dcr_env->dcrn[dcrn];
1257 if (dcr->dcr_write == NULL)
1258 goto error;
1259 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1260
1261 return 0;
1262
1263 error:
1264 if (dcr_env->write_error != NULL)
1265 return (*dcr_env->write_error)(dcrn);
1266
1267 return -1;
1268 }
1269
1270 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1271 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1272 {
1273 ppc_dcr_t *dcr_env;
1274 ppc_dcrn_t *dcr;
1275
1276 dcr_env = env->dcr_env;
1277 if (dcr_env == NULL)
1278 return -1;
1279 if (dcrn < 0 || dcrn >= DCRN_NB)
1280 return -1;
1281 dcr = &dcr_env->dcrn[dcrn];
1282 if (dcr->opaque != NULL ||
1283 dcr->dcr_read != NULL ||
1284 dcr->dcr_write != NULL)
1285 return -1;
1286 dcr->opaque = opaque;
1287 dcr->dcr_read = dcr_read;
1288 dcr->dcr_write = dcr_write;
1289
1290 return 0;
1291 }
1292
1293 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1294 int (*write_error)(int dcrn))
1295 {
1296 ppc_dcr_t *dcr_env;
1297
1298 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1299 dcr_env->read_error = read_error;
1300 dcr_env->write_error = write_error;
1301 env->dcr_env = dcr_env;
1302
1303 return 0;
1304 }
1305
1306 /*****************************************************************************/
1307 /* Debug port */
1308 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1309 {
1310 addr &= 0xF;
1311 switch (addr) {
1312 case 0:
1313 printf("%c", val);
1314 break;
1315 case 1:
1316 printf("\n");
1317 fflush(stdout);
1318 break;
1319 case 2:
1320 printf("Set loglevel to %04" PRIx32 "\n", val);
1321 qemu_set_log(val | 0x100);
1322 break;
1323 }
1324 }
1325
1326 /* CPU device-tree ID helpers */
1327 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu)
1328 {
1329 return cpu->cpu_dt_id;
1330 }
1331
1332 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
1333 {
1334 CPUState *cs;
1335
1336 CPU_FOREACH(cs) {
1337 PowerPCCPU *cpu = POWERPC_CPU(cs);
1338
1339 if (cpu->cpu_dt_id == cpu_dt_id) {
1340 return cpu;
1341 }
1342 }
1343
1344 return NULL;
1345 }
QEmu