2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "hw/audio/soundhw.h"
26 #include "intel-hda.h"
27 #include "intel-hda-defs.h"
28 #include "sysemu/dma.h"
29 #include "qapi/error.h"
31 /* --------------------------------------------------------------------- */
34 static Property hda_props
[] = {
35 DEFINE_PROP_UINT32("cad", HDACodecDevice
, cad
, -1),
36 DEFINE_PROP_END_OF_LIST()
39 static const TypeInfo hda_codec_bus_info
= {
42 .instance_size
= sizeof(HDACodecBus
),
45 void hda_codec_bus_init(DeviceState
*dev
, HDACodecBus
*bus
, size_t bus_size
,
46 hda_codec_response_func response
,
47 hda_codec_xfer_func xfer
)
49 qbus_create_inplace(bus
, bus_size
, TYPE_HDA_BUS
, dev
, NULL
);
50 bus
->response
= response
;
54 static void hda_codec_dev_realize(DeviceState
*qdev
, Error
**errp
)
56 HDACodecBus
*bus
= HDA_BUS(qdev
->parent_bus
);
57 HDACodecDevice
*dev
= HDA_CODEC_DEVICE(qdev
);
58 HDACodecDeviceClass
*cdc
= HDA_CODEC_DEVICE_GET_CLASS(dev
);
61 dev
->cad
= bus
->next_cad
;
64 error_setg(errp
, "HDA audio codec address is full");
67 bus
->next_cad
= dev
->cad
+ 1;
68 if (cdc
->init(dev
) != 0) {
69 error_setg(errp
, "HDA audio init failed");
73 static void hda_codec_dev_unrealize(DeviceState
*qdev
, Error
**errp
)
75 HDACodecDevice
*dev
= HDA_CODEC_DEVICE(qdev
);
76 HDACodecDeviceClass
*cdc
= HDA_CODEC_DEVICE_GET_CLASS(dev
);
83 HDACodecDevice
*hda_codec_find(HDACodecBus
*bus
, uint32_t cad
)
88 QTAILQ_FOREACH(kid
, &bus
->qbus
.children
, sibling
) {
89 DeviceState
*qdev
= kid
->child
;
90 cdev
= HDA_CODEC_DEVICE(qdev
);
91 if (cdev
->cad
== cad
) {
98 void hda_codec_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
100 HDACodecBus
*bus
= HDA_BUS(dev
->qdev
.parent_bus
);
101 bus
->response(dev
, solicited
, response
);
104 bool hda_codec_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
105 uint8_t *buf
, uint32_t len
)
107 HDACodecBus
*bus
= HDA_BUS(dev
->qdev
.parent_bus
);
108 return bus
->xfer(dev
, stnr
, output
, buf
, len
);
111 /* --------------------------------------------------------------------- */
112 /* intel hda emulation */
114 typedef struct IntelHDAStream IntelHDAStream
;
115 typedef struct IntelHDAState IntelHDAState
;
116 typedef struct IntelHDAReg IntelHDAReg
;
124 struct IntelHDAStream
{
137 uint32_t bsize
, be
, bp
;
140 struct IntelHDAState
{
177 IntelHDAStream st
[8];
182 int64_t wall_base_ns
;
185 const IntelHDAReg
*last_reg
;
189 uint32_t repeat_count
;
197 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
199 #define INTEL_HDA(obj) \
200 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
203 const char *name
; /* register name */
204 uint32_t size
; /* size in bytes */
205 uint32_t reset
; /* reset value */
206 uint32_t wmask
; /* write mask */
207 uint32_t wclear
; /* write 1 to clear bits */
208 uint32_t offset
; /* location in IntelHDAState */
209 uint32_t shift
; /* byte access entries for dwords */
211 void (*whandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
);
212 void (*rhandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
);
215 static void intel_hda_reset(DeviceState
*dev
);
217 /* --------------------------------------------------------------------- */
219 static hwaddr
intel_hda_addr(uint32_t lbase
, uint32_t ubase
)
221 return ((uint64_t)ubase
<< 32) | lbase
;
224 static void intel_hda_update_int_sts(IntelHDAState
*d
)
229 /* update controller status */
230 if (d
->rirb_sts
& ICH6_RBSTS_IRQ
) {
233 if (d
->rirb_sts
& ICH6_RBSTS_OVERRUN
) {
236 if (d
->state_sts
& d
->wake_en
) {
240 /* update stream status */
241 for (i
= 0; i
< 8; i
++) {
242 /* buffer completion interrupt */
243 if (d
->st
[i
].ctl
& (1 << 26)) {
248 /* update global status */
249 if (sts
& d
->int_ctl
) {
256 static void intel_hda_update_irq(IntelHDAState
*d
)
258 bool msi
= msi_enabled(&d
->pci
);
261 intel_hda_update_int_sts(d
);
262 if (d
->int_sts
& (1U << 31) && d
->int_ctl
& (1U << 31)) {
267 dprint(d
, 2, "%s: level %d [%s]\n", __FUNCTION__
,
268 level
, msi
? "msi" : "intx");
271 msi_notify(&d
->pci
, 0);
274 pci_set_irq(&d
->pci
, level
);
278 static int intel_hda_send_command(IntelHDAState
*d
, uint32_t verb
)
280 uint32_t cad
, nid
, data
;
281 HDACodecDevice
*codec
;
282 HDACodecDeviceClass
*cdc
;
284 cad
= (verb
>> 28) & 0x0f;
285 if (verb
& (1 << 27)) {
286 /* indirect node addressing, not specified in HDA 1.0 */
287 dprint(d
, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__
);
290 nid
= (verb
>> 20) & 0x7f;
291 data
= verb
& 0xfffff;
293 codec
= hda_codec_find(&d
->codecs
, cad
);
295 dprint(d
, 1, "%s: addressed non-existing codec\n", __FUNCTION__
);
298 cdc
= HDA_CODEC_DEVICE_GET_CLASS(codec
);
299 cdc
->command(codec
, nid
, data
);
303 static void intel_hda_corb_run(IntelHDAState
*d
)
308 if (d
->ics
& ICH6_IRS_BUSY
) {
309 dprint(d
, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__
, d
->icw
);
310 intel_hda_send_command(d
, d
->icw
);
315 if (!(d
->corb_ctl
& ICH6_CORBCTL_RUN
)) {
316 dprint(d
, 2, "%s: !run\n", __FUNCTION__
);
319 if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
320 dprint(d
, 2, "%s: corb ring empty\n", __FUNCTION__
);
323 if (d
->rirb_count
== d
->rirb_cnt
) {
324 dprint(d
, 2, "%s: rirb count reached\n", __FUNCTION__
);
328 rp
= (d
->corb_rp
+ 1) & 0xff;
329 addr
= intel_hda_addr(d
->corb_lbase
, d
->corb_ubase
);
330 verb
= ldl_le_pci_dma(&d
->pci
, addr
+ 4*rp
);
333 dprint(d
, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__
, rp
, verb
);
334 intel_hda_send_command(d
, verb
);
338 static void intel_hda_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
340 HDACodecBus
*bus
= HDA_BUS(dev
->qdev
.parent_bus
);
341 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
345 if (d
->ics
& ICH6_IRS_BUSY
) {
346 dprint(d
, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
347 __FUNCTION__
, response
, dev
->cad
);
349 d
->ics
&= ~(ICH6_IRS_BUSY
| 0xf0);
350 d
->ics
|= (ICH6_IRS_VALID
| (dev
->cad
<< 4));
354 if (!(d
->rirb_ctl
& ICH6_RBCTL_DMA_EN
)) {
355 dprint(d
, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__
);
359 ex
= (solicited
? 0 : (1 << 4)) | dev
->cad
;
360 wp
= (d
->rirb_wp
+ 1) & 0xff;
361 addr
= intel_hda_addr(d
->rirb_lbase
, d
->rirb_ubase
);
362 stl_le_pci_dma(&d
->pci
, addr
+ 8*wp
, response
);
363 stl_le_pci_dma(&d
->pci
, addr
+ 8*wp
+ 4, ex
);
366 dprint(d
, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
367 __FUNCTION__
, wp
, response
, ex
);
370 if (d
->rirb_count
== d
->rirb_cnt
) {
371 dprint(d
, 2, "%s: rirb count reached (%d)\n", __FUNCTION__
, d
->rirb_count
);
372 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
373 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
374 intel_hda_update_irq(d
);
376 } else if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
377 dprint(d
, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__
,
378 d
->rirb_count
, d
->rirb_cnt
);
379 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
380 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
381 intel_hda_update_irq(d
);
386 static bool intel_hda_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
387 uint8_t *buf
, uint32_t len
)
389 HDACodecBus
*bus
= HDA_BUS(dev
->qdev
.parent_bus
);
390 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
392 uint32_t s
, copy
, left
;
396 st
= output
? d
->st
+ 4 : d
->st
;
397 for (s
= 0; s
< 4; s
++) {
398 if (stnr
== ((st
[s
].ctl
>> 20) & 0x0f)) {
406 if (st
->bpl
== NULL
) {
409 if (st
->ctl
& (1 << 26)) {
411 * Wait with the next DMA xfer until the guest
412 * has acked the buffer completion interrupt
419 while (left
> 0 && s
-- > 0) {
421 if (copy
> st
->bsize
- st
->lpib
)
422 copy
= st
->bsize
- st
->lpib
;
423 if (copy
> st
->bpl
[st
->be
].len
- st
->bp
)
424 copy
= st
->bpl
[st
->be
].len
- st
->bp
;
426 dprint(d
, 3, "dma: entry %d, pos %d/%d, copy %d\n",
427 st
->be
, st
->bp
, st
->bpl
[st
->be
].len
, copy
);
429 pci_dma_rw(&d
->pci
, st
->bpl
[st
->be
].addr
+ st
->bp
, buf
, copy
, !output
);
435 if (st
->bpl
[st
->be
].len
== st
->bp
) {
436 /* bpl entry filled */
437 if (st
->bpl
[st
->be
].flags
& 0x01) {
442 if (st
->be
== st
->bentries
) {
443 /* bpl wrap around */
449 if (d
->dp_lbase
& 0x01) {
451 addr
= intel_hda_addr(d
->dp_lbase
& ~0x01, d
->dp_ubase
);
452 stl_le_pci_dma(&d
->pci
, addr
+ 8*s
, st
->lpib
);
454 dprint(d
, 3, "dma: --\n");
457 st
->ctl
|= (1 << 26); /* buffer completion interrupt */
458 intel_hda_update_irq(d
);
463 static void intel_hda_parse_bdl(IntelHDAState
*d
, IntelHDAStream
*st
)
469 addr
= intel_hda_addr(st
->bdlp_lbase
, st
->bdlp_ubase
);
470 st
->bentries
= st
->lvi
+1;
472 st
->bpl
= g_malloc(sizeof(bpl
) * st
->bentries
);
473 for (i
= 0; i
< st
->bentries
; i
++, addr
+= 16) {
474 pci_dma_read(&d
->pci
, addr
, buf
, 16);
475 st
->bpl
[i
].addr
= le64_to_cpu(*(uint64_t *)buf
);
476 st
->bpl
[i
].len
= le32_to_cpu(*(uint32_t *)(buf
+ 8));
477 st
->bpl
[i
].flags
= le32_to_cpu(*(uint32_t *)(buf
+ 12));
478 dprint(d
, 1, "bdl/%d: 0x%" PRIx64
" +0x%x, 0x%x\n",
479 i
, st
->bpl
[i
].addr
, st
->bpl
[i
].len
, st
->bpl
[i
].flags
);
488 static void intel_hda_notify_codecs(IntelHDAState
*d
, uint32_t stream
, bool running
, bool output
)
491 HDACodecDevice
*cdev
;
493 QTAILQ_FOREACH(kid
, &d
->codecs
.qbus
.children
, sibling
) {
494 DeviceState
*qdev
= kid
->child
;
495 HDACodecDeviceClass
*cdc
;
497 cdev
= HDA_CODEC_DEVICE(qdev
);
498 cdc
= HDA_CODEC_DEVICE_GET_CLASS(cdev
);
500 cdc
->stream(cdev
, stream
, running
, output
);
505 /* --------------------------------------------------------------------- */
507 static void intel_hda_set_g_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
509 if ((d
->g_ctl
& ICH6_GCTL_RESET
) == 0) {
510 intel_hda_reset(DEVICE(d
));
514 static void intel_hda_set_wake_en(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
516 intel_hda_update_irq(d
);
519 static void intel_hda_set_state_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
521 intel_hda_update_irq(d
);
524 static void intel_hda_set_int_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
526 intel_hda_update_irq(d
);
529 static void intel_hda_get_wall_clk(IntelHDAState
*d
, const IntelHDAReg
*reg
)
533 ns
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - d
->wall_base_ns
;
534 d
->wall_clk
= (uint32_t)(ns
* 24 / 1000); /* 24 MHz */
537 static void intel_hda_set_corb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
539 intel_hda_corb_run(d
);
542 static void intel_hda_set_corb_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
544 intel_hda_corb_run(d
);
547 static void intel_hda_set_rirb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
549 if (d
->rirb_wp
& ICH6_RIRBWP_RST
) {
554 static void intel_hda_set_rirb_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
556 intel_hda_update_irq(d
);
558 if ((old
& ICH6_RBSTS_IRQ
) && !(d
->rirb_sts
& ICH6_RBSTS_IRQ
)) {
559 /* cleared ICH6_RBSTS_IRQ */
561 intel_hda_corb_run(d
);
565 static void intel_hda_set_ics(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
567 if (d
->ics
& ICH6_IRS_BUSY
) {
568 intel_hda_corb_run(d
);
572 static void intel_hda_set_st_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
574 bool output
= reg
->stream
>= 4;
575 IntelHDAStream
*st
= d
->st
+ reg
->stream
;
577 if (st
->ctl
& 0x01) {
579 dprint(d
, 1, "st #%d: reset\n", reg
->stream
);
580 st
->ctl
= SD_STS_FIFO_READY
<< 24;
582 if ((st
->ctl
& 0x02) != (old
& 0x02)) {
583 uint32_t stnr
= (st
->ctl
>> 20) & 0x0f;
584 /* run bit flipped */
585 if (st
->ctl
& 0x02) {
587 dprint(d
, 1, "st #%d: start %d (ring buf %d bytes)\n",
588 reg
->stream
, stnr
, st
->cbl
);
589 intel_hda_parse_bdl(d
, st
);
590 intel_hda_notify_codecs(d
, stnr
, true, output
);
593 dprint(d
, 1, "st #%d: stop %d\n", reg
->stream
, stnr
);
594 intel_hda_notify_codecs(d
, stnr
, false, output
);
597 intel_hda_update_irq(d
);
600 /* --------------------------------------------------------------------- */
602 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
604 static const struct IntelHDAReg regtab
[] = {
606 [ ICH6_REG_GCAP
] = {
611 [ ICH6_REG_VMIN
] = {
615 [ ICH6_REG_VMAJ
] = {
620 [ ICH6_REG_OUTPAY
] = {
625 [ ICH6_REG_INPAY
] = {
630 [ ICH6_REG_GCTL
] = {
634 .offset
= offsetof(IntelHDAState
, g_ctl
),
635 .whandler
= intel_hda_set_g_ctl
,
637 [ ICH6_REG_WAKEEN
] = {
641 .offset
= offsetof(IntelHDAState
, wake_en
),
642 .whandler
= intel_hda_set_wake_en
,
644 [ ICH6_REG_STATESTS
] = {
649 .offset
= offsetof(IntelHDAState
, state_sts
),
650 .whandler
= intel_hda_set_state_sts
,
654 [ ICH6_REG_INTCTL
] = {
658 .offset
= offsetof(IntelHDAState
, int_ctl
),
659 .whandler
= intel_hda_set_int_ctl
,
661 [ ICH6_REG_INTSTS
] = {
665 .wclear
= 0xc00000ff,
666 .offset
= offsetof(IntelHDAState
, int_sts
),
670 [ ICH6_REG_WALLCLK
] = {
673 .offset
= offsetof(IntelHDAState
, wall_clk
),
674 .rhandler
= intel_hda_get_wall_clk
,
676 [ ICH6_REG_WALLCLK
+ 0x2000 ] = {
677 .name
= "WALLCLK(alias)",
679 .offset
= offsetof(IntelHDAState
, wall_clk
),
680 .rhandler
= intel_hda_get_wall_clk
,
684 [ ICH6_REG_CORBLBASE
] = {
688 .offset
= offsetof(IntelHDAState
, corb_lbase
),
690 [ ICH6_REG_CORBUBASE
] = {
694 .offset
= offsetof(IntelHDAState
, corb_ubase
),
696 [ ICH6_REG_CORBWP
] = {
700 .offset
= offsetof(IntelHDAState
, corb_wp
),
701 .whandler
= intel_hda_set_corb_wp
,
703 [ ICH6_REG_CORBRP
] = {
707 .offset
= offsetof(IntelHDAState
, corb_rp
),
709 [ ICH6_REG_CORBCTL
] = {
713 .offset
= offsetof(IntelHDAState
, corb_ctl
),
714 .whandler
= intel_hda_set_corb_ctl
,
716 [ ICH6_REG_CORBSTS
] = {
721 .offset
= offsetof(IntelHDAState
, corb_sts
),
723 [ ICH6_REG_CORBSIZE
] = {
727 .offset
= offsetof(IntelHDAState
, corb_size
),
729 [ ICH6_REG_RIRBLBASE
] = {
733 .offset
= offsetof(IntelHDAState
, rirb_lbase
),
735 [ ICH6_REG_RIRBUBASE
] = {
739 .offset
= offsetof(IntelHDAState
, rirb_ubase
),
741 [ ICH6_REG_RIRBWP
] = {
745 .offset
= offsetof(IntelHDAState
, rirb_wp
),
746 .whandler
= intel_hda_set_rirb_wp
,
748 [ ICH6_REG_RINTCNT
] = {
752 .offset
= offsetof(IntelHDAState
, rirb_cnt
),
754 [ ICH6_REG_RIRBCTL
] = {
758 .offset
= offsetof(IntelHDAState
, rirb_ctl
),
760 [ ICH6_REG_RIRBSTS
] = {
765 .offset
= offsetof(IntelHDAState
, rirb_sts
),
766 .whandler
= intel_hda_set_rirb_sts
,
768 [ ICH6_REG_RIRBSIZE
] = {
772 .offset
= offsetof(IntelHDAState
, rirb_size
),
775 [ ICH6_REG_DPLBASE
] = {
779 .offset
= offsetof(IntelHDAState
, dp_lbase
),
781 [ ICH6_REG_DPUBASE
] = {
785 .offset
= offsetof(IntelHDAState
, dp_ubase
),
792 .offset
= offsetof(IntelHDAState
, icw
),
797 .offset
= offsetof(IntelHDAState
, irr
),
804 .offset
= offsetof(IntelHDAState
, ics
),
805 .whandler
= intel_hda_set_ics
,
808 #define HDA_STREAM(_t, _i) \
809 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
811 .name = _t stringify(_i) " CTL", \
813 .wmask = 0x1cff001f, \
814 .offset = offsetof(IntelHDAState, st[_i].ctl), \
815 .whandler = intel_hda_set_st_ctl, \
817 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
819 .name = _t stringify(_i) " CTL(stnr)", \
822 .wmask = 0x00ff0000, \
823 .offset = offsetof(IntelHDAState, st[_i].ctl), \
824 .whandler = intel_hda_set_st_ctl, \
826 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
828 .name = _t stringify(_i) " CTL(sts)", \
831 .wmask = 0x1c000000, \
832 .wclear = 0x1c000000, \
833 .offset = offsetof(IntelHDAState, st[_i].ctl), \
834 .whandler = intel_hda_set_st_ctl, \
835 .reset = SD_STS_FIFO_READY << 24 \
837 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
839 .name = _t stringify(_i) " LPIB", \
841 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
845 .name = _t stringify(_i) " LPIB(alias)", \
847 .offset = offsetof(IntelHDAState, st[_i].lpib), \
849 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
851 .name = _t stringify(_i) " CBL", \
853 .wmask = 0xffffffff, \
854 .offset = offsetof(IntelHDAState, st[_i].cbl), \
856 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
858 .name = _t stringify(_i) " LVI", \
861 .offset = offsetof(IntelHDAState, st[_i].lvi), \
863 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
865 .name = _t stringify(_i) " FIFOS", \
867 .reset = HDA_BUFFER_SIZE, \
869 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
871 .name = _t stringify(_i) " FMT", \
874 .offset = offsetof(IntelHDAState, st[_i].fmt), \
876 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
878 .name = _t stringify(_i) " BDLPL", \
880 .wmask = 0xffffff80, \
881 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
883 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
885 .name = _t stringify(_i) " BDLPU", \
887 .wmask = 0xffffffff, \
888 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
903 static const IntelHDAReg
*intel_hda_reg_find(IntelHDAState
*d
, hwaddr addr
)
905 const IntelHDAReg
*reg
;
907 if (addr
>= ARRAY_SIZE(regtab
)) {
911 if (reg
->name
== NULL
) {
917 dprint(d
, 1, "unknown register, addr 0x%x\n", (int) addr
);
921 static uint32_t *intel_hda_reg_addr(IntelHDAState
*d
, const IntelHDAReg
*reg
)
923 uint8_t *addr
= (void*)d
;
926 return (uint32_t*)addr
;
929 static void intel_hda_reg_write(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t val
,
940 time_t now
= time(NULL
);
941 if (d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== val
) {
943 if (d
->last_sec
!= now
) {
944 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
949 if (d
->repeat_count
) {
950 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
952 dprint(d
, 2, "write %-16s: 0x%x (%x)\n", reg
->name
, val
, wmask
);
960 assert(reg
->offset
!= 0);
962 addr
= intel_hda_reg_addr(d
, reg
);
967 wmask
<<= reg
->shift
;
971 *addr
|= wmask
& val
;
972 *addr
&= ~(val
& reg
->wclear
);
975 reg
->whandler(d
, reg
, old
);
979 static uint32_t intel_hda_reg_read(IntelHDAState
*d
, const IntelHDAReg
*reg
,
989 reg
->rhandler(d
, reg
);
992 if (reg
->offset
== 0) {
993 /* constant read-only register */
996 addr
= intel_hda_reg_addr(d
, reg
);
1004 time_t now
= time(NULL
);
1005 if (!d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== ret
) {
1007 if (d
->last_sec
!= now
) {
1008 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1010 d
->repeat_count
= 0;
1013 if (d
->repeat_count
) {
1014 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1016 dprint(d
, 2, "read %-16s: 0x%x (%x)\n", reg
->name
, ret
, rmask
);
1021 d
->repeat_count
= 0;
1027 static void intel_hda_regs_reset(IntelHDAState
*d
)
1032 for (i
= 0; i
< ARRAY_SIZE(regtab
); i
++) {
1033 if (regtab
[i
].name
== NULL
) {
1036 if (regtab
[i
].offset
== 0) {
1039 addr
= intel_hda_reg_addr(d
, regtab
+ i
);
1040 *addr
= regtab
[i
].reset
;
1044 /* --------------------------------------------------------------------- */
1046 static void intel_hda_mmio_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
1048 IntelHDAState
*d
= opaque
;
1049 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1051 intel_hda_reg_write(d
, reg
, val
, 0xff);
1054 static void intel_hda_mmio_writew(void *opaque
, hwaddr addr
, uint32_t val
)
1056 IntelHDAState
*d
= opaque
;
1057 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1059 intel_hda_reg_write(d
, reg
, val
, 0xffff);
1062 static void intel_hda_mmio_writel(void *opaque
, hwaddr addr
, uint32_t val
)
1064 IntelHDAState
*d
= opaque
;
1065 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1067 intel_hda_reg_write(d
, reg
, val
, 0xffffffff);
1070 static uint32_t intel_hda_mmio_readb(void *opaque
, hwaddr addr
)
1072 IntelHDAState
*d
= opaque
;
1073 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1075 return intel_hda_reg_read(d
, reg
, 0xff);
1078 static uint32_t intel_hda_mmio_readw(void *opaque
, hwaddr addr
)
1080 IntelHDAState
*d
= opaque
;
1081 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1083 return intel_hda_reg_read(d
, reg
, 0xffff);
1086 static uint32_t intel_hda_mmio_readl(void *opaque
, hwaddr addr
)
1088 IntelHDAState
*d
= opaque
;
1089 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1091 return intel_hda_reg_read(d
, reg
, 0xffffffff);
1094 static const MemoryRegionOps intel_hda_mmio_ops
= {
1097 intel_hda_mmio_readb
,
1098 intel_hda_mmio_readw
,
1099 intel_hda_mmio_readl
,
1102 intel_hda_mmio_writeb
,
1103 intel_hda_mmio_writew
,
1104 intel_hda_mmio_writel
,
1107 .endianness
= DEVICE_NATIVE_ENDIAN
,
1110 /* --------------------------------------------------------------------- */
1112 static void intel_hda_reset(DeviceState
*dev
)
1115 IntelHDAState
*d
= INTEL_HDA(dev
);
1116 HDACodecDevice
*cdev
;
1118 intel_hda_regs_reset(d
);
1119 d
->wall_base_ns
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1122 QTAILQ_FOREACH(kid
, &d
->codecs
.qbus
.children
, sibling
) {
1123 DeviceState
*qdev
= kid
->child
;
1124 cdev
= HDA_CODEC_DEVICE(qdev
);
1125 device_reset(DEVICE(cdev
));
1126 d
->state_sts
|= (1 << cdev
->cad
);
1128 intel_hda_update_irq(d
);
1131 static void intel_hda_realize(PCIDevice
*pci
, Error
**errp
)
1133 IntelHDAState
*d
= INTEL_HDA(pci
);
1134 uint8_t *conf
= d
->pci
.config
;
1138 d
->name
= object_get_typename(OBJECT(d
));
1140 pci_config_set_interrupt_pin(conf
, 1);
1142 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1145 if (d
->msi
!= ON_OFF_AUTO_OFF
) {
1146 ret
= msi_init(&d
->pci
, d
->old_msi_addr
? 0x50 : 0x60,
1147 1, true, false, &err
);
1148 /* Any error other than -ENOTSUP(board's MSI support is broken)
1149 * is a programming error */
1150 assert(!ret
|| ret
== -ENOTSUP
);
1151 if (ret
&& d
->msi
== ON_OFF_AUTO_ON
) {
1152 /* Can't satisfy user's explicit msi=on request, fail */
1153 error_append_hint(&err
, "You have to use msi=auto (default) or "
1154 "msi=off with this machine type.\n");
1155 error_propagate(errp
, err
);
1158 assert(!err
|| d
->msi
== ON_OFF_AUTO_AUTO
);
1159 /* With msi=auto, we fall back to MSI off silently */
1163 memory_region_init_io(&d
->mmio
, OBJECT(d
), &intel_hda_mmio_ops
, d
,
1164 "intel-hda", 0x4000);
1165 pci_register_bar(&d
->pci
, 0, 0, &d
->mmio
);
1167 hda_codec_bus_init(DEVICE(pci
), &d
->codecs
, sizeof(d
->codecs
),
1168 intel_hda_response
, intel_hda_xfer
);
1171 static void intel_hda_exit(PCIDevice
*pci
)
1173 IntelHDAState
*d
= INTEL_HDA(pci
);
1175 msi_uninit(&d
->pci
);
1178 static int intel_hda_post_load(void *opaque
, int version
)
1180 IntelHDAState
* d
= opaque
;
1183 dprint(d
, 1, "%s\n", __FUNCTION__
);
1184 for (i
= 0; i
< ARRAY_SIZE(d
->st
); i
++) {
1185 if (d
->st
[i
].ctl
& 0x02) {
1186 intel_hda_parse_bdl(d
, &d
->st
[i
]);
1189 intel_hda_update_irq(d
);
1193 static const VMStateDescription vmstate_intel_hda_stream
= {
1194 .name
= "intel-hda-stream",
1196 .fields
= (VMStateField
[]) {
1197 VMSTATE_UINT32(ctl
, IntelHDAStream
),
1198 VMSTATE_UINT32(lpib
, IntelHDAStream
),
1199 VMSTATE_UINT32(cbl
, IntelHDAStream
),
1200 VMSTATE_UINT32(lvi
, IntelHDAStream
),
1201 VMSTATE_UINT32(fmt
, IntelHDAStream
),
1202 VMSTATE_UINT32(bdlp_lbase
, IntelHDAStream
),
1203 VMSTATE_UINT32(bdlp_ubase
, IntelHDAStream
),
1204 VMSTATE_END_OF_LIST()
1208 static const VMStateDescription vmstate_intel_hda
= {
1209 .name
= "intel-hda",
1211 .post_load
= intel_hda_post_load
,
1212 .fields
= (VMStateField
[]) {
1213 VMSTATE_PCI_DEVICE(pci
, IntelHDAState
),
1216 VMSTATE_UINT32(g_ctl
, IntelHDAState
),
1217 VMSTATE_UINT32(wake_en
, IntelHDAState
),
1218 VMSTATE_UINT32(state_sts
, IntelHDAState
),
1219 VMSTATE_UINT32(int_ctl
, IntelHDAState
),
1220 VMSTATE_UINT32(int_sts
, IntelHDAState
),
1221 VMSTATE_UINT32(wall_clk
, IntelHDAState
),
1222 VMSTATE_UINT32(corb_lbase
, IntelHDAState
),
1223 VMSTATE_UINT32(corb_ubase
, IntelHDAState
),
1224 VMSTATE_UINT32(corb_rp
, IntelHDAState
),
1225 VMSTATE_UINT32(corb_wp
, IntelHDAState
),
1226 VMSTATE_UINT32(corb_ctl
, IntelHDAState
),
1227 VMSTATE_UINT32(corb_sts
, IntelHDAState
),
1228 VMSTATE_UINT32(corb_size
, IntelHDAState
),
1229 VMSTATE_UINT32(rirb_lbase
, IntelHDAState
),
1230 VMSTATE_UINT32(rirb_ubase
, IntelHDAState
),
1231 VMSTATE_UINT32(rirb_wp
, IntelHDAState
),
1232 VMSTATE_UINT32(rirb_cnt
, IntelHDAState
),
1233 VMSTATE_UINT32(rirb_ctl
, IntelHDAState
),
1234 VMSTATE_UINT32(rirb_sts
, IntelHDAState
),
1235 VMSTATE_UINT32(rirb_size
, IntelHDAState
),
1236 VMSTATE_UINT32(dp_lbase
, IntelHDAState
),
1237 VMSTATE_UINT32(dp_ubase
, IntelHDAState
),
1238 VMSTATE_UINT32(icw
, IntelHDAState
),
1239 VMSTATE_UINT32(irr
, IntelHDAState
),
1240 VMSTATE_UINT32(ics
, IntelHDAState
),
1241 VMSTATE_STRUCT_ARRAY(st
, IntelHDAState
, 8, 0,
1242 vmstate_intel_hda_stream
,
1245 /* additional state info */
1246 VMSTATE_UINT32(rirb_count
, IntelHDAState
),
1247 VMSTATE_INT64(wall_base_ns
, IntelHDAState
),
1249 VMSTATE_END_OF_LIST()
1253 static Property intel_hda_properties
[] = {
1254 DEFINE_PROP_UINT32("debug", IntelHDAState
, debug
, 0),
1255 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState
, msi
, ON_OFF_AUTO_AUTO
),
1256 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState
, old_msi_addr
, false),
1257 DEFINE_PROP_END_OF_LIST(),
1260 static void intel_hda_class_init(ObjectClass
*klass
, void *data
)
1262 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1263 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1265 k
->realize
= intel_hda_realize
;
1266 k
->exit
= intel_hda_exit
;
1267 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1268 k
->class_id
= PCI_CLASS_MULTIMEDIA_HD_AUDIO
;
1269 dc
->reset
= intel_hda_reset
;
1270 dc
->vmsd
= &vmstate_intel_hda
;
1271 dc
->props
= intel_hda_properties
;
1274 static void intel_hda_class_init_ich6(ObjectClass
*klass
, void *data
)
1276 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1277 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1279 k
->device_id
= 0x2668;
1281 set_bit(DEVICE_CATEGORY_SOUND
, dc
->categories
);
1282 dc
->desc
= "Intel HD Audio Controller (ich6)";
1285 static void intel_hda_class_init_ich9(ObjectClass
*klass
, void *data
)
1287 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1288 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1290 k
->device_id
= 0x293e;
1292 set_bit(DEVICE_CATEGORY_SOUND
, dc
->categories
);
1293 dc
->desc
= "Intel HD Audio Controller (ich9)";
1296 static const TypeInfo intel_hda_info
= {
1297 .name
= TYPE_INTEL_HDA_GENERIC
,
1298 .parent
= TYPE_PCI_DEVICE
,
1299 .instance_size
= sizeof(IntelHDAState
),
1300 .class_init
= intel_hda_class_init
,
1304 static const TypeInfo intel_hda_info_ich6
= {
1305 .name
= "intel-hda",
1306 .parent
= TYPE_INTEL_HDA_GENERIC
,
1307 .class_init
= intel_hda_class_init_ich6
,
1310 static const TypeInfo intel_hda_info_ich9
= {
1311 .name
= "ich9-intel-hda",
1312 .parent
= TYPE_INTEL_HDA_GENERIC
,
1313 .class_init
= intel_hda_class_init_ich9
,
1316 static void hda_codec_device_class_init(ObjectClass
*klass
, void *data
)
1318 DeviceClass
*k
= DEVICE_CLASS(klass
);
1319 k
->realize
= hda_codec_dev_realize
;
1320 k
->unrealize
= hda_codec_dev_unrealize
;
1321 set_bit(DEVICE_CATEGORY_SOUND
, k
->categories
);
1322 k
->bus_type
= TYPE_HDA_BUS
;
1323 k
->props
= hda_props
;
1326 static const TypeInfo hda_codec_device_type_info
= {
1327 .name
= TYPE_HDA_CODEC_DEVICE
,
1328 .parent
= TYPE_DEVICE
,
1329 .instance_size
= sizeof(HDACodecDevice
),
1331 .class_size
= sizeof(HDACodecDeviceClass
),
1332 .class_init
= hda_codec_device_class_init
,
1336 * create intel hda controller with codec attached to it,
1337 * so '-soundhw hda' works.
1339 static int intel_hda_and_codec_init(PCIBus
*bus
)
1341 DeviceState
*controller
;
1345 controller
= DEVICE(pci_create_simple(bus
, -1, "intel-hda"));
1346 hdabus
= QLIST_FIRST(&controller
->child_bus
);
1347 codec
= qdev_create(hdabus
, "hda-duplex");
1348 qdev_init_nofail(codec
);
1352 static void intel_hda_register_types(void)
1354 type_register_static(&hda_codec_bus_info
);
1355 type_register_static(&intel_hda_info
);
1356 type_register_static(&intel_hda_info_ich6
);
1357 type_register_static(&intel_hda_info_ich9
);
1358 type_register_static(&hda_codec_device_type_info
);
1359 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init
);
1362 type_init(intel_hda_register_types
)