4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #include "qapi/qmp/qerror.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
34 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
36 ARMCPU
*cpu
= ARM_CPU(cs
);
38 cpu
->env
.regs
[15] = value
;
41 static bool arm_cpu_has_work(CPUState
*cs
)
43 ARMCPU
*cpu
= ARM_CPU(cs
);
45 return !cpu
->powered_off
46 && cs
->interrupt_request
&
47 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
49 | CPU_INTERRUPT_EXITTB
);
52 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
54 /* Reset a single ARMCPRegInfo register */
55 ARMCPRegInfo
*ri
= value
;
58 if (ri
->type
& ARM_CP_SPECIAL
) {
63 ri
->resetfn(&cpu
->env
, ri
);
67 /* A zero offset is never possible as it would be regs[0]
68 * so we use it to indicate that reset is being handled elsewhere.
69 * This is basically only used for fields in non-core coprocessors
70 * (like the pxa2xx ones).
72 if (!ri
->fieldoffset
) {
76 if (cpreg_field_is_64bit(ri
)) {
77 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
79 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
83 /* CPUClass::reset() */
84 static void arm_cpu_reset(CPUState
*s
)
86 ARMCPU
*cpu
= ARM_CPU(s
);
87 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
88 CPUARMState
*env
= &cpu
->env
;
92 memset(env
, 0, offsetof(CPUARMState
, features
));
93 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
94 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
95 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
96 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
97 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
99 cpu
->powered_off
= cpu
->start_powered_off
;
100 s
->halted
= cpu
->start_powered_off
;
102 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
103 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
106 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
107 /* 64 bit CPUs always start in 64 bit mode */
109 #if defined(CONFIG_USER_ONLY)
110 env
->pstate
= PSTATE_MODE_EL0t
;
111 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
112 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
113 /* and to the FP/Neon instructions */
114 env
->cp15
.c1_coproc
= deposit64(env
->cp15
.c1_coproc
, 20, 2, 3);
116 env
->pstate
= PSTATE_MODE_EL1h
;
117 env
->pc
= cpu
->rvbar
;
120 #if defined(CONFIG_USER_ONLY)
121 /* Userspace expects access to cp10 and cp11 for FP/Neon */
122 env
->cp15
.c1_coproc
= deposit64(env
->cp15
.c1_coproc
, 20, 4, 0xf);
126 #if defined(CONFIG_USER_ONLY)
127 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
128 /* For user mode we must enable access to coprocessors */
129 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
130 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
131 env
->cp15
.c15_cpar
= 3;
132 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
133 env
->cp15
.c15_cpar
= 1;
136 /* SVC mode with interrupts disabled. */
137 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
138 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
139 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
140 * clear at reset. Initial SP and PC are loaded from ROM.
143 uint32_t initial_msp
; /* Loaded from 0x0 */
144 uint32_t initial_pc
; /* Loaded from 0x4 */
147 env
->daif
&= ~PSTATE_I
;
150 /* Address zero is covered by ROM which hasn't yet been
151 * copied into physical memory.
153 initial_msp
= ldl_p(rom
);
154 initial_pc
= ldl_p(rom
+ 4);
156 /* Address zero not covered by a ROM blob, or the ROM blob
157 * is in non-modifiable memory and this is a second reset after
158 * it got copied into memory. In the latter case, rom_ptr
159 * will return a NULL pointer and we should use ldl_phys instead.
161 initial_msp
= ldl_phys(s
->as
, 0);
162 initial_pc
= ldl_phys(s
->as
, 4);
165 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
166 env
->regs
[15] = initial_pc
& ~1;
167 env
->thumb
= initial_pc
& 1;
170 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
171 * executing as AArch32 then check if highvecs are enabled and
172 * adjust the PC accordingly.
174 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
175 env
->regs
[15] = 0xFFFF0000;
178 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
180 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
181 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
182 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
183 set_float_detect_tininess(float_tininess_before_rounding
,
184 &env
->vfp
.fp_status
);
185 set_float_detect_tininess(float_tininess_before_rounding
,
186 &env
->vfp
.standard_fp_status
);
189 #ifndef CONFIG_USER_ONLY
191 kvm_arm_reset_vcpu(cpu
);
195 hw_breakpoint_update_all(cpu
);
196 hw_watchpoint_update_all(cpu
);
199 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
201 CPUClass
*cc
= CPU_GET_CLASS(cs
);
204 if (interrupt_request
& CPU_INTERRUPT_FIQ
205 && arm_excp_unmasked(cs
, EXCP_FIQ
)) {
206 cs
->exception_index
= EXCP_FIQ
;
207 cc
->do_interrupt(cs
);
210 if (interrupt_request
& CPU_INTERRUPT_HARD
211 && arm_excp_unmasked(cs
, EXCP_IRQ
)) {
212 cs
->exception_index
= EXCP_IRQ
;
213 cc
->do_interrupt(cs
);
216 if (interrupt_request
& CPU_INTERRUPT_VIRQ
217 && arm_excp_unmasked(cs
, EXCP_VIRQ
)) {
218 cs
->exception_index
= EXCP_VIRQ
;
219 cc
->do_interrupt(cs
);
222 if (interrupt_request
& CPU_INTERRUPT_VFIQ
223 && arm_excp_unmasked(cs
, EXCP_VFIQ
)) {
224 cs
->exception_index
= EXCP_VFIQ
;
225 cc
->do_interrupt(cs
);
232 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
233 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
235 CPUClass
*cc
= CPU_GET_CLASS(cs
);
236 ARMCPU
*cpu
= ARM_CPU(cs
);
237 CPUARMState
*env
= &cpu
->env
;
241 if (interrupt_request
& CPU_INTERRUPT_FIQ
242 && !(env
->daif
& PSTATE_F
)) {
243 cs
->exception_index
= EXCP_FIQ
;
244 cc
->do_interrupt(cs
);
247 /* ARMv7-M interrupt return works by loading a magic value
248 * into the PC. On real hardware the load causes the
249 * return to occur. The qemu implementation performs the
250 * jump normally, then does the exception return when the
251 * CPU tries to execute code at the magic address.
252 * This will cause the magic PC value to be pushed to
253 * the stack if an interrupt occurred at the wrong time.
254 * We avoid this by disabling interrupts when
255 * pc contains a magic address.
257 if (interrupt_request
& CPU_INTERRUPT_HARD
258 && !(env
->daif
& PSTATE_I
)
259 && (env
->regs
[15] < 0xfffffff0)) {
260 cs
->exception_index
= EXCP_IRQ
;
261 cc
->do_interrupt(cs
);
268 #ifndef CONFIG_USER_ONLY
269 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
271 ARMCPU
*cpu
= opaque
;
272 CPUARMState
*env
= &cpu
->env
;
273 CPUState
*cs
= CPU(cpu
);
274 static const int mask
[] = {
275 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
276 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
277 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
278 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
284 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
285 hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
292 cpu_interrupt(cs
, mask
[irq
]);
294 cpu_reset_interrupt(cs
, mask
[irq
]);
298 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq
);
302 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
305 ARMCPU
*cpu
= opaque
;
306 CPUState
*cs
= CPU(cpu
);
307 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
311 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
314 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
317 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq
);
319 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
320 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
325 static inline void set_feature(CPUARMState
*env
, int feature
)
327 env
->features
|= 1ULL << feature
;
330 static inline void unset_feature(CPUARMState
*env
, int feature
)
332 env
->features
&= ~(1ULL << feature
);
335 static void arm_cpu_initfn(Object
*obj
)
337 CPUState
*cs
= CPU(obj
);
338 ARMCPU
*cpu
= ARM_CPU(obj
);
341 cs
->env_ptr
= &cpu
->env
;
342 cpu_exec_init(&cpu
->env
);
343 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
346 #ifndef CONFIG_USER_ONLY
347 /* Our inbound IRQ and FIQ lines */
349 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
350 * the same interface as non-KVM CPUs.
352 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
354 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
357 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
358 arm_gt_ptimer_cb
, cpu
);
359 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
360 arm_gt_vtimer_cb
, cpu
);
361 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
362 ARRAY_SIZE(cpu
->gt_timer_outputs
));
365 /* DTB consumers generally don't in fact care what the 'compatible'
366 * string is, so always provide some string and trust that a hypothetical
367 * picky DTB consumer will also provide a helpful error message.
369 cpu
->dtb_compatible
= "qemu,unknown";
370 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
371 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
374 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
377 arm_translate_init();
382 static Property arm_cpu_reset_cbar_property
=
383 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
385 static Property arm_cpu_reset_hivecs_property
=
386 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
388 static Property arm_cpu_rvbar_property
=
389 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
391 static Property arm_cpu_has_el3_property
=
392 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
394 static void arm_cpu_post_init(Object
*obj
)
396 ARMCPU
*cpu
= ARM_CPU(obj
);
398 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
399 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
400 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
404 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
405 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
409 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
410 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
414 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
415 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
416 * prevent "has_el3" from existing on CPUs which cannot support EL3.
418 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
423 static void arm_cpu_finalizefn(Object
*obj
)
425 ARMCPU
*cpu
= ARM_CPU(obj
);
426 g_hash_table_destroy(cpu
->cp_regs
);
429 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
431 CPUState
*cs
= CPU(dev
);
432 ARMCPU
*cpu
= ARM_CPU(dev
);
433 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
434 CPUARMState
*env
= &cpu
->env
;
436 /* Some features automatically imply others: */
437 if (arm_feature(env
, ARM_FEATURE_V8
)) {
438 set_feature(env
, ARM_FEATURE_V7
);
439 set_feature(env
, ARM_FEATURE_ARM_DIV
);
440 set_feature(env
, ARM_FEATURE_LPAE
);
442 if (arm_feature(env
, ARM_FEATURE_V7
)) {
443 set_feature(env
, ARM_FEATURE_VAPA
);
444 set_feature(env
, ARM_FEATURE_THUMB2
);
445 set_feature(env
, ARM_FEATURE_MPIDR
);
446 if (!arm_feature(env
, ARM_FEATURE_M
)) {
447 set_feature(env
, ARM_FEATURE_V6K
);
449 set_feature(env
, ARM_FEATURE_V6
);
452 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
453 set_feature(env
, ARM_FEATURE_V6
);
454 set_feature(env
, ARM_FEATURE_MVFR
);
456 if (arm_feature(env
, ARM_FEATURE_V6
)) {
457 set_feature(env
, ARM_FEATURE_V5
);
458 if (!arm_feature(env
, ARM_FEATURE_M
)) {
459 set_feature(env
, ARM_FEATURE_AUXCR
);
462 if (arm_feature(env
, ARM_FEATURE_V5
)) {
463 set_feature(env
, ARM_FEATURE_V4T
);
465 if (arm_feature(env
, ARM_FEATURE_M
)) {
466 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
468 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
469 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
471 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
472 set_feature(env
, ARM_FEATURE_VFP3
);
473 set_feature(env
, ARM_FEATURE_VFP_FP16
);
475 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
476 set_feature(env
, ARM_FEATURE_VFP
);
478 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
479 set_feature(env
, ARM_FEATURE_V7MP
);
480 set_feature(env
, ARM_FEATURE_PXN
);
482 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
483 set_feature(env
, ARM_FEATURE_CBAR
);
486 if (cpu
->reset_hivecs
) {
487 cpu
->reset_sctlr
|= (1 << 13);
491 /* If the has_el3 CPU property is disabled then we need to disable the
494 unset_feature(env
, ARM_FEATURE_EL3
);
496 /* Disable the security extension feature bits in the processor feature
497 * register as well. This is id_pfr1[7:4].
499 cpu
->id_pfr1
&= ~0xf0;
502 register_cp_regs_for_features(cpu
);
503 arm_cpu_register_gdb_regs_for_features(cpu
);
505 init_cpreg_list(cpu
);
510 acc
->parent_realize(dev
, errp
);
513 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
522 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpu_model
);
523 oc
= object_class_by_name(typename
);
525 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
526 object_class_is_abstract(oc
)) {
532 /* CPU models. These are not needed for the AArch64 linux-user build. */
533 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
535 static void arm926_initfn(Object
*obj
)
537 ARMCPU
*cpu
= ARM_CPU(obj
);
539 cpu
->dtb_compatible
= "arm,arm926";
540 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
541 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
542 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
543 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
544 cpu
->midr
= 0x41069265;
545 cpu
->reset_fpsid
= 0x41011090;
546 cpu
->ctr
= 0x1dd20d2;
547 cpu
->reset_sctlr
= 0x00090078;
550 static void arm946_initfn(Object
*obj
)
552 ARMCPU
*cpu
= ARM_CPU(obj
);
554 cpu
->dtb_compatible
= "arm,arm946";
555 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
556 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
557 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
558 cpu
->midr
= 0x41059461;
559 cpu
->ctr
= 0x0f004006;
560 cpu
->reset_sctlr
= 0x00000078;
563 static void arm1026_initfn(Object
*obj
)
565 ARMCPU
*cpu
= ARM_CPU(obj
);
567 cpu
->dtb_compatible
= "arm,arm1026";
568 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
569 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
570 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
571 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
572 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
573 cpu
->midr
= 0x4106a262;
574 cpu
->reset_fpsid
= 0x410110a0;
575 cpu
->ctr
= 0x1dd20d2;
576 cpu
->reset_sctlr
= 0x00090078;
577 cpu
->reset_auxcr
= 1;
579 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
580 ARMCPRegInfo ifar
= {
581 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
583 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
586 define_one_arm_cp_reg(cpu
, &ifar
);
590 static void arm1136_r2_initfn(Object
*obj
)
592 ARMCPU
*cpu
= ARM_CPU(obj
);
593 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
594 * older core than plain "arm1136". In particular this does not
595 * have the v6K features.
596 * These ID register values are correct for 1136 but may be wrong
597 * for 1136_r2 (in particular r0p2 does not actually implement most
598 * of the ID registers).
601 cpu
->dtb_compatible
= "arm,arm1136";
602 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
603 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
604 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
605 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
606 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
607 cpu
->midr
= 0x4107b362;
608 cpu
->reset_fpsid
= 0x410120b4;
609 cpu
->mvfr0
= 0x11111111;
610 cpu
->mvfr1
= 0x00000000;
611 cpu
->ctr
= 0x1dd20d2;
612 cpu
->reset_sctlr
= 0x00050078;
613 cpu
->id_pfr0
= 0x111;
617 cpu
->id_mmfr0
= 0x01130003;
618 cpu
->id_mmfr1
= 0x10030302;
619 cpu
->id_mmfr2
= 0x01222110;
620 cpu
->id_isar0
= 0x00140011;
621 cpu
->id_isar1
= 0x12002111;
622 cpu
->id_isar2
= 0x11231111;
623 cpu
->id_isar3
= 0x01102131;
624 cpu
->id_isar4
= 0x141;
625 cpu
->reset_auxcr
= 7;
628 static void arm1136_initfn(Object
*obj
)
630 ARMCPU
*cpu
= ARM_CPU(obj
);
632 cpu
->dtb_compatible
= "arm,arm1136";
633 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
634 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
635 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
636 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
637 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
638 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
639 cpu
->midr
= 0x4117b363;
640 cpu
->reset_fpsid
= 0x410120b4;
641 cpu
->mvfr0
= 0x11111111;
642 cpu
->mvfr1
= 0x00000000;
643 cpu
->ctr
= 0x1dd20d2;
644 cpu
->reset_sctlr
= 0x00050078;
645 cpu
->id_pfr0
= 0x111;
649 cpu
->id_mmfr0
= 0x01130003;
650 cpu
->id_mmfr1
= 0x10030302;
651 cpu
->id_mmfr2
= 0x01222110;
652 cpu
->id_isar0
= 0x00140011;
653 cpu
->id_isar1
= 0x12002111;
654 cpu
->id_isar2
= 0x11231111;
655 cpu
->id_isar3
= 0x01102131;
656 cpu
->id_isar4
= 0x141;
657 cpu
->reset_auxcr
= 7;
660 static void arm1176_initfn(Object
*obj
)
662 ARMCPU
*cpu
= ARM_CPU(obj
);
664 cpu
->dtb_compatible
= "arm,arm1176";
665 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
666 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
667 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
668 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
669 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
670 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
671 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
672 cpu
->midr
= 0x410fb767;
673 cpu
->reset_fpsid
= 0x410120b5;
674 cpu
->mvfr0
= 0x11111111;
675 cpu
->mvfr1
= 0x00000000;
676 cpu
->ctr
= 0x1dd20d2;
677 cpu
->reset_sctlr
= 0x00050078;
678 cpu
->id_pfr0
= 0x111;
682 cpu
->id_mmfr0
= 0x01130003;
683 cpu
->id_mmfr1
= 0x10030302;
684 cpu
->id_mmfr2
= 0x01222100;
685 cpu
->id_isar0
= 0x0140011;
686 cpu
->id_isar1
= 0x12002111;
687 cpu
->id_isar2
= 0x11231121;
688 cpu
->id_isar3
= 0x01102131;
689 cpu
->id_isar4
= 0x01141;
690 cpu
->reset_auxcr
= 7;
693 static void arm11mpcore_initfn(Object
*obj
)
695 ARMCPU
*cpu
= ARM_CPU(obj
);
697 cpu
->dtb_compatible
= "arm,arm11mpcore";
698 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
699 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
700 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
701 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
702 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
703 cpu
->midr
= 0x410fb022;
704 cpu
->reset_fpsid
= 0x410120b4;
705 cpu
->mvfr0
= 0x11111111;
706 cpu
->mvfr1
= 0x00000000;
707 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
708 cpu
->id_pfr0
= 0x111;
712 cpu
->id_mmfr0
= 0x01100103;
713 cpu
->id_mmfr1
= 0x10020302;
714 cpu
->id_mmfr2
= 0x01222000;
715 cpu
->id_isar0
= 0x00100011;
716 cpu
->id_isar1
= 0x12002111;
717 cpu
->id_isar2
= 0x11221011;
718 cpu
->id_isar3
= 0x01102131;
719 cpu
->id_isar4
= 0x141;
720 cpu
->reset_auxcr
= 1;
723 static void cortex_m3_initfn(Object
*obj
)
725 ARMCPU
*cpu
= ARM_CPU(obj
);
726 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
727 set_feature(&cpu
->env
, ARM_FEATURE_M
);
728 cpu
->midr
= 0x410fc231;
731 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
733 CPUClass
*cc
= CPU_CLASS(oc
);
735 #ifndef CONFIG_USER_ONLY
736 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
739 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
742 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
743 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
744 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
745 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
746 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
750 static void cortex_a8_initfn(Object
*obj
)
752 ARMCPU
*cpu
= ARM_CPU(obj
);
754 cpu
->dtb_compatible
= "arm,cortex-a8";
755 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
756 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
757 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
758 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
759 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
760 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
761 cpu
->midr
= 0x410fc080;
762 cpu
->reset_fpsid
= 0x410330c0;
763 cpu
->mvfr0
= 0x11110222;
764 cpu
->mvfr1
= 0x00011100;
765 cpu
->ctr
= 0x82048004;
766 cpu
->reset_sctlr
= 0x00c50078;
767 cpu
->id_pfr0
= 0x1031;
769 cpu
->id_dfr0
= 0x400;
771 cpu
->id_mmfr0
= 0x31100003;
772 cpu
->id_mmfr1
= 0x20000000;
773 cpu
->id_mmfr2
= 0x01202000;
774 cpu
->id_mmfr3
= 0x11;
775 cpu
->id_isar0
= 0x00101111;
776 cpu
->id_isar1
= 0x12112111;
777 cpu
->id_isar2
= 0x21232031;
778 cpu
->id_isar3
= 0x11112131;
779 cpu
->id_isar4
= 0x00111142;
780 cpu
->dbgdidr
= 0x15141000;
781 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
782 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
783 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
784 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
785 cpu
->reset_auxcr
= 2;
786 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
789 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
790 /* power_control should be set to maximum latency. Again,
791 * default to 0 and set by private hook
793 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
794 .access
= PL1_RW
, .resetvalue
= 0,
795 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
796 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
797 .access
= PL1_RW
, .resetvalue
= 0,
798 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
799 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
800 .access
= PL1_RW
, .resetvalue
= 0,
801 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
802 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
803 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
804 /* TLB lockdown control */
805 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
806 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
807 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
808 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
809 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
810 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
811 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
812 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
813 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
814 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
818 static void cortex_a9_initfn(Object
*obj
)
820 ARMCPU
*cpu
= ARM_CPU(obj
);
822 cpu
->dtb_compatible
= "arm,cortex-a9";
823 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
824 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
825 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
826 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
827 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
828 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
829 /* Note that A9 supports the MP extensions even for
830 * A9UP and single-core A9MP (which are both different
831 * and valid configurations; we don't model A9UP).
833 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
834 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
835 cpu
->midr
= 0x410fc090;
836 cpu
->reset_fpsid
= 0x41033090;
837 cpu
->mvfr0
= 0x11110222;
838 cpu
->mvfr1
= 0x01111111;
839 cpu
->ctr
= 0x80038003;
840 cpu
->reset_sctlr
= 0x00c50078;
841 cpu
->id_pfr0
= 0x1031;
843 cpu
->id_dfr0
= 0x000;
845 cpu
->id_mmfr0
= 0x00100103;
846 cpu
->id_mmfr1
= 0x20000000;
847 cpu
->id_mmfr2
= 0x01230000;
848 cpu
->id_mmfr3
= 0x00002111;
849 cpu
->id_isar0
= 0x00101111;
850 cpu
->id_isar1
= 0x13112111;
851 cpu
->id_isar2
= 0x21232041;
852 cpu
->id_isar3
= 0x11112131;
853 cpu
->id_isar4
= 0x00111142;
854 cpu
->dbgdidr
= 0x35141000;
855 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
856 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
857 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
858 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
861 #ifndef CONFIG_USER_ONLY
862 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
864 /* Linux wants the number of processors from here.
865 * Might as well set the interrupt-controller bit too.
867 return ((smp_cpus
- 1) << 24) | (1 << 23);
871 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
872 #ifndef CONFIG_USER_ONLY
873 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
874 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
875 .writefn
= arm_cp_write_ignore
, },
877 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
878 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
882 static void cortex_a15_initfn(Object
*obj
)
884 ARMCPU
*cpu
= ARM_CPU(obj
);
886 cpu
->dtb_compatible
= "arm,cortex-a15";
887 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
888 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
889 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
890 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
891 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
892 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
893 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
894 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
895 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
896 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
897 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
898 cpu
->midr
= 0x412fc0f1;
899 cpu
->reset_fpsid
= 0x410430f0;
900 cpu
->mvfr0
= 0x10110222;
901 cpu
->mvfr1
= 0x11111111;
902 cpu
->ctr
= 0x8444c004;
903 cpu
->reset_sctlr
= 0x00c50078;
904 cpu
->id_pfr0
= 0x00001131;
905 cpu
->id_pfr1
= 0x00011011;
906 cpu
->id_dfr0
= 0x02010555;
907 cpu
->id_afr0
= 0x00000000;
908 cpu
->id_mmfr0
= 0x10201105;
909 cpu
->id_mmfr1
= 0x20000000;
910 cpu
->id_mmfr2
= 0x01240000;
911 cpu
->id_mmfr3
= 0x02102211;
912 cpu
->id_isar0
= 0x02101110;
913 cpu
->id_isar1
= 0x13112111;
914 cpu
->id_isar2
= 0x21232041;
915 cpu
->id_isar3
= 0x11112131;
916 cpu
->id_isar4
= 0x10011142;
917 cpu
->dbgdidr
= 0x3515f021;
918 cpu
->clidr
= 0x0a200023;
919 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
920 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
921 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
922 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
925 static void ti925t_initfn(Object
*obj
)
927 ARMCPU
*cpu
= ARM_CPU(obj
);
928 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
929 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
930 cpu
->midr
= ARM_CPUID_TI925T
;
931 cpu
->ctr
= 0x5109149;
932 cpu
->reset_sctlr
= 0x00000070;
935 static void sa1100_initfn(Object
*obj
)
937 ARMCPU
*cpu
= ARM_CPU(obj
);
939 cpu
->dtb_compatible
= "intel,sa1100";
940 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
941 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
942 cpu
->midr
= 0x4401A11B;
943 cpu
->reset_sctlr
= 0x00000070;
946 static void sa1110_initfn(Object
*obj
)
948 ARMCPU
*cpu
= ARM_CPU(obj
);
949 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
950 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
951 cpu
->midr
= 0x6901B119;
952 cpu
->reset_sctlr
= 0x00000070;
955 static void pxa250_initfn(Object
*obj
)
957 ARMCPU
*cpu
= ARM_CPU(obj
);
959 cpu
->dtb_compatible
= "marvell,xscale";
960 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
961 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
962 cpu
->midr
= 0x69052100;
963 cpu
->ctr
= 0xd172172;
964 cpu
->reset_sctlr
= 0x00000078;
967 static void pxa255_initfn(Object
*obj
)
969 ARMCPU
*cpu
= ARM_CPU(obj
);
971 cpu
->dtb_compatible
= "marvell,xscale";
972 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
973 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
974 cpu
->midr
= 0x69052d00;
975 cpu
->ctr
= 0xd172172;
976 cpu
->reset_sctlr
= 0x00000078;
979 static void pxa260_initfn(Object
*obj
)
981 ARMCPU
*cpu
= ARM_CPU(obj
);
983 cpu
->dtb_compatible
= "marvell,xscale";
984 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
985 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
986 cpu
->midr
= 0x69052903;
987 cpu
->ctr
= 0xd172172;
988 cpu
->reset_sctlr
= 0x00000078;
991 static void pxa261_initfn(Object
*obj
)
993 ARMCPU
*cpu
= ARM_CPU(obj
);
995 cpu
->dtb_compatible
= "marvell,xscale";
996 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
997 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
998 cpu
->midr
= 0x69052d05;
999 cpu
->ctr
= 0xd172172;
1000 cpu
->reset_sctlr
= 0x00000078;
1003 static void pxa262_initfn(Object
*obj
)
1005 ARMCPU
*cpu
= ARM_CPU(obj
);
1007 cpu
->dtb_compatible
= "marvell,xscale";
1008 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1009 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1010 cpu
->midr
= 0x69052d06;
1011 cpu
->ctr
= 0xd172172;
1012 cpu
->reset_sctlr
= 0x00000078;
1015 static void pxa270a0_initfn(Object
*obj
)
1017 ARMCPU
*cpu
= ARM_CPU(obj
);
1019 cpu
->dtb_compatible
= "marvell,xscale";
1020 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1021 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1022 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1023 cpu
->midr
= 0x69054110;
1024 cpu
->ctr
= 0xd172172;
1025 cpu
->reset_sctlr
= 0x00000078;
1028 static void pxa270a1_initfn(Object
*obj
)
1030 ARMCPU
*cpu
= ARM_CPU(obj
);
1032 cpu
->dtb_compatible
= "marvell,xscale";
1033 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1034 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1035 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1036 cpu
->midr
= 0x69054111;
1037 cpu
->ctr
= 0xd172172;
1038 cpu
->reset_sctlr
= 0x00000078;
1041 static void pxa270b0_initfn(Object
*obj
)
1043 ARMCPU
*cpu
= ARM_CPU(obj
);
1045 cpu
->dtb_compatible
= "marvell,xscale";
1046 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1047 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1048 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1049 cpu
->midr
= 0x69054112;
1050 cpu
->ctr
= 0xd172172;
1051 cpu
->reset_sctlr
= 0x00000078;
1054 static void pxa270b1_initfn(Object
*obj
)
1056 ARMCPU
*cpu
= ARM_CPU(obj
);
1058 cpu
->dtb_compatible
= "marvell,xscale";
1059 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1060 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1061 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1062 cpu
->midr
= 0x69054113;
1063 cpu
->ctr
= 0xd172172;
1064 cpu
->reset_sctlr
= 0x00000078;
1067 static void pxa270c0_initfn(Object
*obj
)
1069 ARMCPU
*cpu
= ARM_CPU(obj
);
1071 cpu
->dtb_compatible
= "marvell,xscale";
1072 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1073 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1074 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1075 cpu
->midr
= 0x69054114;
1076 cpu
->ctr
= 0xd172172;
1077 cpu
->reset_sctlr
= 0x00000078;
1080 static void pxa270c5_initfn(Object
*obj
)
1082 ARMCPU
*cpu
= ARM_CPU(obj
);
1084 cpu
->dtb_compatible
= "marvell,xscale";
1085 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1086 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1087 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1088 cpu
->midr
= 0x69054117;
1089 cpu
->ctr
= 0xd172172;
1090 cpu
->reset_sctlr
= 0x00000078;
1093 #ifdef CONFIG_USER_ONLY
1094 static void arm_any_initfn(Object
*obj
)
1096 ARMCPU
*cpu
= ARM_CPU(obj
);
1097 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1098 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1099 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1100 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1101 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1102 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1103 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1104 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1105 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1106 cpu
->midr
= 0xffffffff;
1110 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1112 typedef struct ARMCPUInfo
{
1114 void (*initfn
)(Object
*obj
);
1115 void (*class_init
)(ObjectClass
*oc
, void *data
);
1118 static const ARMCPUInfo arm_cpus
[] = {
1119 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1120 { .name
= "arm926", .initfn
= arm926_initfn
},
1121 { .name
= "arm946", .initfn
= arm946_initfn
},
1122 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1123 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1124 * older core than plain "arm1136". In particular this does not
1125 * have the v6K features.
1127 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1128 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1129 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1130 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1131 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1132 .class_init
= arm_v7m_class_init
},
1133 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1134 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1135 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1136 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1137 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1138 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1139 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1140 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1141 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1142 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1143 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1144 /* "pxa270" is an alias for "pxa270-a0" */
1145 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1146 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1147 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1148 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1149 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1150 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1151 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1152 #ifdef CONFIG_USER_ONLY
1153 { .name
= "any", .initfn
= arm_any_initfn
},
1159 static Property arm_cpu_properties
[] = {
1160 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1161 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1162 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1163 DEFINE_PROP_END_OF_LIST()
1166 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1168 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1169 CPUClass
*cc
= CPU_CLASS(acc
);
1170 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1172 acc
->parent_realize
= dc
->realize
;
1173 dc
->realize
= arm_cpu_realizefn
;
1174 dc
->props
= arm_cpu_properties
;
1176 acc
->parent_reset
= cc
->reset
;
1177 cc
->reset
= arm_cpu_reset
;
1179 cc
->class_by_name
= arm_cpu_class_by_name
;
1180 cc
->has_work
= arm_cpu_has_work
;
1181 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1182 cc
->dump_state
= arm_cpu_dump_state
;
1183 cc
->set_pc
= arm_cpu_set_pc
;
1184 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1185 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1186 #ifdef CONFIG_USER_ONLY
1187 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1189 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1190 cc
->get_phys_page_debug
= arm_cpu_get_phys_page_debug
;
1191 cc
->vmsd
= &vmstate_arm_cpu
;
1193 cc
->gdb_num_core_regs
= 26;
1194 cc
->gdb_core_xml_file
= "arm-core.xml";
1195 cc
->gdb_stop_before_watchpoint
= true;
1196 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1199 static void cpu_register(const ARMCPUInfo
*info
)
1201 TypeInfo type_info
= {
1202 .parent
= TYPE_ARM_CPU
,
1203 .instance_size
= sizeof(ARMCPU
),
1204 .instance_init
= info
->initfn
,
1205 .class_size
= sizeof(ARMCPUClass
),
1206 .class_init
= info
->class_init
,
1209 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1210 type_register(&type_info
);
1211 g_free((void *)type_info
.name
);
1214 static const TypeInfo arm_cpu_type_info
= {
1215 .name
= TYPE_ARM_CPU
,
1217 .instance_size
= sizeof(ARMCPU
),
1218 .instance_init
= arm_cpu_initfn
,
1219 .instance_post_init
= arm_cpu_post_init
,
1220 .instance_finalize
= arm_cpu_finalizefn
,
1222 .class_size
= sizeof(ARMCPUClass
),
1223 .class_init
= arm_cpu_class_init
,
1226 static void arm_cpu_register_types(void)
1228 const ARMCPUInfo
*info
= arm_cpus
;
1230 type_register_static(&arm_cpu_type_info
);
1232 while (info
->name
) {
1238 type_init(arm_cpu_register_types
)