4 * Generate helpers used by TCG for qemu_ld/st ops and code load
7 * Included from target op helpers and exec.c.
9 * Copyright (c) 2003 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/timer.h"
25 #include "exec/address-spaces.h"
26 #include "exec/memory.h"
28 #define DATA_SIZE (1 << SHIFT)
33 #define SDATA_TYPE int64_t
34 #define DATA_TYPE uint64_t
38 #define SDATA_TYPE int32_t
39 #define DATA_TYPE uint32_t
43 #define SDATA_TYPE int16_t
44 #define DATA_TYPE uint16_t
48 #define SDATA_TYPE int8_t
49 #define DATA_TYPE uint8_t
51 #error unsupported data size
55 /* For the benefit of TCG generated code, we want to avoid the complication
56 of ABI-specific return type promotion and always return a value extended
57 to the register size of the host. This is tcg_target_long, except in the
58 case of a 32-bit host and 64-bit data, and for that we always have
59 uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
61 # define WORD_TYPE DATA_TYPE
62 # define USUFFIX SUFFIX
64 # define WORD_TYPE tcg_target_ulong
65 # define USUFFIX glue(u, SUFFIX)
66 # define SSUFFIX glue(s, SUFFIX)
69 #ifdef SOFTMMU_CODE_ACCESS
70 #define READ_ACCESS_TYPE 2
71 #define ADDR_READ addr_code
73 #define READ_ACCESS_TYPE 0
74 #define ADDR_READ addr_read
78 # define BSWAP(X) bswap64(X)
80 # define BSWAP(X) bswap32(X)
82 # define BSWAP(X) bswap16(X)
87 #ifdef TARGET_WORDS_BIGENDIAN
88 # define TGT_BE(X) (X)
89 # define TGT_LE(X) BSWAP(X)
91 # define TGT_BE(X) BSWAP(X)
92 # define TGT_LE(X) (X)
96 # define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
97 # define helper_be_ld_name helper_le_ld_name
98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
99 # define helper_be_lds_name helper_le_lds_name
100 # define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
101 # define helper_be_st_name helper_le_st_name
103 # define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
104 # define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
107 # define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
108 # define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
111 #ifdef TARGET_WORDS_BIGENDIAN
112 # define helper_te_ld_name helper_be_ld_name
113 # define helper_te_st_name helper_be_st_name
115 # define helper_te_ld_name helper_le_ld_name
116 # define helper_te_st_name helper_le_st_name
119 static inline DATA_TYPE
glue(io_read
, SUFFIX
)(CPUArchState
*env
,
125 CPUState
*cpu
= ENV_GET_CPU(env
);
126 MemoryRegion
*mr
= iotlb_to_region(cpu
->as
, physaddr
);
128 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
129 env
->mem_io_pc
= retaddr
;
130 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !can_do_io(env
)) {
131 cpu_io_recompile(env
, retaddr
);
134 env
->mem_io_vaddr
= addr
;
135 io_mem_read(mr
, physaddr
, &val
, 1 << SHIFT
);
139 #ifdef SOFTMMU_CODE_ACCESS
140 static __attribute__((unused
))
142 WORD_TYPE
helper_le_ld_name(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
145 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
146 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
150 /* Adjust the given return address. */
151 retaddr
-= GETPC_ADJ
;
153 /* If the TLB entry is for a different page, reload and try again. */
154 if ((addr
& TARGET_PAGE_MASK
)
155 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
157 if ((addr
& (DATA_SIZE
- 1)) != 0) {
158 do_unaligned_access(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
161 tlb_fill(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
162 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
165 /* Handle an IO access. */
166 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
168 if ((addr
& (DATA_SIZE
- 1)) != 0) {
169 goto do_unaligned_access
;
171 ioaddr
= env
->iotlb
[mmu_idx
][index
];
173 /* ??? Note that the io helpers always read data in the target
174 byte ordering. We should push the LE/BE request down into io. */
175 res
= glue(io_read
, SUFFIX
)(env
, ioaddr
, addr
, retaddr
);
180 /* Handle slow unaligned access (it spans two pages or IO). */
182 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
183 >= TARGET_PAGE_SIZE
)) {
184 target_ulong addr1
, addr2
;
185 DATA_TYPE res1
, res2
;
189 do_unaligned_access(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
191 addr1
= addr
& ~(DATA_SIZE
- 1);
192 addr2
= addr1
+ DATA_SIZE
;
193 /* Note the adjustment at the beginning of the function.
194 Undo that for the recursion. */
195 res1
= helper_le_ld_name(env
, addr1
, mmu_idx
, retaddr
+ GETPC_ADJ
);
196 res2
= helper_le_ld_name(env
, addr2
, mmu_idx
, retaddr
+ GETPC_ADJ
);
197 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
199 /* Little-endian combine. */
200 res
= (res1
>> shift
) | (res2
<< ((DATA_SIZE
* 8) - shift
));
204 /* Handle aligned access or unaligned access in the same page. */
206 if ((addr
& (DATA_SIZE
- 1)) != 0) {
207 do_unaligned_access(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
211 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
213 res
= glue(glue(ld
, LSUFFIX
), _p
)((uint8_t *)haddr
);
215 res
= glue(glue(ld
, LSUFFIX
), _le_p
)((uint8_t *)haddr
);
221 #ifdef SOFTMMU_CODE_ACCESS
222 static __attribute__((unused
))
224 WORD_TYPE
helper_be_ld_name(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
227 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
228 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
232 /* Adjust the given return address. */
233 retaddr
-= GETPC_ADJ
;
235 /* If the TLB entry is for a different page, reload and try again. */
236 if ((addr
& TARGET_PAGE_MASK
)
237 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
239 if ((addr
& (DATA_SIZE
- 1)) != 0) {
240 do_unaligned_access(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
243 tlb_fill(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
244 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
247 /* Handle an IO access. */
248 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
250 if ((addr
& (DATA_SIZE
- 1)) != 0) {
251 goto do_unaligned_access
;
253 ioaddr
= env
->iotlb
[mmu_idx
][index
];
255 /* ??? Note that the io helpers always read data in the target
256 byte ordering. We should push the LE/BE request down into io. */
257 res
= glue(io_read
, SUFFIX
)(env
, ioaddr
, addr
, retaddr
);
262 /* Handle slow unaligned access (it spans two pages or IO). */
264 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
265 >= TARGET_PAGE_SIZE
)) {
266 target_ulong addr1
, addr2
;
267 DATA_TYPE res1
, res2
;
271 do_unaligned_access(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
273 addr1
= addr
& ~(DATA_SIZE
- 1);
274 addr2
= addr1
+ DATA_SIZE
;
275 /* Note the adjustment at the beginning of the function.
276 Undo that for the recursion. */
277 res1
= helper_be_ld_name(env
, addr1
, mmu_idx
, retaddr
+ GETPC_ADJ
);
278 res2
= helper_be_ld_name(env
, addr2
, mmu_idx
, retaddr
+ GETPC_ADJ
);
279 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
281 /* Big-endian combine. */
282 res
= (res1
<< shift
) | (res2
>> ((DATA_SIZE
* 8) - shift
));
286 /* Handle aligned access or unaligned access in the same page. */
288 if ((addr
& (DATA_SIZE
- 1)) != 0) {
289 do_unaligned_access(env
, addr
, READ_ACCESS_TYPE
, mmu_idx
, retaddr
);
293 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
294 res
= glue(glue(ld
, LSUFFIX
), _be_p
)((uint8_t *)haddr
);
297 #endif /* DATA_SIZE > 1 */
300 glue(glue(helper_ld
, SUFFIX
), MMUSUFFIX
)(CPUArchState
*env
, target_ulong addr
,
303 return helper_te_ld_name (env
, addr
, mmu_idx
, GETRA());
306 #ifndef SOFTMMU_CODE_ACCESS
308 /* Provide signed versions of the load routines as well. We can of course
309 avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
310 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
311 WORD_TYPE
helper_le_lds_name(CPUArchState
*env
, target_ulong addr
,
312 int mmu_idx
, uintptr_t retaddr
)
314 return (SDATA_TYPE
)helper_le_ld_name(env
, addr
, mmu_idx
, retaddr
);
318 WORD_TYPE
helper_be_lds_name(CPUArchState
*env
, target_ulong addr
,
319 int mmu_idx
, uintptr_t retaddr
)
321 return (SDATA_TYPE
)helper_be_ld_name(env
, addr
, mmu_idx
, retaddr
);
326 static inline void glue(io_write
, SUFFIX
)(CPUArchState
*env
,
332 CPUState
*cpu
= ENV_GET_CPU(env
);
333 MemoryRegion
*mr
= iotlb_to_region(cpu
->as
, physaddr
);
335 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
336 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !can_do_io(env
)) {
337 cpu_io_recompile(env
, retaddr
);
340 env
->mem_io_vaddr
= addr
;
341 env
->mem_io_pc
= retaddr
;
342 io_mem_write(mr
, physaddr
, val
, 1 << SHIFT
);
345 void helper_le_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
346 int mmu_idx
, uintptr_t retaddr
)
348 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
349 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
352 /* Adjust the given return address. */
353 retaddr
-= GETPC_ADJ
;
355 /* If the TLB entry is for a different page, reload and try again. */
356 if ((addr
& TARGET_PAGE_MASK
)
357 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
359 if ((addr
& (DATA_SIZE
- 1)) != 0) {
360 do_unaligned_access(env
, addr
, 1, mmu_idx
, retaddr
);
363 tlb_fill(env
, addr
, 1, mmu_idx
, retaddr
);
364 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
367 /* Handle an IO access. */
368 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
370 if ((addr
& (DATA_SIZE
- 1)) != 0) {
371 goto do_unaligned_access
;
373 ioaddr
= env
->iotlb
[mmu_idx
][index
];
375 /* ??? Note that the io helpers always read data in the target
376 byte ordering. We should push the LE/BE request down into io. */
378 glue(io_write
, SUFFIX
)(env
, ioaddr
, val
, addr
, retaddr
);
382 /* Handle slow unaligned access (it spans two pages or IO). */
384 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
385 >= TARGET_PAGE_SIZE
)) {
389 do_unaligned_access(env
, addr
, 1, mmu_idx
, retaddr
);
391 /* XXX: not efficient, but simple */
392 /* Note: relies on the fact that tlb_fill() does not remove the
393 * previous page from the TLB cache. */
394 for (i
= DATA_SIZE
- 1; i
>= 0; i
--) {
395 /* Little-endian extract. */
396 uint8_t val8
= val
>> (i
* 8);
397 /* Note the adjustment at the beginning of the function.
398 Undo that for the recursion. */
399 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
400 mmu_idx
, retaddr
+ GETPC_ADJ
);
405 /* Handle aligned access or unaligned access in the same page. */
407 if ((addr
& (DATA_SIZE
- 1)) != 0) {
408 do_unaligned_access(env
, addr
, 1, mmu_idx
, retaddr
);
412 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
414 glue(glue(st
, SUFFIX
), _p
)((uint8_t *)haddr
, val
);
416 glue(glue(st
, SUFFIX
), _le_p
)((uint8_t *)haddr
, val
);
421 void helper_be_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
422 int mmu_idx
, uintptr_t retaddr
)
424 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
425 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
428 /* Adjust the given return address. */
429 retaddr
-= GETPC_ADJ
;
431 /* If the TLB entry is for a different page, reload and try again. */
432 if ((addr
& TARGET_PAGE_MASK
)
433 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
435 if ((addr
& (DATA_SIZE
- 1)) != 0) {
436 do_unaligned_access(env
, addr
, 1, mmu_idx
, retaddr
);
439 tlb_fill(env
, addr
, 1, mmu_idx
, retaddr
);
440 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
443 /* Handle an IO access. */
444 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
446 if ((addr
& (DATA_SIZE
- 1)) != 0) {
447 goto do_unaligned_access
;
449 ioaddr
= env
->iotlb
[mmu_idx
][index
];
451 /* ??? Note that the io helpers always read data in the target
452 byte ordering. We should push the LE/BE request down into io. */
454 glue(io_write
, SUFFIX
)(env
, ioaddr
, val
, addr
, retaddr
);
458 /* Handle slow unaligned access (it spans two pages or IO). */
460 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
461 >= TARGET_PAGE_SIZE
)) {
465 do_unaligned_access(env
, addr
, 1, mmu_idx
, retaddr
);
467 /* XXX: not efficient, but simple */
468 /* Note: relies on the fact that tlb_fill() does not remove the
469 * previous page from the TLB cache. */
470 for (i
= DATA_SIZE
- 1; i
>= 0; i
--) {
471 /* Big-endian extract. */
472 uint8_t val8
= val
>> (((DATA_SIZE
- 1) * 8) - (i
* 8));
473 /* Note the adjustment at the beginning of the function.
474 Undo that for the recursion. */
475 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
476 mmu_idx
, retaddr
+ GETPC_ADJ
);
481 /* Handle aligned access or unaligned access in the same page. */
483 if ((addr
& (DATA_SIZE
- 1)) != 0) {
484 do_unaligned_access(env
, addr
, 1, mmu_idx
, retaddr
);
488 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
489 glue(glue(st
, SUFFIX
), _be_p
)((uint8_t *)haddr
, val
);
491 #endif /* DATA_SIZE > 1 */
494 glue(glue(helper_st
, SUFFIX
), MMUSUFFIX
)(CPUArchState
*env
, target_ulong addr
,
495 DATA_TYPE val
, int mmu_idx
)
497 helper_te_st_name(env
, addr
, val
, mmu_idx
, GETRA());
500 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
502 #undef READ_ACCESS_TYPE
518 #undef helper_le_ld_name
519 #undef helper_be_ld_name
520 #undef helper_le_lds_name
521 #undef helper_be_lds_name
522 #undef helper_le_st_name
523 #undef helper_be_st_name
524 #undef helper_te_ld_name
525 #undef helper_te_st_name