hw/isa/pc87312.c

   1 /*
   2  * QEMU National Semiconductor PC87312 (Super I/O)
   3  *
   4  * Copyright (c) 2010-2012 Herve Poussineau
   5  * Copyright (c) 2011-2012 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/isa/pc87312.h"
  27 #include "qemu/error-report.h"
  28 #include "sysemu/blockdev.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/char.h"
  31 #include "trace.h"
  32
  33
  34 #define REG_FER 0
  35 #define REG_FAR 1
  36 #define REG_PTR 2
  37
  38 #define FER_PARALLEL_EN   0x01
  39 #define FER_UART1_EN      0x02
  40 #define FER_UART2_EN      0x04
  41 #define FER_FDC_EN        0x08
  42 #define FER_FDC_4         0x10
  43 #define FER_FDC_ADDR      0x20
  44 #define FER_IDE_EN        0x40
  45 #define FER_IDE_ADDR      0x80
  46
  47 #define FAR_PARALLEL_ADDR 0x03
  48 #define FAR_UART1_ADDR    0x0C
  49 #define FAR_UART2_ADDR    0x30
  50 #define FAR_UART_3_4      0xC0
  51
  52 #define PTR_POWER_DOWN    0x01
  53 #define PTR_CLOCK_DOWN    0x02
  54 #define PTR_PWDN          0x04
  55 #define PTR_IRQ_5_7       0x08
  56 #define PTR_UART1_TEST    0x10
  57 #define PTR_UART2_TEST    0x20
  58 #define PTR_LOCK_CONF     0x40
  59 #define PTR_EPP_MODE      0x80
  60
  61
  62 /* Parallel port */
  63
  64 static inline bool is_parallel_enabled(PC87312State *s)
  65 {
  66     return s->regs[REG_FER] & FER_PARALLEL_EN;
  67 }
  68
  69 static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
  70
  71 static inline uint32_t get_parallel_iobase(PC87312State *s)
  72 {
  73     return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
  74 }
  75
  76 static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };
  77
  78 static inline uint32_t get_parallel_irq(PC87312State *s)
  79 {
  80     int idx;
  81     idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
  82     if (idx == 0) {
  83         return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
  84     } else {
  85         return parallel_irq[idx];
  86     }
  87 }
  88
  89 static inline bool is_parallel_epp(PC87312State *s)
  90 {
  91     return s->regs[REG_PTR] & PTR_EPP_MODE;
  92 }
  93
  94
  95 /* UARTs */
  96
  97 static const uint32_t uart_base[2][4] = {
  98     { 0x3e8, 0x338, 0x2e8, 0x220 },
  99     { 0x2e8, 0x238, 0x2e0, 0x228 }
 100 };
 101
 102 static inline uint32_t get_uart_iobase(PC87312State *s, int i)
 103 {
 104     int idx;
 105     idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
 106     if (idx == 0) {
 107         return 0x3f8;
 108     } else if (idx == 1) {
 109         return 0x2f8;
 110     } else {
 111         return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
 112     }
 113 }
 114
 115 static inline uint32_t get_uart_irq(PC87312State *s, int i)
 116 {
 117     int idx;
 118     idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
 119     return (idx & 1) ? 3 : 4;
 120 }
 121
 122 static inline bool is_uart_enabled(PC87312State *s, int i)
 123 {
 124     return s->regs[REG_FER] & (FER_UART1_EN << i);
 125 }
 126
 127
 128 /* Floppy controller */
 129
 130 static inline bool is_fdc_enabled(PC87312State *s)
 131 {
 132     return s->regs[REG_FER] & FER_FDC_EN;
 133 }
 134
 135 static inline uint32_t get_fdc_iobase(PC87312State *s)
 136 {
 137     return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
 138 }
 139
 140
 141 /* IDE controller */
 142
 143 static inline bool is_ide_enabled(PC87312State *s)
 144 {
 145     return s->regs[REG_FER] & FER_IDE_EN;
 146 }
 147
 148 static inline uint32_t get_ide_iobase(PC87312State *s)
 149 {
 150     return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
 151 }
 152
 153
 154 static void reconfigure_devices(PC87312State *s)
 155 {
 156     error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
 157                  s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
 158 }
 159
 160 static void pc87312_soft_reset(PC87312State *s)
 161 {
 162     static const uint8_t fer_init[] = {
 163         0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
 164         0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
 165         0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
 166         0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
 167     };
 168     static const uint8_t far_init[] = {
 169         0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
 170         0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
 171         0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
 172         0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
 173     };
 174     static const uint8_t ptr_init[] = {
 175         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 176         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 177         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 178         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
 179     };
 180
 181     s->read_id_step = 0;
 182     s->selected_index = REG_FER;
 183
 184     s->regs[REG_FER] = fer_init[s->config & 0x1f];
 185     s->regs[REG_FAR] = far_init[s->config & 0x1f];
 186     s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
 187 }
 188
 189 static void pc87312_hard_reset(PC87312State *s)
 190 {
 191     pc87312_soft_reset(s);
 192 }
 193
 194 static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
 195                              unsigned int size)
 196 {
 197     PC87312State *s = opaque;
 198
 199     trace_pc87312_io_write(addr, val);
 200
 201     if ((addr & 1) == 0) {
 202         /* Index register */
 203         s->read_id_step = 2;
 204         s->selected_index = val;
 205     } else {
 206         /* Data register */
 207         if (s->selected_index < 3) {
 208             s->regs[s->selected_index] = val;
 209             reconfigure_devices(s);
 210         }
 211     }
 212 }
 213
 214 static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
 215 {
 216     PC87312State *s = opaque;
 217     uint32_t val;
 218
 219     if ((addr & 1) == 0) {
 220         /* Index register */
 221         if (s->read_id_step++ == 0) {
 222             val = 0x88;
 223         } else if (s->read_id_step++ == 1) {
 224             val = 0;
 225         } else {
 226             val = s->selected_index;
 227         }
 228     } else {
 229         /* Data register */
 230         if (s->selected_index < 3) {
 231             val = s->regs[s->selected_index];
 232         } else {
 233             /* Invalid selected index */
 234             val = 0;
 235         }
 236     }
 237
 238     trace_pc87312_io_read(addr, val);
 239     return val;
 240 }
 241
 242 static const MemoryRegionOps pc87312_io_ops = {
 243     .read  = pc87312_io_read,
 244     .write = pc87312_io_write,
 245     .endianness = DEVICE_LITTLE_ENDIAN,
 246     .valid = {
 247         .min_access_size = 1,
 248         .max_access_size = 1,
 249     },
 250 };
 251
 252 static int pc87312_post_load(void *opaque, int version_id)
 253 {
 254     PC87312State *s = opaque;
 255
 256     reconfigure_devices(s);
 257     return 0;
 258 }
 259
 260 static void pc87312_reset(DeviceState *d)
 261 {
 262     PC87312State *s = PC87312(d);
 263
 264     pc87312_soft_reset(s);
 265 }
 266
 267 static void pc87312_realize(DeviceState *dev, Error **errp)
 268 {
 269     PC87312State *s;
 270     DeviceState *d;
 271     ISADevice *isa;
 272     ISABus *bus;
 273     CharDriverState *chr;
 274     DriveInfo *drive;
 275     char name[5];
 276     int i;
 277
 278     s = PC87312(dev);
 279     isa = ISA_DEVICE(dev);
 280     bus = isa_bus_from_device(isa);
 281     isa_register_ioport(isa, &s->io, s->iobase);
 282     pc87312_hard_reset(s);
 283
 284     if (is_parallel_enabled(s)) {
 285         chr = parallel_hds[0];
 286         if (chr == NULL) {
 287             chr = qemu_chr_new("par0", "null", NULL);
 288         }
 289         isa = isa_create(bus, "isa-parallel");
 290         d = DEVICE(isa);
 291         qdev_prop_set_uint32(d, "index", 0);
 292         qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s));
 293         qdev_prop_set_uint32(d, "irq", get_parallel_irq(s));
 294         qdev_prop_set_chr(d, "chardev", chr);
 295         qdev_init_nofail(d);
 296         s->parallel.dev = isa;
 297         trace_pc87312_info_parallel(get_parallel_iobase(s),
 298                                     get_parallel_irq(s));
 299     }
 300
 301     for (i = 0; i < 2; i++) {
 302         if (is_uart_enabled(s, i)) {
 303             chr = serial_hds[i];
 304             if (chr == NULL) {
 305                 snprintf(name, sizeof(name), "ser%d", i);
 306                 chr = qemu_chr_new(name, "null", NULL);
 307             }
 308             isa = isa_create(bus, "isa-serial");
 309             d = DEVICE(isa);
 310             qdev_prop_set_uint32(d, "index", i);
 311             qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i));
 312             qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i));
 313             qdev_prop_set_chr(d, "chardev", chr);
 314             qdev_init_nofail(d);
 315             s->uart[i].dev = isa;
 316             trace_pc87312_info_serial(i, get_uart_iobase(s, i),
 317                                       get_uart_irq(s, i));
 318         }
 319     }
 320
 321     if (is_fdc_enabled(s)) {
 322         isa = isa_create(bus, "isa-fdc");
 323         d = DEVICE(isa);
 324         qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s));
 325         qdev_prop_set_uint32(d, "irq", 6);
 326         drive = drive_get(IF_FLOPPY, 0, 0);
 327         if (drive != NULL) {
 328             qdev_prop_set_drive_nofail(d, "driveA", drive->bdrv);
 329         }
 330         drive = drive_get(IF_FLOPPY, 0, 1);
 331         if (drive != NULL) {
 332             qdev_prop_set_drive_nofail(d, "driveB", drive->bdrv);
 333         }
 334         qdev_init_nofail(d);
 335         s->fdc.dev = isa;
 336         trace_pc87312_info_floppy(get_fdc_iobase(s));
 337     }
 338
 339     if (is_ide_enabled(s)) {
 340         isa = isa_create(bus, "isa-ide");
 341         d = DEVICE(isa);
 342         qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s));
 343         qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206);
 344         qdev_prop_set_uint32(d, "irq", 14);
 345         qdev_init_nofail(d);
 346         s->ide.dev = isa;
 347         trace_pc87312_info_ide(get_ide_iobase(s));
 348     }
 349 }
 350
 351 static void pc87312_initfn(Object *obj)
 352 {
 353     PC87312State *s = PC87312(obj);
 354
 355     memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
 356 }
 357
 358 static const VMStateDescription vmstate_pc87312 = {
 359     .name = "pc87312",
 360     .version_id = 1,
 361     .minimum_version_id = 1,
 362     .post_load = pc87312_post_load,
 363     .fields = (VMStateField[]) {
 364         VMSTATE_UINT8(read_id_step, PC87312State),
 365         VMSTATE_UINT8(selected_index, PC87312State),
 366         VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
 367         VMSTATE_END_OF_LIST()
 368     }
 369 };
 370
 371 static Property pc87312_properties[] = {
 372     DEFINE_PROP_UINT32("iobase", PC87312State, iobase, 0x398),
 373     DEFINE_PROP_UINT8("config", PC87312State, config, 1),
 374     DEFINE_PROP_END_OF_LIST()
 375 };
 376
 377 static void pc87312_class_init(ObjectClass *klass, void *data)
 378 {
 379     DeviceClass *dc = DEVICE_CLASS(klass);
 380
 381     dc->realize = pc87312_realize;
 382     dc->reset = pc87312_reset;
 383     dc->vmsd = &vmstate_pc87312;
 384     dc->props = pc87312_properties;
 385 }
 386
 387 static const TypeInfo pc87312_type_info = {
 388     .name          = TYPE_PC87312,
 389     .parent        = TYPE_ISA_DEVICE,
 390     .instance_size = sizeof(PC87312State),
 391     .instance_init = pc87312_initfn,
 392     .class_init    = pc87312_class_init,
 393 };
 394
 395 static void pc87312_register_types(void)
 396 {
 397     type_register_static(&pc87312_type_info);
 398 }
 399
 400 type_init(pc87312_register_types)