4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/tcg.h"
30 #include "qemu/range.h"
31 #include "qapi/qapi-commands-machine-target.h"
32 #include "qapi/error.h"
33 #include "qemu/guest-random.h"
36 #include "exec/cpu_ldst.h"
37 #include "semihosting/common-semi.h"
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
41 #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
43 #ifndef CONFIG_USER_ONLY
45 static bool get_phys_addr_lpae(CPUARMState
*env
, uint64_t address
,
46 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
48 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
49 target_ulong
*page_size_ptr
,
50 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
51 __attribute__((nonnull
));
54 static void switch_mode(CPUARMState
*env
, int mode
);
55 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
);
57 static int vfp_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
59 ARMCPU
*cpu
= env_archcpu(env
);
60 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
62 /* VFP data registers are always little-endian. */
64 return gdb_get_reg64(buf
, *aa32_vfp_dreg(env
, reg
));
66 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
67 /* Aliases for Q regs. */
70 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
71 return gdb_get_reg128(buf
, q
[0], q
[1]);
74 switch (reg
- nregs
) {
75 case 0: return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); break;
76 case 1: return gdb_get_reg32(buf
, vfp_get_fpscr(env
)); break;
77 case 2: return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); break;
82 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
84 ARMCPU
*cpu
= env_archcpu(env
);
85 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
88 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
91 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
94 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
96 q
[1] = ldq_le_p(buf
+ 8);
100 switch (reg
- nregs
) {
101 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
102 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
103 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
108 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
113 /* 128 bit FP register - quads are in LE order */
114 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
115 return gdb_get_reg128(buf
, q
[1], q
[0]);
119 return gdb_get_reg32(buf
, vfp_get_fpsr(env
));
122 return gdb_get_reg32(buf
,vfp_get_fpcr(env
));
128 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
132 /* 128 bit FP register */
134 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
135 q
[0] = ldq_le_p(buf
);
136 q
[1] = ldq_le_p(buf
+ 8);
141 vfp_set_fpsr(env
, ldl_p(buf
));
145 vfp_set_fpcr(env
, ldl_p(buf
));
152 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
154 assert(ri
->fieldoffset
);
155 if (cpreg_field_is_64bit(ri
)) {
156 return CPREG_FIELD64(env
, ri
);
158 return CPREG_FIELD32(env
, ri
);
162 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
165 assert(ri
->fieldoffset
);
166 if (cpreg_field_is_64bit(ri
)) {
167 CPREG_FIELD64(env
, ri
) = value
;
169 CPREG_FIELD32(env
, ri
) = value
;
173 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
175 return (char *)env
+ ri
->fieldoffset
;
178 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
180 /* Raw read of a coprocessor register (as needed for migration, etc). */
181 if (ri
->type
& ARM_CP_CONST
) {
182 return ri
->resetvalue
;
183 } else if (ri
->raw_readfn
) {
184 return ri
->raw_readfn(env
, ri
);
185 } else if (ri
->readfn
) {
186 return ri
->readfn(env
, ri
);
188 return raw_read(env
, ri
);
192 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
195 /* Raw write of a coprocessor register (as needed for migration, etc).
196 * Note that constant registers are treated as write-ignored; the
197 * caller should check for success by whether a readback gives the
200 if (ri
->type
& ARM_CP_CONST
) {
202 } else if (ri
->raw_writefn
) {
203 ri
->raw_writefn(env
, ri
, v
);
204 } else if (ri
->writefn
) {
205 ri
->writefn(env
, ri
, v
);
207 raw_write(env
, ri
, v
);
212 * arm_get/set_gdb_*: get/set a gdb register
213 * @env: the CPU state
214 * @buf: a buffer to copy to/from
215 * @reg: register number (offset from start of group)
217 * We return the number of bytes copied
220 static int arm_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
222 ARMCPU
*cpu
= env_archcpu(env
);
223 const ARMCPRegInfo
*ri
;
226 key
= cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
[reg
];
227 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
229 if (cpreg_field_is_64bit(ri
)) {
230 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
232 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
238 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
243 #ifdef TARGET_AARCH64
244 static int arm_gdb_get_svereg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
246 ARMCPU
*cpu
= env_archcpu(env
);
249 /* The first 32 registers are the zregs */
253 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
++) {
254 len
+= gdb_get_reg128(buf
,
255 env
->vfp
.zregs
[reg
].d
[vq
* 2 + 1],
256 env
->vfp
.zregs
[reg
].d
[vq
* 2]);
261 return gdb_get_reg32(buf
, vfp_get_fpsr(env
));
263 return gdb_get_reg32(buf
, vfp_get_fpcr(env
));
264 /* then 16 predicates and the ffr */
269 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
= vq
+ 4) {
270 len
+= gdb_get_reg64(buf
, env
->vfp
.pregs
[preg
].p
[vq
/ 4]);
277 * We report in Vector Granules (VG) which is 64bit in a Z reg
278 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
280 int vq
= sve_zcr_len_for_el(env
, arm_current_el(env
)) + 1;
281 return gdb_get_reg64(buf
, vq
* 2);
284 /* gdbstub asked for something out our range */
285 qemu_log_mask(LOG_UNIMP
, "%s: out of range register %d", __func__
, reg
);
292 static int arm_gdb_set_svereg(CPUARMState
*env
, uint8_t *buf
, int reg
)
294 ARMCPU
*cpu
= env_archcpu(env
);
296 /* The first 32 registers are the zregs */
298 /* The first 32 registers are the zregs */
302 uint64_t *p
= (uint64_t *) buf
;
303 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
++) {
304 env
->vfp
.zregs
[reg
].d
[vq
* 2 + 1] = *p
++;
305 env
->vfp
.zregs
[reg
].d
[vq
* 2] = *p
++;
311 vfp_set_fpsr(env
, *(uint32_t *)buf
);
314 vfp_set_fpcr(env
, *(uint32_t *)buf
);
320 uint64_t *p
= (uint64_t *) buf
;
321 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
= vq
+ 4) {
322 env
->vfp
.pregs
[preg
].p
[vq
/ 4] = *p
++;
328 /* cannot set vg via gdbstub */
331 /* gdbstub asked for something out our range */
337 #endif /* TARGET_AARCH64 */
339 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
341 /* Return true if the regdef would cause an assertion if you called
342 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
343 * program bug for it not to have the NO_RAW flag).
344 * NB that returning false here doesn't necessarily mean that calling
345 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
346 * read/write access functions which are safe for raw use" from "has
347 * read/write access functions which have side effects but has forgotten
348 * to provide raw access functions".
349 * The tests here line up with the conditions in read/write_raw_cp_reg()
350 * and assertions in raw_read()/raw_write().
352 if ((ri
->type
& ARM_CP_CONST
) ||
354 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
360 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
362 /* Write the coprocessor state from cpu->env to the (index,value) list. */
366 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
367 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
368 const ARMCPRegInfo
*ri
;
371 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
376 if (ri
->type
& ARM_CP_NO_RAW
) {
380 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
383 * Only sync if the previous list->cpustate sync succeeded.
384 * Rather than tracking the success/failure state for every
385 * item in the list, we just recheck "does the raw write we must
386 * have made in write_list_to_cpustate() read back OK" here.
388 uint64_t oldval
= cpu
->cpreg_values
[i
];
390 if (oldval
== newval
) {
394 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
395 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
399 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
401 cpu
->cpreg_values
[i
] = newval
;
406 bool write_list_to_cpustate(ARMCPU
*cpu
)
411 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
412 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
413 uint64_t v
= cpu
->cpreg_values
[i
];
414 const ARMCPRegInfo
*ri
;
416 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
421 if (ri
->type
& ARM_CP_NO_RAW
) {
424 /* Write value and confirm it reads back as written
425 * (to catch read-only registers and partially read-only
426 * registers where the incoming migration value doesn't match)
428 write_raw_cp_reg(&cpu
->env
, ri
, v
);
429 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
436 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
438 ARMCPU
*cpu
= opaque
;
440 const ARMCPRegInfo
*ri
;
442 regidx
= *(uint32_t *)key
;
443 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
445 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
446 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
447 /* The value array need not be initialized at this point */
448 cpu
->cpreg_array_len
++;
452 static void count_cpreg(gpointer key
, gpointer opaque
)
454 ARMCPU
*cpu
= opaque
;
456 const ARMCPRegInfo
*ri
;
458 regidx
= *(uint32_t *)key
;
459 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
461 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
462 cpu
->cpreg_array_len
++;
466 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
468 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
469 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
480 void init_cpreg_list(ARMCPU
*cpu
)
482 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
483 * Note that we require cpreg_tuples[] to be sorted by key ID.
488 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
489 keys
= g_list_sort(keys
, cpreg_key_compare
);
491 cpu
->cpreg_array_len
= 0;
493 g_list_foreach(keys
, count_cpreg
, cpu
);
495 arraylen
= cpu
->cpreg_array_len
;
496 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
497 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
498 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
499 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
500 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
501 cpu
->cpreg_array_len
= 0;
503 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
505 assert(cpu
->cpreg_array_len
== arraylen
);
511 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
513 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
514 const ARMCPRegInfo
*ri
,
517 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
518 arm_is_secure_below_el3(env
)) {
519 return CP_ACCESS_TRAP_UNCATEGORIZED
;
524 /* Some secure-only AArch32 registers trap to EL3 if used from
525 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
526 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
527 * We assume that the .access field is set to PL1_RW.
529 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
530 const ARMCPRegInfo
*ri
,
533 if (arm_current_el(env
) == 3) {
536 if (arm_is_secure_below_el3(env
)) {
537 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
538 return CP_ACCESS_TRAP_EL2
;
540 return CP_ACCESS_TRAP_EL3
;
542 /* This will be EL1 NS and EL2 NS, which just UNDEF */
543 return CP_ACCESS_TRAP_UNCATEGORIZED
;
546 static uint64_t arm_mdcr_el2_eff(CPUARMState
*env
)
548 return arm_is_el2_enabled(env
) ? env
->cp15
.mdcr_el2
: 0;
551 /* Check for traps to "powerdown debug" registers, which are controlled
554 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
557 int el
= arm_current_el(env
);
558 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
559 bool mdcr_el2_tdosa
= (mdcr_el2
& MDCR_TDOSA
) || (mdcr_el2
& MDCR_TDE
) ||
560 (arm_hcr_el2_eff(env
) & HCR_TGE
);
562 if (el
< 2 && mdcr_el2_tdosa
) {
563 return CP_ACCESS_TRAP_EL2
;
565 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
566 return CP_ACCESS_TRAP_EL3
;
571 /* Check for traps to "debug ROM" registers, which are controlled
572 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
574 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
577 int el
= arm_current_el(env
);
578 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
579 bool mdcr_el2_tdra
= (mdcr_el2
& MDCR_TDRA
) || (mdcr_el2
& MDCR_TDE
) ||
580 (arm_hcr_el2_eff(env
) & HCR_TGE
);
582 if (el
< 2 && mdcr_el2_tdra
) {
583 return CP_ACCESS_TRAP_EL2
;
585 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
586 return CP_ACCESS_TRAP_EL3
;
591 /* Check for traps to general debug registers, which are controlled
592 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
594 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 int el
= arm_current_el(env
);
598 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
599 bool mdcr_el2_tda
= (mdcr_el2
& MDCR_TDA
) || (mdcr_el2
& MDCR_TDE
) ||
600 (arm_hcr_el2_eff(env
) & HCR_TGE
);
602 if (el
< 2 && mdcr_el2_tda
) {
603 return CP_ACCESS_TRAP_EL2
;
605 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
606 return CP_ACCESS_TRAP_EL3
;
611 /* Check for traps to performance monitor registers, which are controlled
612 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
614 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
617 int el
= arm_current_el(env
);
618 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
620 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
621 return CP_ACCESS_TRAP_EL2
;
623 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
624 return CP_ACCESS_TRAP_EL3
;
629 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
630 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
633 if (arm_current_el(env
) == 1) {
634 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
635 if (arm_hcr_el2_eff(env
) & trap
) {
636 return CP_ACCESS_TRAP_EL2
;
642 /* Check for traps from EL1 due to HCR_EL2.TSW. */
643 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
646 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
647 return CP_ACCESS_TRAP_EL2
;
652 /* Check for traps from EL1 due to HCR_EL2.TACR. */
653 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
656 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
657 return CP_ACCESS_TRAP_EL2
;
662 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
663 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
666 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
667 return CP_ACCESS_TRAP_EL2
;
672 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
674 ARMCPU
*cpu
= env_archcpu(env
);
676 raw_write(env
, ri
, value
);
677 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
680 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
682 ARMCPU
*cpu
= env_archcpu(env
);
684 if (raw_read(env
, ri
) != value
) {
685 /* Unlike real hardware the qemu TLB uses virtual addresses,
686 * not modified virtual addresses, so this causes a TLB flush.
689 raw_write(env
, ri
, value
);
693 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 ARMCPU
*cpu
= env_archcpu(env
);
698 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
699 && !extended_addresses_enabled(env
)) {
700 /* For VMSA (when not using the LPAE long descriptor page table
701 * format) this register includes the ASID, so do a TLB flush.
702 * For PMSA it is purely a process ID and no action is needed.
706 raw_write(env
, ri
, value
);
709 /* IS variants of TLB operations must affect all cores */
710 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
713 CPUState
*cs
= env_cpu(env
);
715 tlb_flush_all_cpus_synced(cs
);
718 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
721 CPUState
*cs
= env_cpu(env
);
723 tlb_flush_all_cpus_synced(cs
);
726 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
729 CPUState
*cs
= env_cpu(env
);
731 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
734 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
737 CPUState
*cs
= env_cpu(env
);
739 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
743 * Non-IS variants of TLB operations are upgraded to
744 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
745 * force broadcast of these operations.
747 static bool tlb_force_broadcast(CPUARMState
*env
)
749 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
752 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
755 /* Invalidate all (TLBIALL) */
756 CPUState
*cs
= env_cpu(env
);
758 if (tlb_force_broadcast(env
)) {
759 tlb_flush_all_cpus_synced(cs
);
765 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
768 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
769 CPUState
*cs
= env_cpu(env
);
771 value
&= TARGET_PAGE_MASK
;
772 if (tlb_force_broadcast(env
)) {
773 tlb_flush_page_all_cpus_synced(cs
, value
);
775 tlb_flush_page(cs
, value
);
779 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
782 /* Invalidate by ASID (TLBIASID) */
783 CPUState
*cs
= env_cpu(env
);
785 if (tlb_force_broadcast(env
)) {
786 tlb_flush_all_cpus_synced(cs
);
792 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
795 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
796 CPUState
*cs
= env_cpu(env
);
798 value
&= TARGET_PAGE_MASK
;
799 if (tlb_force_broadcast(env
)) {
800 tlb_flush_page_all_cpus_synced(cs
, value
);
802 tlb_flush_page(cs
, value
);
806 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
809 CPUState
*cs
= env_cpu(env
);
811 tlb_flush_by_mmuidx(cs
,
813 ARMMMUIdxBit_E10_1_PAN
|
817 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
820 CPUState
*cs
= env_cpu(env
);
822 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
824 ARMMMUIdxBit_E10_1_PAN
|
829 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
832 CPUState
*cs
= env_cpu(env
);
834 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
837 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
840 CPUState
*cs
= env_cpu(env
);
842 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
845 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
848 CPUState
*cs
= env_cpu(env
);
849 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
851 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
854 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
857 CPUState
*cs
= env_cpu(env
);
858 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
860 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
864 static const ARMCPRegInfo cp_reginfo
[] = {
865 /* Define the secure and non-secure FCSE identifier CP registers
866 * separately because there is no secure bank in V8 (no _EL3). This allows
867 * the secure register to be properly reset and migrated. There is also no
868 * v8 EL1 version of the register so the non-secure instance stands alone.
871 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
872 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
873 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
874 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
875 { .name
= "FCSEIDR_S",
876 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
877 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
878 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
879 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
880 /* Define the secure and non-secure context identifier CP registers
881 * separately because there is no secure bank in V8 (no _EL3). This allows
882 * the secure register to be properly reset and migrated. In the
883 * non-secure case, the 32-bit register will have reset and migration
884 * disabled during registration as it is handled by the 64-bit instance.
886 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
887 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
888 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
889 .secure
= ARM_CP_SECSTATE_NS
,
890 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
891 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
892 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
893 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
894 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
895 .secure
= ARM_CP_SECSTATE_S
,
896 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
897 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
901 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
902 /* NB: Some of these registers exist in v8 but with more precise
903 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
905 /* MMU Domain access control / MPU write buffer control */
907 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
908 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
909 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
910 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
911 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
912 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
913 * For v6 and v5, these mappings are overly broad.
915 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
916 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
917 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
918 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
919 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
920 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
921 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
922 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
923 /* Cache maintenance ops; some of this space may be overridden later. */
924 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
925 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
926 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
930 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
931 /* Not all pre-v6 cores implemented this WFI, so this is slightly
934 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
935 .access
= PL1_W
, .type
= ARM_CP_WFI
},
939 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
940 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
941 * is UNPREDICTABLE; we choose to NOP as most implementations do).
943 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
944 .access
= PL1_W
, .type
= ARM_CP_WFI
},
945 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
946 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
947 * OMAPCP will override this space.
949 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
950 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
952 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
953 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
955 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
956 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
957 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
959 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
960 * implementing it as RAZ means the "debug architecture version" bits
961 * will read as a reserved value, which should cause Linux to not try
962 * to use the debug hardware.
964 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
965 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
966 /* MMU TLB control. Note that the wildcarding means we cover not just
967 * the unified TLB ops but also the dside/iside/inner-shareable variants.
969 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
970 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
971 .type
= ARM_CP_NO_RAW
},
972 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
973 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
974 .type
= ARM_CP_NO_RAW
},
975 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
976 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
977 .type
= ARM_CP_NO_RAW
},
978 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
979 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
980 .type
= ARM_CP_NO_RAW
},
981 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
982 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
983 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
984 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
988 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
993 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
994 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
995 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
996 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
997 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
999 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
1000 /* VFP coprocessor: cp10 & cp11 [23:20] */
1001 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
1003 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
1004 /* ASEDIS [31] bit is RAO/WI */
1008 /* VFPv3 and upwards with NEON implement 32 double precision
1009 * registers (D0-D31).
1011 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
1012 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
1020 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1021 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1023 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
1024 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
1025 value
&= ~(0xf << 20);
1026 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
1029 env
->cp15
.cpacr_el1
= value
;
1032 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1035 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1036 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1038 uint64_t value
= env
->cp15
.cpacr_el1
;
1040 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
1041 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
1042 value
&= ~(0xf << 20);
1048 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1050 /* Call cpacr_write() so that we reset with the correct RAO bits set
1051 * for our CPU features.
1053 cpacr_write(env
, ri
, 0);
1056 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1059 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1060 /* Check if CPACR accesses are to be trapped to EL2 */
1061 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
1062 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
)) {
1063 return CP_ACCESS_TRAP_EL2
;
1064 /* Check if CPACR accesses are to be trapped to EL3 */
1065 } else if (arm_current_el(env
) < 3 &&
1066 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
1067 return CP_ACCESS_TRAP_EL3
;
1071 return CP_ACCESS_OK
;
1074 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1077 /* Check if CPTR accesses are set to trap to EL3 */
1078 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
1079 return CP_ACCESS_TRAP_EL3
;
1082 return CP_ACCESS_OK
;
1085 static const ARMCPRegInfo v6_cp_reginfo
[] = {
1086 /* prefetch by MVA in v6, NOP in v7 */
1087 { .name
= "MVA_prefetch",
1088 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
1089 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1090 /* We need to break the TB after ISB to execute self-modifying code
1091 * correctly and also to take any pending interrupts immediately.
1092 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
1094 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
1095 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
1096 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
1097 .access
= PL0_W
, .type
= ARM_CP_NOP
},
1098 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
1099 .access
= PL0_W
, .type
= ARM_CP_NOP
},
1100 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1101 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
1102 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1103 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1105 /* Watchpoint Fault Address Register : should actually only be present
1106 * for 1136, 1176, 11MPCore.
1108 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1109 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1110 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1111 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1112 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1113 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1117 /* Definitions for the PMU registers */
1118 #define PMCRN_MASK 0xf800
1119 #define PMCRN_SHIFT 11
1128 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1129 * which can be written as 1 to trigger behaviour but which stay RAZ).
1131 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1133 #define PMXEVTYPER_P 0x80000000
1134 #define PMXEVTYPER_U 0x40000000
1135 #define PMXEVTYPER_NSK 0x20000000
1136 #define PMXEVTYPER_NSU 0x10000000
1137 #define PMXEVTYPER_NSH 0x08000000
1138 #define PMXEVTYPER_M 0x04000000
1139 #define PMXEVTYPER_MT 0x02000000
1140 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1141 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1142 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1143 PMXEVTYPER_M | PMXEVTYPER_MT | \
1144 PMXEVTYPER_EVTCOUNT)
1146 #define PMCCFILTR 0xf8000000
1147 #define PMCCFILTR_M PMXEVTYPER_M
1148 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1150 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1152 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1155 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1156 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1158 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1161 typedef struct pm_event
{
1162 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1163 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1164 bool (*supported
)(CPUARMState
*);
1166 * Retrieve the current count of the underlying event. The programmed
1167 * counters hold a difference from the return value from this function
1169 uint64_t (*get_count
)(CPUARMState
*);
1171 * Return how many nanoseconds it will take (at a minimum) for count events
1172 * to occur. A negative value indicates the counter will never overflow, or
1173 * that the counter has otherwise arranged for the overflow bit to be set
1174 * and the PMU interrupt to be raised on overflow.
1176 int64_t (*ns_per_count
)(uint64_t);
1179 static bool event_always_supported(CPUARMState
*env
)
1184 static uint64_t swinc_get_count(CPUARMState
*env
)
1187 * SW_INCR events are written directly to the pmevcntr's by writes to
1188 * PMSWINC, so there is no underlying count maintained by the PMU itself
1193 static int64_t swinc_ns_per(uint64_t ignored
)
1199 * Return the underlying cycle count for the PMU cycle counters. If we're in
1200 * usermode, simply return 0.
1202 static uint64_t cycles_get_count(CPUARMState
*env
)
1204 #ifndef CONFIG_USER_ONLY
1205 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1206 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1208 return cpu_get_host_ticks();
1212 #ifndef CONFIG_USER_ONLY
1213 static int64_t cycles_ns_per(uint64_t cycles
)
1215 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1218 static bool instructions_supported(CPUARMState
*env
)
1220 return icount_enabled() == 1; /* Precise instruction counting */
1223 static uint64_t instructions_get_count(CPUARMState
*env
)
1225 return (uint64_t)icount_get_raw();
1228 static int64_t instructions_ns_per(uint64_t icount
)
1230 return icount_to_ns((int64_t)icount
);
1234 static bool pmu_8_1_events_supported(CPUARMState
*env
)
1236 /* For events which are supported in any v8.1 PMU */
1237 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
1240 static bool pmu_8_4_events_supported(CPUARMState
*env
)
1242 /* For events which are supported in any v8.1 PMU */
1243 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
1246 static uint64_t zero_event_get_count(CPUARMState
*env
)
1248 /* For events which on QEMU never fire, so their count is always zero */
1252 static int64_t zero_event_ns_per(uint64_t cycles
)
1254 /* An event which never fires can never overflow */
1258 static const pm_event pm_events
[] = {
1259 { .number
= 0x000, /* SW_INCR */
1260 .supported
= event_always_supported
,
1261 .get_count
= swinc_get_count
,
1262 .ns_per_count
= swinc_ns_per
,
1264 #ifndef CONFIG_USER_ONLY
1265 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1266 .supported
= instructions_supported
,
1267 .get_count
= instructions_get_count
,
1268 .ns_per_count
= instructions_ns_per
,
1270 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1271 .supported
= event_always_supported
,
1272 .get_count
= cycles_get_count
,
1273 .ns_per_count
= cycles_ns_per
,
1276 { .number
= 0x023, /* STALL_FRONTEND */
1277 .supported
= pmu_8_1_events_supported
,
1278 .get_count
= zero_event_get_count
,
1279 .ns_per_count
= zero_event_ns_per
,
1281 { .number
= 0x024, /* STALL_BACKEND */
1282 .supported
= pmu_8_1_events_supported
,
1283 .get_count
= zero_event_get_count
,
1284 .ns_per_count
= zero_event_ns_per
,
1286 { .number
= 0x03c, /* STALL */
1287 .supported
= pmu_8_4_events_supported
,
1288 .get_count
= zero_event_get_count
,
1289 .ns_per_count
= zero_event_ns_per
,
1294 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1295 * events (i.e. the statistical profiling extension), this implementation
1296 * should first be updated to something sparse instead of the current
1297 * supported_event_map[] array.
1299 #define MAX_EVENT_ID 0x3c
1300 #define UNSUPPORTED_EVENT UINT16_MAX
1301 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1304 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1305 * of ARM event numbers to indices in our pm_events array.
1307 * Note: Events in the 0x40XX range are not currently supported.
1309 void pmu_init(ARMCPU
*cpu
)
1314 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1317 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1318 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1323 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1324 const pm_event
*cnt
= &pm_events
[i
];
1325 assert(cnt
->number
<= MAX_EVENT_ID
);
1326 /* We do not currently support events in the 0x40xx range */
1327 assert(cnt
->number
<= 0x3f);
1329 if (cnt
->supported(&cpu
->env
)) {
1330 supported_event_map
[cnt
->number
] = i
;
1331 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1332 if (cnt
->number
& 0x20) {
1333 cpu
->pmceid1
|= event_mask
;
1335 cpu
->pmceid0
|= event_mask
;
1342 * Check at runtime whether a PMU event is supported for the current machine
1344 static bool event_supported(uint16_t number
)
1346 if (number
> MAX_EVENT_ID
) {
1349 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1352 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1355 /* Performance monitor registers user accessibility is controlled
1356 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1357 * trapping to EL2 or EL3 for other accesses.
1359 int el
= arm_current_el(env
);
1360 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1362 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1363 return CP_ACCESS_TRAP
;
1365 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1366 return CP_ACCESS_TRAP_EL2
;
1368 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1369 return CP_ACCESS_TRAP_EL3
;
1372 return CP_ACCESS_OK
;
1375 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1376 const ARMCPRegInfo
*ri
,
1379 /* ER: event counter read trap control */
1380 if (arm_feature(env
, ARM_FEATURE_V8
)
1381 && arm_current_el(env
) == 0
1382 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1384 return CP_ACCESS_OK
;
1387 return pmreg_access(env
, ri
, isread
);
1390 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1391 const ARMCPRegInfo
*ri
,
1394 /* SW: software increment write trap control */
1395 if (arm_feature(env
, ARM_FEATURE_V8
)
1396 && arm_current_el(env
) == 0
1397 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1399 return CP_ACCESS_OK
;
1402 return pmreg_access(env
, ri
, isread
);
1405 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1406 const ARMCPRegInfo
*ri
,
1409 /* ER: event counter read trap control */
1410 if (arm_feature(env
, ARM_FEATURE_V8
)
1411 && arm_current_el(env
) == 0
1412 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1413 return CP_ACCESS_OK
;
1416 return pmreg_access(env
, ri
, isread
);
1419 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1420 const ARMCPRegInfo
*ri
,
1423 /* CR: cycle counter read trap control */
1424 if (arm_feature(env
, ARM_FEATURE_V8
)
1425 && arm_current_el(env
) == 0
1426 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1428 return CP_ACCESS_OK
;
1431 return pmreg_access(env
, ri
, isread
);
1434 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1435 * the current EL, security state, and register configuration.
1437 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1440 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1441 bool enabled
, prohibited
, filtered
;
1442 bool secure
= arm_is_secure(env
);
1443 int el
= arm_current_el(env
);
1444 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1445 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1447 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1451 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1452 (counter
< hpmn
|| counter
== 31)) {
1453 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1455 e
= mdcr_el2
& MDCR_HPME
;
1457 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1460 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1461 prohibited
= mdcr_el2
& MDCR_HPMD
;
1466 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1467 !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1470 if (prohibited
&& counter
== 31) {
1471 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1474 if (counter
== 31) {
1475 filter
= env
->cp15
.pmccfiltr_el0
;
1477 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1480 p
= filter
& PMXEVTYPER_P
;
1481 u
= filter
& PMXEVTYPER_U
;
1482 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1483 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1484 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1485 m
= arm_el_is_aa64(env
, 1) &&
1486 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1489 filtered
= secure
? u
: u
!= nsu
;
1490 } else if (el
== 1) {
1491 filtered
= secure
? p
: p
!= nsk
;
1492 } else if (el
== 2) {
1498 if (counter
!= 31) {
1500 * If not checking PMCCNTR, ensure the counter is setup to an event we
1503 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1504 if (!event_supported(event
)) {
1509 return enabled
&& !prohibited
&& !filtered
;
1512 static void pmu_update_irq(CPUARMState
*env
)
1514 ARMCPU
*cpu
= env_archcpu(env
);
1515 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1516 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1520 * Ensure c15_ccnt is the guest-visible count so that operations such as
1521 * enabling/disabling the counter or filtering, modifying the count itself,
1522 * etc. can be done logically. This is essentially a no-op if the counter is
1523 * not enabled at the time of the call.
1525 static void pmccntr_op_start(CPUARMState
*env
)
1527 uint64_t cycles
= cycles_get_count(env
);
1529 if (pmu_counter_enabled(env
, 31)) {
1530 uint64_t eff_cycles
= cycles
;
1531 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1532 /* Increment once every 64 processor clock cycles */
1536 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1538 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1539 1ull << 63 : 1ull << 31;
1540 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1541 env
->cp15
.c9_pmovsr
|= (1 << 31);
1542 pmu_update_irq(env
);
1545 env
->cp15
.c15_ccnt
= new_pmccntr
;
1547 env
->cp15
.c15_ccnt_delta
= cycles
;
1551 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1552 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1555 static void pmccntr_op_finish(CPUARMState
*env
)
1557 if (pmu_counter_enabled(env
, 31)) {
1558 #ifndef CONFIG_USER_ONLY
1559 /* Calculate when the counter will next overflow */
1560 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1561 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1562 remaining_cycles
= (uint32_t)remaining_cycles
;
1564 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1566 if (overflow_in
> 0) {
1567 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1569 ARMCPU
*cpu
= env_archcpu(env
);
1570 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1574 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1575 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1576 /* Increment once every 64 processor clock cycles */
1579 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1583 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1586 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1588 if (event_supported(event
)) {
1589 uint16_t event_idx
= supported_event_map
[event
];
1590 count
= pm_events
[event_idx
].get_count(env
);
1593 if (pmu_counter_enabled(env
, counter
)) {
1594 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1596 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1597 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1598 pmu_update_irq(env
);
1600 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1602 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1605 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1607 if (pmu_counter_enabled(env
, counter
)) {
1608 #ifndef CONFIG_USER_ONLY
1609 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1610 uint16_t event_idx
= supported_event_map
[event
];
1611 uint64_t delta
= UINT32_MAX
-
1612 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1613 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1615 if (overflow_in
> 0) {
1616 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1618 ARMCPU
*cpu
= env_archcpu(env
);
1619 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1623 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1624 env
->cp15
.c14_pmevcntr
[counter
];
1628 void pmu_op_start(CPUARMState
*env
)
1631 pmccntr_op_start(env
);
1632 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1633 pmevcntr_op_start(env
, i
);
1637 void pmu_op_finish(CPUARMState
*env
)
1640 pmccntr_op_finish(env
);
1641 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1642 pmevcntr_op_finish(env
, i
);
1646 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1648 pmu_op_start(&cpu
->env
);
1651 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1653 pmu_op_finish(&cpu
->env
);
1656 void arm_pmu_timer_cb(void *opaque
)
1658 ARMCPU
*cpu
= opaque
;
1661 * Update all the counter values based on the current underlying counts,
1662 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1663 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1664 * counter may expire.
1666 pmu_op_start(&cpu
->env
);
1667 pmu_op_finish(&cpu
->env
);
1670 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1675 if (value
& PMCRC
) {
1676 /* The counter has been reset */
1677 env
->cp15
.c15_ccnt
= 0;
1680 if (value
& PMCRP
) {
1682 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1683 env
->cp15
.c14_pmevcntr
[i
] = 0;
1687 env
->cp15
.c9_pmcr
&= ~PMCR_WRITEABLE_MASK
;
1688 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITEABLE_MASK
);
1693 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1697 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1698 /* Increment a counter's count iff: */
1699 if ((value
& (1 << i
)) && /* counter's bit is set */
1700 /* counter is enabled and not filtered */
1701 pmu_counter_enabled(env
, i
) &&
1702 /* counter is SW_INCR */
1703 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1704 pmevcntr_op_start(env
, i
);
1707 * Detect if this write causes an overflow since we can't predict
1708 * PMSWINC overflows like we can for other events
1710 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1712 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1713 env
->cp15
.c9_pmovsr
|= (1 << i
);
1714 pmu_update_irq(env
);
1717 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1719 pmevcntr_op_finish(env
, i
);
1724 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1727 pmccntr_op_start(env
);
1728 ret
= env
->cp15
.c15_ccnt
;
1729 pmccntr_op_finish(env
);
1733 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1736 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1737 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1738 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1741 env
->cp15
.c9_pmselr
= value
& 0x1f;
1744 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1747 pmccntr_op_start(env
);
1748 env
->cp15
.c15_ccnt
= value
;
1749 pmccntr_op_finish(env
);
1752 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1755 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1757 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1760 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1763 pmccntr_op_start(env
);
1764 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1765 pmccntr_op_finish(env
);
1768 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1771 pmccntr_op_start(env
);
1772 /* M is not accessible from AArch32 */
1773 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1774 (value
& PMCCFILTR
);
1775 pmccntr_op_finish(env
);
1778 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1780 /* M is not visible in AArch32 */
1781 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1784 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1787 value
&= pmu_counter_mask(env
);
1788 env
->cp15
.c9_pmcnten
|= value
;
1791 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1794 value
&= pmu_counter_mask(env
);
1795 env
->cp15
.c9_pmcnten
&= ~value
;
1798 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1801 value
&= pmu_counter_mask(env
);
1802 env
->cp15
.c9_pmovsr
&= ~value
;
1803 pmu_update_irq(env
);
1806 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1809 value
&= pmu_counter_mask(env
);
1810 env
->cp15
.c9_pmovsr
|= value
;
1811 pmu_update_irq(env
);
1814 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1815 uint64_t value
, const uint8_t counter
)
1817 if (counter
== 31) {
1818 pmccfiltr_write(env
, ri
, value
);
1819 } else if (counter
< pmu_num_counters(env
)) {
1820 pmevcntr_op_start(env
, counter
);
1823 * If this counter's event type is changing, store the current
1824 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1825 * pmevcntr_op_finish has the correct baseline when it converts back to
1828 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1829 PMXEVTYPER_EVTCOUNT
;
1830 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1831 if (old_event
!= new_event
) {
1833 if (event_supported(new_event
)) {
1834 uint16_t event_idx
= supported_event_map
[new_event
];
1835 count
= pm_events
[event_idx
].get_count(env
);
1837 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1840 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1841 pmevcntr_op_finish(env
, counter
);
1843 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1844 * PMSELR value is equal to or greater than the number of implemented
1845 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1849 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1850 const uint8_t counter
)
1852 if (counter
== 31) {
1853 return env
->cp15
.pmccfiltr_el0
;
1854 } else if (counter
< pmu_num_counters(env
)) {
1855 return env
->cp15
.c14_pmevtyper
[counter
];
1858 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1859 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1865 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1868 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1869 pmevtyper_write(env
, ri
, value
, counter
);
1872 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1875 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1876 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1879 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1880 * pmu_op_finish calls when loading saved state for a migration. Because
1881 * we're potentially updating the type of event here, the value written to
1882 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1883 * different counter type. Therefore, we need to set this value to the
1884 * current count for the counter type we're writing so that pmu_op_finish
1885 * has the correct count for its calculation.
1887 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1888 if (event_supported(event
)) {
1889 uint16_t event_idx
= supported_event_map
[event
];
1890 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1891 pm_events
[event_idx
].get_count(env
);
1895 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1897 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1898 return pmevtyper_read(env
, ri
, counter
);
1901 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1904 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1907 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1909 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1912 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1913 uint64_t value
, uint8_t counter
)
1915 if (counter
< pmu_num_counters(env
)) {
1916 pmevcntr_op_start(env
, counter
);
1917 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1918 pmevcntr_op_finish(env
, counter
);
1921 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1922 * are CONSTRAINED UNPREDICTABLE.
1926 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1929 if (counter
< pmu_num_counters(env
)) {
1931 pmevcntr_op_start(env
, counter
);
1932 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1933 pmevcntr_op_finish(env
, counter
);
1936 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1937 * are CONSTRAINED UNPREDICTABLE. */
1942 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1945 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1946 pmevcntr_write(env
, ri
, value
, counter
);
1949 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1951 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1952 return pmevcntr_read(env
, ri
, counter
);
1955 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1958 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1959 assert(counter
< pmu_num_counters(env
));
1960 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1961 pmevcntr_write(env
, ri
, value
, counter
);
1964 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1966 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1967 assert(counter
< pmu_num_counters(env
));
1968 return env
->cp15
.c14_pmevcntr
[counter
];
1971 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1974 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1977 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1979 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1982 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1985 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1986 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1988 env
->cp15
.c9_pmuserenr
= value
& 1;
1992 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1995 /* We have no event counters so only the C bit can be changed */
1996 value
&= pmu_counter_mask(env
);
1997 env
->cp15
.c9_pminten
|= value
;
1998 pmu_update_irq(env
);
2001 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2004 value
&= pmu_counter_mask(env
);
2005 env
->cp15
.c9_pminten
&= ~value
;
2006 pmu_update_irq(env
);
2009 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2012 /* Note that even though the AArch64 view of this register has bits
2013 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
2014 * architectural requirements for bits which are RES0 only in some
2015 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
2016 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
2018 raw_write(env
, ri
, value
& ~0x1FULL
);
2021 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2023 /* Begin with base v8.0 state. */
2024 uint32_t valid_mask
= 0x3fff;
2025 ARMCPU
*cpu
= env_archcpu(env
);
2027 if (ri
->state
== ARM_CP_STATE_AA64
) {
2028 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
2029 !cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
2030 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
2032 valid_mask
&= ~SCR_NET
;
2034 if (cpu_isar_feature(aa64_lor
, cpu
)) {
2035 valid_mask
|= SCR_TLOR
;
2037 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
2038 valid_mask
|= SCR_API
| SCR_APK
;
2040 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
2041 valid_mask
|= SCR_EEL2
;
2043 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2044 valid_mask
|= SCR_ATA
;
2047 valid_mask
&= ~(SCR_RW
| SCR_ST
);
2050 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2051 valid_mask
&= ~SCR_HCE
;
2053 /* On ARMv7, SMD (or SCD as it is called in v7) is only
2054 * supported if EL2 exists. The bit is UNK/SBZP when
2055 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
2056 * when EL2 is unavailable.
2057 * On ARMv8, this bit is always available.
2059 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2060 !arm_feature(env
, ARM_FEATURE_V8
)) {
2061 valid_mask
&= ~SCR_SMD
;
2065 /* Clear all-context RES0 bits. */
2066 value
&= valid_mask
;
2067 raw_write(env
, ri
, value
);
2070 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2073 * scr_write will set the RES1 bits on an AArch64-only CPU.
2074 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
2076 scr_write(env
, ri
, 0);
2079 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
2080 const ARMCPRegInfo
*ri
,
2083 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
2084 return CP_ACCESS_TRAP_EL2
;
2087 return CP_ACCESS_OK
;
2090 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2092 ARMCPU
*cpu
= env_archcpu(env
);
2094 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
2097 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
2098 ri
->secure
& ARM_CP_SECSTATE_S
);
2100 return cpu
->ccsidr
[index
];
2103 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2106 raw_write(env
, ri
, value
& 0xf);
2109 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2111 CPUState
*cs
= env_cpu(env
);
2112 bool el1
= arm_current_el(env
) == 1;
2113 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
2116 if (hcr_el2
& HCR_IMO
) {
2117 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2121 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2126 if (hcr_el2
& HCR_FMO
) {
2127 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2131 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2136 /* External aborts are not possible in QEMU so A bit is always clear */
2140 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2143 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2144 return CP_ACCESS_TRAP_EL2
;
2147 return CP_ACCESS_OK
;
2150 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2153 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2154 return access_aa64_tid1(env
, ri
, isread
);
2157 return CP_ACCESS_OK
;
2160 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2161 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2162 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2163 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2164 /* Performance monitors are implementation defined in v7,
2165 * but with an ARM recommended set of registers, which we
2168 * Performance registers fall into three categories:
2169 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2170 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2171 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2172 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2173 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2175 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2176 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2177 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2178 .writefn
= pmcntenset_write
,
2179 .accessfn
= pmreg_access
,
2180 .raw_writefn
= raw_write
},
2181 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
2182 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2183 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2184 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2185 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2186 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2188 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2189 .accessfn
= pmreg_access
,
2190 .writefn
= pmcntenclr_write
,
2191 .type
= ARM_CP_ALIAS
},
2192 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2193 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2194 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2195 .type
= ARM_CP_ALIAS
,
2196 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2197 .writefn
= pmcntenclr_write
},
2198 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2199 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2200 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2201 .accessfn
= pmreg_access
,
2202 .writefn
= pmovsr_write
,
2203 .raw_writefn
= raw_write
},
2204 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2205 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2206 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2207 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2208 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2209 .writefn
= pmovsr_write
,
2210 .raw_writefn
= raw_write
},
2211 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2212 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2213 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2214 .writefn
= pmswinc_write
},
2215 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2216 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2217 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2218 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2219 .writefn
= pmswinc_write
},
2220 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2221 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2222 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2223 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2224 .raw_writefn
= raw_write
},
2225 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2226 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2227 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2228 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2229 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2230 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2231 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2232 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2233 .accessfn
= pmreg_access_ccntr
},
2234 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2235 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2236 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2238 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2239 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2240 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2241 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2242 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2243 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2244 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2246 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2247 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2248 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2249 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2251 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2253 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2254 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2255 .accessfn
= pmreg_access
,
2256 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2257 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2258 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2259 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2260 .accessfn
= pmreg_access
,
2261 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2262 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2263 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2264 .accessfn
= pmreg_access_xevcntr
,
2265 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2266 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2267 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2268 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2269 .accessfn
= pmreg_access_xevcntr
,
2270 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2271 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2272 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2273 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2275 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2276 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2277 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2278 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2279 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2281 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2282 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2283 .access
= PL1_RW
, .accessfn
= access_tpm
,
2284 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2285 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2287 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2288 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2289 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2290 .access
= PL1_RW
, .accessfn
= access_tpm
,
2292 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2293 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2294 .resetvalue
= 0x0 },
2295 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2296 .access
= PL1_RW
, .accessfn
= access_tpm
,
2297 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2298 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2299 .writefn
= pmintenclr_write
, },
2300 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2301 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2302 .access
= PL1_RW
, .accessfn
= access_tpm
,
2303 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2305 .writefn
= pmintenclr_write
},
2306 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2307 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2309 .accessfn
= access_aa64_tid2
,
2310 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2311 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2312 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2314 .accessfn
= access_aa64_tid2
,
2315 .writefn
= csselr_write
, .resetvalue
= 0,
2316 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2317 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2318 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2319 * just RAZ for all cores:
2321 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2322 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2323 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2324 .accessfn
= access_aa64_tid1
,
2326 /* Auxiliary fault status registers: these also are IMPDEF, and we
2327 * choose to RAZ/WI for all cores.
2329 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2330 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2331 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2332 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2333 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2334 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2335 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2336 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2337 /* MAIR can just read-as-written because we don't implement caches
2338 * and so don't need to care about memory attributes.
2340 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2341 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2342 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2343 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2345 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2346 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2347 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2349 /* For non-long-descriptor page tables these are PRRR and NMRR;
2350 * regardless they still act as reads-as-written for QEMU.
2352 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2353 * allows them to assign the correct fieldoffset based on the endianness
2354 * handled in the field definitions.
2356 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2357 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2358 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2359 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2360 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2361 .resetfn
= arm_cp_reset_ignore
},
2362 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2363 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2364 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2365 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2366 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2367 .resetfn
= arm_cp_reset_ignore
},
2368 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2369 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2370 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2371 /* 32 bit ITLB invalidates */
2372 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2373 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2374 .writefn
= tlbiall_write
},
2375 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2376 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2377 .writefn
= tlbimva_write
},
2378 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2379 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2380 .writefn
= tlbiasid_write
},
2381 /* 32 bit DTLB invalidates */
2382 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2383 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2384 .writefn
= tlbiall_write
},
2385 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2386 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2387 .writefn
= tlbimva_write
},
2388 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2389 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2390 .writefn
= tlbiasid_write
},
2391 /* 32 bit TLB invalidates */
2392 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2393 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2394 .writefn
= tlbiall_write
},
2395 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2396 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2397 .writefn
= tlbimva_write
},
2398 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2399 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2400 .writefn
= tlbiasid_write
},
2401 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2402 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2403 .writefn
= tlbimvaa_write
},
2407 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2408 /* 32 bit TLB invalidates, Inner Shareable */
2409 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2410 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2411 .writefn
= tlbiall_is_write
},
2412 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2413 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2414 .writefn
= tlbimva_is_write
},
2415 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2416 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2417 .writefn
= tlbiasid_is_write
},
2418 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2419 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2420 .writefn
= tlbimvaa_is_write
},
2424 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2425 /* PMOVSSET is not implemented in v7 before v7ve */
2426 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2427 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2428 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2429 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2430 .writefn
= pmovsset_write
,
2431 .raw_writefn
= raw_write
},
2432 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2433 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2434 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2435 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2436 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2437 .writefn
= pmovsset_write
,
2438 .raw_writefn
= raw_write
},
2442 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2449 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2452 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2453 return CP_ACCESS_TRAP
;
2455 return CP_ACCESS_OK
;
2458 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2459 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2460 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2462 .writefn
= teecr_write
},
2463 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2464 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2465 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2469 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2470 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2471 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2473 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2474 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2476 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2477 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2478 .resetfn
= arm_cp_reset_ignore
},
2479 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2480 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2481 .access
= PL0_R
|PL1_W
,
2482 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2484 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2485 .access
= PL0_R
|PL1_W
,
2486 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2487 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2488 .resetfn
= arm_cp_reset_ignore
},
2489 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2490 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2492 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2493 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2495 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2496 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2501 #ifndef CONFIG_USER_ONLY
2503 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2506 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2507 * Writable only at the highest implemented exception level.
2509 int el
= arm_current_el(env
);
2515 hcr
= arm_hcr_el2_eff(env
);
2516 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2517 cntkctl
= env
->cp15
.cnthctl_el2
;
2519 cntkctl
= env
->cp15
.c14_cntkctl
;
2521 if (!extract32(cntkctl
, 0, 2)) {
2522 return CP_ACCESS_TRAP
;
2526 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2527 arm_is_secure_below_el3(env
)) {
2528 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2529 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2537 if (!isread
&& el
< arm_highest_el(env
)) {
2538 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2541 return CP_ACCESS_OK
;
2544 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2547 unsigned int cur_el
= arm_current_el(env
);
2548 bool has_el2
= arm_is_el2_enabled(env
);
2549 uint64_t hcr
= arm_hcr_el2_eff(env
);
2553 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2554 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2555 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2556 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2559 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2560 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2561 return CP_ACCESS_TRAP
;
2564 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2565 if (hcr
& HCR_E2H
) {
2566 if (timeridx
== GTIMER_PHYS
&&
2567 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2568 return CP_ACCESS_TRAP_EL2
;
2571 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2572 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2573 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2574 return CP_ACCESS_TRAP_EL2
;
2580 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2581 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2583 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2584 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2585 return CP_ACCESS_TRAP_EL2
;
2589 return CP_ACCESS_OK
;
2592 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2595 unsigned int cur_el
= arm_current_el(env
);
2596 bool has_el2
= arm_is_el2_enabled(env
);
2597 uint64_t hcr
= arm_hcr_el2_eff(env
);
2601 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2602 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2603 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2604 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2608 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2609 * EL0 if EL0[PV]TEN is zero.
2611 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2612 return CP_ACCESS_TRAP
;
2617 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2618 if (hcr
& HCR_E2H
) {
2619 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2620 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2621 return CP_ACCESS_TRAP_EL2
;
2624 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2625 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2626 return CP_ACCESS_TRAP_EL2
;
2632 return CP_ACCESS_OK
;
2635 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2636 const ARMCPRegInfo
*ri
,
2639 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2642 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2643 const ARMCPRegInfo
*ri
,
2646 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2649 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2652 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2655 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2658 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2661 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2662 const ARMCPRegInfo
*ri
,
2665 /* The AArch64 register view of the secure physical timer is
2666 * always accessible from EL3, and configurably accessible from
2669 switch (arm_current_el(env
)) {
2671 if (!arm_is_secure(env
)) {
2672 return CP_ACCESS_TRAP
;
2674 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2675 return CP_ACCESS_TRAP_EL3
;
2677 return CP_ACCESS_OK
;
2680 return CP_ACCESS_TRAP
;
2682 return CP_ACCESS_OK
;
2684 g_assert_not_reached();
2688 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2690 ARMCPU
*cpu
= env_archcpu(env
);
2692 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2695 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2697 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2700 /* Timer enabled: calculate and set current ISTATUS, irq, and
2701 * reset timer to when ISTATUS next has to change
2703 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2704 cpu
->env
.cp15
.cntvoff_el2
: 0;
2705 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2706 /* Note that this must be unsigned 64 bit arithmetic: */
2707 int istatus
= count
- offset
>= gt
->cval
;
2711 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2713 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2714 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2717 /* Next transition is when count rolls back over to zero */
2718 nexttick
= UINT64_MAX
;
2720 /* Next transition is when we hit cval */
2721 nexttick
= gt
->cval
+ offset
;
2723 /* Note that the desired next expiry time might be beyond the
2724 * signed-64-bit range of a QEMUTimer -- in this case we just
2725 * set the timer for as far in the future as possible. When the
2726 * timer expires we will reset the timer for any remaining period.
2728 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2729 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2731 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2733 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2735 /* Timer disabled: ISTATUS and timer output always clear */
2737 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2738 timer_del(cpu
->gt_timer
[timeridx
]);
2739 trace_arm_gt_recalc_disabled(timeridx
);
2743 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2746 ARMCPU
*cpu
= env_archcpu(env
);
2748 timer_del(cpu
->gt_timer
[timeridx
]);
2751 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2753 return gt_get_countervalue(env
);
2756 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2760 switch (arm_current_el(env
)) {
2762 hcr
= arm_hcr_el2_eff(env
);
2763 if (hcr
& HCR_E2H
) {
2768 hcr
= arm_hcr_el2_eff(env
);
2769 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2775 return env
->cp15
.cntvoff_el2
;
2778 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2780 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2783 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2787 trace_arm_gt_cval_write(timeridx
, value
);
2788 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2789 gt_recalc_timer(env_archcpu(env
), timeridx
);
2792 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2795 uint64_t offset
= 0;
2799 case GTIMER_HYPVIRT
:
2800 offset
= gt_virt_cnt_offset(env
);
2804 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2805 (gt_get_countervalue(env
) - offset
));
2808 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2812 uint64_t offset
= 0;
2816 case GTIMER_HYPVIRT
:
2817 offset
= gt_virt_cnt_offset(env
);
2821 trace_arm_gt_tval_write(timeridx
, value
);
2822 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2823 sextract64(value
, 0, 32);
2824 gt_recalc_timer(env_archcpu(env
), timeridx
);
2827 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2831 ARMCPU
*cpu
= env_archcpu(env
);
2832 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2834 trace_arm_gt_ctl_write(timeridx
, value
);
2835 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2836 if ((oldval
^ value
) & 1) {
2837 /* Enable toggled */
2838 gt_recalc_timer(cpu
, timeridx
);
2839 } else if ((oldval
^ value
) & 2) {
2840 /* IMASK toggled: don't need to recalculate,
2841 * just set the interrupt line based on ISTATUS
2843 int irqstate
= (oldval
& 4) && !(value
& 2);
2845 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2846 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2850 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2852 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2855 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2858 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2861 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2863 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2866 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2869 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2872 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2875 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2878 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2880 switch (arm_mmu_idx(env
)) {
2881 case ARMMMUIdx_E20_0
:
2882 case ARMMMUIdx_E20_2
:
2883 case ARMMMUIdx_E20_2_PAN
:
2884 case ARMMMUIdx_SE20_0
:
2885 case ARMMMUIdx_SE20_2
:
2886 case ARMMMUIdx_SE20_2_PAN
:
2893 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2895 switch (arm_mmu_idx(env
)) {
2896 case ARMMMUIdx_E20_0
:
2897 case ARMMMUIdx_E20_2
:
2898 case ARMMMUIdx_E20_2_PAN
:
2899 case ARMMMUIdx_SE20_0
:
2900 case ARMMMUIdx_SE20_2
:
2901 case ARMMMUIdx_SE20_2_PAN
:
2902 return GTIMER_HYPVIRT
;
2908 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2909 const ARMCPRegInfo
*ri
)
2911 int timeridx
= gt_phys_redir_timeridx(env
);
2912 return env
->cp15
.c14_timer
[timeridx
].cval
;
2915 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2918 int timeridx
= gt_phys_redir_timeridx(env
);
2919 gt_cval_write(env
, ri
, timeridx
, value
);
2922 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2923 const ARMCPRegInfo
*ri
)
2925 int timeridx
= gt_phys_redir_timeridx(env
);
2926 return gt_tval_read(env
, ri
, timeridx
);
2929 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2932 int timeridx
= gt_phys_redir_timeridx(env
);
2933 gt_tval_write(env
, ri
, timeridx
, value
);
2936 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2937 const ARMCPRegInfo
*ri
)
2939 int timeridx
= gt_phys_redir_timeridx(env
);
2940 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2943 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2946 int timeridx
= gt_phys_redir_timeridx(env
);
2947 gt_ctl_write(env
, ri
, timeridx
, value
);
2950 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2952 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2955 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2958 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2961 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2963 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2966 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2969 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2972 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2975 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2978 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2981 ARMCPU
*cpu
= env_archcpu(env
);
2983 trace_arm_gt_cntvoff_write(value
);
2984 raw_write(env
, ri
, value
);
2985 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2988 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2989 const ARMCPRegInfo
*ri
)
2991 int timeridx
= gt_virt_redir_timeridx(env
);
2992 return env
->cp15
.c14_timer
[timeridx
].cval
;
2995 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2998 int timeridx
= gt_virt_redir_timeridx(env
);
2999 gt_cval_write(env
, ri
, timeridx
, value
);
3002 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
3003 const ARMCPRegInfo
*ri
)
3005 int timeridx
= gt_virt_redir_timeridx(env
);
3006 return gt_tval_read(env
, ri
, timeridx
);
3009 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3012 int timeridx
= gt_virt_redir_timeridx(env
);
3013 gt_tval_write(env
, ri
, timeridx
, value
);
3016 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
3017 const ARMCPRegInfo
*ri
)
3019 int timeridx
= gt_virt_redir_timeridx(env
);
3020 return env
->cp15
.c14_timer
[timeridx
].ctl
;
3023 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3026 int timeridx
= gt_virt_redir_timeridx(env
);
3027 gt_ctl_write(env
, ri
, timeridx
, value
);
3030 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3032 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3035 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3038 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3041 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3043 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3046 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3049 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3052 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3055 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3058 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3060 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3063 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3066 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3069 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3071 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3074 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3077 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3080 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3083 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3086 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3088 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3091 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3094 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3097 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3099 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3102 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3105 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3108 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3111 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3114 void arm_gt_ptimer_cb(void *opaque
)
3116 ARMCPU
*cpu
= opaque
;
3118 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3121 void arm_gt_vtimer_cb(void *opaque
)
3123 ARMCPU
*cpu
= opaque
;
3125 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3128 void arm_gt_htimer_cb(void *opaque
)
3130 ARMCPU
*cpu
= opaque
;
3132 gt_recalc_timer(cpu
, GTIMER_HYP
);
3135 void arm_gt_stimer_cb(void *opaque
)
3137 ARMCPU
*cpu
= opaque
;
3139 gt_recalc_timer(cpu
, GTIMER_SEC
);
3142 void arm_gt_hvtimer_cb(void *opaque
)
3144 ARMCPU
*cpu
= opaque
;
3146 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3149 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3151 ARMCPU
*cpu
= env_archcpu(env
);
3153 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3156 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3157 /* Note that CNTFRQ is purely reads-as-written for the benefit
3158 * of software; writing it doesn't actually change the timer frequency.
3159 * Our reset value matches the fixed frequency we implement the timer at.
3161 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3162 .type
= ARM_CP_ALIAS
,
3163 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3164 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3166 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3167 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3168 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3169 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3170 .resetfn
= arm_gt_cntfrq_reset
,
3172 /* overall control: mostly access permissions */
3173 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3174 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3176 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3179 /* per-timer control */
3180 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3181 .secure
= ARM_CP_SECSTATE_NS
,
3182 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3183 .accessfn
= gt_ptimer_access
,
3184 .fieldoffset
= offsetoflow32(CPUARMState
,
3185 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3186 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3187 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3189 { .name
= "CNTP_CTL_S",
3190 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3191 .secure
= ARM_CP_SECSTATE_S
,
3192 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3193 .accessfn
= gt_ptimer_access
,
3194 .fieldoffset
= offsetoflow32(CPUARMState
,
3195 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3196 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3198 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3199 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3200 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3201 .accessfn
= gt_ptimer_access
,
3202 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3204 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3205 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3207 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3208 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3209 .accessfn
= gt_vtimer_access
,
3210 .fieldoffset
= offsetoflow32(CPUARMState
,
3211 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3212 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3213 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3215 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3216 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3217 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3218 .accessfn
= gt_vtimer_access
,
3219 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3221 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3222 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3224 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3225 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3226 .secure
= ARM_CP_SECSTATE_NS
,
3227 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3228 .accessfn
= gt_ptimer_access
,
3229 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3231 { .name
= "CNTP_TVAL_S",
3232 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3233 .secure
= ARM_CP_SECSTATE_S
,
3234 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3235 .accessfn
= gt_ptimer_access
,
3236 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3238 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3239 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3240 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3241 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3242 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3244 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3245 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3246 .accessfn
= gt_vtimer_access
,
3247 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3249 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3250 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3251 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3252 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3253 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3255 /* The counter itself */
3256 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3257 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3258 .accessfn
= gt_pct_access
,
3259 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3261 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3262 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3263 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3264 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3266 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3267 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3268 .accessfn
= gt_vct_access
,
3269 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3271 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3272 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3273 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3274 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3276 /* Comparison value, indicating when the timer goes off */
3277 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3278 .secure
= ARM_CP_SECSTATE_NS
,
3280 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3281 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3282 .accessfn
= gt_ptimer_access
,
3283 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3284 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3286 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3287 .secure
= ARM_CP_SECSTATE_S
,
3289 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3291 .accessfn
= gt_ptimer_access
,
3292 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3294 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3295 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3298 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3299 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3300 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3301 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3303 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3305 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3306 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3307 .accessfn
= gt_vtimer_access
,
3308 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3309 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3311 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3312 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3315 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3316 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3317 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3318 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3320 /* Secure timer -- this is actually restricted to only EL3
3321 * and configurably Secure-EL1 via the accessfn.
3323 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3324 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3325 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3326 .accessfn
= gt_stimer_access
,
3327 .readfn
= gt_sec_tval_read
,
3328 .writefn
= gt_sec_tval_write
,
3329 .resetfn
= gt_sec_timer_reset
,
3331 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3333 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3334 .accessfn
= gt_stimer_access
,
3335 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3337 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3339 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3340 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3341 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3342 .accessfn
= gt_stimer_access
,
3343 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3344 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3349 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3352 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3353 return CP_ACCESS_TRAP
;
3355 return CP_ACCESS_OK
;
3360 /* In user-mode most of the generic timer registers are inaccessible
3361 * however modern kernels (4.12+) allow access to cntvct_el0
3364 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3366 ARMCPU
*cpu
= env_archcpu(env
);
3368 /* Currently we have no support for QEMUTimer in linux-user so we
3369 * can't call gt_get_countervalue(env), instead we directly
3370 * call the lower level functions.
3372 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3375 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3376 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3377 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3378 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3379 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3380 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3382 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3383 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3384 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3385 .readfn
= gt_virt_cnt_read
,
3392 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3394 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3395 raw_write(env
, ri
, value
);
3396 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3397 raw_write(env
, ri
, value
& 0xfffff6ff);
3399 raw_write(env
, ri
, value
& 0xfffff1ff);
3403 #ifndef CONFIG_USER_ONLY
3404 /* get_phys_addr() isn't present for user-mode-only targets */
3406 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3410 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3411 * Secure EL1 (which can only happen if EL3 is AArch64).
3412 * They are simply UNDEF if executed from NS EL1.
3413 * They function normally from EL2 or EL3.
3415 if (arm_current_el(env
) == 1) {
3416 if (arm_is_secure_below_el3(env
)) {
3417 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3418 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3420 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3422 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3425 return CP_ACCESS_OK
;
3429 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3430 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3433 target_ulong page_size
;
3437 bool format64
= false;
3438 MemTxAttrs attrs
= {};
3439 ARMMMUFaultInfo fi
= {};
3440 ARMCacheAttrs cacheattrs
= {};
3442 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3443 &prot
, &page_size
, &fi
, &cacheattrs
);
3447 * Some kinds of translation fault must cause exceptions rather
3448 * than being reported in the PAR.
3450 int current_el
= arm_current_el(env
);
3452 uint32_t syn
, fsr
, fsc
;
3453 bool take_exc
= false;
3455 if (fi
.s1ptw
&& current_el
== 1
3456 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3458 * Synchronous stage 2 fault on an access made as part of the
3459 * translation table walk for AT S1E0* or AT S1E1* insn
3460 * executed from NS EL1. If this is a synchronous external abort
3461 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3462 * to EL3. Otherwise the fault is taken as an exception to EL2,
3463 * and HPFAR_EL2 holds the faulting IPA.
3465 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3466 (env
->cp15
.scr_el3
& SCR_EA
)) {
3469 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3470 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3471 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3476 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3478 * Synchronous external aborts during a translation table walk
3479 * are taken as Data Abort exceptions.
3482 if (current_el
== 3) {
3488 target_el
= exception_target_el(env
);
3494 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3495 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3496 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3497 fsr
= arm_fi_to_lfsc(&fi
);
3498 fsc
= extract32(fsr
, 0, 6);
3500 fsr
= arm_fi_to_sfsc(&fi
);
3504 * Report exception with ESR indicating a fault due to a
3505 * translation table walk for a cache maintenance instruction.
3507 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3508 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3509 env
->exception
.vaddress
= value
;
3510 env
->exception
.fsr
= fsr
;
3511 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3517 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3520 * * TTBCR.EAE determines whether the result is returned using the
3521 * 32-bit or the 64-bit PAR format
3522 * * Instructions executed in Hyp mode always use the 64bit format
3524 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3525 * * The Non-secure TTBCR.EAE bit is set to 1
3526 * * The implementation includes EL2, and the value of HCR.VM is 1
3528 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3530 * ATS1Hx always uses the 64bit format.
3532 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3534 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3535 if (mmu_idx
== ARMMMUIdx_E10_0
||
3536 mmu_idx
== ARMMMUIdx_E10_1
||
3537 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3538 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3540 format64
|= arm_current_el(env
) == 2;
3546 /* Create a 64-bit PAR */
3547 par64
= (1 << 11); /* LPAE bit always set */
3549 par64
|= phys_addr
& ~0xfffULL
;
3550 if (!attrs
.secure
) {
3551 par64
|= (1 << 9); /* NS */
3553 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3554 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3556 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3559 par64
|= (fsr
& 0x3f) << 1; /* FS */
3561 par64
|= (1 << 9); /* S */
3564 par64
|= (1 << 8); /* PTW */
3568 /* fsr is a DFSR/IFSR value for the short descriptor
3569 * translation table format (with WnR always clear).
3570 * Convert it to a 32-bit PAR.
3573 /* We do not set any attribute bits in the PAR */
3574 if (page_size
== (1 << 24)
3575 && arm_feature(env
, ARM_FEATURE_V7
)) {
3576 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3578 par64
= phys_addr
& 0xfffff000;
3580 if (!attrs
.secure
) {
3581 par64
|= (1 << 9); /* NS */
3584 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3586 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3587 ((fsr
& 0xf) << 1) | 1;
3592 #endif /* CONFIG_TCG */
3594 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3597 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3600 int el
= arm_current_el(env
);
3601 bool secure
= arm_is_secure_below_el3(env
);
3603 switch (ri
->opc2
& 6) {
3605 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3608 mmu_idx
= ARMMMUIdx_SE3
;
3611 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3614 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3615 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3616 : ARMMMUIdx_Stage1_E1_PAN
);
3618 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3622 g_assert_not_reached();
3626 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3629 mmu_idx
= ARMMMUIdx_SE10_0
;
3632 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3633 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3636 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3639 g_assert_not_reached();
3643 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3644 mmu_idx
= ARMMMUIdx_E10_1
;
3647 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3648 mmu_idx
= ARMMMUIdx_E10_0
;
3651 g_assert_not_reached();
3654 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3656 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3658 /* Handled by hardware accelerator. */
3659 g_assert_not_reached();
3660 #endif /* CONFIG_TCG */
3663 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3667 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3670 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3672 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3674 /* Handled by hardware accelerator. */
3675 g_assert_not_reached();
3676 #endif /* CONFIG_TCG */
3679 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3682 if (arm_current_el(env
) == 3 &&
3683 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3684 return CP_ACCESS_TRAP
;
3686 return CP_ACCESS_OK
;
3689 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3693 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3695 int secure
= arm_is_secure_below_el3(env
);
3697 switch (ri
->opc2
& 6) {
3700 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3701 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3702 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3703 : ARMMMUIdx_Stage1_E1_PAN
);
3705 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3708 case 4: /* AT S1E2R, AT S1E2W */
3709 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3711 case 6: /* AT S1E3R, AT S1E3W */
3712 mmu_idx
= ARMMMUIdx_SE3
;
3715 g_assert_not_reached();
3718 case 2: /* AT S1E0R, AT S1E0W */
3719 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3721 case 4: /* AT S12E1R, AT S12E1W */
3722 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3724 case 6: /* AT S12E0R, AT S12E0W */
3725 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3728 g_assert_not_reached();
3731 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3733 /* Handled by hardware accelerator. */
3734 g_assert_not_reached();
3735 #endif /* CONFIG_TCG */
3739 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3740 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3741 .access
= PL1_RW
, .resetvalue
= 0,
3742 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3743 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3744 .writefn
= par_write
},
3745 #ifndef CONFIG_USER_ONLY
3746 /* This underdecoding is safe because the reginfo is NO_RAW. */
3747 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3748 .access
= PL1_W
, .accessfn
= ats_access
,
3749 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3754 /* Return basic MPU access permission bits. */
3755 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3762 for (i
= 0; i
< 16; i
+= 2) {
3763 ret
|= (val
>> i
) & mask
;
3769 /* Pad basic MPU access permission bits to extended format. */
3770 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3777 for (i
= 0; i
< 16; i
+= 2) {
3778 ret
|= (val
& mask
) << i
;
3784 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3787 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3790 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3792 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3795 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3798 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3801 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3803 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3806 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3808 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3814 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3818 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3821 ARMCPU
*cpu
= env_archcpu(env
);
3822 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3828 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3829 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3833 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3836 ARMCPU
*cpu
= env_archcpu(env
);
3837 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3839 if (value
>= nrgs
) {
3840 qemu_log_mask(LOG_GUEST_ERROR
,
3841 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3842 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3846 raw_write(env
, ri
, value
);
3849 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3850 /* Reset for all these registers is handled in arm_cpu_reset(),
3851 * because the PMSAv7 is also used by M-profile CPUs, which do
3852 * not register cpregs but still need the state to be reset.
3854 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3855 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3856 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3857 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3858 .resetfn
= arm_cp_reset_ignore
},
3859 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3860 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3861 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3862 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3863 .resetfn
= arm_cp_reset_ignore
},
3864 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3865 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3866 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3867 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3868 .resetfn
= arm_cp_reset_ignore
},
3869 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3871 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3872 .writefn
= pmsav7_rgnr_write
,
3873 .resetfn
= arm_cp_reset_ignore
},
3877 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3878 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3879 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3880 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3881 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3882 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3883 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3884 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3885 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3886 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3888 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3890 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3892 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3894 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3896 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3897 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3899 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3900 /* Protection region base and size registers */
3901 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3902 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3903 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3904 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3905 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3906 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3907 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3908 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3909 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3910 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3911 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3912 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3913 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3914 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3915 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3916 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3917 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3918 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3919 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3920 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3921 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3922 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3923 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3924 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3928 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3931 TCR
*tcr
= raw_ptr(env
, ri
);
3932 int maskshift
= extract32(value
, 0, 3);
3934 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3935 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3936 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3937 * using Long-desciptor translation table format */
3938 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3939 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3940 /* In an implementation that includes the Security Extensions
3941 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3942 * Short-descriptor translation table format.
3944 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3950 /* Update the masks corresponding to the TCR bank being written
3951 * Note that we always calculate mask and base_mask, but
3952 * they are only used for short-descriptor tables (ie if EAE is 0);
3953 * for long-descriptor tables the TCR fields are used differently
3954 * and the mask and base_mask values are meaningless.
3956 tcr
->raw_tcr
= value
;
3957 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3958 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3961 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3964 ARMCPU
*cpu
= env_archcpu(env
);
3965 TCR
*tcr
= raw_ptr(env
, ri
);
3967 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3968 /* With LPAE the TTBCR could result in a change of ASID
3969 * via the TTBCR.A1 bit, so do a TLB flush.
3971 tlb_flush(CPU(cpu
));
3973 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3974 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3975 vmsa_ttbcr_raw_write(env
, ri
, value
);
3978 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3980 TCR
*tcr
= raw_ptr(env
, ri
);
3982 /* Reset both the TCR as well as the masks corresponding to the bank of
3983 * the TCR being reset.
3987 tcr
->base_mask
= 0xffffc000u
;
3990 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3993 ARMCPU
*cpu
= env_archcpu(env
);
3994 TCR
*tcr
= raw_ptr(env
, ri
);
3996 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3997 tlb_flush(CPU(cpu
));
3998 tcr
->raw_tcr
= value
;
4001 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4004 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4005 if (cpreg_field_is_64bit(ri
) &&
4006 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4007 ARMCPU
*cpu
= env_archcpu(env
);
4008 tlb_flush(CPU(cpu
));
4010 raw_write(env
, ri
, value
);
4013 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4017 * If we are running with E2&0 regime, then an ASID is active.
4018 * Flush if that might be changing. Note we're not checking
4019 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4020 * holds the active ASID, only checking the field that might.
4022 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4023 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4024 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4025 ARMMMUIdxBit_E20_2_PAN
|
4028 if (arm_is_secure_below_el3(env
)) {
4029 mask
>>= ARM_MMU_IDX_A_NS
;
4032 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4034 raw_write(env
, ri
, value
);
4037 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4040 ARMCPU
*cpu
= env_archcpu(env
);
4041 CPUState
*cs
= CPU(cpu
);
4044 * A change in VMID to the stage2 page table (Stage2) invalidates
4045 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
4047 if (raw_read(env
, ri
) != value
) {
4048 uint16_t mask
= ARMMMUIdxBit_E10_1
|
4049 ARMMMUIdxBit_E10_1_PAN
|
4052 if (arm_is_secure_below_el3(env
)) {
4053 mask
>>= ARM_MMU_IDX_A_NS
;
4056 tlb_flush_by_mmuidx(cs
, mask
);
4057 raw_write(env
, ri
, value
);
4061 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4062 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4063 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4064 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4065 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4066 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4067 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4068 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4069 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4070 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4071 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4072 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4073 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4074 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4075 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4076 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4077 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4082 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4083 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4084 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4085 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4086 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4087 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4088 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4089 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4090 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4091 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4092 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4093 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4094 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4095 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4096 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4097 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4098 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4099 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4100 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4101 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4102 .writefn
= vmsa_tcr_el12_write
,
4103 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
4104 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4105 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4106 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4107 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4108 .raw_writefn
= vmsa_ttbcr_raw_write
,
4109 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4110 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4114 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4115 * qemu tlbs nor adjusting cached masks.
4117 static const ARMCPRegInfo ttbcr2_reginfo
= {
4118 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4119 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4120 .type
= ARM_CP_ALIAS
,
4121 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4122 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
4125 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4128 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4129 /* The OS_TYPE bit in this register changes the reported CPUID! */
4130 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4131 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4134 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4137 env
->cp15
.c15_threadid
= value
& 0xffff;
4140 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4143 /* Wait-for-interrupt (deprecated) */
4144 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4147 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4150 /* On OMAP there are registers indicating the max/min index of dcache lines
4151 * containing a dirty line; cache flush operations have to reset these.
4153 env
->cp15
.c15_i_max
= 0x000;
4154 env
->cp15
.c15_i_min
= 0xff0;
4157 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4158 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4159 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4160 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4162 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4163 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4164 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4166 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4167 .writefn
= omap_ticonfig_write
},
4168 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4170 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4171 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4172 .access
= PL1_RW
, .resetvalue
= 0xff0,
4173 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4174 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4176 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4177 .writefn
= omap_threadid_write
},
4178 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4179 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4180 .type
= ARM_CP_NO_RAW
,
4181 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4182 /* TODO: Peripheral port remap register:
4183 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4184 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4187 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4188 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4189 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4190 .writefn
= omap_cachemaint_write
},
4191 { .name
= "C9", .cp
= 15, .crn
= 9,
4192 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4193 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4197 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4200 env
->cp15
.c15_cpar
= value
& 0x3fff;
4203 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4204 { .name
= "XSCALE_CPAR",
4205 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4206 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4207 .writefn
= xscale_cpar_write
, },
4208 { .name
= "XSCALE_AUXCR",
4209 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4210 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4212 /* XScale specific cache-lockdown: since we have no cache we NOP these
4213 * and hope the guest does not really rely on cache behaviour.
4215 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4216 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4217 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4218 { .name
= "XSCALE_UNLOCK_ICACHE",
4219 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4220 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4221 { .name
= "XSCALE_DCACHE_LOCK",
4222 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4223 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4224 { .name
= "XSCALE_UNLOCK_DCACHE",
4225 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4226 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4230 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4231 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4232 * implementation of this implementation-defined space.
4233 * Ideally this should eventually disappear in favour of actually
4234 * implementing the correct behaviour for all cores.
4236 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4237 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4239 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4244 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4245 /* Cache status: RAZ because we have no cache so it's always clean */
4246 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4247 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4252 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4253 /* We never have a a block transfer operation in progress */
4254 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4255 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4257 /* The cache ops themselves: these all NOP for QEMU */
4258 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4259 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4260 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4261 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4262 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4263 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4264 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4265 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4266 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4267 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4268 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4269 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4273 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4274 /* The cache test-and-clean instructions always return (1 << 30)
4275 * to indicate that there are no dirty cache lines.
4277 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4278 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4279 .resetvalue
= (1 << 30) },
4280 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4281 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4282 .resetvalue
= (1 << 30) },
4286 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4287 /* Ignore ReadBuffer accesses */
4288 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4289 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4290 .access
= PL1_RW
, .resetvalue
= 0,
4291 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4295 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4297 unsigned int cur_el
= arm_current_el(env
);
4299 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4300 return env
->cp15
.vpidr_el2
;
4302 return raw_read(env
, ri
);
4305 static uint64_t mpidr_read_val(CPUARMState
*env
)
4307 ARMCPU
*cpu
= env_archcpu(env
);
4308 uint64_t mpidr
= cpu
->mp_affinity
;
4310 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4311 mpidr
|= (1U << 31);
4312 /* Cores which are uniprocessor (non-coherent)
4313 * but still implement the MP extensions set
4314 * bit 30. (For instance, Cortex-R5).
4316 if (cpu
->mp_is_up
) {
4317 mpidr
|= (1u << 30);
4323 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4325 unsigned int cur_el
= arm_current_el(env
);
4327 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4328 return env
->cp15
.vmpidr_el2
;
4330 return mpidr_read_val(env
);
4333 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4335 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4336 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4337 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4338 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4339 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4340 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4341 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4342 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4343 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4344 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4345 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4346 offsetof(CPUARMState
, cp15
.par_ns
)} },
4347 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4348 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4349 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4350 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4351 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4352 .writefn
= vmsa_ttbr_write
, },
4353 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4354 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4355 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4356 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4357 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4358 .writefn
= vmsa_ttbr_write
, },
4362 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4364 return vfp_get_fpcr(env
);
4367 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4370 vfp_set_fpcr(env
, value
);
4373 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4375 return vfp_get_fpsr(env
);
4378 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4381 vfp_set_fpsr(env
, value
);
4384 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4387 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4388 return CP_ACCESS_TRAP
;
4390 return CP_ACCESS_OK
;
4393 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4396 env
->daif
= value
& PSTATE_DAIF
;
4399 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4401 return env
->pstate
& PSTATE_PAN
;
4404 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4407 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4410 static const ARMCPRegInfo pan_reginfo
= {
4411 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4412 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4413 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4414 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4417 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4419 return env
->pstate
& PSTATE_UAO
;
4422 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4425 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4428 static const ARMCPRegInfo uao_reginfo
= {
4429 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4430 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4431 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4432 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4435 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4437 return env
->pstate
& PSTATE_DIT
;
4440 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4443 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4446 static const ARMCPRegInfo dit_reginfo
= {
4447 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4448 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4449 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4450 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4453 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4455 return env
->pstate
& PSTATE_SSBS
;
4458 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4461 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4464 static const ARMCPRegInfo ssbs_reginfo
= {
4465 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4466 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4467 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4468 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4471 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4472 const ARMCPRegInfo
*ri
,
4475 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4476 switch (arm_current_el(env
)) {
4478 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4479 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4480 return CP_ACCESS_TRAP
;
4484 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4485 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4486 return CP_ACCESS_TRAP_EL2
;
4490 return CP_ACCESS_OK
;
4493 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4494 const ARMCPRegInfo
*ri
,
4497 /* Cache invalidate/clean to Point of Unification... */
4498 switch (arm_current_el(env
)) {
4500 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4501 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4502 return CP_ACCESS_TRAP
;
4506 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4507 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4508 return CP_ACCESS_TRAP_EL2
;
4512 return CP_ACCESS_OK
;
4515 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4516 * Page D4-1736 (DDI0487A.b)
4519 static int vae1_tlbmask(CPUARMState
*env
)
4521 uint64_t hcr
= arm_hcr_el2_eff(env
);
4524 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4525 mask
= ARMMMUIdxBit_E20_2
|
4526 ARMMMUIdxBit_E20_2_PAN
|
4529 mask
= ARMMMUIdxBit_E10_1
|
4530 ARMMMUIdxBit_E10_1_PAN
|
4534 if (arm_is_secure_below_el3(env
)) {
4535 mask
>>= ARM_MMU_IDX_A_NS
;
4541 /* Return 56 if TBI is enabled, 64 otherwise. */
4542 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4545 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
4546 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4547 int select
= extract64(addr
, 55, 1);
4549 return (tbi
>> select
) & 1 ? 56 : 64;
4552 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4554 uint64_t hcr
= arm_hcr_el2_eff(env
);
4557 /* Only the regime of the mmu_idx below is significant. */
4558 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4559 mmu_idx
= ARMMMUIdx_E20_0
;
4561 mmu_idx
= ARMMMUIdx_E10_0
;
4564 if (arm_is_secure_below_el3(env
)) {
4565 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4568 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4571 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4574 CPUState
*cs
= env_cpu(env
);
4575 int mask
= vae1_tlbmask(env
);
4577 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4580 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4583 CPUState
*cs
= env_cpu(env
);
4584 int mask
= vae1_tlbmask(env
);
4586 if (tlb_force_broadcast(env
)) {
4587 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4589 tlb_flush_by_mmuidx(cs
, mask
);
4593 static int alle1_tlbmask(CPUARMState
*env
)
4596 * Note that the 'ALL' scope must invalidate both stage 1 and
4597 * stage 2 translations, whereas most other scopes only invalidate
4598 * stage 1 translations.
4600 if (arm_is_secure_below_el3(env
)) {
4601 return ARMMMUIdxBit_SE10_1
|
4602 ARMMMUIdxBit_SE10_1_PAN
|
4603 ARMMMUIdxBit_SE10_0
;
4605 return ARMMMUIdxBit_E10_1
|
4606 ARMMMUIdxBit_E10_1_PAN
|
4611 static int e2_tlbmask(CPUARMState
*env
)
4613 if (arm_is_secure_below_el3(env
)) {
4614 return ARMMMUIdxBit_SE20_0
|
4615 ARMMMUIdxBit_SE20_2
|
4616 ARMMMUIdxBit_SE20_2_PAN
|
4619 return ARMMMUIdxBit_E20_0
|
4620 ARMMMUIdxBit_E20_2
|
4621 ARMMMUIdxBit_E20_2_PAN
|
4626 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4629 CPUState
*cs
= env_cpu(env
);
4630 int mask
= alle1_tlbmask(env
);
4632 tlb_flush_by_mmuidx(cs
, mask
);
4635 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4638 CPUState
*cs
= env_cpu(env
);
4639 int mask
= e2_tlbmask(env
);
4641 tlb_flush_by_mmuidx(cs
, mask
);
4644 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4647 ARMCPU
*cpu
= env_archcpu(env
);
4648 CPUState
*cs
= CPU(cpu
);
4650 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4653 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4656 CPUState
*cs
= env_cpu(env
);
4657 int mask
= alle1_tlbmask(env
);
4659 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4662 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4665 CPUState
*cs
= env_cpu(env
);
4666 int mask
= e2_tlbmask(env
);
4668 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4671 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4674 CPUState
*cs
= env_cpu(env
);
4676 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4679 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4682 /* Invalidate by VA, EL2
4683 * Currently handles both VAE2 and VALE2, since we don't support
4684 * flush-last-level-only.
4686 CPUState
*cs
= env_cpu(env
);
4687 int mask
= e2_tlbmask(env
);
4688 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4690 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4693 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4696 /* Invalidate by VA, EL3
4697 * Currently handles both VAE3 and VALE3, since we don't support
4698 * flush-last-level-only.
4700 ARMCPU
*cpu
= env_archcpu(env
);
4701 CPUState
*cs
= CPU(cpu
);
4702 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4704 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4707 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4710 CPUState
*cs
= env_cpu(env
);
4711 int mask
= vae1_tlbmask(env
);
4712 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4713 int bits
= vae1_tlbbits(env
, pageaddr
);
4715 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4718 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4721 /* Invalidate by VA, EL1&0 (AArch64 version).
4722 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4723 * since we don't support flush-for-specific-ASID-only or
4724 * flush-last-level-only.
4726 CPUState
*cs
= env_cpu(env
);
4727 int mask
= vae1_tlbmask(env
);
4728 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4729 int bits
= vae1_tlbbits(env
, pageaddr
);
4731 if (tlb_force_broadcast(env
)) {
4732 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4734 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4738 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4741 CPUState
*cs
= env_cpu(env
);
4742 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4743 bool secure
= arm_is_secure_below_el3(env
);
4744 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4745 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
,
4748 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4751 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4754 CPUState
*cs
= env_cpu(env
);
4755 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4756 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4758 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4759 ARMMMUIdxBit_SE3
, bits
);
4762 #ifdef TARGET_AARCH64
4763 static uint64_t tlbi_aa64_range_get_length(CPUARMState
*env
,
4766 unsigned int page_shift
;
4767 unsigned int page_size_granule
;
4773 num
= extract64(value
, 39, 4);
4774 scale
= extract64(value
, 44, 2);
4775 page_size_granule
= extract64(value
, 46, 2);
4777 page_shift
= page_size_granule
* 2 + 12;
4779 if (page_size_granule
== 0) {
4780 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid page size granule %d\n",
4785 exponent
= (5 * scale
) + 1;
4786 length
= (num
+ 1) << (exponent
+ page_shift
);
4791 static uint64_t tlbi_aa64_range_get_base(CPUARMState
*env
, uint64_t value
,
4794 /* TODO: ARMv8.7 FEAT_LPA2 */
4798 pageaddr
= sextract64(value
, 0, 37) << TARGET_PAGE_BITS
;
4800 pageaddr
= extract64(value
, 0, 37) << TARGET_PAGE_BITS
;
4806 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4807 int idxmap
, bool synced
)
4809 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4810 bool two_ranges
= regime_has_2_ranges(one_idx
);
4811 uint64_t baseaddr
, length
;
4814 baseaddr
= tlbi_aa64_range_get_base(env
, value
, two_ranges
);
4815 length
= tlbi_aa64_range_get_length(env
, value
);
4816 bits
= tlbbits_for_regime(env
, one_idx
, baseaddr
);
4819 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4825 tlb_flush_range_by_mmuidx(env_cpu(env
), baseaddr
,
4826 length
, idxmap
, bits
);
4830 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4831 const ARMCPRegInfo
*ri
,
4835 * Invalidate by VA range, EL1&0.
4836 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4837 * since we don't support flush-for-specific-ASID-only or
4838 * flush-last-level-only.
4841 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4842 tlb_force_broadcast(env
));
4845 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4846 const ARMCPRegInfo
*ri
,
4850 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4851 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4852 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4853 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4854 * shareable specific flushes.
4857 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4860 static int vae2_tlbmask(CPUARMState
*env
)
4862 return (arm_is_secure_below_el3(env
)
4863 ? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
);
4866 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4867 const ARMCPRegInfo
*ri
,
4871 * Invalidate by VA range, EL2.
4872 * Currently handles all of RVAE2 and RVALE2,
4873 * since we don't support flush-for-specific-ASID-only or
4874 * flush-last-level-only.
4877 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4878 tlb_force_broadcast(env
));
4883 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4884 const ARMCPRegInfo
*ri
,
4888 * Invalidate by VA range, Inner/Outer Shareable, EL2.
4889 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
4890 * since we don't support flush-for-specific-ASID-only,
4891 * flush-last-level-only or inner/outer shareable specific flushes.
4894 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
4898 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
4899 const ARMCPRegInfo
*ri
,
4903 * Invalidate by VA range, EL3.
4904 * Currently handles all of RVAE3 and RVALE3,
4905 * since we don't support flush-for-specific-ASID-only or
4906 * flush-last-level-only.
4909 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
,
4910 tlb_force_broadcast(env
));
4913 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
4914 const ARMCPRegInfo
*ri
,
4918 * Invalidate by VA range, EL3, Inner/Outer Shareable.
4919 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
4920 * since we don't support flush-for-specific-ASID-only,
4921 * flush-last-level-only or inner/outer specific flushes.
4924 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
, true);
4928 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4931 int cur_el
= arm_current_el(env
);
4934 uint64_t hcr
= arm_hcr_el2_eff(env
);
4937 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4938 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4939 return CP_ACCESS_TRAP_EL2
;
4942 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4943 return CP_ACCESS_TRAP
;
4945 if (hcr
& HCR_TDZ
) {
4946 return CP_ACCESS_TRAP_EL2
;
4949 } else if (hcr
& HCR_TDZ
) {
4950 return CP_ACCESS_TRAP_EL2
;
4953 return CP_ACCESS_OK
;
4956 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4958 ARMCPU
*cpu
= env_archcpu(env
);
4959 int dzp_bit
= 1 << 4;
4961 /* DZP indicates whether DC ZVA access is allowed */
4962 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4965 return cpu
->dcz_blocksize
| dzp_bit
;
4968 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4971 if (!(env
->pstate
& PSTATE_SP
)) {
4972 /* Access to SP_EL0 is undefined if it's being used as
4973 * the stack pointer.
4975 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4977 return CP_ACCESS_OK
;
4980 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4982 return env
->pstate
& PSTATE_SP
;
4985 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4987 update_spsel(env
, val
);
4990 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4993 ARMCPU
*cpu
= env_archcpu(env
);
4995 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4996 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5000 /* ??? Lots of these bits are not implemented. */
5002 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5003 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5004 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5006 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5007 SCTLR_ATA0
| SCTLR_ATA
);
5011 if (raw_read(env
, ri
) == value
) {
5012 /* Skip the TLB flush if nothing actually changed; Linux likes
5013 * to do a lot of pointless SCTLR writes.
5018 raw_write(env
, ri
, value
);
5020 /* This may enable/disable the MMU, so do a TLB flush. */
5021 tlb_flush(CPU(cpu
));
5023 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5025 * Normally we would always end the TB on an SCTLR write; see the
5026 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5027 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5028 * of hflags from the translator, so do it here.
5030 arm_rebuild_hflags(env
);
5034 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5037 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
5038 return CP_ACCESS_TRAP_FP_EL2
;
5040 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
5041 return CP_ACCESS_TRAP_FP_EL3
;
5043 return CP_ACCESS_OK
;
5046 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5049 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
5052 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5053 /* Minimal set of EL0-visible registers. This will need to be expanded
5054 * significantly for system emulation of AArch64 CPUs.
5056 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5057 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5058 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5059 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5060 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5061 .type
= ARM_CP_NO_RAW
,
5062 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5063 .fieldoffset
= offsetof(CPUARMState
, daif
),
5064 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5065 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5066 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5067 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5068 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5069 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5070 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5071 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5072 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5073 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5074 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5075 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5076 .readfn
= aa64_dczid_read
},
5077 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5078 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5079 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5080 #ifndef CONFIG_USER_ONLY
5081 /* Avoid overhead of an access check that always passes in user-mode */
5082 .accessfn
= aa64_zva_access
,
5085 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5086 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5087 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5088 /* Cache ops: all NOPs since we don't emulate caches */
5089 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5090 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5091 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5092 .accessfn
= aa64_cacheop_pou_access
},
5093 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5094 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5095 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5096 .accessfn
= aa64_cacheop_pou_access
},
5097 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5098 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5099 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5100 .accessfn
= aa64_cacheop_pou_access
},
5101 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5102 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5103 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5104 .type
= ARM_CP_NOP
},
5105 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5106 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5107 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5108 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5109 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5110 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5111 .accessfn
= aa64_cacheop_poc_access
},
5112 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5113 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5114 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5115 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5116 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5117 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5118 .accessfn
= aa64_cacheop_pou_access
},
5119 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5120 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5121 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5122 .accessfn
= aa64_cacheop_poc_access
},
5123 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5124 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5125 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5126 /* TLBI operations */
5127 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5128 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5129 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5130 .writefn
= tlbi_aa64_vmalle1is_write
},
5131 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5132 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5133 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5134 .writefn
= tlbi_aa64_vae1is_write
},
5135 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5136 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5137 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5138 .writefn
= tlbi_aa64_vmalle1is_write
},
5139 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5140 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5141 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5142 .writefn
= tlbi_aa64_vae1is_write
},
5143 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5144 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5145 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5146 .writefn
= tlbi_aa64_vae1is_write
},
5147 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5148 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5149 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5150 .writefn
= tlbi_aa64_vae1is_write
},
5151 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5152 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5153 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5154 .writefn
= tlbi_aa64_vmalle1_write
},
5155 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5156 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5157 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5158 .writefn
= tlbi_aa64_vae1_write
},
5159 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5160 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5161 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5162 .writefn
= tlbi_aa64_vmalle1_write
},
5163 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5164 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5165 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5166 .writefn
= tlbi_aa64_vae1_write
},
5167 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5168 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5169 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5170 .writefn
= tlbi_aa64_vae1_write
},
5171 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5172 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5173 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5174 .writefn
= tlbi_aa64_vae1_write
},
5175 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5176 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5177 .access
= PL2_W
, .type
= ARM_CP_NOP
},
5178 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5179 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5180 .access
= PL2_W
, .type
= ARM_CP_NOP
},
5181 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5182 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5183 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5184 .writefn
= tlbi_aa64_alle1is_write
},
5185 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5186 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5187 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5188 .writefn
= tlbi_aa64_alle1is_write
},
5189 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5190 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5191 .access
= PL2_W
, .type
= ARM_CP_NOP
},
5192 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5193 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5194 .access
= PL2_W
, .type
= ARM_CP_NOP
},
5195 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5196 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5197 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5198 .writefn
= tlbi_aa64_alle1_write
},
5199 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5200 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5201 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5202 .writefn
= tlbi_aa64_alle1is_write
},
5203 #ifndef CONFIG_USER_ONLY
5204 /* 64 bit address translation operations */
5205 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5206 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5207 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5208 .writefn
= ats_write64
},
5209 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5210 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5211 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5212 .writefn
= ats_write64
},
5213 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5214 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5215 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5216 .writefn
= ats_write64
},
5217 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5218 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5219 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5220 .writefn
= ats_write64
},
5221 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5222 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5223 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5224 .writefn
= ats_write64
},
5225 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5226 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5227 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5228 .writefn
= ats_write64
},
5229 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5230 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5231 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5232 .writefn
= ats_write64
},
5233 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5234 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5235 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5236 .writefn
= ats_write64
},
5237 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5238 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5239 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5240 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5241 .writefn
= ats_write64
},
5242 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5243 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5244 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5245 .writefn
= ats_write64
},
5246 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5247 .type
= ARM_CP_ALIAS
,
5248 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5249 .access
= PL1_RW
, .resetvalue
= 0,
5250 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5251 .writefn
= par_write
},
5253 /* TLB invalidate last level of translation table walk */
5254 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5255 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5256 .writefn
= tlbimva_is_write
},
5257 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5258 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5259 .writefn
= tlbimvaa_is_write
},
5260 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5261 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5262 .writefn
= tlbimva_write
},
5263 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5264 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5265 .writefn
= tlbimvaa_write
},
5266 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5267 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5268 .writefn
= tlbimva_hyp_write
},
5269 { .name
= "TLBIMVALHIS",
5270 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5271 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5272 .writefn
= tlbimva_hyp_is_write
},
5273 { .name
= "TLBIIPAS2",
5274 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5275 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5276 { .name
= "TLBIIPAS2IS",
5277 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5278 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5279 { .name
= "TLBIIPAS2L",
5280 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5281 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5282 { .name
= "TLBIIPAS2LIS",
5283 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5284 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5285 /* 32 bit cache operations */
5286 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5287 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5288 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5289 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5290 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5291 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5292 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5293 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5294 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5295 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5296 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5297 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5298 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5299 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5300 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5301 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5302 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5303 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5304 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5305 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5306 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5307 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5308 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5309 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5310 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5311 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5312 /* MMU Domain access control / MPU write buffer control */
5313 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5314 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5315 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5316 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5317 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5318 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5319 .type
= ARM_CP_ALIAS
,
5320 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5322 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5323 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5324 .type
= ARM_CP_ALIAS
,
5325 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5327 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5328 /* We rely on the access checks not allowing the guest to write to the
5329 * state field when SPSel indicates that it's being used as the stack
5332 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5333 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5334 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5335 .type
= ARM_CP_ALIAS
,
5336 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5337 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5338 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5339 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5340 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5341 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5342 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5343 .type
= ARM_CP_NO_RAW
,
5344 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5345 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5346 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5347 .type
= ARM_CP_ALIAS
,
5348 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
5349 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
5350 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5351 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5352 .access
= PL2_RW
, .resetvalue
= 0,
5353 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5354 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5355 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5356 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5357 .access
= PL2_RW
, .resetvalue
= 0,
5358 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5359 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5360 .type
= ARM_CP_ALIAS
,
5361 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5363 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5364 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5365 .type
= ARM_CP_ALIAS
,
5366 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5368 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5369 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5370 .type
= ARM_CP_ALIAS
,
5371 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5373 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5374 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5375 .type
= ARM_CP_ALIAS
,
5376 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5378 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5379 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5380 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5382 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5383 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5384 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5385 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5386 .writefn
= sdcr_write
,
5387 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5391 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
5392 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
5393 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5394 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5396 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
5397 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5398 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5400 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5401 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5402 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5403 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5404 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5405 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5407 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5408 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5409 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5410 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5411 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5412 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5413 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5415 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5416 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5417 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5418 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5419 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5420 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5422 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5423 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5424 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5426 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5427 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5428 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5430 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5431 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5432 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5434 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5435 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5436 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5437 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5438 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5439 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5440 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5441 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5442 .cp
= 15, .opc1
= 6, .crm
= 2,
5443 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5444 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
5445 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5446 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5447 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5448 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5449 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5450 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5451 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5452 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5453 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5454 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5455 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5456 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5457 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5458 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5460 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5461 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5462 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5463 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5464 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5465 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5466 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5467 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5469 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5470 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5471 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5472 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5473 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5475 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5476 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5477 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5478 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5479 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5480 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5481 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5482 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5483 .access
= PL2_RW
, .accessfn
= access_tda
,
5484 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5485 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5486 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5487 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5488 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5489 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5490 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5491 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5492 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5493 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5494 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5495 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5496 .type
= ARM_CP_CONST
,
5497 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5498 .access
= PL2_RW
, .resetvalue
= 0 },
5502 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5503 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
5504 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5505 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5507 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5511 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5513 ARMCPU
*cpu
= env_archcpu(env
);
5515 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5516 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5518 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5521 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5522 valid_mask
&= ~HCR_HCD
;
5523 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5524 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5525 * However, if we're using the SMC PSCI conduit then QEMU is
5526 * effectively acting like EL3 firmware and so the guest at
5527 * EL2 should retain the ability to prevent EL1 from being
5528 * able to make SMC calls into the ersatz firmware, so in
5529 * that case HCR.TSC should be read/write.
5531 valid_mask
&= ~HCR_TSC
;
5534 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5535 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5536 valid_mask
|= HCR_E2H
;
5538 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5539 valid_mask
|= HCR_TLOR
;
5541 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5542 valid_mask
|= HCR_API
| HCR_APK
;
5544 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5545 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5549 /* Clear RES0 bits. */
5550 value
&= valid_mask
;
5553 * These bits change the MMU setup:
5554 * HCR_VM enables stage 2 translation
5555 * HCR_PTW forbids certain page-table setups
5556 * HCR_DC disables stage1 and enables stage2 translation
5557 * HCR_DCT enables tagging on (disabled) stage1 translation
5559 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
)) {
5560 tlb_flush(CPU(cpu
));
5562 env
->cp15
.hcr_el2
= value
;
5565 * Updates to VI and VF require us to update the status of
5566 * virtual interrupts, which are the logical OR of these bits
5567 * and the state of the input lines from the GIC. (This requires
5568 * that we have the iothread lock, which is done by marking the
5569 * reginfo structs as ARM_CP_IO.)
5570 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5571 * possible for it to be taken immediately, because VIRQ and
5572 * VFIQ are masked unless running at EL0 or EL1, and HCR
5573 * can only be written at EL2.
5575 g_assert(qemu_mutex_iothread_locked());
5576 arm_cpu_update_virq(cpu
);
5577 arm_cpu_update_vfiq(cpu
);
5580 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5582 do_hcr_write(env
, value
, 0);
5585 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5588 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5589 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5590 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5593 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5596 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5597 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5598 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5602 * Return the effective value of HCR_EL2.
5603 * Bits that are not included here:
5604 * RW (read from SCR_EL3.RW as needed)
5606 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5608 uint64_t ret
= env
->cp15
.hcr_el2
;
5610 if (!arm_is_el2_enabled(env
)) {
5612 * "This register has no effect if EL2 is not enabled in the
5613 * current Security state". This is ARMv8.4-SecEL2 speak for
5614 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5616 * Prior to that, the language was "In an implementation that
5617 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5618 * as if this field is 0 for all purposes other than a direct
5619 * read or write access of HCR_EL2". With lots of enumeration
5620 * on a per-field basis. In current QEMU, this is condition
5621 * is arm_is_secure_below_el3.
5623 * Since the v8.4 language applies to the entire register, and
5624 * appears to be backward compatible, use that.
5630 * For a cpu that supports both aarch64 and aarch32, we can set bits
5631 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5632 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5634 if (!arm_el_is_aa64(env
, 2)) {
5635 uint64_t aa32_valid
;
5638 * These bits are up-to-date as of ARMv8.6.
5639 * For HCR, it's easiest to list just the 2 bits that are invalid.
5640 * For HCR2, list those that are valid.
5642 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5643 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5644 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5648 if (ret
& HCR_TGE
) {
5649 /* These bits are up-to-date as of ARMv8.6. */
5650 if (ret
& HCR_E2H
) {
5651 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5652 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5653 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5654 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5655 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5656 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5658 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5660 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5661 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5662 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5669 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5673 * For A-profile AArch32 EL3, if NSACR.CP10
5674 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5676 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5677 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5678 value
&= ~(0x3 << 10);
5679 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
5681 env
->cp15
.cptr_el
[2] = value
;
5684 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5687 * For A-profile AArch32 EL3, if NSACR.CP10
5688 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5690 uint64_t value
= env
->cp15
.cptr_el
[2];
5692 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5693 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5699 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5700 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5702 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5703 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5704 .writefn
= hcr_write
},
5705 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5706 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5707 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5708 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5709 .writefn
= hcr_writelow
},
5710 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5711 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5712 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5713 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5714 .type
= ARM_CP_ALIAS
,
5715 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5717 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5718 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5719 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5720 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5721 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5722 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5723 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5724 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5725 .type
= ARM_CP_ALIAS
,
5726 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5728 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5729 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5730 .type
= ARM_CP_ALIAS
,
5731 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5733 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5734 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5735 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5736 .access
= PL2_RW
, .writefn
= vbar_write
,
5737 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5739 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5740 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5741 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5742 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5743 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5744 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5745 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5746 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5747 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5748 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5749 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5750 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5752 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5753 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5754 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5755 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5756 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5757 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5758 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5760 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5761 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5762 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5763 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5765 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5766 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5767 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5769 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5770 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5771 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5773 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5774 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5775 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5776 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5777 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5778 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5779 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5780 .type
= ARM_CP_ALIAS
,
5781 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5782 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5783 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5784 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5786 /* no .writefn needed as this can't cause an ASID change;
5787 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5789 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5790 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5791 .cp
= 15, .opc1
= 6, .crm
= 2,
5792 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5793 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5794 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5795 .writefn
= vttbr_write
},
5796 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5797 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5798 .access
= PL2_RW
, .writefn
= vttbr_write
,
5799 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5800 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5801 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5802 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5803 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5804 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5805 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5806 .access
= PL2_RW
, .resetvalue
= 0,
5807 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5808 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5809 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5810 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5811 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5812 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5813 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5814 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5815 { .name
= "TLBIALLNSNH",
5816 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5817 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5818 .writefn
= tlbiall_nsnh_write
},
5819 { .name
= "TLBIALLNSNHIS",
5820 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5821 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5822 .writefn
= tlbiall_nsnh_is_write
},
5823 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5824 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5825 .writefn
= tlbiall_hyp_write
},
5826 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5827 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5828 .writefn
= tlbiall_hyp_is_write
},
5829 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5830 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5831 .writefn
= tlbimva_hyp_write
},
5832 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5833 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5834 .writefn
= tlbimva_hyp_is_write
},
5835 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5836 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5837 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5838 .writefn
= tlbi_aa64_alle2_write
},
5839 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5840 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5841 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5842 .writefn
= tlbi_aa64_vae2_write
},
5843 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5844 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5845 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5846 .writefn
= tlbi_aa64_vae2_write
},
5847 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5848 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5849 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5850 .writefn
= tlbi_aa64_alle2is_write
},
5851 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5852 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5853 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5854 .writefn
= tlbi_aa64_vae2is_write
},
5855 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5856 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5857 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5858 .writefn
= tlbi_aa64_vae2is_write
},
5859 #ifndef CONFIG_USER_ONLY
5860 /* Unlike the other EL2-related AT operations, these must
5861 * UNDEF from EL3 if EL2 is not implemented, which is why we
5862 * define them here rather than with the rest of the AT ops.
5864 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5865 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5866 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5867 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5868 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5869 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5870 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5871 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5872 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5873 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5874 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5875 * to behave as if SCR.NS was 1.
5877 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5879 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5880 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5882 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5883 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5884 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5885 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5886 * reset values as IMPDEF. We choose to reset to 3 to comply with
5887 * both ARMv7 and ARMv8.
5889 .access
= PL2_RW
, .resetvalue
= 3,
5890 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5891 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5892 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5893 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5894 .writefn
= gt_cntvoff_write
,
5895 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5896 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5897 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5898 .writefn
= gt_cntvoff_write
,
5899 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5900 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5901 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5902 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5903 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5904 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5905 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5906 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5907 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5908 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5909 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5910 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5911 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5912 .resetfn
= gt_hyp_timer_reset
,
5913 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5914 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5916 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5918 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5920 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5922 /* The only field of MDCR_EL2 that has a defined architectural reset value
5923 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
5925 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5926 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5927 .access
= PL2_RW
, .resetvalue
= PMCR_NUM_COUNTERS
,
5928 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5929 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5930 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5931 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5932 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5933 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5934 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5936 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5937 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5938 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5940 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5944 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5945 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5946 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5947 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5949 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5950 .writefn
= hcr_writehigh
},
5954 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5957 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5958 return CP_ACCESS_OK
;
5960 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5963 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5964 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5965 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5966 .access
= PL2_RW
, .accessfn
= sel2_access
,
5967 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5968 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5969 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5970 .access
= PL2_RW
, .accessfn
= sel2_access
,
5971 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5975 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5978 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5979 * At Secure EL1 it traps to EL3 or EL2.
5981 if (arm_current_el(env
) == 3) {
5982 return CP_ACCESS_OK
;
5984 if (arm_is_secure_below_el3(env
)) {
5985 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5986 return CP_ACCESS_TRAP_EL2
;
5988 return CP_ACCESS_TRAP_EL3
;
5990 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5992 return CP_ACCESS_OK
;
5994 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5997 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5998 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5999 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6000 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6001 .resetfn
= scr_reset
, .writefn
= scr_write
},
6002 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6003 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6004 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6005 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6006 .writefn
= scr_write
},
6007 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6008 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6009 .access
= PL3_RW
, .resetvalue
= 0,
6010 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6012 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6013 .access
= PL3_RW
, .resetvalue
= 0,
6014 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6015 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6016 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6017 .writefn
= vbar_write
, .resetvalue
= 0,
6018 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6019 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6020 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6021 .access
= PL3_RW
, .resetvalue
= 0,
6022 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6023 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6024 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6026 /* no .writefn needed as this can't cause an ASID change;
6027 * we must provide a .raw_writefn and .resetfn because we handle
6028 * reset and migration for the AArch32 TTBCR(S), which might be
6029 * using mask and base_mask.
6031 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
6032 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6033 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6034 .type
= ARM_CP_ALIAS
,
6035 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6037 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6038 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6039 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6040 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6041 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6042 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6043 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6044 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6045 .type
= ARM_CP_ALIAS
,
6046 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6048 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6049 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6050 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6051 .access
= PL3_RW
, .writefn
= vbar_write
,
6052 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6054 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6055 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6056 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6057 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6058 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6059 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6060 .access
= PL3_RW
, .resetvalue
= 0,
6061 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6062 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6063 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6064 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6066 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6067 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6068 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6070 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6071 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6072 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6074 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6075 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6076 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6077 .writefn
= tlbi_aa64_alle3is_write
},
6078 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6079 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6080 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6081 .writefn
= tlbi_aa64_vae3is_write
},
6082 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6083 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6084 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6085 .writefn
= tlbi_aa64_vae3is_write
},
6086 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6087 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6088 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6089 .writefn
= tlbi_aa64_alle3_write
},
6090 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6091 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6092 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6093 .writefn
= tlbi_aa64_vae3_write
},
6094 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6095 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6096 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6097 .writefn
= tlbi_aa64_vae3_write
},
6101 #ifndef CONFIG_USER_ONLY
6102 /* Test if system register redirection is to occur in the current state. */
6103 static bool redirect_for_e2h(CPUARMState
*env
)
6105 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6108 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6112 if (redirect_for_e2h(env
)) {
6113 /* Switch to the saved EL2 version of the register. */
6115 readfn
= ri
->readfn
;
6117 readfn
= ri
->orig_readfn
;
6119 if (readfn
== NULL
) {
6122 return readfn(env
, ri
);
6125 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6130 if (redirect_for_e2h(env
)) {
6131 /* Switch to the saved EL2 version of the register. */
6133 writefn
= ri
->writefn
;
6135 writefn
= ri
->orig_writefn
;
6137 if (writefn
== NULL
) {
6138 writefn
= raw_write
;
6140 writefn(env
, ri
, value
);
6143 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6146 uint32_t src_key
, dst_key
, new_key
;
6147 const char *src_name
, *dst_name
, *new_name
;
6148 bool (*feature
)(const ARMISARegisters
*id
);
6151 #define K(op0, op1, crn, crm, op2) \
6152 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6154 static const struct E2HAlias aliases
[] = {
6155 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6156 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6157 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6158 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6159 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6160 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6161 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6162 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6163 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6164 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6165 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6166 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6167 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6168 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6169 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6170 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6171 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6172 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6173 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6174 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6175 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6176 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6177 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6178 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6179 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6180 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6181 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6182 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6183 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6184 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6185 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6186 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6189 * Note that redirection of ZCR is mentioned in the description
6190 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6191 * not in the summary table.
6193 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6194 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6196 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6197 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6199 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6200 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6206 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6207 const struct E2HAlias
*a
= &aliases
[i
];
6208 ARMCPRegInfo
*src_reg
, *dst_reg
;
6210 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6214 src_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->src_key
);
6215 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->dst_key
);
6216 g_assert(src_reg
!= NULL
);
6217 g_assert(dst_reg
!= NULL
);
6219 /* Cross-compare names to detect typos in the keys. */
6220 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6221 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6223 /* None of the core system registers use opaque; we will. */
6224 g_assert(src_reg
->opaque
== NULL
);
6226 /* Create alias before redirection so we dup the right data. */
6228 ARMCPRegInfo
*new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6229 uint32_t *new_key
= g_memdup(&a
->new_key
, sizeof(uint32_t));
6232 new_reg
->name
= a
->new_name
;
6233 new_reg
->type
|= ARM_CP_ALIAS
;
6234 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6235 new_reg
->access
&= PL2_RW
| PL3_RW
;
6237 ok
= g_hash_table_insert(cpu
->cp_regs
, new_key
, new_reg
);
6241 src_reg
->opaque
= dst_reg
;
6242 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6243 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6244 if (!src_reg
->raw_readfn
) {
6245 src_reg
->raw_readfn
= raw_read
;
6247 if (!src_reg
->raw_writefn
) {
6248 src_reg
->raw_writefn
= raw_write
;
6250 src_reg
->readfn
= el2_e2h_read
;
6251 src_reg
->writefn
= el2_e2h_write
;
6256 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6259 int cur_el
= arm_current_el(env
);
6262 uint64_t hcr
= arm_hcr_el2_eff(env
);
6265 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6266 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6267 return CP_ACCESS_TRAP_EL2
;
6270 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6271 return CP_ACCESS_TRAP
;
6273 if (hcr
& HCR_TID2
) {
6274 return CP_ACCESS_TRAP_EL2
;
6277 } else if (hcr
& HCR_TID2
) {
6278 return CP_ACCESS_TRAP_EL2
;
6282 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6283 return CP_ACCESS_TRAP_EL2
;
6286 return CP_ACCESS_OK
;
6289 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6292 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
6293 * read via a bit in OSLSR_EL1.
6297 if (ri
->state
== ARM_CP_STATE_AA32
) {
6298 oslock
= (value
== 0xC5ACCE55);
6303 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
6306 static const ARMCPRegInfo debug_cp_reginfo
[] = {
6307 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
6308 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
6309 * unlike DBGDRAR it is never accessible from EL0.
6310 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6313 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
6314 .access
= PL0_R
, .accessfn
= access_tdra
,
6315 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6316 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
6317 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6318 .access
= PL1_R
, .accessfn
= access_tdra
,
6319 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6320 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
6321 .access
= PL0_R
, .accessfn
= access_tdra
,
6322 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6323 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6324 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
6325 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6326 .access
= PL1_RW
, .accessfn
= access_tda
,
6327 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
6329 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
6330 * We don't implement the configurable EL0 access.
6332 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
6333 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6334 .type
= ARM_CP_ALIAS
,
6335 .access
= PL1_R
, .accessfn
= access_tda
,
6336 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
6337 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
6338 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
6339 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6340 .accessfn
= access_tdosa
,
6341 .writefn
= oslar_write
},
6342 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
6343 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
6344 .access
= PL1_R
, .resetvalue
= 10,
6345 .accessfn
= access_tdosa
,
6346 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
6347 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6348 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6349 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
6350 .access
= PL1_RW
, .accessfn
= access_tdosa
,
6351 .type
= ARM_CP_NOP
},
6352 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6353 * implement vector catch debug events yet.
6356 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6357 .access
= PL1_RW
, .accessfn
= access_tda
,
6358 .type
= ARM_CP_NOP
},
6359 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6360 * to save and restore a 32-bit guest's DBGVCR)
6362 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
6363 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
6364 .access
= PL2_RW
, .accessfn
= access_tda
,
6365 .type
= ARM_CP_NOP
},
6366 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6367 * Channel but Linux may try to access this register. The 32-bit
6368 * alias is DBGDCCINT.
6370 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
6371 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6372 .access
= PL1_RW
, .accessfn
= access_tda
,
6373 .type
= ARM_CP_NOP
},
6377 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
6378 /* 64 bit access versions of the (dummy) debug registers */
6379 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
6380 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6381 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
6382 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6386 /* Return the exception level to which exceptions should be taken
6387 * via SVEAccessTrap. If an exception should be routed through
6388 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6389 * take care of raising that exception.
6390 * C.f. the ARM pseudocode function CheckSVEEnabled.
6392 int sve_exception_el(CPUARMState
*env
, int el
)
6394 #ifndef CONFIG_USER_ONLY
6395 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
6397 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6398 bool disabled
= false;
6400 /* The CPACR.ZEN controls traps to EL1:
6401 * 0, 2 : trap EL0 and EL1 accesses
6402 * 1 : trap only EL0 accesses
6403 * 3 : trap no accesses
6405 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
6407 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
6412 return hcr_el2
& HCR_TGE
? 2 : 1;
6415 /* Check CPACR.FPEN. */
6416 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
6418 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
6426 /* CPTR_EL2. Since TZ and TFP are positive,
6427 * they will be zero when EL2 is not present.
6429 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6430 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
6433 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
6438 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6439 if (arm_feature(env
, ARM_FEATURE_EL3
)
6440 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
6447 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
6451 end_len
= start_len
&= 0xf;
6452 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
6453 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
6454 assert(end_len
< start_len
);
6460 * Given that SVE is enabled, return the vector length for EL.
6462 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
6464 ARMCPU
*cpu
= env_archcpu(env
);
6465 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
6468 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
6470 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6471 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
6473 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6474 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
6477 return sve_zcr_get_valid_len(cpu
, zcr_len
);
6480 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6483 int cur_el
= arm_current_el(env
);
6484 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
6487 /* Bits other than [3:0] are RAZ/WI. */
6488 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6489 raw_write(env
, ri
, value
& 0xf);
6492 * Because we arrived here, we know both FP and SVE are enabled;
6493 * otherwise we would have trapped access to the ZCR_ELn register.
6495 new_len
= sve_zcr_len_for_el(env
, cur_el
);
6496 if (new_len
< old_len
) {
6497 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6501 static const ARMCPRegInfo zcr_el1_reginfo
= {
6502 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6503 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6504 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6505 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6506 .writefn
= zcr_write
, .raw_writefn
= raw_write
6509 static const ARMCPRegInfo zcr_el2_reginfo
= {
6510 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6511 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6512 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6513 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6514 .writefn
= zcr_write
, .raw_writefn
= raw_write
6517 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
6518 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6519 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6520 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6521 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
6524 static const ARMCPRegInfo zcr_el3_reginfo
= {
6525 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6526 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6527 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6528 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6529 .writefn
= zcr_write
, .raw_writefn
= raw_write
6532 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6534 CPUARMState
*env
= &cpu
->env
;
6536 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6537 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6539 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6541 if (env
->cpu_watchpoint
[n
]) {
6542 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6543 env
->cpu_watchpoint
[n
] = NULL
;
6546 if (!extract64(wcr
, 0, 1)) {
6547 /* E bit clear : watchpoint disabled */
6551 switch (extract64(wcr
, 3, 2)) {
6553 /* LSC 00 is reserved and must behave as if the wp is disabled */
6556 flags
|= BP_MEM_READ
;
6559 flags
|= BP_MEM_WRITE
;
6562 flags
|= BP_MEM_ACCESS
;
6566 /* Attempts to use both MASK and BAS fields simultaneously are
6567 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6568 * thus generating a watchpoint for every byte in the masked region.
6570 mask
= extract64(wcr
, 24, 4);
6571 if (mask
== 1 || mask
== 2) {
6572 /* Reserved values of MASK; we must act as if the mask value was
6573 * some non-reserved value, or as if the watchpoint were disabled.
6574 * We choose the latter.
6578 /* Watchpoint covers an aligned area up to 2GB in size */
6580 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6581 * whether the watchpoint fires when the unmasked bits match; we opt
6582 * to generate the exceptions.
6586 /* Watchpoint covers bytes defined by the byte address select bits */
6587 int bas
= extract64(wcr
, 5, 8);
6590 if (extract64(wvr
, 2, 1)) {
6591 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6592 * ignored, and BAS[3:0] define which bytes to watch.
6598 /* This must act as if the watchpoint is disabled */
6602 /* The BAS bits are supposed to be programmed to indicate a contiguous
6603 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6604 * we fire for each byte in the word/doubleword addressed by the WVR.
6605 * We choose to ignore any non-zero bits after the first range of 1s.
6607 basstart
= ctz32(bas
);
6608 len
= cto32(bas
>> basstart
);
6612 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6613 &env
->cpu_watchpoint
[n
]);
6616 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6619 CPUARMState
*env
= &cpu
->env
;
6621 /* Completely clear out existing QEMU watchpoints and our array, to
6622 * avoid possible stale entries following migration load.
6624 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6625 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6627 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6628 hw_watchpoint_update(cpu
, i
);
6632 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6635 ARMCPU
*cpu
= env_archcpu(env
);
6638 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6639 * register reads and behaves as if values written are sign extended.
6640 * Bits [1:0] are RES0.
6642 value
= sextract64(value
, 0, 49) & ~3ULL;
6644 raw_write(env
, ri
, value
);
6645 hw_watchpoint_update(cpu
, i
);
6648 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6651 ARMCPU
*cpu
= env_archcpu(env
);
6654 raw_write(env
, ri
, value
);
6655 hw_watchpoint_update(cpu
, i
);
6658 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6660 CPUARMState
*env
= &cpu
->env
;
6661 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6662 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6667 if (env
->cpu_breakpoint
[n
]) {
6668 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6669 env
->cpu_breakpoint
[n
] = NULL
;
6672 if (!extract64(bcr
, 0, 1)) {
6673 /* E bit clear : watchpoint disabled */
6677 bt
= extract64(bcr
, 20, 4);
6680 case 4: /* unlinked address mismatch (reserved if AArch64) */
6681 case 5: /* linked address mismatch (reserved if AArch64) */
6682 qemu_log_mask(LOG_UNIMP
,
6683 "arm: address mismatch breakpoint types not implemented\n");
6685 case 0: /* unlinked address match */
6686 case 1: /* linked address match */
6688 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6689 * we behave as if the register was sign extended. Bits [1:0] are
6690 * RES0. The BAS field is used to allow setting breakpoints on 16
6691 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6692 * a bp will fire if the addresses covered by the bp and the addresses
6693 * covered by the insn overlap but the insn doesn't start at the
6694 * start of the bp address range. We choose to require the insn and
6695 * the bp to have the same address. The constraints on writing to
6696 * BAS enforced in dbgbcr_write mean we have only four cases:
6697 * 0b0000 => no breakpoint
6698 * 0b0011 => breakpoint on addr
6699 * 0b1100 => breakpoint on addr + 2
6700 * 0b1111 => breakpoint on addr
6701 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6703 int bas
= extract64(bcr
, 5, 4);
6704 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
6713 case 2: /* unlinked context ID match */
6714 case 8: /* unlinked VMID match (reserved if no EL2) */
6715 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6716 qemu_log_mask(LOG_UNIMP
,
6717 "arm: unlinked context breakpoint types not implemented\n");
6719 case 9: /* linked VMID match (reserved if no EL2) */
6720 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6721 case 3: /* linked context ID match */
6723 /* We must generate no events for Linked context matches (unless
6724 * they are linked to by some other bp/wp, which is handled in
6725 * updates for the linking bp/wp). We choose to also generate no events
6726 * for reserved values.
6731 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6734 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6737 CPUARMState
*env
= &cpu
->env
;
6739 /* Completely clear out existing QEMU breakpoints and our array, to
6740 * avoid possible stale entries following migration load.
6742 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6743 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6745 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6746 hw_breakpoint_update(cpu
, i
);
6750 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6753 ARMCPU
*cpu
= env_archcpu(env
);
6756 raw_write(env
, ri
, value
);
6757 hw_breakpoint_update(cpu
, i
);
6760 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6763 ARMCPU
*cpu
= env_archcpu(env
);
6766 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6769 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6770 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6772 raw_write(env
, ri
, value
);
6773 hw_breakpoint_update(cpu
, i
);
6776 static void define_debug_regs(ARMCPU
*cpu
)
6778 /* Define v7 and v8 architectural debug registers.
6779 * These are just dummy implementations for now.
6782 int wrps
, brps
, ctx_cmps
;
6785 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
6786 * use AArch32. Given that bit 15 is RES1, if the value is 0 then
6787 * the register must not exist for this cpu.
6789 if (cpu
->isar
.dbgdidr
!= 0) {
6790 ARMCPRegInfo dbgdidr
= {
6791 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0,
6792 .opc1
= 0, .opc2
= 0,
6793 .access
= PL0_R
, .accessfn
= access_tda
,
6794 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6796 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6799 /* Note that all these register fields hold "number of Xs minus 1". */
6800 brps
= arm_num_brps(cpu
);
6801 wrps
= arm_num_wrps(cpu
);
6802 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6804 assert(ctx_cmps
<= brps
);
6806 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6808 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6809 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6812 for (i
= 0; i
< brps
; i
++) {
6813 ARMCPRegInfo dbgregs
[] = {
6814 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
6815 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6816 .access
= PL1_RW
, .accessfn
= access_tda
,
6817 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6818 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6820 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
6821 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6822 .access
= PL1_RW
, .accessfn
= access_tda
,
6823 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6824 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6828 define_arm_cp_regs(cpu
, dbgregs
);
6831 for (i
= 0; i
< wrps
; i
++) {
6832 ARMCPRegInfo dbgregs
[] = {
6833 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
6834 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6835 .access
= PL1_RW
, .accessfn
= access_tda
,
6836 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6837 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6839 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
6840 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6841 .access
= PL1_RW
, .accessfn
= access_tda
,
6842 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6843 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6847 define_arm_cp_regs(cpu
, dbgregs
);
6851 static void define_pmu_regs(ARMCPU
*cpu
)
6854 * v7 performance monitor control register: same implementor
6855 * field as main ID register, and we implement four counters in
6856 * addition to the cycle count register.
6858 unsigned int i
, pmcrn
= PMCR_NUM_COUNTERS
;
6859 ARMCPRegInfo pmcr
= {
6860 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6862 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6863 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6864 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6865 .raw_writefn
= raw_write
,
6867 ARMCPRegInfo pmcr64
= {
6868 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6869 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6870 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6872 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6873 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
) |
6875 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6877 define_one_arm_cp_reg(cpu
, &pmcr
);
6878 define_one_arm_cp_reg(cpu
, &pmcr64
);
6879 for (i
= 0; i
< pmcrn
; i
++) {
6880 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6881 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6882 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6883 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6884 ARMCPRegInfo pmev_regs
[] = {
6885 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6886 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6887 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6888 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6889 .accessfn
= pmreg_access
},
6890 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6891 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6892 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6894 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6895 .raw_readfn
= pmevcntr_rawread
,
6896 .raw_writefn
= pmevcntr_rawwrite
},
6897 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6898 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6899 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6900 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6901 .accessfn
= pmreg_access
},
6902 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6903 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6904 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6906 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6907 .raw_writefn
= pmevtyper_rawwrite
},
6910 define_arm_cp_regs(cpu
, pmev_regs
);
6911 g_free(pmevcntr_name
);
6912 g_free(pmevcntr_el0_name
);
6913 g_free(pmevtyper_name
);
6914 g_free(pmevtyper_el0_name
);
6916 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6917 ARMCPRegInfo v81_pmu_regs
[] = {
6918 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6919 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6920 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6921 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6922 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6923 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6924 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6925 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6928 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6930 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6931 static const ARMCPRegInfo v84_pmmir
= {
6932 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6933 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6934 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6937 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6941 /* We don't know until after realize whether there's a GICv3
6942 * attached, and that is what registers the gicv3 sysregs.
6943 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6946 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6948 ARMCPU
*cpu
= env_archcpu(env
);
6949 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6951 if (env
->gicv3state
) {
6957 #ifndef CONFIG_USER_ONLY
6958 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6960 ARMCPU
*cpu
= env_archcpu(env
);
6961 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6963 if (env
->gicv3state
) {
6970 /* Shared logic between LORID and the rest of the LOR* registers.
6971 * Secure state exclusion has already been dealt with.
6973 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6974 const ARMCPRegInfo
*ri
, bool isread
)
6976 int el
= arm_current_el(env
);
6978 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6979 return CP_ACCESS_TRAP_EL2
;
6981 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6982 return CP_ACCESS_TRAP_EL3
;
6984 return CP_ACCESS_OK
;
6987 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6988 const ARMCPRegInfo
*ri
, bool isread
)
6990 if (arm_is_secure_below_el3(env
)) {
6991 /* Access denied in secure mode. */
6992 return CP_ACCESS_TRAP
;
6994 return access_lor_ns(env
, ri
, isread
);
6998 * A trivial implementation of ARMv8.1-LOR leaves all of these
6999 * registers fixed at 0, which indicates that there are zero
7000 * supported Limited Ordering regions.
7002 static const ARMCPRegInfo lor_reginfo
[] = {
7003 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7004 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7005 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7006 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7007 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7008 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7009 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7010 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7011 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7012 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7013 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7014 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7015 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7016 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7017 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7018 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7019 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7020 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7021 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7022 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7026 #ifdef TARGET_AARCH64
7027 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7030 int el
= arm_current_el(env
);
7033 arm_feature(env
, ARM_FEATURE_EL2
) &&
7034 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7035 return CP_ACCESS_TRAP_EL2
;
7038 arm_feature(env
, ARM_FEATURE_EL3
) &&
7039 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7040 return CP_ACCESS_TRAP_EL3
;
7042 return CP_ACCESS_OK
;
7045 static const ARMCPRegInfo pauth_reginfo
[] = {
7046 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7047 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7048 .access
= PL1_RW
, .accessfn
= access_pauth
,
7049 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7050 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7051 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7052 .access
= PL1_RW
, .accessfn
= access_pauth
,
7053 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7054 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7055 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7056 .access
= PL1_RW
, .accessfn
= access_pauth
,
7057 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7058 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7059 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7060 .access
= PL1_RW
, .accessfn
= access_pauth
,
7061 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7062 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7063 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7064 .access
= PL1_RW
, .accessfn
= access_pauth
,
7065 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7066 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7067 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7068 .access
= PL1_RW
, .accessfn
= access_pauth
,
7069 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7070 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7071 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7072 .access
= PL1_RW
, .accessfn
= access_pauth
,
7073 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7074 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7075 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7076 .access
= PL1_RW
, .accessfn
= access_pauth
,
7077 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7078 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7079 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7080 .access
= PL1_RW
, .accessfn
= access_pauth
,
7081 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7082 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7083 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7084 .access
= PL1_RW
, .accessfn
= access_pauth
,
7085 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7089 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7090 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7091 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7092 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7093 .writefn
= tlbi_aa64_rvae1is_write
},
7094 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7095 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7096 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7097 .writefn
= tlbi_aa64_rvae1is_write
},
7098 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7099 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7100 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7101 .writefn
= tlbi_aa64_rvae1is_write
},
7102 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7103 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7104 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7105 .writefn
= tlbi_aa64_rvae1is_write
},
7106 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7107 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7108 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7109 .writefn
= tlbi_aa64_rvae1is_write
},
7110 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7111 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7112 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7113 .writefn
= tlbi_aa64_rvae1is_write
},
7114 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7115 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7116 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7117 .writefn
= tlbi_aa64_rvae1is_write
},
7118 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7119 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7120 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7121 .writefn
= tlbi_aa64_rvae1is_write
},
7122 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7123 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7124 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7125 .writefn
= tlbi_aa64_rvae1_write
},
7126 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7127 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7128 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7129 .writefn
= tlbi_aa64_rvae1_write
},
7130 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7131 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7132 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7133 .writefn
= tlbi_aa64_rvae1_write
},
7134 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7135 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7136 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7137 .writefn
= tlbi_aa64_rvae1_write
},
7138 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7139 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7140 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7141 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7142 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7143 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7144 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7145 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7146 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7147 .writefn
= tlbi_aa64_rvae2is_write
},
7148 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7149 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7150 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7151 .writefn
= tlbi_aa64_rvae2is_write
},
7152 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7153 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7154 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7155 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7156 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7157 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7158 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7159 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7160 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7161 .writefn
= tlbi_aa64_rvae2is_write
},
7162 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7163 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7164 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7165 .writefn
= tlbi_aa64_rvae2is_write
},
7166 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7167 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7168 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7169 .writefn
= tlbi_aa64_rvae2_write
},
7170 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7171 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7172 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7173 .writefn
= tlbi_aa64_rvae2_write
},
7174 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7175 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7176 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7177 .writefn
= tlbi_aa64_rvae3is_write
},
7178 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7179 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7180 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7181 .writefn
= tlbi_aa64_rvae3is_write
},
7182 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7183 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7184 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7185 .writefn
= tlbi_aa64_rvae3is_write
},
7186 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7187 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7188 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7189 .writefn
= tlbi_aa64_rvae3is_write
},
7190 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7191 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7192 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7193 .writefn
= tlbi_aa64_rvae3_write
},
7194 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7195 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7196 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7197 .writefn
= tlbi_aa64_rvae3_write
},
7201 static const ARMCPRegInfo tlbios_reginfo
[] = {
7202 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7203 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7204 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7205 .writefn
= tlbi_aa64_vmalle1is_write
},
7206 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7207 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7208 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7209 .writefn
= tlbi_aa64_vmalle1is_write
},
7210 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7211 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7212 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7213 .writefn
= tlbi_aa64_alle2is_write
},
7214 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7215 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7216 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7217 .writefn
= tlbi_aa64_alle1is_write
},
7218 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7219 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7220 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7221 .writefn
= tlbi_aa64_alle1is_write
},
7222 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7223 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7224 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7225 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7226 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7227 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7228 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7229 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7230 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7231 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7232 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7233 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7234 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7235 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7236 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7237 .writefn
= tlbi_aa64_alle3is_write
},
7241 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7246 /* Success sets NZCV = 0000. */
7247 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7249 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7251 * ??? Failed, for unknown reasons in the crypto subsystem.
7252 * The best we can do is log the reason and return the
7253 * timed-out indication to the guest. There is no reason
7254 * we know to expect this failure to be transitory, so the
7255 * guest may well hang retrying the operation.
7257 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7258 ri
->name
, error_get_pretty(err
));
7261 env
->ZF
= 0; /* NZCF = 0100 */
7267 /* We do not support re-seeding, so the two registers operate the same. */
7268 static const ARMCPRegInfo rndr_reginfo
[] = {
7269 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7270 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7271 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7272 .access
= PL0_R
, .readfn
= rndr_readfn
},
7273 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7274 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7275 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7276 .access
= PL0_R
, .readfn
= rndr_readfn
},
7280 #ifndef CONFIG_USER_ONLY
7281 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7284 ARMCPU
*cpu
= env_archcpu(env
);
7285 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7286 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7287 uint64_t vaddr_in
= (uint64_t) value
;
7288 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7290 int mem_idx
= cpu_mmu_index(env
, false);
7292 /* This won't be crossing page boundaries */
7293 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7299 /* RCU lock is already being held */
7300 mr
= memory_region_from_host(haddr
, &offset
);
7303 memory_region_writeback(mr
, offset
, dline_size
);
7308 static const ARMCPRegInfo dcpop_reg
[] = {
7309 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7310 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7311 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7312 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7316 static const ARMCPRegInfo dcpodp_reg
[] = {
7317 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7318 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7319 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7320 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7323 #endif /*CONFIG_USER_ONLY*/
7325 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7328 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7329 return CP_ACCESS_TRAP_EL2
;
7332 return CP_ACCESS_OK
;
7335 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7338 int el
= arm_current_el(env
);
7340 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
7341 uint64_t hcr
= arm_hcr_el2_eff(env
);
7342 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7343 return CP_ACCESS_TRAP_EL2
;
7347 arm_feature(env
, ARM_FEATURE_EL3
) &&
7348 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7349 return CP_ACCESS_TRAP_EL3
;
7351 return CP_ACCESS_OK
;
7354 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7356 return env
->pstate
& PSTATE_TCO
;
7359 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7361 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7364 static const ARMCPRegInfo mte_reginfo
[] = {
7365 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7366 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7367 .access
= PL1_RW
, .accessfn
= access_mte
,
7368 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7369 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7370 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7371 .access
= PL1_RW
, .accessfn
= access_mte
,
7372 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7373 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7374 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7375 .access
= PL2_RW
, .accessfn
= access_mte
,
7376 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7377 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7378 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7380 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7381 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7382 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7383 .access
= PL1_RW
, .accessfn
= access_mte
,
7384 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7385 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7386 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7387 .access
= PL1_RW
, .accessfn
= access_mte
,
7388 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7389 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7390 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7391 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7392 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7393 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7394 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7395 .type
= ARM_CP_NO_RAW
,
7396 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7397 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7398 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7399 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7400 .accessfn
= aa64_cacheop_poc_access
},
7401 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7402 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7403 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7404 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7405 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7406 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7407 .accessfn
= aa64_cacheop_poc_access
},
7408 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7409 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7410 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7411 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7412 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7413 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7414 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7415 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7416 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7417 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7418 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7419 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7420 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7421 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7422 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7426 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7427 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7428 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7429 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7433 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7434 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7435 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7436 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7437 .accessfn
= aa64_cacheop_poc_access
},
7438 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7439 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7440 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7441 .accessfn
= aa64_cacheop_poc_access
},
7442 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7443 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7444 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7445 .accessfn
= aa64_cacheop_poc_access
},
7446 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7447 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7448 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7449 .accessfn
= aa64_cacheop_poc_access
},
7450 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7451 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7452 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7453 .accessfn
= aa64_cacheop_poc_access
},
7454 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7455 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7456 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7457 .accessfn
= aa64_cacheop_poc_access
},
7458 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7459 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7460 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7461 .accessfn
= aa64_cacheop_poc_access
},
7462 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7463 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7464 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7465 .accessfn
= aa64_cacheop_poc_access
},
7466 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7467 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7468 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7469 #ifndef CONFIG_USER_ONLY
7470 /* Avoid overhead of an access check that always passes in user-mode */
7471 .accessfn
= aa64_zva_access
,
7474 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7475 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7476 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7477 #ifndef CONFIG_USER_ONLY
7478 /* Avoid overhead of an access check that always passes in user-mode */
7479 .accessfn
= aa64_zva_access
,
7487 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7490 int el
= arm_current_el(env
);
7493 uint64_t sctlr
= arm_sctlr(env
, el
);
7494 if (!(sctlr
& SCTLR_EnRCTX
)) {
7495 return CP_ACCESS_TRAP
;
7497 } else if (el
== 1) {
7498 uint64_t hcr
= arm_hcr_el2_eff(env
);
7500 return CP_ACCESS_TRAP_EL2
;
7503 return CP_ACCESS_OK
;
7506 static const ARMCPRegInfo predinv_reginfo
[] = {
7507 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7508 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7509 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7510 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7511 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7512 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7513 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7514 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7515 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7517 * Note the AArch32 opcodes have a different OPC1.
7519 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7520 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7521 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7522 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7523 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7524 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7525 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7526 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7527 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7531 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7533 /* Read the high 32 bits of the current CCSIDR */
7534 return extract64(ccsidr_read(env
, ri
), 32, 32);
7537 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7538 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7539 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7541 .accessfn
= access_aa64_tid2
,
7542 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7546 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7549 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7550 return CP_ACCESS_TRAP_EL2
;
7553 return CP_ACCESS_OK
;
7556 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7559 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7560 return access_aa64_tid3(env
, ri
, isread
);
7563 return CP_ACCESS_OK
;
7566 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7569 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7570 return CP_ACCESS_TRAP_EL2
;
7573 return CP_ACCESS_OK
;
7576 static const ARMCPRegInfo jazelle_regs
[] = {
7578 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7579 .access
= PL1_R
, .accessfn
= access_jazelle
,
7580 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7582 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7583 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7585 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7586 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7590 static const ARMCPRegInfo vhe_reginfo
[] = {
7591 { .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7592 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7594 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2]) },
7595 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7596 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7597 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7598 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7599 #ifndef CONFIG_USER_ONLY
7600 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7601 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7603 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7604 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7605 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7606 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7607 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7608 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7609 .resetfn
= gt_hv_timer_reset
,
7610 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7611 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7613 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7615 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7616 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7617 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7618 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7619 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7620 .access
= PL2_RW
, .accessfn
= e2h_access
,
7621 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7622 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7623 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7624 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7625 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7626 .access
= PL2_RW
, .accessfn
= e2h_access
,
7627 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7628 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7629 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7630 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7631 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7632 .access
= PL2_RW
, .accessfn
= e2h_access
,
7633 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7634 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7635 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7636 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7637 .access
= PL2_RW
, .accessfn
= e2h_access
,
7638 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7639 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7640 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7641 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7642 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7643 .access
= PL2_RW
, .accessfn
= e2h_access
,
7644 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7645 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7646 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7647 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7648 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7649 .access
= PL2_RW
, .accessfn
= e2h_access
,
7650 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7655 #ifndef CONFIG_USER_ONLY
7656 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7657 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7658 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7659 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7660 .writefn
= ats_write64
},
7661 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7662 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7663 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7664 .writefn
= ats_write64
},
7668 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7669 { .name
= "ATS1CPRP",
7670 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7671 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7672 .writefn
= ats_write
},
7673 { .name
= "ATS1CPWP",
7674 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7675 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7676 .writefn
= ats_write
},
7682 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7683 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7684 * is non-zero, which is never for ARMv7, optionally in ARMv8
7685 * and mandatorily for ARMv8.2 and up.
7686 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7687 * implementation is RAZ/WI we can ignore this detail, as we
7690 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7691 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7692 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7693 .access
= PL1_RW
, .accessfn
= access_tacr
,
7694 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7695 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7696 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7697 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7702 void register_cp_regs_for_features(ARMCPU
*cpu
)
7704 /* Register all the coprocessor registers based on feature bits */
7705 CPUARMState
*env
= &cpu
->env
;
7706 if (arm_feature(env
, ARM_FEATURE_M
)) {
7707 /* M profile has no coprocessor registers */
7711 define_arm_cp_regs(cpu
, cp_reginfo
);
7712 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7713 /* Must go early as it is full of wildcards that may be
7714 * overridden by later definitions.
7716 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7719 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7720 /* The ID registers all have impdef reset values */
7721 ARMCPRegInfo v6_idregs
[] = {
7722 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7723 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7724 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7725 .accessfn
= access_aa32_tid3
,
7726 .resetvalue
= cpu
->isar
.id_pfr0
},
7727 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7728 * the value of the GIC field until after we define these regs.
7730 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7731 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7732 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7733 .accessfn
= access_aa32_tid3
,
7734 .readfn
= id_pfr1_read
,
7735 .writefn
= arm_cp_write_ignore
},
7736 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7737 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7738 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7739 .accessfn
= access_aa32_tid3
,
7740 .resetvalue
= cpu
->isar
.id_dfr0
},
7741 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7742 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7743 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7744 .accessfn
= access_aa32_tid3
,
7745 .resetvalue
= cpu
->id_afr0
},
7746 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7747 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7748 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7749 .accessfn
= access_aa32_tid3
,
7750 .resetvalue
= cpu
->isar
.id_mmfr0
},
7751 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7752 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7753 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7754 .accessfn
= access_aa32_tid3
,
7755 .resetvalue
= cpu
->isar
.id_mmfr1
},
7756 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7757 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7758 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7759 .accessfn
= access_aa32_tid3
,
7760 .resetvalue
= cpu
->isar
.id_mmfr2
},
7761 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7762 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7763 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7764 .accessfn
= access_aa32_tid3
,
7765 .resetvalue
= cpu
->isar
.id_mmfr3
},
7766 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7767 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7768 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7769 .accessfn
= access_aa32_tid3
,
7770 .resetvalue
= cpu
->isar
.id_isar0
},
7771 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7772 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7773 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7774 .accessfn
= access_aa32_tid3
,
7775 .resetvalue
= cpu
->isar
.id_isar1
},
7776 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7777 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7778 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7779 .accessfn
= access_aa32_tid3
,
7780 .resetvalue
= cpu
->isar
.id_isar2
},
7781 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7782 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7783 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7784 .accessfn
= access_aa32_tid3
,
7785 .resetvalue
= cpu
->isar
.id_isar3
},
7786 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7787 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7788 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7789 .accessfn
= access_aa32_tid3
,
7790 .resetvalue
= cpu
->isar
.id_isar4
},
7791 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7792 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7793 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7794 .accessfn
= access_aa32_tid3
,
7795 .resetvalue
= cpu
->isar
.id_isar5
},
7796 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7797 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7798 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7799 .accessfn
= access_aa32_tid3
,
7800 .resetvalue
= cpu
->isar
.id_mmfr4
},
7801 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7802 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7803 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7804 .accessfn
= access_aa32_tid3
,
7805 .resetvalue
= cpu
->isar
.id_isar6
},
7808 define_arm_cp_regs(cpu
, v6_idregs
);
7809 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7811 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7813 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7814 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7816 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7817 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7818 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7820 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7821 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7823 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7824 ARMCPRegInfo clidr
= {
7825 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7826 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7827 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7828 .accessfn
= access_aa64_tid2
,
7829 .resetvalue
= cpu
->clidr
7831 define_one_arm_cp_reg(cpu
, &clidr
);
7832 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7833 define_debug_regs(cpu
);
7834 define_pmu_regs(cpu
);
7836 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7838 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7839 /* AArch64 ID registers, which all have impdef reset values.
7840 * Note that within the ID register ranges the unused slots
7841 * must all RAZ, not UNDEF; future architecture versions may
7842 * define new registers here.
7844 ARMCPRegInfo v8_idregs
[] = {
7846 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7847 * emulation because we don't know the right value for the
7848 * GIC field until after we define these regs.
7850 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7851 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7853 #ifdef CONFIG_USER_ONLY
7854 .type
= ARM_CP_CONST
,
7855 .resetvalue
= cpu
->isar
.id_aa64pfr0
7857 .type
= ARM_CP_NO_RAW
,
7858 .accessfn
= access_aa64_tid3
,
7859 .readfn
= id_aa64pfr0_read
,
7860 .writefn
= arm_cp_write_ignore
7863 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7864 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7865 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7866 .accessfn
= access_aa64_tid3
,
7867 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7868 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7869 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7870 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7871 .accessfn
= access_aa64_tid3
,
7873 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7874 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7875 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7876 .accessfn
= access_aa64_tid3
,
7878 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7879 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7880 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7881 .accessfn
= access_aa64_tid3
,
7882 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
7883 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7884 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7885 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7886 .accessfn
= access_aa64_tid3
,
7888 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7889 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7890 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7891 .accessfn
= access_aa64_tid3
,
7893 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7894 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7895 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7896 .accessfn
= access_aa64_tid3
,
7898 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7899 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7900 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7901 .accessfn
= access_aa64_tid3
,
7902 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7903 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7904 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7905 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7906 .accessfn
= access_aa64_tid3
,
7907 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7908 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7909 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7910 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7911 .accessfn
= access_aa64_tid3
,
7913 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7914 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7915 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7916 .accessfn
= access_aa64_tid3
,
7918 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7919 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7920 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7921 .accessfn
= access_aa64_tid3
,
7922 .resetvalue
= cpu
->id_aa64afr0
},
7923 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7924 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7925 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7926 .accessfn
= access_aa64_tid3
,
7927 .resetvalue
= cpu
->id_aa64afr1
},
7928 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7929 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7930 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7931 .accessfn
= access_aa64_tid3
,
7933 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7934 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7935 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7936 .accessfn
= access_aa64_tid3
,
7938 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7939 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7940 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7941 .accessfn
= access_aa64_tid3
,
7942 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7943 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7944 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7945 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7946 .accessfn
= access_aa64_tid3
,
7947 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7948 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7949 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7950 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7951 .accessfn
= access_aa64_tid3
,
7953 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7954 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7955 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7956 .accessfn
= access_aa64_tid3
,
7958 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7959 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7960 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7961 .accessfn
= access_aa64_tid3
,
7963 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7964 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7965 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7966 .accessfn
= access_aa64_tid3
,
7968 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7969 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7970 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7971 .accessfn
= access_aa64_tid3
,
7973 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7974 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7975 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7976 .accessfn
= access_aa64_tid3
,
7978 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7979 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7980 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7981 .accessfn
= access_aa64_tid3
,
7982 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7983 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7984 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7985 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7986 .accessfn
= access_aa64_tid3
,
7987 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7988 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7989 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7990 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7991 .accessfn
= access_aa64_tid3
,
7992 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7993 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7994 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7995 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7996 .accessfn
= access_aa64_tid3
,
7998 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7999 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8000 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8001 .accessfn
= access_aa64_tid3
,
8003 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8004 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8005 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8006 .accessfn
= access_aa64_tid3
,
8008 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8009 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8010 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8011 .accessfn
= access_aa64_tid3
,
8013 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8014 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8015 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8016 .accessfn
= access_aa64_tid3
,
8018 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8019 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8020 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8021 .accessfn
= access_aa64_tid3
,
8022 .resetvalue
= cpu
->isar
.mvfr0
},
8023 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8024 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8025 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8026 .accessfn
= access_aa64_tid3
,
8027 .resetvalue
= cpu
->isar
.mvfr1
},
8028 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8029 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8030 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8031 .accessfn
= access_aa64_tid3
,
8032 .resetvalue
= cpu
->isar
.mvfr2
},
8033 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8034 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8035 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8036 .accessfn
= access_aa64_tid3
,
8038 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8039 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8040 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8041 .accessfn
= access_aa64_tid3
,
8042 .resetvalue
= cpu
->isar
.id_pfr2
},
8043 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8044 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8045 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8046 .accessfn
= access_aa64_tid3
,
8048 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8049 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8050 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8051 .accessfn
= access_aa64_tid3
,
8053 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8056 .accessfn
= access_aa64_tid3
,
8058 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8059 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8060 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8061 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8062 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8063 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8064 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8065 .resetvalue
= cpu
->pmceid0
},
8066 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8067 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8068 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8069 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8070 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8071 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8072 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8073 .resetvalue
= cpu
->pmceid1
},
8076 #ifdef CONFIG_USER_ONLY
8077 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8078 { .name
= "ID_AA64PFR0_EL1",
8079 .exported_bits
= 0x000f000f00ff0000,
8080 .fixed_bits
= 0x0000000000000011 },
8081 { .name
= "ID_AA64PFR1_EL1",
8082 .exported_bits
= 0x00000000000000f0 },
8083 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8085 { .name
= "ID_AA64ZFR0_EL1" },
8086 { .name
= "ID_AA64MMFR0_EL1",
8087 .fixed_bits
= 0x00000000ff000000 },
8088 { .name
= "ID_AA64MMFR1_EL1" },
8089 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8091 { .name
= "ID_AA64DFR0_EL1",
8092 .fixed_bits
= 0x0000000000000006 },
8093 { .name
= "ID_AA64DFR1_EL1" },
8094 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8096 { .name
= "ID_AA64AFR*",
8098 { .name
= "ID_AA64ISAR0_EL1",
8099 .exported_bits
= 0x00fffffff0fffff0 },
8100 { .name
= "ID_AA64ISAR1_EL1",
8101 .exported_bits
= 0x000000f0ffffffff },
8102 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8104 REGUSERINFO_SENTINEL
8106 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8108 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
8109 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8110 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8111 ARMCPRegInfo rvbar
= {
8112 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8113 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8114 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
8116 define_one_arm_cp_reg(cpu
, &rvbar
);
8118 define_arm_cp_regs(cpu
, v8_idregs
);
8119 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8121 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
8122 uint64_t vmpidr_def
= mpidr_read_val(env
);
8123 ARMCPRegInfo vpidr_regs
[] = {
8124 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8125 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8126 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8127 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
8128 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8129 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8130 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8131 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8132 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8133 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8134 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8135 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8136 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
8137 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8138 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8139 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8141 .resetvalue
= vmpidr_def
,
8142 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8145 define_arm_cp_regs(cpu
, vpidr_regs
);
8146 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8147 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8148 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8150 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8151 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8153 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
8154 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8155 ARMCPRegInfo rvbar
= {
8156 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8157 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8158 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
8160 define_one_arm_cp_reg(cpu
, &rvbar
);
8163 /* If EL2 is missing but higher ELs are enabled, we need to
8164 * register the no_el2 reginfos.
8166 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8167 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
8168 * of MIDR_EL1 and MPIDR_EL1.
8170 ARMCPRegInfo vpidr_regs
[] = {
8171 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
8172 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8173 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8174 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
8175 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8176 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
8177 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8178 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8179 .type
= ARM_CP_NO_RAW
,
8180 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
8183 define_arm_cp_regs(cpu
, vpidr_regs
);
8184 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
8185 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8186 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
8190 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8191 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8192 ARMCPRegInfo el3_regs
[] = {
8193 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8194 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8195 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
8196 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8197 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8199 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8200 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8201 .resetvalue
= cpu
->reset_sctlr
},
8205 define_arm_cp_regs(cpu
, el3_regs
);
8207 /* The behaviour of NSACR is sufficiently various that we don't
8208 * try to describe it in a single reginfo:
8209 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8210 * reads as constant 0xc00 from NS EL1 and NS EL2
8211 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8212 * if v7 without EL3, register doesn't exist
8213 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8215 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8216 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8217 ARMCPRegInfo nsacr
= {
8218 .name
= "NSACR", .type
= ARM_CP_CONST
,
8219 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8220 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8223 define_one_arm_cp_reg(cpu
, &nsacr
);
8225 ARMCPRegInfo nsacr
= {
8227 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8228 .access
= PL3_RW
| PL1_R
,
8230 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8232 define_one_arm_cp_reg(cpu
, &nsacr
);
8235 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8236 ARMCPRegInfo nsacr
= {
8237 .name
= "NSACR", .type
= ARM_CP_CONST
,
8238 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8242 define_one_arm_cp_reg(cpu
, &nsacr
);
8246 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8247 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8248 /* PMSAv6 not implemented */
8249 assert(arm_feature(env
, ARM_FEATURE_V7
));
8250 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8251 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8253 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8256 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8257 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8258 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8259 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8260 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8263 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8264 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8266 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8267 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8269 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8270 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8272 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8273 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8275 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8276 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8278 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8279 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8281 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8282 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8284 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8285 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8287 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8288 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8290 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8291 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8293 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8294 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8296 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8297 define_arm_cp_regs(cpu
, jazelle_regs
);
8299 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
8300 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8301 * be read-only (ie write causes UNDEF exception).
8304 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8305 /* Pre-v8 MIDR space.
8306 * Note that the MIDR isn't a simple constant register because
8307 * of the TI925 behaviour where writes to another register can
8308 * cause the MIDR value to change.
8310 * Unimplemented registers in the c15 0 0 0 space default to
8311 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8312 * and friends override accordingly.
8315 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8316 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8317 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8318 .readfn
= midr_read
,
8319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8320 .type
= ARM_CP_OVERRIDE
},
8321 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8323 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8324 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8326 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8327 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8329 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8330 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8332 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8333 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8335 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8336 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8339 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8340 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8341 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8342 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8343 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8344 .readfn
= midr_read
},
8345 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
8346 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8347 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8348 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8349 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8350 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8351 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8352 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8353 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8355 .accessfn
= access_aa64_tid1
,
8356 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8359 ARMCPRegInfo id_cp_reginfo
[] = {
8360 /* These are common to v8 and pre-v8 */
8362 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8363 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8364 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8365 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8366 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8367 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8368 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8369 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8371 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8373 .accessfn
= access_aa32_tid1
,
8374 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8377 /* TLBTR is specific to VMSA */
8378 ARMCPRegInfo id_tlbtr_reginfo
= {
8380 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8382 .accessfn
= access_aa32_tid1
,
8383 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8385 /* MPUIR is specific to PMSA V6+ */
8386 ARMCPRegInfo id_mpuir_reginfo
= {
8388 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8389 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8390 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8392 ARMCPRegInfo crn0_wi_reginfo
= {
8393 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8394 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8395 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8397 #ifdef CONFIG_USER_ONLY
8398 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8399 { .name
= "MIDR_EL1",
8400 .exported_bits
= 0x00000000ffffffff },
8401 { .name
= "REVIDR_EL1" },
8402 REGUSERINFO_SENTINEL
8404 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8406 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8407 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8409 /* Register the blanket "writes ignored" value first to cover the
8410 * whole space. Then update the specific ID registers to allow write
8411 * access, so that they ignore writes rather than causing them to
8414 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8415 for (r
= id_pre_v8_midr_cp_reginfo
;
8416 r
->type
!= ARM_CP_SENTINEL
; r
++) {
8419 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8422 id_mpuir_reginfo
.access
= PL1_RW
;
8423 id_tlbtr_reginfo
.access
= PL1_RW
;
8425 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8426 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8428 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8430 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8431 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8432 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8433 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8434 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8438 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8439 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8440 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8441 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8442 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8445 #ifdef CONFIG_USER_ONLY
8446 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8447 { .name
= "MPIDR_EL1",
8448 .fixed_bits
= 0x0000000080000000 },
8449 REGUSERINFO_SENTINEL
8451 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8453 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8456 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8457 ARMCPRegInfo auxcr_reginfo
[] = {
8458 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8459 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8460 .access
= PL1_RW
, .accessfn
= access_tacr
,
8461 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8462 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8463 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8464 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8466 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8467 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8468 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8472 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8473 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8474 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8478 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8480 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8481 * There are two flavours:
8482 * (1) older 32-bit only cores have a simple 32-bit CBAR
8483 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8484 * 32-bit register visible to AArch32 at a different encoding
8485 * to the "flavour 1" register and with the bits rearranged to
8486 * be able to squash a 64-bit address into the 32-bit view.
8487 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8488 * in future if we support AArch32-only configs of some of the
8489 * AArch64 cores we might need to add a specific feature flag
8490 * to indicate cores with "flavour 2" CBAR.
8492 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8493 /* 32 bit view is [31:18] 0...0 [43:32]. */
8494 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8495 | extract64(cpu
->reset_cbar
, 32, 12);
8496 ARMCPRegInfo cbar_reginfo
[] = {
8498 .type
= ARM_CP_CONST
,
8499 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8500 .access
= PL1_R
, .resetvalue
= cbar32
},
8501 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8502 .type
= ARM_CP_CONST
,
8503 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8504 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8507 /* We don't implement a r/w 64 bit CBAR currently */
8508 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8509 define_arm_cp_regs(cpu
, cbar_reginfo
);
8511 ARMCPRegInfo cbar
= {
8513 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8514 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8515 .fieldoffset
= offsetof(CPUARMState
,
8516 cp15
.c15_config_base_address
)
8518 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8519 cbar
.access
= PL1_R
;
8520 cbar
.fieldoffset
= 0;
8521 cbar
.type
= ARM_CP_CONST
;
8523 define_one_arm_cp_reg(cpu
, &cbar
);
8527 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8528 ARMCPRegInfo vbar_cp_reginfo
[] = {
8529 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8530 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8531 .access
= PL1_RW
, .writefn
= vbar_write
,
8532 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8533 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8537 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8540 /* Generic registers whose values depend on the implementation */
8542 ARMCPRegInfo sctlr
= {
8543 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8544 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8545 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8546 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8547 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8548 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8549 .raw_writefn
= raw_write
,
8551 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8552 /* Normally we would always end the TB on an SCTLR write, but Linux
8553 * arch/arm/mach-pxa/sleep.S expects two instructions following
8554 * an MMU enable to execute from cache. Imitate this behaviour.
8556 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8558 define_one_arm_cp_reg(cpu
, &sctlr
);
8561 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8562 define_arm_cp_regs(cpu
, lor_reginfo
);
8564 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8565 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8567 #ifndef CONFIG_USER_ONLY
8568 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8569 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8571 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8572 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8575 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8576 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8579 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8580 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8582 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8583 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8586 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8587 define_arm_cp_regs(cpu
, vhe_reginfo
);
8590 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8591 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
8592 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
8593 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
8595 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
8597 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8598 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
8602 #ifdef TARGET_AARCH64
8603 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8604 define_arm_cp_regs(cpu
, pauth_reginfo
);
8606 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8607 define_arm_cp_regs(cpu
, rndr_reginfo
);
8609 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8610 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8612 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8613 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8615 #ifndef CONFIG_USER_ONLY
8616 /* Data Cache clean instructions up to PoP */
8617 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8618 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8620 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8621 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8624 #endif /*CONFIG_USER_ONLY*/
8627 * If full MTE is enabled, add all of the system registers.
8628 * If only "instructions available at EL0" are enabled,
8629 * then define only a RAZ/WI version of PSTATE.TCO.
8631 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8632 define_arm_cp_regs(cpu
, mte_reginfo
);
8633 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8634 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8635 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8636 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8640 if (cpu_isar_feature(any_predinv
, cpu
)) {
8641 define_arm_cp_regs(cpu
, predinv_reginfo
);
8644 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8645 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8648 #ifndef CONFIG_USER_ONLY
8650 * Register redirections and aliases must be done last,
8651 * after the registers from the other extensions have been defined.
8653 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8654 define_arm_vh_e2h_redirects_aliases(cpu
);
8659 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
8661 CPUState
*cs
= CPU(cpu
);
8662 CPUARMState
*env
= &cpu
->env
;
8664 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8666 * The lower part of each SVE register aliases to the FPU
8667 * registers so we don't need to include both.
8669 #ifdef TARGET_AARCH64
8670 if (isar_feature_aa64_sve(&cpu
->isar
)) {
8671 gdb_register_coprocessor(cs
, arm_gdb_get_svereg
, arm_gdb_set_svereg
,
8672 arm_gen_dynamic_svereg_xml(cs
, cs
->gdb_num_regs
),
8673 "sve-registers.xml", 0);
8677 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
8678 aarch64_fpu_gdb_set_reg
,
8679 34, "aarch64-fpu.xml", 0);
8681 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
8682 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8683 51, "arm-neon.xml", 0);
8684 } else if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
8685 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8686 35, "arm-vfp3.xml", 0);
8687 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
8688 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8689 19, "arm-vfp.xml", 0);
8691 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
8692 arm_gen_dynamic_sysreg_xml(cs
, cs
->gdb_num_regs
),
8693 "system-registers.xml", 0);
8697 /* Sort alphabetically by type name, except for "any". */
8698 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8700 ObjectClass
*class_a
= (ObjectClass
*)a
;
8701 ObjectClass
*class_b
= (ObjectClass
*)b
;
8702 const char *name_a
, *name_b
;
8704 name_a
= object_class_get_name(class_a
);
8705 name_b
= object_class_get_name(class_b
);
8706 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8708 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8711 return strcmp(name_a
, name_b
);
8715 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8717 ObjectClass
*oc
= data
;
8718 const char *typename
;
8721 typename
= object_class_get_name(oc
);
8722 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8723 qemu_printf(" %s\n", name
);
8727 void arm_cpu_list(void)
8731 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8732 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8733 qemu_printf("Available CPUs:\n");
8734 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8738 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8740 ObjectClass
*oc
= data
;
8741 CpuDefinitionInfoList
**cpu_list
= user_data
;
8742 CpuDefinitionInfo
*info
;
8743 const char *typename
;
8745 typename
= object_class_get_name(oc
);
8746 info
= g_malloc0(sizeof(*info
));
8747 info
->name
= g_strndup(typename
,
8748 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8749 info
->q_typename
= g_strdup(typename
);
8751 QAPI_LIST_PREPEND(*cpu_list
, info
);
8754 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8756 CpuDefinitionInfoList
*cpu_list
= NULL
;
8759 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8760 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8766 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8767 void *opaque
, int state
, int secstate
,
8768 int crm
, int opc1
, int opc2
,
8771 /* Private utility function for define_one_arm_cp_reg_with_opaque():
8772 * add a single reginfo struct to the hash table.
8774 uint32_t *key
= g_new(uint32_t, 1);
8775 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
8776 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
8777 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
8779 r2
->name
= g_strdup(name
);
8780 /* Reset the secure state to the specific incoming state. This is
8781 * necessary as the register may have been defined with both states.
8783 r2
->secure
= secstate
;
8785 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
8786 /* Register is banked (using both entries in array).
8787 * Overwriting fieldoffset as the array is only used to define
8788 * banked registers but later only fieldoffset is used.
8790 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8793 if (state
== ARM_CP_STATE_AA32
) {
8794 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
8795 /* If the register is banked then we don't need to migrate or
8796 * reset the 32-bit instance in certain cases:
8798 * 1) If the register has both 32-bit and 64-bit instances then we
8799 * can count on the 64-bit instance taking care of the
8801 * 2) If ARMv8 is enabled then we can count on a 64-bit version
8802 * taking care of the secure bank. This requires that separate
8803 * 32 and 64-bit definitions are provided.
8805 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8806 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
8807 r2
->type
|= ARM_CP_ALIAS
;
8809 } else if ((secstate
!= r
->secure
) && !ns
) {
8810 /* The register is not banked so we only want to allow migration of
8811 * the non-secure instance.
8813 r2
->type
|= ARM_CP_ALIAS
;
8816 if (r
->state
== ARM_CP_STATE_BOTH
) {
8817 /* We assume it is a cp15 register if the .cp field is left unset.
8823 #ifdef HOST_WORDS_BIGENDIAN
8824 if (r2
->fieldoffset
) {
8825 r2
->fieldoffset
+= sizeof(uint32_t);
8830 if (state
== ARM_CP_STATE_AA64
) {
8831 /* To allow abbreviation of ARMCPRegInfo
8832 * definitions, we treat cp == 0 as equivalent to
8833 * the value for "standard guest-visible sysreg".
8834 * STATE_BOTH definitions are also always "standard
8835 * sysreg" in their AArch64 view (the .cp value may
8836 * be non-zero for the benefit of the AArch32 view).
8838 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8839 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
8841 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
8842 r2
->opc0
, opc1
, opc2
);
8844 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
8847 r2
->opaque
= opaque
;
8849 /* reginfo passed to helpers is correct for the actual access,
8850 * and is never ARM_CP_STATE_BOTH:
8853 /* Make sure reginfo passed to helpers for wildcarded regs
8854 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8859 /* By convention, for wildcarded registers only the first
8860 * entry is used for migration; the others are marked as
8861 * ALIAS so we don't try to transfer the register
8862 * multiple times. Special registers (ie NOP/WFI) are
8863 * never migratable and not even raw-accessible.
8865 if ((r
->type
& ARM_CP_SPECIAL
)) {
8866 r2
->type
|= ARM_CP_NO_RAW
;
8868 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8869 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8870 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8871 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8874 /* Check that raw accesses are either forbidden or handled. Note that
8875 * we can't assert this earlier because the setup of fieldoffset for
8876 * banked registers has to be done first.
8878 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8879 assert(!raw_accessors_invalid(r2
));
8882 /* Overriding of an existing definition must be explicitly
8885 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8886 ARMCPRegInfo
*oldreg
;
8887 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
8888 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
8889 fprintf(stderr
, "Register redefined: cp=%d %d bit "
8890 "crn=%d crm=%d opc1=%d opc2=%d, "
8891 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
8892 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
8893 oldreg
->name
, r2
->name
);
8894 g_assert_not_reached();
8897 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
8901 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8902 const ARMCPRegInfo
*r
, void *opaque
)
8904 /* Define implementations of coprocessor registers.
8905 * We store these in a hashtable because typically
8906 * there are less than 150 registers in a space which
8907 * is 16*16*16*8*8 = 262144 in size.
8908 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8909 * If a register is defined twice then the second definition is
8910 * used, so this can be used to define some generic registers and
8911 * then override them with implementation specific variations.
8912 * At least one of the original and the second definition should
8913 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8914 * against accidental use.
8916 * The state field defines whether the register is to be
8917 * visible in the AArch32 or AArch64 execution state. If the
8918 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8919 * reginfo structure for the AArch32 view, which sees the lower
8920 * 32 bits of the 64 bit register.
8922 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8923 * be wildcarded. AArch64 registers are always considered to be 64
8924 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8925 * the register, if any.
8927 int crm
, opc1
, opc2
, state
;
8928 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8929 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8930 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8931 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8932 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8933 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8934 /* 64 bit registers have only CRm and Opc1 fields */
8935 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8936 /* op0 only exists in the AArch64 encodings */
8937 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8938 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8939 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8941 * This API is only for Arm's system coprocessors (14 and 15) or
8942 * (M-profile or v7A-and-earlier only) for implementation defined
8943 * coprocessors in the range 0..7. Our decode assumes this, since
8944 * 8..13 can be used for other insns including VFP and Neon. See
8945 * valid_cp() in translate.c. Assert here that we haven't tried
8946 * to use an invalid coprocessor number.
8949 case ARM_CP_STATE_BOTH
:
8950 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8955 case ARM_CP_STATE_AA32
:
8956 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8957 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8958 assert(r
->cp
>= 14 && r
->cp
<= 15);
8960 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8963 case ARM_CP_STATE_AA64
:
8964 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8967 g_assert_not_reached();
8969 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8970 * encodes a minimum access level for the register. We roll this
8971 * runtime check into our general permission check code, so check
8972 * here that the reginfo's specified permissions are strict enough
8973 * to encompass the generic architectural permission check.
8975 if (r
->state
!= ARM_CP_STATE_AA32
) {
8979 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8980 mask
= PL0U_R
| PL1_RW
;
9000 /* min_EL EL1, secure mode only (we don't check the latter) */
9004 /* broken reginfo with out-of-range opc1 */
9008 /* assert our permissions are not too lax (stricter is fine) */
9009 assert((r
->access
& ~mask
) == 0);
9012 /* Check that the register definition has enough info to handle
9013 * reads and writes if they are permitted.
9015 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
9016 if (r
->access
& PL3_R
) {
9017 assert((r
->fieldoffset
||
9018 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9021 if (r
->access
& PL3_W
) {
9022 assert((r
->fieldoffset
||
9023 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9027 /* Bad type field probably means missing sentinel at end of reg list */
9028 assert(cptype_valid(r
->type
));
9029 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9030 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9031 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9032 for (state
= ARM_CP_STATE_AA32
;
9033 state
<= ARM_CP_STATE_AA64
; state
++) {
9034 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9037 if (state
== ARM_CP_STATE_AA32
) {
9038 /* Under AArch32 CP registers can be common
9039 * (same for secure and non-secure world) or banked.
9043 switch (r
->secure
) {
9044 case ARM_CP_SECSTATE_S
:
9045 case ARM_CP_SECSTATE_NS
:
9046 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9047 r
->secure
, crm
, opc1
, opc2
,
9051 name
= g_strdup_printf("%s_S", r
->name
);
9052 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9054 crm
, opc1
, opc2
, name
);
9056 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9058 crm
, opc1
, opc2
, r
->name
);
9062 /* AArch64 registers get mapped to non-secure instance
9064 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9066 crm
, opc1
, opc2
, r
->name
);
9074 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
9075 const ARMCPRegInfo
*regs
, void *opaque
)
9077 /* Define a whole list of registers */
9078 const ARMCPRegInfo
*r
;
9079 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
9080 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
9085 * Modify ARMCPRegInfo for access from userspace.
9087 * This is a data driven modification directed by
9088 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9089 * user-space cannot alter any values and dynamic values pertaining to
9090 * execution state are hidden from user space view anyway.
9092 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
9094 const ARMCPRegUserSpaceInfo
*m
;
9097 for (m
= mods
; m
->name
; m
++) {
9098 GPatternSpec
*pat
= NULL
;
9100 pat
= g_pattern_spec_new(m
->name
);
9102 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
9103 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9104 r
->type
= ARM_CP_CONST
;
9108 } else if (strcmp(r
->name
, m
->name
) == 0) {
9109 r
->type
= ARM_CP_CONST
;
9111 r
->resetvalue
&= m
->exported_bits
;
9112 r
->resetvalue
|= m
->fixed_bits
;
9117 g_pattern_spec_free(pat
);
9122 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9124 return g_hash_table_lookup(cpregs
, &encoded_cp
);
9127 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9130 /* Helper coprocessor write function for write-ignore registers */
9133 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9135 /* Helper coprocessor write function for read-as-zero registers */
9139 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9141 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9144 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9146 /* Return true if it is not valid for us to switch to
9147 * this CPU mode (ie all the UNPREDICTABLE cases in
9148 * the ARM ARM CPSRWriteByInstr pseudocode).
9151 /* Changes to or from Hyp via MSR and CPS are illegal. */
9152 if (write_type
== CPSRWriteByInstr
&&
9153 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9154 mode
== ARM_CPU_MODE_HYP
)) {
9159 case ARM_CPU_MODE_USR
:
9161 case ARM_CPU_MODE_SYS
:
9162 case ARM_CPU_MODE_SVC
:
9163 case ARM_CPU_MODE_ABT
:
9164 case ARM_CPU_MODE_UND
:
9165 case ARM_CPU_MODE_IRQ
:
9166 case ARM_CPU_MODE_FIQ
:
9167 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
9168 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9170 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9171 * and CPS are treated as illegal mode changes.
9173 if (write_type
== CPSRWriteByInstr
&&
9174 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9175 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9179 case ARM_CPU_MODE_HYP
:
9180 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9181 case ARM_CPU_MODE_MON
:
9182 return arm_current_el(env
) < 3;
9188 uint32_t cpsr_read(CPUARMState
*env
)
9191 ZF
= (env
->ZF
== 0);
9192 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9193 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9194 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9195 | ((env
->condexec_bits
& 0xfc) << 8)
9196 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9199 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9200 CPSRWriteType write_type
)
9202 uint32_t changed_daif
;
9204 if (mask
& CPSR_NZCV
) {
9205 env
->ZF
= (~val
) & CPSR_Z
;
9207 env
->CF
= (val
>> 29) & 1;
9208 env
->VF
= (val
<< 3) & 0x80000000;
9211 env
->QF
= ((val
& CPSR_Q
) != 0);
9213 env
->thumb
= ((val
& CPSR_T
) != 0);
9214 if (mask
& CPSR_IT_0_1
) {
9215 env
->condexec_bits
&= ~3;
9216 env
->condexec_bits
|= (val
>> 25) & 3;
9218 if (mask
& CPSR_IT_2_7
) {
9219 env
->condexec_bits
&= 3;
9220 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9222 if (mask
& CPSR_GE
) {
9223 env
->GE
= (val
>> 16) & 0xf;
9226 /* In a V7 implementation that includes the security extensions but does
9227 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9228 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9229 * bits respectively.
9231 * In a V8 implementation, it is permitted for privileged software to
9232 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9234 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9235 arm_feature(env
, ARM_FEATURE_EL3
) &&
9236 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9237 !arm_is_secure(env
)) {
9239 changed_daif
= (env
->daif
^ val
) & mask
;
9241 if (changed_daif
& CPSR_A
) {
9242 /* Check to see if we are allowed to change the masking of async
9243 * abort exceptions from a non-secure state.
9245 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9246 qemu_log_mask(LOG_GUEST_ERROR
,
9247 "Ignoring attempt to switch CPSR_A flag from "
9248 "non-secure world with SCR.AW bit clear\n");
9253 if (changed_daif
& CPSR_F
) {
9254 /* Check to see if we are allowed to change the masking of FIQ
9255 * exceptions from a non-secure state.
9257 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9258 qemu_log_mask(LOG_GUEST_ERROR
,
9259 "Ignoring attempt to switch CPSR_F flag from "
9260 "non-secure world with SCR.FW bit clear\n");
9264 /* Check whether non-maskable FIQ (NMFI) support is enabled.
9265 * If this bit is set software is not allowed to mask
9266 * FIQs, but is allowed to set CPSR_F to 0.
9268 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9270 qemu_log_mask(LOG_GUEST_ERROR
,
9271 "Ignoring attempt to enable CPSR_F flag "
9272 "(non-maskable FIQ [NMFI] support enabled)\n");
9278 env
->daif
&= ~(CPSR_AIF
& mask
);
9279 env
->daif
|= val
& CPSR_AIF
& mask
;
9281 if (write_type
!= CPSRWriteRaw
&&
9282 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9283 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9284 /* Note that we can only get here in USR mode if this is a
9285 * gdb stub write; for this case we follow the architectural
9286 * behaviour for guest writes in USR mode of ignoring an attempt
9287 * to switch mode. (Those are caught by translate.c for writes
9288 * triggered by guest instructions.)
9291 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9292 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9293 * v7, and has defined behaviour in v8:
9294 * + leave CPSR.M untouched
9295 * + allow changes to the other CPSR fields
9297 * For user changes via the GDB stub, we don't set PSTATE.IL,
9298 * as this would be unnecessarily harsh for a user error.
9301 if (write_type
!= CPSRWriteByGDBStub
&&
9302 arm_feature(env
, ARM_FEATURE_V8
)) {
9306 qemu_log_mask(LOG_GUEST_ERROR
,
9307 "Illegal AArch32 mode switch attempt from %s to %s\n",
9308 aarch32_mode_name(env
->uncached_cpsr
),
9309 aarch32_mode_name(val
));
9311 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9312 write_type
== CPSRWriteExceptionReturn
?
9313 "Exception return from AArch32" :
9314 "AArch32 mode switch from",
9315 aarch32_mode_name(env
->uncached_cpsr
),
9316 aarch32_mode_name(val
), env
->regs
[15]);
9317 switch_mode(env
, val
& CPSR_M
);
9320 mask
&= ~CACHED_CPSR_BITS
;
9321 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9324 /* Sign/zero extend */
9325 uint32_t HELPER(sxtb16
)(uint32_t x
)
9328 res
= (uint16_t)(int8_t)x
;
9329 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9333 uint32_t HELPER(uxtb16
)(uint32_t x
)
9336 res
= (uint16_t)(uint8_t)x
;
9337 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9341 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
9345 if (num
== INT_MIN
&& den
== -1)
9350 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
9357 uint32_t HELPER(rbit
)(uint32_t x
)
9362 #ifdef CONFIG_USER_ONLY
9364 static void switch_mode(CPUARMState
*env
, int mode
)
9366 ARMCPU
*cpu
= env_archcpu(env
);
9368 if (mode
!= ARM_CPU_MODE_USR
) {
9369 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9373 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9374 uint32_t cur_el
, bool secure
)
9379 void aarch64_sync_64_to_32(CPUARMState
*env
)
9381 g_assert_not_reached();
9386 static void switch_mode(CPUARMState
*env
, int mode
)
9391 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9392 if (mode
== old_mode
)
9395 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9396 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9397 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9398 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9399 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9400 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9403 i
= bank_number(old_mode
);
9404 env
->banked_r13
[i
] = env
->regs
[13];
9405 env
->banked_spsr
[i
] = env
->spsr
;
9407 i
= bank_number(mode
);
9408 env
->regs
[13] = env
->banked_r13
[i
];
9409 env
->spsr
= env
->banked_spsr
[i
];
9411 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9412 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9415 /* Physical Interrupt Target EL Lookup Table
9417 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9419 * The below multi-dimensional table is used for looking up the target
9420 * exception level given numerous condition criteria. Specifically, the
9421 * target EL is based on SCR and HCR routing controls as well as the
9422 * currently executing EL and secure state.
9425 * target_el_table[2][2][2][2][2][4]
9426 * | | | | | +--- Current EL
9427 * | | | | +------ Non-secure(0)/Secure(1)
9428 * | | | +--------- HCR mask override
9429 * | | +------------ SCR exec state control
9430 * | +--------------- SCR mask override
9431 * +------------------ 32-bit(0)/64-bit(1) EL3
9433 * The table values are as such:
9437 * The ARM ARM target EL table includes entries indicating that an "exception
9438 * is not taken". The two cases where this is applicable are:
9439 * 1) An exception is taken from EL3 but the SCR does not have the exception
9441 * 2) An exception is taken from EL2 but the HCR does not have the exception
9443 * In these two cases, the below table contain a target of EL1. This value is
9444 * returned as it is expected that the consumer of the table data will check
9445 * for "target EL >= current EL" to ensure the exception is not taken.
9449 * BIT IRQ IMO Non-secure Secure
9450 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9452 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9453 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9454 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9455 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9456 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9457 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9458 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9459 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9460 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9461 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9462 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9463 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9464 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9465 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9466 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9467 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9468 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9472 * Determine the target EL for physical exceptions
9474 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9475 uint32_t cur_el
, bool secure
)
9477 CPUARMState
*env
= cs
->env_ptr
;
9482 /* Is the highest EL AArch64? */
9483 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9486 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9487 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9489 /* Either EL2 is the highest EL (and so the EL2 register width
9490 * is given by is64); or there is no EL2 or EL3, in which case
9491 * the value of 'rw' does not affect the table lookup anyway.
9496 hcr_el2
= arm_hcr_el2_eff(env
);
9499 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9500 hcr
= hcr_el2
& HCR_IMO
;
9503 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9504 hcr
= hcr_el2
& HCR_FMO
;
9507 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9508 hcr
= hcr_el2
& HCR_AMO
;
9513 * For these purposes, TGE and AMO/IMO/FMO both force the
9514 * interrupt to EL2. Fold TGE into the bit extracted above.
9516 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9518 /* Perform a table-lookup for the target EL given the current state */
9519 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9521 assert(target_el
> 0);
9526 void arm_log_exception(int idx
)
9528 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9529 const char *exc
= NULL
;
9530 static const char * const excnames
[] = {
9531 [EXCP_UDEF
] = "Undefined Instruction",
9533 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9534 [EXCP_DATA_ABORT
] = "Data Abort",
9537 [EXCP_BKPT
] = "Breakpoint",
9538 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9539 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9540 [EXCP_HVC
] = "Hypervisor Call",
9541 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9542 [EXCP_SMC
] = "Secure Monitor Call",
9543 [EXCP_VIRQ
] = "Virtual IRQ",
9544 [EXCP_VFIQ
] = "Virtual FIQ",
9545 [EXCP_SEMIHOST
] = "Semihosting call",
9546 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9547 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9548 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9549 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9550 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9551 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9554 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9555 exc
= excnames
[idx
];
9560 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
9565 * Function used to synchronize QEMU's AArch64 register set with AArch32
9566 * register set. This is necessary when switching between AArch32 and AArch64
9569 void aarch64_sync_32_to_64(CPUARMState
*env
)
9572 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9574 /* We can blanket copy R[0:7] to X[0:7] */
9575 for (i
= 0; i
< 8; i
++) {
9576 env
->xregs
[i
] = env
->regs
[i
];
9580 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9581 * Otherwise, they come from the banked user regs.
9583 if (mode
== ARM_CPU_MODE_FIQ
) {
9584 for (i
= 8; i
< 13; i
++) {
9585 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9588 for (i
= 8; i
< 13; i
++) {
9589 env
->xregs
[i
] = env
->regs
[i
];
9594 * Registers x13-x23 are the various mode SP and FP registers. Registers
9595 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9596 * from the mode banked register.
9598 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9599 env
->xregs
[13] = env
->regs
[13];
9600 env
->xregs
[14] = env
->regs
[14];
9602 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9603 /* HYP is an exception in that it is copied from r14 */
9604 if (mode
== ARM_CPU_MODE_HYP
) {
9605 env
->xregs
[14] = env
->regs
[14];
9607 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9611 if (mode
== ARM_CPU_MODE_HYP
) {
9612 env
->xregs
[15] = env
->regs
[13];
9614 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9617 if (mode
== ARM_CPU_MODE_IRQ
) {
9618 env
->xregs
[16] = env
->regs
[14];
9619 env
->xregs
[17] = env
->regs
[13];
9621 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9622 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9625 if (mode
== ARM_CPU_MODE_SVC
) {
9626 env
->xregs
[18] = env
->regs
[14];
9627 env
->xregs
[19] = env
->regs
[13];
9629 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9630 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9633 if (mode
== ARM_CPU_MODE_ABT
) {
9634 env
->xregs
[20] = env
->regs
[14];
9635 env
->xregs
[21] = env
->regs
[13];
9637 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9638 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9641 if (mode
== ARM_CPU_MODE_UND
) {
9642 env
->xregs
[22] = env
->regs
[14];
9643 env
->xregs
[23] = env
->regs
[13];
9645 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9646 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9650 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9651 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9652 * FIQ bank for r8-r14.
9654 if (mode
== ARM_CPU_MODE_FIQ
) {
9655 for (i
= 24; i
< 31; i
++) {
9656 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9659 for (i
= 24; i
< 29; i
++) {
9660 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9662 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9663 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9666 env
->pc
= env
->regs
[15];
9670 * Function used to synchronize QEMU's AArch32 register set with AArch64
9671 * register set. This is necessary when switching between AArch32 and AArch64
9674 void aarch64_sync_64_to_32(CPUARMState
*env
)
9677 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9679 /* We can blanket copy X[0:7] to R[0:7] */
9680 for (i
= 0; i
< 8; i
++) {
9681 env
->regs
[i
] = env
->xregs
[i
];
9685 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9686 * Otherwise, we copy x8-x12 into the banked user regs.
9688 if (mode
== ARM_CPU_MODE_FIQ
) {
9689 for (i
= 8; i
< 13; i
++) {
9690 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9693 for (i
= 8; i
< 13; i
++) {
9694 env
->regs
[i
] = env
->xregs
[i
];
9699 * Registers r13 & r14 depend on the current mode.
9700 * If we are in a given mode, we copy the corresponding x registers to r13
9701 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9704 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9705 env
->regs
[13] = env
->xregs
[13];
9706 env
->regs
[14] = env
->xregs
[14];
9708 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9711 * HYP is an exception in that it does not have its own banked r14 but
9712 * shares the USR r14
9714 if (mode
== ARM_CPU_MODE_HYP
) {
9715 env
->regs
[14] = env
->xregs
[14];
9717 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9721 if (mode
== ARM_CPU_MODE_HYP
) {
9722 env
->regs
[13] = env
->xregs
[15];
9724 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9727 if (mode
== ARM_CPU_MODE_IRQ
) {
9728 env
->regs
[14] = env
->xregs
[16];
9729 env
->regs
[13] = env
->xregs
[17];
9731 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9732 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9735 if (mode
== ARM_CPU_MODE_SVC
) {
9736 env
->regs
[14] = env
->xregs
[18];
9737 env
->regs
[13] = env
->xregs
[19];
9739 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9740 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9743 if (mode
== ARM_CPU_MODE_ABT
) {
9744 env
->regs
[14] = env
->xregs
[20];
9745 env
->regs
[13] = env
->xregs
[21];
9747 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9748 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9751 if (mode
== ARM_CPU_MODE_UND
) {
9752 env
->regs
[14] = env
->xregs
[22];
9753 env
->regs
[13] = env
->xregs
[23];
9755 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9756 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9759 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9760 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9761 * FIQ bank for r8-r14.
9763 if (mode
== ARM_CPU_MODE_FIQ
) {
9764 for (i
= 24; i
< 31; i
++) {
9765 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9768 for (i
= 24; i
< 29; i
++) {
9769 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9771 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9772 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9775 env
->regs
[15] = env
->pc
;
9778 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9779 uint32_t mask
, uint32_t offset
,
9784 /* Change the CPU state so as to actually take the exception. */
9785 switch_mode(env
, new_mode
);
9788 * For exceptions taken to AArch32 we must clear the SS bit in both
9789 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9791 env
->pstate
&= ~PSTATE_SS
;
9792 env
->spsr
= cpsr_read(env
);
9793 /* Clear IT bits. */
9794 env
->condexec_bits
= 0;
9795 /* Switch to the new mode, and to the correct instruction set. */
9796 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9798 /* This must be after mode switching. */
9799 new_el
= arm_current_el(env
);
9801 /* Set new mode endianness */
9802 env
->uncached_cpsr
&= ~CPSR_E
;
9803 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9804 env
->uncached_cpsr
|= CPSR_E
;
9806 /* J and IL must always be cleared for exception entry */
9807 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9810 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
9811 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
9812 env
->uncached_cpsr
|= CPSR_SSBS
;
9814 env
->uncached_cpsr
&= ~CPSR_SSBS
;
9818 if (new_mode
== ARM_CPU_MODE_HYP
) {
9819 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9820 env
->elr_el
[2] = env
->regs
[15];
9822 /* CPSR.PAN is normally preserved preserved unless... */
9823 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9826 if (!arm_is_secure_below_el3(env
)) {
9827 /* ... the target is EL3, from non-secure state. */
9828 env
->uncached_cpsr
&= ~CPSR_PAN
;
9831 /* ... the target is EL3, from secure state ... */
9834 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9835 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9836 env
->uncached_cpsr
|= CPSR_PAN
;
9842 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9843 * and we should just guard the thumb mode on V4
9845 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9847 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9849 env
->regs
[14] = env
->regs
[15] + offset
;
9851 env
->regs
[15] = newpc
;
9852 arm_rebuild_hflags(env
);
9855 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9858 * Handle exception entry to Hyp mode; this is sufficiently
9859 * different to entry to other AArch32 modes that we handle it
9862 * The vector table entry used is always the 0x14 Hyp mode entry point,
9863 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9864 * The offset applied to the preferred return address is always zero
9865 * (see DDI0487C.a section G1.12.3).
9866 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9868 uint32_t addr
, mask
;
9869 ARMCPU
*cpu
= ARM_CPU(cs
);
9870 CPUARMState
*env
= &cpu
->env
;
9872 switch (cs
->exception_index
) {
9880 /* Fall through to prefetch abort. */
9881 case EXCP_PREFETCH_ABORT
:
9882 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9883 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9884 (uint32_t)env
->exception
.vaddress
);
9887 case EXCP_DATA_ABORT
:
9888 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9889 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9890 (uint32_t)env
->exception
.vaddress
);
9906 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9909 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9910 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9912 * QEMU syndrome values are v8-style. v7 has the IL bit
9913 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9914 * If this is a v7 CPU, squash the IL bit in those cases.
9916 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9917 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9918 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9919 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9920 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9923 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9926 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9931 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9934 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9937 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9941 addr
+= env
->cp15
.hvbar
;
9943 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9946 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9948 ARMCPU
*cpu
= ARM_CPU(cs
);
9949 CPUARMState
*env
= &cpu
->env
;
9956 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9957 switch (syn_get_ec(env
->exception
.syndrome
)) {
9959 case EC_BREAKPOINT_SAME_EL
:
9963 case EC_WATCHPOINT_SAME_EL
:
9969 case EC_VECTORCATCH
:
9978 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9981 if (env
->exception
.target_el
== 2) {
9982 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9986 switch (cs
->exception_index
) {
9988 new_mode
= ARM_CPU_MODE_UND
;
9997 new_mode
= ARM_CPU_MODE_SVC
;
10000 /* The PC already points to the next instruction. */
10004 /* Fall through to prefetch abort. */
10005 case EXCP_PREFETCH_ABORT
:
10006 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10007 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10008 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10009 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10010 new_mode
= ARM_CPU_MODE_ABT
;
10012 mask
= CPSR_A
| CPSR_I
;
10015 case EXCP_DATA_ABORT
:
10016 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10017 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10018 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10019 env
->exception
.fsr
,
10020 (uint32_t)env
->exception
.vaddress
);
10021 new_mode
= ARM_CPU_MODE_ABT
;
10023 mask
= CPSR_A
| CPSR_I
;
10027 new_mode
= ARM_CPU_MODE_IRQ
;
10029 /* Disable IRQ and imprecise data aborts. */
10030 mask
= CPSR_A
| CPSR_I
;
10032 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10033 /* IRQ routed to monitor mode */
10034 new_mode
= ARM_CPU_MODE_MON
;
10039 new_mode
= ARM_CPU_MODE_FIQ
;
10041 /* Disable FIQ, IRQ and imprecise data aborts. */
10042 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10043 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10044 /* FIQ routed to monitor mode */
10045 new_mode
= ARM_CPU_MODE_MON
;
10050 new_mode
= ARM_CPU_MODE_IRQ
;
10052 /* Disable IRQ and imprecise data aborts. */
10053 mask
= CPSR_A
| CPSR_I
;
10057 new_mode
= ARM_CPU_MODE_FIQ
;
10059 /* Disable FIQ, IRQ and imprecise data aborts. */
10060 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10064 new_mode
= ARM_CPU_MODE_MON
;
10066 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10070 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10071 return; /* Never happens. Keep compiler happy. */
10074 if (new_mode
== ARM_CPU_MODE_MON
) {
10075 addr
+= env
->cp15
.mvbar
;
10076 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10077 /* High vectors. When enabled, base address cannot be remapped. */
10078 addr
+= 0xffff0000;
10080 /* ARM v7 architectures provide a vector base address register to remap
10081 * the interrupt vector table.
10082 * This register is only followed in non-monitor mode, and is banked.
10083 * Note: only bits 31:5 are valid.
10085 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10088 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10089 env
->cp15
.scr_el3
&= ~SCR_NS
;
10092 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10095 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10098 * Return the register number of the AArch64 view of the AArch32
10099 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10100 * be that of the AArch32 mode the exception came from.
10102 int mode
= env
->uncached_cpsr
& CPSR_M
;
10104 switch (aarch32_reg
) {
10106 return aarch32_reg
;
10108 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10111 case ARM_CPU_MODE_USR
:
10112 case ARM_CPU_MODE_SYS
:
10114 case ARM_CPU_MODE_HYP
:
10116 case ARM_CPU_MODE_IRQ
:
10118 case ARM_CPU_MODE_SVC
:
10120 case ARM_CPU_MODE_ABT
:
10122 case ARM_CPU_MODE_UND
:
10124 case ARM_CPU_MODE_FIQ
:
10127 g_assert_not_reached();
10131 case ARM_CPU_MODE_USR
:
10132 case ARM_CPU_MODE_SYS
:
10133 case ARM_CPU_MODE_HYP
:
10135 case ARM_CPU_MODE_IRQ
:
10137 case ARM_CPU_MODE_SVC
:
10139 case ARM_CPU_MODE_ABT
:
10141 case ARM_CPU_MODE_UND
:
10143 case ARM_CPU_MODE_FIQ
:
10146 g_assert_not_reached();
10151 g_assert_not_reached();
10155 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10157 uint32_t ret
= cpsr_read(env
);
10159 /* Move DIT to the correct location for SPSR_ELx */
10160 if (ret
& CPSR_DIT
) {
10164 /* Merge PSTATE.SS into SPSR_ELx */
10165 ret
|= env
->pstate
& PSTATE_SS
;
10170 /* Handle exception entry to a target EL which is using AArch64 */
10171 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10173 ARMCPU
*cpu
= ARM_CPU(cs
);
10174 CPUARMState
*env
= &cpu
->env
;
10175 unsigned int new_el
= env
->exception
.target_el
;
10176 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10177 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10178 unsigned int old_mode
;
10179 unsigned int cur_el
= arm_current_el(env
);
10183 * Note that new_el can never be 0. If cur_el is 0, then
10184 * el0_a64 is is_a64(), else el0_a64 is ignored.
10186 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10188 if (cur_el
< new_el
) {
10189 /* Entry vector offset depends on whether the implemented EL
10190 * immediately lower than the target level is using AArch32 or AArch64
10197 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10200 hcr
= arm_hcr_el2_eff(env
);
10201 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10202 is_aa64
= (hcr
& HCR_RW
) != 0;
10207 is_aa64
= is_a64(env
);
10210 g_assert_not_reached();
10218 } else if (pstate_read(env
) & PSTATE_SP
) {
10222 switch (cs
->exception_index
) {
10223 case EXCP_PREFETCH_ABORT
:
10224 case EXCP_DATA_ABORT
:
10225 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10226 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10227 env
->cp15
.far_el
[new_el
]);
10233 case EXCP_HYP_TRAP
:
10235 switch (syn_get_ec(env
->exception
.syndrome
)) {
10236 case EC_ADVSIMDFPACCESSTRAP
:
10238 * QEMU internal FP/SIMD syndromes from AArch32 include the
10239 * TA and coproc fields which are only exposed if the exception
10240 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10241 * AArch64 format syndrome.
10243 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10245 case EC_CP14RTTRAP
:
10246 case EC_CP15RTTRAP
:
10247 case EC_CP14DTTRAP
:
10249 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10250 * the raw register field from the insn; when taking this to
10251 * AArch64 we must convert it to the AArch64 view of the register
10252 * number. Notice that we read a 4-bit AArch32 register number and
10253 * write back a 5-bit AArch64 one.
10255 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10256 rt
= aarch64_regnum(env
, rt
);
10257 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10260 case EC_CP15RRTTRAP
:
10261 case EC_CP14RRTTRAP
:
10262 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10263 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10264 rt
= aarch64_regnum(env
, rt
);
10265 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10267 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10268 rt
= aarch64_regnum(env
, rt
);
10269 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10273 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10284 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10288 old_mode
= pstate_read(env
);
10289 aarch64_save_sp(env
, arm_current_el(env
));
10290 env
->elr_el
[new_el
] = env
->pc
;
10292 old_mode
= cpsr_read_for_spsr_elx(env
);
10293 env
->elr_el
[new_el
] = env
->regs
[15];
10295 aarch64_sync_32_to_64(env
);
10297 env
->condexec_bits
= 0;
10299 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10301 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10302 env
->elr_el
[new_el
]);
10304 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10305 /* The value of PSTATE.PAN is normally preserved, except when ... */
10306 new_mode
|= old_mode
& PSTATE_PAN
;
10309 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10310 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10311 != (HCR_E2H
| HCR_TGE
)) {
10316 /* ... the target is EL1 ... */
10317 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10318 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10319 new_mode
|= PSTATE_PAN
;
10324 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10325 new_mode
|= PSTATE_TCO
;
10328 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10329 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10330 new_mode
|= PSTATE_SSBS
;
10332 new_mode
&= ~PSTATE_SSBS
;
10336 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10338 aarch64_restore_sp(env
, new_el
);
10339 helper_rebuild_hflags_a64(env
, new_el
);
10343 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10344 new_el
, env
->pc
, pstate_read(env
));
10348 * Do semihosting call and set the appropriate return value. All the
10349 * permission and validity checks have been done at translate time.
10351 * We only see semihosting exceptions in TCG only as they are not
10352 * trapped to the hypervisor in KVM.
10355 static void handle_semihosting(CPUState
*cs
)
10357 ARMCPU
*cpu
= ARM_CPU(cs
);
10358 CPUARMState
*env
= &cpu
->env
;
10361 qemu_log_mask(CPU_LOG_INT
,
10362 "...handling as semihosting call 0x%" PRIx64
"\n",
10364 env
->xregs
[0] = do_common_semihosting(cs
);
10367 qemu_log_mask(CPU_LOG_INT
,
10368 "...handling as semihosting call 0x%x\n",
10370 env
->regs
[0] = do_common_semihosting(cs
);
10371 env
->regs
[15] += env
->thumb
? 2 : 4;
10376 /* Handle a CPU exception for A and R profile CPUs.
10377 * Do any appropriate logging, handle PSCI calls, and then hand off
10378 * to the AArch64-entry or AArch32-entry function depending on the
10379 * target exception level's register width.
10381 * Note: this is used for both TCG (as the do_interrupt tcg op),
10382 * and KVM to re-inject guest debug exceptions, and to
10383 * inject a Synchronous-External-Abort.
10385 void arm_cpu_do_interrupt(CPUState
*cs
)
10387 ARMCPU
*cpu
= ARM_CPU(cs
);
10388 CPUARMState
*env
= &cpu
->env
;
10389 unsigned int new_el
= env
->exception
.target_el
;
10391 assert(!arm_feature(env
, ARM_FEATURE_M
));
10393 arm_log_exception(cs
->exception_index
);
10394 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10396 if (qemu_loglevel_mask(CPU_LOG_INT
)
10397 && !excp_is_internal(cs
->exception_index
)) {
10398 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10399 syn_get_ec(env
->exception
.syndrome
),
10400 env
->exception
.syndrome
);
10403 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10404 arm_handle_psci_call(cpu
);
10405 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10410 * Semihosting semantics depend on the register width of the code
10411 * that caused the exception, not the target exception level, so
10412 * must be handled here.
10415 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10416 handle_semihosting(cs
);
10421 /* Hooks may change global state so BQL should be held, also the
10422 * BQL needs to be held for any modification of
10423 * cs->interrupt_request.
10425 g_assert(qemu_mutex_iothread_locked());
10427 arm_call_pre_el_change_hook(cpu
);
10429 assert(!excp_is_internal(cs
->exception_index
));
10430 if (arm_el_is_aa64(env
, new_el
)) {
10431 arm_cpu_do_interrupt_aarch64(cs
);
10433 arm_cpu_do_interrupt_aarch32(cs
);
10436 arm_call_el_change_hook(cpu
);
10438 if (!kvm_enabled()) {
10439 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10442 #endif /* !CONFIG_USER_ONLY */
10444 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10446 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10448 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10449 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10452 return env
->cp15
.sctlr_el
[el
];
10455 /* Return the SCTLR value which controls this address translation regime */
10456 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10458 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
10461 #ifndef CONFIG_USER_ONLY
10463 /* Return true if the specified stage of address translation is disabled */
10464 static inline bool regime_translation_disabled(CPUARMState
*env
,
10469 if (arm_feature(env
, ARM_FEATURE_M
)) {
10470 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
10471 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
10472 case R_V7M_MPU_CTRL_ENABLE_MASK
:
10473 /* Enabled, but not for HardFault and NMI */
10474 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
10475 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
10476 /* Enabled for all cases */
10480 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
10481 * we warned about that in armv7m_nvic.c when the guest set it.
10487 hcr_el2
= arm_hcr_el2_eff(env
);
10489 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10490 /* HCR.DC means HCR.VM behaves as 1 */
10491 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
10494 if (hcr_el2
& HCR_TGE
) {
10495 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10496 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
10501 if ((hcr_el2
& HCR_DC
) && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
10502 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10506 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
10509 static inline bool regime_translation_big_endian(CPUARMState
*env
,
10512 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
10515 /* Return the TTBR associated with this translation regime */
10516 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10519 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10520 return env
->cp15
.vttbr_el2
;
10522 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
10523 return env
->cp15
.vsttbr_el2
;
10526 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
10528 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
10532 #endif /* !CONFIG_USER_ONLY */
10534 /* Convert a possible stage1+2 MMU index into the appropriate
10535 * stage 1 MMU index
10537 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
10540 case ARMMMUIdx_SE10_0
:
10541 return ARMMMUIdx_Stage1_SE0
;
10542 case ARMMMUIdx_SE10_1
:
10543 return ARMMMUIdx_Stage1_SE1
;
10544 case ARMMMUIdx_SE10_1_PAN
:
10545 return ARMMMUIdx_Stage1_SE1_PAN
;
10546 case ARMMMUIdx_E10_0
:
10547 return ARMMMUIdx_Stage1_E0
;
10548 case ARMMMUIdx_E10_1
:
10549 return ARMMMUIdx_Stage1_E1
;
10550 case ARMMMUIdx_E10_1_PAN
:
10551 return ARMMMUIdx_Stage1_E1_PAN
;
10557 /* Return true if the translation regime is using LPAE format page tables */
10558 static inline bool regime_using_lpae_format(CPUARMState
*env
,
10561 int el
= regime_el(env
, mmu_idx
);
10562 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
10565 if (arm_feature(env
, ARM_FEATURE_LPAE
)
10566 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
10572 /* Returns true if the stage 1 translation regime is using LPAE format page
10573 * tables. Used when raising alignment exceptions, whose FSR changes depending
10574 * on whether the long or short descriptor format is in use. */
10575 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10577 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10579 return regime_using_lpae_format(env
, mmu_idx
);
10582 #ifndef CONFIG_USER_ONLY
10583 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10586 case ARMMMUIdx_SE10_0
:
10587 case ARMMMUIdx_E20_0
:
10588 case ARMMMUIdx_SE20_0
:
10589 case ARMMMUIdx_Stage1_E0
:
10590 case ARMMMUIdx_Stage1_SE0
:
10591 case ARMMMUIdx_MUser
:
10592 case ARMMMUIdx_MSUser
:
10593 case ARMMMUIdx_MUserNegPri
:
10594 case ARMMMUIdx_MSUserNegPri
:
10598 case ARMMMUIdx_E10_0
:
10599 case ARMMMUIdx_E10_1
:
10600 case ARMMMUIdx_E10_1_PAN
:
10601 g_assert_not_reached();
10605 /* Translate section/page access permissions to page
10606 * R/W protection flags
10608 * @env: CPUARMState
10609 * @mmu_idx: MMU index indicating required translation regime
10610 * @ap: The 3-bit access permissions (AP[2:0])
10611 * @domain_prot: The 2-bit domain access permissions
10613 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10614 int ap
, int domain_prot
)
10616 bool is_user
= regime_is_user(env
, mmu_idx
);
10618 if (domain_prot
== 3) {
10619 return PAGE_READ
| PAGE_WRITE
;
10624 if (arm_feature(env
, ARM_FEATURE_V7
)) {
10627 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
10629 return is_user
? 0 : PAGE_READ
;
10636 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10641 return PAGE_READ
| PAGE_WRITE
;
10644 return PAGE_READ
| PAGE_WRITE
;
10645 case 4: /* Reserved. */
10648 return is_user
? 0 : PAGE_READ
;
10652 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
10657 g_assert_not_reached();
10661 /* Translate section/page access permissions to page
10662 * R/W protection flags.
10664 * @ap: The 2-bit simple AP (AP[2:1])
10665 * @is_user: TRUE if accessing from PL0
10667 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
10671 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10673 return PAGE_READ
| PAGE_WRITE
;
10675 return is_user
? 0 : PAGE_READ
;
10679 g_assert_not_reached();
10684 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
10686 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
10689 /* Translate S2 section/page access permissions to protection flags
10691 * @env: CPUARMState
10692 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10693 * @xn: XN (execute-never) bits
10694 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
10696 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
10704 prot
|= PAGE_WRITE
;
10707 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
10725 g_assert_not_reached();
10728 if (!extract32(xn
, 1, 1)) {
10729 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
10737 /* Translate section/page access permissions to protection flags
10739 * @env: CPUARMState
10740 * @mmu_idx: MMU index indicating required translation regime
10741 * @is_aa64: TRUE if AArch64
10742 * @ap: The 2-bit simple AP (AP[2:1])
10743 * @ns: NS (non-secure) bit
10744 * @xn: XN (execute-never) bit
10745 * @pxn: PXN (privileged execute-never) bit
10747 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
10748 int ap
, int ns
, int xn
, int pxn
)
10750 bool is_user
= regime_is_user(env
, mmu_idx
);
10751 int prot_rw
, user_rw
;
10755 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
10756 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
10758 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
10762 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
10763 /* PAN forbids data accesses but doesn't affect insn fetch */
10766 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
10770 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
10774 /* TODO have_wxn should be replaced with
10775 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10776 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10777 * compatible processors have EL2, which is required for [U]WXN.
10779 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
10782 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
10786 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
10787 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
10789 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10790 switch (regime_el(env
, mmu_idx
)) {
10794 xn
= xn
|| !(user_rw
& PAGE_READ
);
10798 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
10800 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
10801 (uwxn
&& (user_rw
& PAGE_WRITE
));
10811 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
10814 return prot_rw
| PAGE_EXEC
;
10817 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10818 uint32_t *table
, uint32_t address
)
10820 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10821 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10823 if (address
& tcr
->mask
) {
10824 if (tcr
->raw_tcr
& TTBCR_PD1
) {
10825 /* Translation table walk disabled for TTBR1 */
10828 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
10830 if (tcr
->raw_tcr
& TTBCR_PD0
) {
10831 /* Translation table walk disabled for TTBR0 */
10834 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
10836 *table
|= (address
>> 18) & 0x3ffc;
10840 /* Translate a S1 pagetable walk through S2 if needed. */
10841 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10842 hwaddr addr
, bool *is_secure
,
10843 ARMMMUFaultInfo
*fi
)
10845 if (arm_mmu_idx_is_stage1_of_2(mmu_idx
) &&
10846 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
10847 target_ulong s2size
;
10851 ARMMMUIdx s2_mmu_idx
= *is_secure
? ARMMMUIdx_Stage2_S
10852 : ARMMMUIdx_Stage2
;
10853 ARMCacheAttrs cacheattrs
= {};
10854 MemTxAttrs txattrs
= {};
10856 ret
= get_phys_addr_lpae(env
, addr
, MMU_DATA_LOAD
, s2_mmu_idx
, false,
10857 &s2pa
, &txattrs
, &s2prot
, &s2size
, fi
,
10860 assert(fi
->type
!= ARMFault_None
);
10864 fi
->s1ns
= !*is_secure
;
10867 if ((arm_hcr_el2_eff(env
) & HCR_PTW
) &&
10868 (cacheattrs
.attrs
& 0xf0) == 0) {
10870 * PTW set and S1 walk touched S2 Device memory:
10871 * generate Permission fault.
10873 fi
->type
= ARMFault_Permission
;
10877 fi
->s1ns
= !*is_secure
;
10881 if (arm_is_secure_below_el3(env
)) {
10882 /* Check if page table walk is to secure or non-secure PA space. */
10884 *is_secure
= !(env
->cp15
.vstcr_el2
.raw_tcr
& VSTCR_SW
);
10886 *is_secure
= !(env
->cp15
.vtcr_el2
.raw_tcr
& VTCR_NSW
);
10889 assert(!*is_secure
);
10897 /* All loads done in the course of a page table walk go through here. */
10898 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10899 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10901 ARMCPU
*cpu
= ARM_CPU(cs
);
10902 CPUARMState
*env
= &cpu
->env
;
10903 MemTxAttrs attrs
= {};
10904 MemTxResult result
= MEMTX_OK
;
10908 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, &is_secure
, fi
);
10909 attrs
.secure
= is_secure
;
10910 as
= arm_addressspace(cs
, attrs
);
10914 if (regime_translation_big_endian(env
, mmu_idx
)) {
10915 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
10917 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
10919 if (result
== MEMTX_OK
) {
10922 fi
->type
= ARMFault_SyncExternalOnWalk
;
10923 fi
->ea
= arm_extabort_type(result
);
10927 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10928 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10930 ARMCPU
*cpu
= ARM_CPU(cs
);
10931 CPUARMState
*env
= &cpu
->env
;
10932 MemTxAttrs attrs
= {};
10933 MemTxResult result
= MEMTX_OK
;
10937 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, &is_secure
, fi
);
10938 attrs
.secure
= is_secure
;
10939 as
= arm_addressspace(cs
, attrs
);
10943 if (regime_translation_big_endian(env
, mmu_idx
)) {
10944 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
10946 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
10948 if (result
== MEMTX_OK
) {
10951 fi
->type
= ARMFault_SyncExternalOnWalk
;
10952 fi
->ea
= arm_extabort_type(result
);
10956 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
10957 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10958 hwaddr
*phys_ptr
, int *prot
,
10959 target_ulong
*page_size
,
10960 ARMMMUFaultInfo
*fi
)
10962 CPUState
*cs
= env_cpu(env
);
10973 /* Pagetable walk. */
10974 /* Lookup l1 descriptor. */
10975 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10976 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10977 fi
->type
= ARMFault_Translation
;
10980 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10982 if (fi
->type
!= ARMFault_None
) {
10986 domain
= (desc
>> 5) & 0x0f;
10987 if (regime_el(env
, mmu_idx
) == 1) {
10988 dacr
= env
->cp15
.dacr_ns
;
10990 dacr
= env
->cp15
.dacr_s
;
10992 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10994 /* Section translation fault. */
10995 fi
->type
= ARMFault_Translation
;
11001 if (domain_prot
== 0 || domain_prot
== 2) {
11002 fi
->type
= ARMFault_Domain
;
11007 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
11008 ap
= (desc
>> 10) & 3;
11009 *page_size
= 1024 * 1024;
11011 /* Lookup l2 entry. */
11013 /* Coarse pagetable. */
11014 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
11016 /* Fine pagetable. */
11017 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
11019 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
11021 if (fi
->type
!= ARMFault_None
) {
11024 switch (desc
& 3) {
11025 case 0: /* Page translation fault. */
11026 fi
->type
= ARMFault_Translation
;
11028 case 1: /* 64k page. */
11029 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
11030 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
11031 *page_size
= 0x10000;
11033 case 2: /* 4k page. */
11034 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
11035 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
11036 *page_size
= 0x1000;
11038 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
11040 /* ARMv6/XScale extended small page format */
11041 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
11042 || arm_feature(env
, ARM_FEATURE_V6
)) {
11043 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
11044 *page_size
= 0x1000;
11046 /* UNPREDICTABLE in ARMv5; we choose to take a
11047 * page translation fault.
11049 fi
->type
= ARMFault_Translation
;
11053 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
11054 *page_size
= 0x400;
11056 ap
= (desc
>> 4) & 3;
11059 /* Never happens, but compiler isn't smart enough to tell. */
11063 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
11064 *prot
|= *prot
? PAGE_EXEC
: 0;
11065 if (!(*prot
& (1 << access_type
))) {
11066 /* Access permission fault. */
11067 fi
->type
= ARMFault_Permission
;
11070 *phys_ptr
= phys_addr
;
11073 fi
->domain
= domain
;
11078 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
11079 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11080 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
11081 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
11083 CPUState
*cs
= env_cpu(env
);
11084 ARMCPU
*cpu
= env_archcpu(env
);
11098 /* Pagetable walk. */
11099 /* Lookup l1 descriptor. */
11100 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
11101 /* Section translation fault if page walk is disabled by PD0 or PD1 */
11102 fi
->type
= ARMFault_Translation
;
11105 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
11107 if (fi
->type
!= ARMFault_None
) {
11111 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
11112 /* Section translation fault, or attempt to use the encoding
11113 * which is Reserved on implementations without PXN.
11115 fi
->type
= ARMFault_Translation
;
11118 if ((type
== 1) || !(desc
& (1 << 18))) {
11119 /* Page or Section. */
11120 domain
= (desc
>> 5) & 0x0f;
11122 if (regime_el(env
, mmu_idx
) == 1) {
11123 dacr
= env
->cp15
.dacr_ns
;
11125 dacr
= env
->cp15
.dacr_s
;
11130 domain_prot
= (dacr
>> (domain
* 2)) & 3;
11131 if (domain_prot
== 0 || domain_prot
== 2) {
11132 /* Section or Page domain fault */
11133 fi
->type
= ARMFault_Domain
;
11137 if (desc
& (1 << 18)) {
11138 /* Supersection. */
11139 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
11140 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
11141 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
11142 *page_size
= 0x1000000;
11145 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
11146 *page_size
= 0x100000;
11148 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
11149 xn
= desc
& (1 << 4);
11151 ns
= extract32(desc
, 19, 1);
11153 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
11154 pxn
= (desc
>> 2) & 1;
11156 ns
= extract32(desc
, 3, 1);
11157 /* Lookup l2 entry. */
11158 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
11159 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
11161 if (fi
->type
!= ARMFault_None
) {
11164 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
11165 switch (desc
& 3) {
11166 case 0: /* Page translation fault. */
11167 fi
->type
= ARMFault_Translation
;
11169 case 1: /* 64k page. */
11170 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
11171 xn
= desc
& (1 << 15);
11172 *page_size
= 0x10000;
11174 case 2: case 3: /* 4k page. */
11175 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
11177 *page_size
= 0x1000;
11180 /* Never happens, but compiler isn't smart enough to tell. */
11184 if (domain_prot
== 3) {
11185 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11187 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
11190 if (xn
&& access_type
== MMU_INST_FETCH
) {
11191 fi
->type
= ARMFault_Permission
;
11195 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
11196 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
11197 /* The simplified model uses AP[0] as an access control bit. */
11198 if ((ap
& 1) == 0) {
11199 /* Access flag fault. */
11200 fi
->type
= ARMFault_AccessFlag
;
11203 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
11205 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
11207 if (*prot
&& !xn
) {
11208 *prot
|= PAGE_EXEC
;
11210 if (!(*prot
& (1 << access_type
))) {
11211 /* Access permission fault. */
11212 fi
->type
= ARMFault_Permission
;
11217 /* The NS bit will (as required by the architecture) have no effect if
11218 * the CPU doesn't support TZ or this is a non-secure translation
11219 * regime, because the attribute will already be non-secure.
11221 attrs
->secure
= false;
11223 *phys_ptr
= phys_addr
;
11226 fi
->domain
= domain
;
11232 * check_s2_mmu_setup
11234 * @is_aa64: True if the translation regime is in AArch64 state
11235 * @startlevel: Suggested starting level
11236 * @inputsize: Bitsize of IPAs
11237 * @stride: Page-table stride (See the ARM ARM)
11239 * Returns true if the suggested S2 translation parameters are OK and
11242 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
11243 int inputsize
, int stride
)
11245 const int grainsize
= stride
+ 3;
11246 int startsizecheck
;
11248 /* Negative levels are never allowed. */
11253 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
11254 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
11259 CPUARMState
*env
= &cpu
->env
;
11260 unsigned int pamax
= arm_pamax(cpu
);
11263 case 13: /* 64KB Pages. */
11264 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
11268 case 11: /* 16KB Pages. */
11269 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
11273 case 9: /* 4KB Pages. */
11274 if (level
== 0 && pamax
<= 42) {
11279 g_assert_not_reached();
11282 /* Inputsize checks. */
11283 if (inputsize
> pamax
&&
11284 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
11285 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
11289 /* AArch32 only supports 4KB pages. Assert on that. */
11290 assert(stride
== 9);
11299 /* Translate from the 4-bit stage 2 representation of
11300 * memory attributes (without cache-allocation hints) to
11301 * the 8-bit representation of the stage 1 MAIR registers
11302 * (which includes allocation hints).
11304 * ref: shared/translation/attrs/S2AttrDecode()
11305 * .../S2ConvertAttrsHints()
11307 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
11309 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
11310 uint8_t loattr
= extract32(s2attrs
, 0, 2);
11311 uint8_t hihint
= 0, lohint
= 0;
11313 if (hiattr
!= 0) { /* normal memory */
11314 if (arm_hcr_el2_eff(env
) & HCR_CD
) { /* cache disabled */
11315 hiattr
= loattr
= 1; /* non-cacheable */
11317 if (hiattr
!= 1) { /* Write-through or write-back */
11318 hihint
= 3; /* RW allocate */
11320 if (loattr
!= 1) { /* Write-through or write-back */
11321 lohint
= 3; /* RW allocate */
11326 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
11328 #endif /* !CONFIG_USER_ONLY */
11330 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11332 if (regime_has_2_ranges(mmu_idx
)) {
11333 return extract64(tcr
, 37, 2);
11334 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11335 return 0; /* VTCR_EL2 */
11337 /* Replicate the single TBI bit so we always have 2 bits. */
11338 return extract32(tcr
, 20, 1) * 3;
11342 static int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11344 if (regime_has_2_ranges(mmu_idx
)) {
11345 return extract64(tcr
, 51, 2);
11346 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11347 return 0; /* VTCR_EL2 */
11349 /* Replicate the single TBID bit so we always have 2 bits. */
11350 return extract32(tcr
, 29, 1) * 3;
11354 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11356 if (regime_has_2_ranges(mmu_idx
)) {
11357 return extract64(tcr
, 57, 2);
11359 /* Replicate the single TCMA bit so we always have 2 bits. */
11360 return extract32(tcr
, 30, 1) * 3;
11364 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11365 ARMMMUIdx mmu_idx
, bool data
)
11367 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11368 bool epd
, hpd
, using16k
, using64k
;
11369 int select
, tsz
, tbi
, max_tsz
;
11371 if (!regime_has_2_ranges(mmu_idx
)) {
11373 tsz
= extract32(tcr
, 0, 6);
11374 using64k
= extract32(tcr
, 14, 1);
11375 using16k
= extract32(tcr
, 15, 1);
11376 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11380 hpd
= extract32(tcr
, 24, 1);
11385 * Bit 55 is always between the two regions, and is canonical for
11386 * determining if address tagging is enabled.
11388 select
= extract64(va
, 55, 1);
11390 tsz
= extract32(tcr
, 0, 6);
11391 epd
= extract32(tcr
, 7, 1);
11392 using64k
= extract32(tcr
, 14, 1);
11393 using16k
= extract32(tcr
, 15, 1);
11394 hpd
= extract64(tcr
, 41, 1);
11396 int tg
= extract32(tcr
, 30, 2);
11397 using16k
= tg
== 1;
11398 using64k
= tg
== 3;
11399 tsz
= extract32(tcr
, 16, 6);
11400 epd
= extract32(tcr
, 23, 1);
11401 hpd
= extract64(tcr
, 42, 1);
11405 if (cpu_isar_feature(aa64_st
, env_archcpu(env
))) {
11406 max_tsz
= 48 - using64k
;
11411 tsz
= MIN(tsz
, max_tsz
);
11412 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
11414 /* Present TBI as a composite with TBID. */
11415 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11417 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11419 tbi
= (tbi
>> select
) & 1;
11421 return (ARMVAParameters
) {
11427 .using16k
= using16k
,
11428 .using64k
= using64k
,
11432 #ifndef CONFIG_USER_ONLY
11433 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
11436 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11437 uint32_t el
= regime_el(env
, mmu_idx
);
11441 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
11443 if (mmu_idx
== ARMMMUIdx_Stage2
) {
11445 bool sext
= extract32(tcr
, 4, 1);
11446 bool sign
= extract32(tcr
, 3, 1);
11449 * If the sign-extend bit is not the same as t0sz[3], the result
11450 * is unpredictable. Flag this as a guest error.
11452 if (sign
!= sext
) {
11453 qemu_log_mask(LOG_GUEST_ERROR
,
11454 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
11456 tsz
= sextract32(tcr
, 0, 4) + 8;
11460 } else if (el
== 2) {
11462 tsz
= extract32(tcr
, 0, 3);
11464 hpd
= extract64(tcr
, 24, 1);
11467 int t0sz
= extract32(tcr
, 0, 3);
11468 int t1sz
= extract32(tcr
, 16, 3);
11471 select
= va
> (0xffffffffu
>> t0sz
);
11473 /* Note that we will detect errors later. */
11474 select
= va
>= ~(0xffffffffu
>> t1sz
);
11478 epd
= extract32(tcr
, 7, 1);
11479 hpd
= extract64(tcr
, 41, 1);
11482 epd
= extract32(tcr
, 23, 1);
11483 hpd
= extract64(tcr
, 42, 1);
11485 /* For aarch32, hpd0 is not enabled without t2e as well. */
11486 hpd
&= extract32(tcr
, 6, 1);
11489 return (ARMVAParameters
) {
11498 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
11500 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11501 * prot and page_size may not be filled in, and the populated fsr value provides
11502 * information on why the translation aborted, in the format of a long-format
11503 * DFSR/IFSR fault register, with the following caveats:
11504 * * the WnR bit is never set (the caller must do this).
11506 * @env: CPUARMState
11507 * @address: virtual address to get physical address for
11508 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
11509 * @mmu_idx: MMU index indicating required translation regime
11510 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
11511 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
11512 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
11513 * @phys_ptr: set to the physical address corresponding to the virtual address
11514 * @attrs: set to the memory transaction attributes to use
11515 * @prot: set to the permissions for the page containing phys_ptr
11516 * @page_size_ptr: set to the size of the page containing phys_ptr
11517 * @fi: set to fault info if the translation fails
11518 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11520 static bool get_phys_addr_lpae(CPUARMState
*env
, uint64_t address
,
11521 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11523 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
11524 target_ulong
*page_size_ptr
,
11525 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11527 ARMCPU
*cpu
= env_archcpu(env
);
11528 CPUState
*cs
= CPU(cpu
);
11529 /* Read an LPAE long-descriptor translation table. */
11530 ARMFaultType fault_type
= ARMFault_Translation
;
11532 ARMVAParameters param
;
11534 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
11535 uint32_t tableattrs
;
11536 target_ulong page_size
;
11539 int addrsize
, inputsize
;
11540 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
11541 int ap
, ns
, xn
, pxn
;
11542 uint32_t el
= regime_el(env
, mmu_idx
);
11543 uint64_t descaddrmask
;
11544 bool aarch64
= arm_el_is_aa64(env
, el
);
11545 bool guarded
= false;
11547 /* TODO: This code does not support shareability levels. */
11549 param
= aa64_va_parameters(env
, address
, mmu_idx
,
11550 access_type
!= MMU_INST_FETCH
);
11552 addrsize
= 64 - 8 * param
.tbi
;
11553 inputsize
= 64 - param
.tsz
;
11555 param
= aa32_va_parameters(env
, address
, mmu_idx
);
11557 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
11558 inputsize
= addrsize
- param
.tsz
;
11562 * We determined the region when collecting the parameters, but we
11563 * have not yet validated that the address is valid for the region.
11564 * Extract the top bits and verify that they all match select.
11566 * For aa32, if inputsize == addrsize, then we have selected the
11567 * region by exclusion in aa32_va_parameters and there is no more
11568 * validation to do here.
11570 if (inputsize
< addrsize
) {
11571 target_ulong top_bits
= sextract64(address
, inputsize
,
11572 addrsize
- inputsize
);
11573 if (-top_bits
!= param
.select
) {
11574 /* The gap between the two regions is a Translation fault */
11575 fault_type
= ARMFault_Translation
;
11580 if (param
.using64k
) {
11582 } else if (param
.using16k
) {
11588 /* Note that QEMU ignores shareability and cacheability attributes,
11589 * so we don't need to do anything with the SH, ORGN, IRGN fields
11590 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11591 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11592 * implement any ASID-like capability so we can ignore it (instead
11593 * we will always flush the TLB any time the ASID is changed).
11595 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
11597 /* Here we should have set up all the parameters for the translation:
11598 * inputsize, ttbr, epd, stride, tbi
11602 /* Translation table walk disabled => Translation fault on TLB miss
11603 * Note: This is always 0 on 64-bit EL2 and EL3.
11608 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
11609 /* The starting level depends on the virtual address size (which can
11610 * be up to 48 bits) and the translation granule size. It indicates
11611 * the number of strides (stride bits at a time) needed to
11612 * consume the bits of the input address. In the pseudocode this is:
11613 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11614 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11615 * our 'stride + 3' and 'stride' is our 'stride'.
11616 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11617 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11618 * = 4 - (inputsize - 4) / stride;
11620 level
= 4 - (inputsize
- 4) / stride
;
11622 /* For stage 2 translations the starting level is specified by the
11623 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11625 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
11626 uint32_t startlevel
;
11629 if (!aarch64
|| stride
== 9) {
11630 /* AArch32 or 4KB pages */
11631 startlevel
= 2 - sl0
;
11633 if (cpu_isar_feature(aa64_st
, cpu
)) {
11637 /* 16KB or 64KB pages */
11638 startlevel
= 3 - sl0
;
11641 /* Check that the starting level is valid. */
11642 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
11643 inputsize
, stride
);
11645 fault_type
= ARMFault_Translation
;
11648 level
= startlevel
;
11651 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
11652 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
11654 /* Now we can extract the actual base address from the TTBR */
11655 descaddr
= extract64(ttbr
, 0, 48);
11657 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
11658 * and also to mask out CnP (bit 0) which could validly be non-zero.
11660 descaddr
&= ~indexmask
;
11662 /* The address field in the descriptor goes up to bit 39 for ARMv7
11663 * but up to bit 47 for ARMv8, but we use the descaddrmask
11664 * up to bit 39 for AArch32, because we don't need other bits in that case
11665 * to construct next descriptor address (anyway they should be all zeroes).
11667 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
11668 ~indexmask_grainsize
;
11670 /* Secure accesses start with the page table in secure memory and
11671 * can be downgraded to non-secure at any step. Non-secure accesses
11672 * remain non-secure. We implement this by just ORing in the NSTable/NS
11673 * bits at each step.
11675 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
11677 uint64_t descriptor
;
11680 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
11682 nstable
= extract32(tableattrs
, 4, 1);
11683 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
11684 if (fi
->type
!= ARMFault_None
) {
11688 if (!(descriptor
& 1) ||
11689 (!(descriptor
& 2) && (level
== 3))) {
11690 /* Invalid, or the Reserved level 3 encoding */
11693 descaddr
= descriptor
& descaddrmask
;
11695 if ((descriptor
& 2) && (level
< 3)) {
11696 /* Table entry. The top five bits are attributes which may
11697 * propagate down through lower levels of the table (and
11698 * which are all arranged so that 0 means "no effect", so
11699 * we can gather them up by ORing in the bits at each level).
11701 tableattrs
|= extract64(descriptor
, 59, 5);
11703 indexmask
= indexmask_grainsize
;
11706 /* Block entry at level 1 or 2, or page entry at level 3.
11707 * These are basically the same thing, although the number
11708 * of bits we pull in from the vaddr varies.
11710 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
11711 descaddr
|= (address
& (page_size
- 1));
11712 /* Extract attributes from the descriptor */
11713 attrs
= extract64(descriptor
, 2, 10)
11714 | (extract64(descriptor
, 52, 12) << 10);
11716 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11717 /* Stage 2 table descriptors do not include any attribute fields */
11720 /* Merge in attributes from table descriptors */
11721 attrs
|= nstable
<< 3; /* NS */
11722 guarded
= extract64(descriptor
, 50, 1); /* GP */
11724 /* HPD disables all the table attributes except NSTable. */
11727 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
11728 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11729 * means "force PL1 access only", which means forcing AP[1] to 0.
11731 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
11732 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
11735 /* Here descaddr is the final physical address, and attributes
11736 * are all in attrs.
11738 fault_type
= ARMFault_AccessFlag
;
11739 if ((attrs
& (1 << 8)) == 0) {
11744 ap
= extract32(attrs
, 4, 2);
11746 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11747 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
11748 xn
= extract32(attrs
, 11, 2);
11749 *prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
11751 ns
= extract32(attrs
, 3, 1);
11752 xn
= extract32(attrs
, 12, 1);
11753 pxn
= extract32(attrs
, 11, 1);
11754 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
11757 fault_type
= ARMFault_Permission
;
11758 if (!(*prot
& (1 << access_type
))) {
11763 /* The NS bit will (as required by the architecture) have no effect if
11764 * the CPU doesn't support TZ or this is a non-secure translation
11765 * regime, because the attribute will already be non-secure.
11767 txattrs
->secure
= false;
11769 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11770 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
11771 arm_tlb_bti_gp(txattrs
) = true;
11774 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11775 cacheattrs
->attrs
= convert_stage2_attrs(env
, extract32(attrs
, 0, 4));
11777 /* Index into MAIR registers for cache attributes */
11778 uint8_t attrindx
= extract32(attrs
, 0, 3);
11779 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
11780 assert(attrindx
<= 7);
11781 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
11783 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
11785 *phys_ptr
= descaddr
;
11786 *page_size_ptr
= page_size
;
11790 fi
->type
= fault_type
;
11792 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11793 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
||
11794 mmu_idx
== ARMMMUIdx_Stage2_S
);
11795 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
11799 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
11801 int32_t address
, int *prot
)
11803 if (!arm_feature(env
, ARM_FEATURE_M
)) {
11804 *prot
= PAGE_READ
| PAGE_WRITE
;
11806 case 0xF0000000 ... 0xFFFFFFFF:
11807 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
11808 /* hivecs execing is ok */
11809 *prot
|= PAGE_EXEC
;
11812 case 0x00000000 ... 0x7FFFFFFF:
11813 *prot
|= PAGE_EXEC
;
11817 /* Default system address map for M profile cores.
11818 * The architecture specifies which regions are execute-never;
11819 * at the MPU level no other checks are defined.
11822 case 0x00000000 ... 0x1fffffff: /* ROM */
11823 case 0x20000000 ... 0x3fffffff: /* SRAM */
11824 case 0x60000000 ... 0x7fffffff: /* RAM */
11825 case 0x80000000 ... 0x9fffffff: /* RAM */
11826 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11828 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11829 case 0xa0000000 ... 0xbfffffff: /* Device */
11830 case 0xc0000000 ... 0xdfffffff: /* Device */
11831 case 0xe0000000 ... 0xffffffff: /* System */
11832 *prot
= PAGE_READ
| PAGE_WRITE
;
11835 g_assert_not_reached();
11840 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
11841 ARMMMUIdx mmu_idx
, bool is_user
)
11843 /* Return true if we should use the default memory map as a
11844 * "background" region if there are no hits against any MPU regions.
11846 CPUARMState
*env
= &cpu
->env
;
11852 if (arm_feature(env
, ARM_FEATURE_M
)) {
11853 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
11854 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
11856 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
11860 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
11862 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11863 return arm_feature(env
, ARM_FEATURE_M
) &&
11864 extract32(address
, 20, 12) == 0xe00;
11867 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
11869 /* True if address is in the M profile system region
11870 * 0xe0000000 - 0xffffffff
11872 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
11875 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
11876 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11877 hwaddr
*phys_ptr
, int *prot
,
11878 target_ulong
*page_size
,
11879 ARMMMUFaultInfo
*fi
)
11881 ARMCPU
*cpu
= env_archcpu(env
);
11883 bool is_user
= regime_is_user(env
, mmu_idx
);
11885 *phys_ptr
= address
;
11886 *page_size
= TARGET_PAGE_SIZE
;
11889 if (regime_translation_disabled(env
, mmu_idx
) ||
11890 m_is_ppb_region(env
, address
)) {
11891 /* MPU disabled or M profile PPB access: use default memory map.
11892 * The other case which uses the default memory map in the
11893 * v7M ARM ARM pseudocode is exception vector reads from the vector
11894 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11895 * which always does a direct read using address_space_ldl(), rather
11896 * than going via this function, so we don't need to check that here.
11898 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11899 } else { /* MPU enabled */
11900 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11901 /* region search */
11902 uint32_t base
= env
->pmsav7
.drbar
[n
];
11903 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
11905 bool srdis
= false;
11907 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
11912 qemu_log_mask(LOG_GUEST_ERROR
,
11913 "DRSR[%d]: Rsize field cannot be 0\n", n
);
11917 rmask
= (1ull << rsize
) - 1;
11919 if (base
& rmask
) {
11920 qemu_log_mask(LOG_GUEST_ERROR
,
11921 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
11922 "to DRSR region size, mask = 0x%" PRIx32
"\n",
11927 if (address
< base
|| address
> base
+ rmask
) {
11929 * Address not in this region. We must check whether the
11930 * region covers addresses in the same page as our address.
11931 * In that case we must not report a size that covers the
11932 * whole page for a subsequent hit against a different MPU
11933 * region or the background region, because it would result in
11934 * incorrect TLB hits for subsequent accesses to addresses that
11935 * are in this MPU region.
11937 if (ranges_overlap(base
, rmask
,
11938 address
& TARGET_PAGE_MASK
,
11939 TARGET_PAGE_SIZE
)) {
11945 /* Region matched */
11947 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
11949 uint32_t srdis_mask
;
11951 rsize
-= 3; /* sub region size (power of 2) */
11952 snd
= ((address
- base
) >> rsize
) & 0x7;
11953 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
11955 srdis_mask
= srdis
? 0x3 : 0x0;
11956 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
11957 /* This will check in groups of 2, 4 and then 8, whether
11958 * the subregion bits are consistent. rsize is incremented
11959 * back up to give the region size, considering consistent
11960 * adjacent subregions as one region. Stop testing if rsize
11961 * is already big enough for an entire QEMU page.
11963 int snd_rounded
= snd
& ~(i
- 1);
11964 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
11965 snd_rounded
+ 8, i
);
11966 if (srdis_mask
^ srdis_multi
) {
11969 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
11976 if (rsize
< TARGET_PAGE_BITS
) {
11977 *page_size
= 1 << rsize
;
11982 if (n
== -1) { /* no hits */
11983 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11984 /* background fault */
11985 fi
->type
= ARMFault_Background
;
11988 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11989 } else { /* a MPU hit! */
11990 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
11991 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
11993 if (m_is_system_region(env
, address
)) {
11994 /* System space is always execute never */
11998 if (is_user
) { /* User mode AP bit decoding */
12003 break; /* no access */
12005 *prot
|= PAGE_WRITE
;
12009 *prot
|= PAGE_READ
| PAGE_EXEC
;
12012 /* for v7M, same as 6; for R profile a reserved value */
12013 if (arm_feature(env
, ARM_FEATURE_M
)) {
12014 *prot
|= PAGE_READ
| PAGE_EXEC
;
12019 qemu_log_mask(LOG_GUEST_ERROR
,
12020 "DRACR[%d]: Bad value for AP bits: 0x%"
12021 PRIx32
"\n", n
, ap
);
12023 } else { /* Priv. mode AP bits decoding */
12026 break; /* no access */
12030 *prot
|= PAGE_WRITE
;
12034 *prot
|= PAGE_READ
| PAGE_EXEC
;
12037 /* for v7M, same as 6; for R profile a reserved value */
12038 if (arm_feature(env
, ARM_FEATURE_M
)) {
12039 *prot
|= PAGE_READ
| PAGE_EXEC
;
12044 qemu_log_mask(LOG_GUEST_ERROR
,
12045 "DRACR[%d]: Bad value for AP bits: 0x%"
12046 PRIx32
"\n", n
, ap
);
12050 /* execute never */
12052 *prot
&= ~PAGE_EXEC
;
12057 fi
->type
= ARMFault_Permission
;
12059 return !(*prot
& (1 << access_type
));
12062 static bool v8m_is_sau_exempt(CPUARMState
*env
,
12063 uint32_t address
, MMUAccessType access_type
)
12065 /* The architecture specifies that certain address ranges are
12066 * exempt from v8M SAU/IDAU checks.
12069 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
12070 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
12071 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
12072 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
12073 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
12074 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
12077 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
12078 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12079 V8M_SAttributes
*sattrs
)
12081 /* Look up the security attributes for this address. Compare the
12082 * pseudocode SecurityCheck() function.
12083 * We assume the caller has zero-initialized *sattrs.
12085 ARMCPU
*cpu
= env_archcpu(env
);
12087 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
12088 int idau_region
= IREGION_NOTVALID
;
12089 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
12090 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
12093 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
12094 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
12096 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
12100 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
12101 /* 0xf0000000..0xffffffff is always S for insn fetches */
12105 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
12106 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
12110 if (idau_region
!= IREGION_NOTVALID
) {
12111 sattrs
->irvalid
= true;
12112 sattrs
->iregion
= idau_region
;
12115 switch (env
->sau
.ctrl
& 3) {
12116 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
12118 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
12121 default: /* SAU.ENABLE == 1 */
12122 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
12123 if (env
->sau
.rlar
[r
] & 1) {
12124 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
12125 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
12127 if (base
<= address
&& limit
>= address
) {
12128 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
12129 sattrs
->subpage
= true;
12131 if (sattrs
->srvalid
) {
12132 /* If we hit in more than one region then we must report
12133 * as Secure, not NS-Callable, with no valid region
12136 sattrs
->ns
= false;
12137 sattrs
->nsc
= false;
12138 sattrs
->sregion
= 0;
12139 sattrs
->srvalid
= false;
12142 if (env
->sau
.rlar
[r
] & 2) {
12143 sattrs
->nsc
= true;
12147 sattrs
->srvalid
= true;
12148 sattrs
->sregion
= r
;
12152 * Address not in this region. We must check whether the
12153 * region covers addresses in the same page as our address.
12154 * In that case we must not report a size that covers the
12155 * whole page for a subsequent hit against a different MPU
12156 * region or the background region, because it would result
12157 * in incorrect TLB hits for subsequent accesses to
12158 * addresses that are in this MPU region.
12160 if (limit
>= base
&&
12161 ranges_overlap(base
, limit
- base
+ 1,
12163 TARGET_PAGE_SIZE
)) {
12164 sattrs
->subpage
= true;
12173 * The IDAU will override the SAU lookup results if it specifies
12174 * higher security than the SAU does.
12177 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
12178 sattrs
->ns
= false;
12179 sattrs
->nsc
= idau_nsc
;
12184 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
12185 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12186 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
12187 int *prot
, bool *is_subpage
,
12188 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
12190 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
12191 * that a full phys-to-virt translation does).
12192 * mregion is (if not NULL) set to the region number which matched,
12193 * or -1 if no region number is returned (MPU off, address did not
12194 * hit a region, address hit in multiple regions).
12195 * We set is_subpage to true if the region hit doesn't cover the
12196 * entire TARGET_PAGE the address is within.
12198 ARMCPU
*cpu
= env_archcpu(env
);
12199 bool is_user
= regime_is_user(env
, mmu_idx
);
12200 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
12202 int matchregion
= -1;
12204 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
12205 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
12207 *is_subpage
= false;
12208 *phys_ptr
= address
;
12214 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
12215 * was an exception vector read from the vector table (which is always
12216 * done using the default system address map), because those accesses
12217 * are done in arm_v7m_load_vector(), which always does a direct
12218 * read using address_space_ldl(), rather than going via this function.
12220 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
12222 } else if (m_is_ppb_region(env
, address
)) {
12225 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
12229 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
12230 /* region search */
12231 /* Note that the base address is bits [31:5] from the register
12232 * with bits [4:0] all zeroes, but the limit address is bits
12233 * [31:5] from the register with bits [4:0] all ones.
12235 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
12236 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
12238 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
12239 /* Region disabled */
12243 if (address
< base
|| address
> limit
) {
12245 * Address not in this region. We must check whether the
12246 * region covers addresses in the same page as our address.
12247 * In that case we must not report a size that covers the
12248 * whole page for a subsequent hit against a different MPU
12249 * region or the background region, because it would result in
12250 * incorrect TLB hits for subsequent accesses to addresses that
12251 * are in this MPU region.
12253 if (limit
>= base
&&
12254 ranges_overlap(base
, limit
- base
+ 1,
12256 TARGET_PAGE_SIZE
)) {
12257 *is_subpage
= true;
12262 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
12263 *is_subpage
= true;
12266 if (matchregion
!= -1) {
12267 /* Multiple regions match -- always a failure (unlike
12268 * PMSAv7 where highest-numbered-region wins)
12270 fi
->type
= ARMFault_Permission
;
12281 /* background fault */
12282 fi
->type
= ARMFault_Background
;
12286 if (matchregion
== -1) {
12287 /* hit using the background region */
12288 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
12290 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
12291 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
12294 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
12295 pxn
= extract32(env
->pmsav8
.rlar
[secure
][matchregion
], 4, 1);
12298 if (m_is_system_region(env
, address
)) {
12299 /* System space is always execute never */
12303 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
12304 if (*prot
&& !xn
&& !(pxn
&& !is_user
)) {
12305 *prot
|= PAGE_EXEC
;
12307 /* We don't need to look the attribute up in the MAIR0/MAIR1
12308 * registers because that only tells us about cacheability.
12311 *mregion
= matchregion
;
12315 fi
->type
= ARMFault_Permission
;
12317 return !(*prot
& (1 << access_type
));
12321 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
12322 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12323 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
12324 int *prot
, target_ulong
*page_size
,
12325 ARMMMUFaultInfo
*fi
)
12327 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
12328 V8M_SAttributes sattrs
= {};
12330 bool mpu_is_subpage
;
12332 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
12333 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
12334 if (access_type
== MMU_INST_FETCH
) {
12335 /* Instruction fetches always use the MMU bank and the
12336 * transaction attribute determined by the fetch address,
12337 * regardless of CPU state. This is painful for QEMU
12338 * to handle, because it would mean we need to encode
12339 * into the mmu_idx not just the (user, negpri) information
12340 * for the current security state but also that for the
12341 * other security state, which would balloon the number
12342 * of mmu_idx values needed alarmingly.
12343 * Fortunately we can avoid this because it's not actually
12344 * possible to arbitrarily execute code from memory with
12345 * the wrong security attribute: it will always generate
12346 * an exception of some kind or another, apart from the
12347 * special case of an NS CPU executing an SG instruction
12348 * in S&NSC memory. So we always just fail the translation
12349 * here and sort things out in the exception handler
12350 * (including possibly emulating an SG instruction).
12352 if (sattrs
.ns
!= !secure
) {
12354 fi
->type
= ARMFault_QEMU_NSCExec
;
12356 fi
->type
= ARMFault_QEMU_SFault
;
12358 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
12359 *phys_ptr
= address
;
12364 /* For data accesses we always use the MMU bank indicated
12365 * by the current CPU state, but the security attributes
12366 * might downgrade a secure access to nonsecure.
12369 txattrs
->secure
= false;
12370 } else if (!secure
) {
12371 /* NS access to S memory must fault.
12372 * Architecturally we should first check whether the
12373 * MPU information for this address indicates that we
12374 * are doing an unaligned access to Device memory, which
12375 * should generate a UsageFault instead. QEMU does not
12376 * currently check for that kind of unaligned access though.
12377 * If we added it we would need to do so as a special case
12378 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
12380 fi
->type
= ARMFault_QEMU_SFault
;
12381 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
12382 *phys_ptr
= address
;
12389 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
12390 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
12391 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
12395 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
12396 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12397 hwaddr
*phys_ptr
, int *prot
,
12398 ARMMMUFaultInfo
*fi
)
12403 bool is_user
= regime_is_user(env
, mmu_idx
);
12405 if (regime_translation_disabled(env
, mmu_idx
)) {
12406 /* MPU disabled. */
12407 *phys_ptr
= address
;
12408 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12412 *phys_ptr
= address
;
12413 for (n
= 7; n
>= 0; n
--) {
12414 base
= env
->cp15
.c6_region
[n
];
12415 if ((base
& 1) == 0) {
12418 mask
= 1 << ((base
>> 1) & 0x1f);
12419 /* Keep this shift separate from the above to avoid an
12420 (undefined) << 32. */
12421 mask
= (mask
<< 1) - 1;
12422 if (((base
^ address
) & ~mask
) == 0) {
12427 fi
->type
= ARMFault_Background
;
12431 if (access_type
== MMU_INST_FETCH
) {
12432 mask
= env
->cp15
.pmsav5_insn_ap
;
12434 mask
= env
->cp15
.pmsav5_data_ap
;
12436 mask
= (mask
>> (n
* 4)) & 0xf;
12439 fi
->type
= ARMFault_Permission
;
12444 fi
->type
= ARMFault_Permission
;
12448 *prot
= PAGE_READ
| PAGE_WRITE
;
12453 *prot
|= PAGE_WRITE
;
12457 *prot
= PAGE_READ
| PAGE_WRITE
;
12461 fi
->type
= ARMFault_Permission
;
12471 /* Bad permission. */
12472 fi
->type
= ARMFault_Permission
;
12476 *prot
|= PAGE_EXEC
;
12480 /* Combine either inner or outer cacheability attributes for normal
12481 * memory, according to table D4-42 and pseudocode procedure
12482 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
12484 * NB: only stage 1 includes allocation hints (RW bits), leading to
12487 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
12489 if (s1
== 4 || s2
== 4) {
12490 /* non-cacheable has precedence */
12492 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
12493 /* stage 1 write-through takes precedence */
12495 } else if (extract32(s2
, 2, 2) == 2) {
12496 /* stage 2 write-through takes precedence, but the allocation hint
12497 * is still taken from stage 1
12499 return (2 << 2) | extract32(s1
, 0, 2);
12500 } else { /* write-back */
12505 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
12506 * and CombineS1S2Desc()
12508 * @s1: Attributes from stage 1 walk
12509 * @s2: Attributes from stage 2 walk
12511 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
12513 uint8_t s1lo
, s2lo
, s1hi
, s2hi
;
12515 bool tagged
= false;
12517 if (s1
.attrs
== 0xf0) {
12522 s1lo
= extract32(s1
.attrs
, 0, 4);
12523 s2lo
= extract32(s2
.attrs
, 0, 4);
12524 s1hi
= extract32(s1
.attrs
, 4, 4);
12525 s2hi
= extract32(s2
.attrs
, 4, 4);
12527 /* Combine shareability attributes (table D4-43) */
12528 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
12529 /* if either are outer-shareable, the result is outer-shareable */
12530 ret
.shareability
= 2;
12531 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
12532 /* if either are inner-shareable, the result is inner-shareable */
12533 ret
.shareability
= 3;
12535 /* both non-shareable */
12536 ret
.shareability
= 0;
12539 /* Combine memory type and cacheability attributes */
12540 if (s1hi
== 0 || s2hi
== 0) {
12541 /* Device has precedence over normal */
12542 if (s1lo
== 0 || s2lo
== 0) {
12543 /* nGnRnE has precedence over anything */
12545 } else if (s1lo
== 4 || s2lo
== 4) {
12546 /* non-Reordering has precedence over Reordering */
12547 ret
.attrs
= 4; /* nGnRE */
12548 } else if (s1lo
== 8 || s2lo
== 8) {
12549 /* non-Gathering has precedence over Gathering */
12550 ret
.attrs
= 8; /* nGRE */
12552 ret
.attrs
= 0xc; /* GRE */
12555 /* Any location for which the resultant memory type is any
12556 * type of Device memory is always treated as Outer Shareable.
12558 ret
.shareability
= 2;
12559 } else { /* Normal memory */
12560 /* Outer/inner cacheability combine independently */
12561 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
12562 | combine_cacheattr_nibble(s1lo
, s2lo
);
12564 if (ret
.attrs
== 0x44) {
12565 /* Any location for which the resultant memory type is Normal
12566 * Inner Non-cacheable, Outer Non-cacheable is always treated
12567 * as Outer Shareable.
12569 ret
.shareability
= 2;
12573 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
12574 if (tagged
&& ret
.attrs
== 0xff) {
12582 /* get_phys_addr - get the physical address for this virtual address
12584 * Find the physical address corresponding to the given virtual address,
12585 * by doing a translation table walk on MMU based systems or using the
12586 * MPU state on MPU based systems.
12588 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12589 * prot and page_size may not be filled in, and the populated fsr value provides
12590 * information on why the translation aborted, in the format of a
12591 * DFSR/IFSR fault register, with the following caveats:
12592 * * we honour the short vs long DFSR format differences.
12593 * * the WnR bit is never set (the caller must do this).
12594 * * for PSMAv5 based systems we don't bother to return a full FSR format
12597 * @env: CPUARMState
12598 * @address: virtual address to get physical address for
12599 * @access_type: 0 for read, 1 for write, 2 for execute
12600 * @mmu_idx: MMU index indicating required translation regime
12601 * @phys_ptr: set to the physical address corresponding to the virtual address
12602 * @attrs: set to the memory transaction attributes to use
12603 * @prot: set to the permissions for the page containing phys_ptr
12604 * @page_size: set to the size of the page containing phys_ptr
12605 * @fi: set to fault info if the translation fails
12606 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
12608 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
12609 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12610 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
12611 target_ulong
*page_size
,
12612 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
12614 ARMMMUIdx s1_mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12616 if (mmu_idx
!= s1_mmu_idx
) {
12617 /* Call ourselves recursively to do the stage 1 and then stage 2
12618 * translations if mmu_idx is a two-stage regime.
12620 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
12624 ARMCacheAttrs cacheattrs2
= {};
12625 ARMMMUIdx s2_mmu_idx
;
12628 ret
= get_phys_addr(env
, address
, access_type
, s1_mmu_idx
, &ipa
,
12629 attrs
, prot
, page_size
, fi
, cacheattrs
);
12631 /* If S1 fails or S2 is disabled, return early. */
12632 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
12637 s2_mmu_idx
= attrs
->secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
12638 is_el0
= mmu_idx
== ARMMMUIdx_E10_0
|| mmu_idx
== ARMMMUIdx_SE10_0
;
12640 /* S1 is done. Now do S2 translation. */
12641 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, s2_mmu_idx
, is_el0
,
12642 phys_ptr
, attrs
, &s2_prot
,
12643 page_size
, fi
, &cacheattrs2
);
12645 /* Combine the S1 and S2 perms. */
12648 /* If S2 fails, return early. */
12653 /* Combine the S1 and S2 cache attributes. */
12654 if (arm_hcr_el2_eff(env
) & HCR_DC
) {
12656 * HCR.DC forces the first stage attributes to
12657 * Normal Non-Shareable,
12658 * Inner Write-Back Read-Allocate Write-Allocate,
12659 * Outer Write-Back Read-Allocate Write-Allocate.
12660 * Do not overwrite Tagged within attrs.
12662 if (cacheattrs
->attrs
!= 0xf0) {
12663 cacheattrs
->attrs
= 0xff;
12665 cacheattrs
->shareability
= 0;
12667 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
12669 /* Check if IPA translates to secure or non-secure PA space. */
12670 if (arm_is_secure_below_el3(env
)) {
12671 if (attrs
->secure
) {
12673 !(env
->cp15
.vstcr_el2
.raw_tcr
& (VSTCR_SA
| VSTCR_SW
));
12676 !((env
->cp15
.vtcr_el2
.raw_tcr
& (VTCR_NSA
| VTCR_NSW
))
12677 || (env
->cp15
.vstcr_el2
.raw_tcr
& VSTCR_SA
));
12683 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12685 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12689 /* The page table entries may downgrade secure to non-secure, but
12690 * cannot upgrade an non-secure translation regime's attributes
12693 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
12694 attrs
->user
= regime_is_user(env
, mmu_idx
);
12696 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12697 * In v7 and earlier it affects all stage 1 translations.
12699 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
12700 && !arm_feature(env
, ARM_FEATURE_V8
)) {
12701 if (regime_el(env
, mmu_idx
) == 3) {
12702 address
+= env
->cp15
.fcseidr_s
;
12704 address
+= env
->cp15
.fcseidr_ns
;
12708 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
12710 *page_size
= TARGET_PAGE_SIZE
;
12712 if (arm_feature(env
, ARM_FEATURE_V8
)) {
12714 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
12715 phys_ptr
, attrs
, prot
, page_size
, fi
);
12716 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
12718 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
12719 phys_ptr
, prot
, page_size
, fi
);
12722 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
12723 phys_ptr
, prot
, fi
);
12725 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
12726 " mmu_idx %u -> %s (prot %c%c%c)\n",
12727 access_type
== MMU_DATA_LOAD
? "reading" :
12728 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
12729 (uint32_t)address
, mmu_idx
,
12730 ret
? "Miss" : "Hit",
12731 *prot
& PAGE_READ
? 'r' : '-',
12732 *prot
& PAGE_WRITE
? 'w' : '-',
12733 *prot
& PAGE_EXEC
? 'x' : '-');
12738 /* Definitely a real MMU, not an MPU */
12740 if (regime_translation_disabled(env
, mmu_idx
)) {
12745 * MMU disabled. S1 addresses within aa64 translation regimes are
12746 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
12748 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
12749 int r_el
= regime_el(env
, mmu_idx
);
12750 if (arm_el_is_aa64(env
, r_el
)) {
12751 int pamax
= arm_pamax(env_archcpu(env
));
12752 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
].raw_tcr
;
12755 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12756 if (access_type
== MMU_INST_FETCH
) {
12757 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12759 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
12760 addrtop
= (tbi
? 55 : 63);
12762 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
12763 fi
->type
= ARMFault_AddressSize
;
12765 fi
->stage2
= false;
12770 * When TBI is disabled, we've just validated that all of the
12771 * bits above PAMax are zero, so logically we only need to
12772 * clear the top byte for TBI. But it's clearer to follow
12773 * the pseudocode set of addrdesc.paddress.
12775 address
= extract64(address
, 0, 52);
12778 *phys_ptr
= address
;
12779 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12780 *page_size
= TARGET_PAGE_SIZE
;
12782 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
12783 hcr
= arm_hcr_el2_eff(env
);
12784 cacheattrs
->shareability
= 0;
12785 if (hcr
& HCR_DC
) {
12786 if (hcr
& HCR_DCT
) {
12787 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
12789 memattr
= 0xff; /* Normal, WB, RWA */
12791 } else if (access_type
== MMU_INST_FETCH
) {
12792 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
12793 memattr
= 0xee; /* Normal, WT, RA, NT */
12795 memattr
= 0x44; /* Normal, NC, No */
12797 cacheattrs
->shareability
= 2; /* outer sharable */
12799 memattr
= 0x00; /* Device, nGnRnE */
12801 cacheattrs
->attrs
= memattr
;
12805 if (regime_using_lpae_format(env
, mmu_idx
)) {
12806 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, false,
12807 phys_ptr
, attrs
, prot
, page_size
,
12809 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
12810 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
12811 phys_ptr
, attrs
, prot
, page_size
, fi
);
12813 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
12814 phys_ptr
, prot
, page_size
, fi
);
12818 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
12821 ARMCPU
*cpu
= ARM_CPU(cs
);
12822 CPUARMState
*env
= &cpu
->env
;
12824 target_ulong page_size
;
12827 ARMMMUFaultInfo fi
= {};
12828 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
12829 ARMCacheAttrs cacheattrs
= {};
12831 *attrs
= (MemTxAttrs
) {};
12833 ret
= get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &phys_addr
,
12834 attrs
, &prot
, &page_size
, &fi
, &cacheattrs
);
12844 /* Note that signed overflow is undefined in C. The following routines are
12845 careful to use unsigned types where modulo arithmetic is required.
12846 Failure to do so _will_ break on newer gcc. */
12848 /* Signed saturating arithmetic. */
12850 /* Perform 16-bit signed saturating addition. */
12851 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
12856 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
12865 /* Perform 8-bit signed saturating addition. */
12866 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
12871 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
12880 /* Perform 16-bit signed saturating subtraction. */
12881 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
12886 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
12895 /* Perform 8-bit signed saturating subtraction. */
12896 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
12901 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
12910 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12911 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12912 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12913 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12916 #include "op_addsub.h"
12918 /* Unsigned saturating arithmetic. */
12919 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
12928 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
12936 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
12945 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
12953 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12954 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12955 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12956 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12959 #include "op_addsub.h"
12961 /* Signed modulo arithmetic. */
12962 #define SARITH16(a, b, n, op) do { \
12964 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12965 RESULT(sum, n, 16); \
12967 ge |= 3 << (n * 2); \
12970 #define SARITH8(a, b, n, op) do { \
12972 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12973 RESULT(sum, n, 8); \
12979 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12980 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12981 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12982 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12986 #include "op_addsub.h"
12988 /* Unsigned modulo arithmetic. */
12989 #define ADD16(a, b, n) do { \
12991 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12992 RESULT(sum, n, 16); \
12993 if ((sum >> 16) == 1) \
12994 ge |= 3 << (n * 2); \
12997 #define ADD8(a, b, n) do { \
12999 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
13000 RESULT(sum, n, 8); \
13001 if ((sum >> 8) == 1) \
13005 #define SUB16(a, b, n) do { \
13007 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
13008 RESULT(sum, n, 16); \
13009 if ((sum >> 16) == 0) \
13010 ge |= 3 << (n * 2); \
13013 #define SUB8(a, b, n) do { \
13015 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
13016 RESULT(sum, n, 8); \
13017 if ((sum >> 8) == 0) \
13024 #include "op_addsub.h"
13026 /* Halved signed arithmetic. */
13027 #define ADD16(a, b, n) \
13028 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
13029 #define SUB16(a, b, n) \
13030 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
13031 #define ADD8(a, b, n) \
13032 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
13033 #define SUB8(a, b, n) \
13034 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
13037 #include "op_addsub.h"
13039 /* Halved unsigned arithmetic. */
13040 #define ADD16(a, b, n) \
13041 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
13042 #define SUB16(a, b, n) \
13043 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
13044 #define ADD8(a, b, n) \
13045 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
13046 #define SUB8(a, b, n) \
13047 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
13050 #include "op_addsub.h"
13052 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
13060 /* Unsigned sum of absolute byte differences. */
13061 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
13064 sum
= do_usad(a
, b
);
13065 sum
+= do_usad(a
>> 8, b
>> 8);
13066 sum
+= do_usad(a
>> 16, b
>> 16);
13067 sum
+= do_usad(a
>> 24, b
>> 24);
13071 /* For ARMv6 SEL instruction. */
13072 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
13084 mask
|= 0xff000000;
13085 return (a
& mask
) | (b
& ~mask
);
13089 * The upper bytes of val (above the number specified by 'bytes') must have
13090 * been zeroed out by the caller.
13092 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13096 stl_le_p(buf
, val
);
13098 /* zlib crc32 converts the accumulator and output to one's complement. */
13099 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
13102 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
13106 stl_le_p(buf
, val
);
13108 /* Linux crc32c converts the output to one's complement. */
13109 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
13112 /* Return the exception level to which FP-disabled exceptions should
13113 * be taken, or 0 if FP is enabled.
13115 int fp_exception_el(CPUARMState
*env
, int cur_el
)
13117 #ifndef CONFIG_USER_ONLY
13118 /* CPACR and the CPTR registers don't exist before v6, so FP is
13119 * always accessible
13121 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
13125 if (arm_feature(env
, ARM_FEATURE_M
)) {
13126 /* CPACR can cause a NOCP UsageFault taken to current security state */
13127 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
13131 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
13132 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
13133 /* FP insns cause a NOCP UsageFault taken to Secure */
13141 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
13142 * 0, 2 : trap EL0 and EL1/PL1 accesses
13143 * 1 : trap only EL0 accesses
13144 * 3 : trap no accesses
13145 * This register is ignored if E2H+TGE are both set.
13147 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
13148 int fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
13153 if (cur_el
== 0 || cur_el
== 1) {
13154 /* Trap to PL1, which might be EL1 or EL3 */
13155 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
13160 if (cur_el
== 3 && !is_a64(env
)) {
13161 /* Secure PL1 running at EL3 */
13176 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
13177 * to control non-secure access to the FPU. It doesn't have any
13178 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
13180 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
13181 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
13182 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
13183 /* FP insns act as UNDEF */
13184 return cur_el
== 2 ? 2 : 1;
13188 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
13189 * check because zero bits in the registers mean "don't trap".
13192 /* CPTR_EL2 : present in v7VE or v8 */
13193 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
13194 && arm_is_el2_enabled(env
)) {
13195 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
13199 /* CPTR_EL3 : present in v8 */
13200 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
13201 /* Trap all FP ops to EL3 */
13208 /* Return the exception level we're running at if this is our mmu_idx */
13209 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
13211 if (mmu_idx
& ARM_MMU_IDX_M
) {
13212 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
13216 case ARMMMUIdx_E10_0
:
13217 case ARMMMUIdx_E20_0
:
13218 case ARMMMUIdx_SE10_0
:
13219 case ARMMMUIdx_SE20_0
:
13221 case ARMMMUIdx_E10_1
:
13222 case ARMMMUIdx_E10_1_PAN
:
13223 case ARMMMUIdx_SE10_1
:
13224 case ARMMMUIdx_SE10_1_PAN
:
13227 case ARMMMUIdx_E20_2
:
13228 case ARMMMUIdx_E20_2_PAN
:
13229 case ARMMMUIdx_SE2
:
13230 case ARMMMUIdx_SE20_2
:
13231 case ARMMMUIdx_SE20_2_PAN
:
13233 case ARMMMUIdx_SE3
:
13236 g_assert_not_reached();
13241 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
13243 g_assert_not_reached();
13247 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
13252 if (arm_feature(env
, ARM_FEATURE_M
)) {
13253 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
13256 /* See ARM pseudo-function ELIsInHost. */
13259 hcr
= arm_hcr_el2_eff(env
);
13260 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
13261 idx
= ARMMMUIdx_E20_0
;
13263 idx
= ARMMMUIdx_E10_0
;
13267 if (env
->pstate
& PSTATE_PAN
) {
13268 idx
= ARMMMUIdx_E10_1_PAN
;
13270 idx
= ARMMMUIdx_E10_1
;
13274 /* Note that TGE does not apply at EL2. */
13275 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
13276 if (env
->pstate
& PSTATE_PAN
) {
13277 idx
= ARMMMUIdx_E20_2_PAN
;
13279 idx
= ARMMMUIdx_E20_2
;
13282 idx
= ARMMMUIdx_E2
;
13286 return ARMMMUIdx_SE3
;
13288 g_assert_not_reached();
13291 if (arm_is_secure_below_el3(env
)) {
13292 idx
&= ~ARM_MMU_IDX_A_NS
;
13298 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
13300 return arm_mmu_idx_el(env
, arm_current_el(env
));
13303 #ifndef CONFIG_USER_ONLY
13304 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
13306 return stage_1_mmu_idx(arm_mmu_idx(env
));
13310 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
13312 CPUARMTBFlags flags
)
13314 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
13315 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
13317 if (arm_singlestep_active(env
)) {
13318 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
13323 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
13325 CPUARMTBFlags flags
)
13327 bool sctlr_b
= arm_sctlr_b(env
);
13330 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
13332 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
13333 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
13335 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
13337 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
13340 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
13343 CPUARMTBFlags flags
= {};
13344 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
13346 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
13347 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
13348 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
13351 if (arm_v7m_is_handler_mode(env
)) {
13352 DP_TBFLAG_M32(flags
, HANDLER
, 1);
13356 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
13357 * is suppressing them because the requested execution priority
13360 if (arm_feature(env
, ARM_FEATURE_V8
) &&
13361 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
13362 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
13363 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
13366 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
13369 static CPUARMTBFlags
rebuild_hflags_aprofile(CPUARMState
*env
)
13371 CPUARMTBFlags flags
= {};
13373 DP_TBFLAG_ANY(flags
, DEBUG_TARGET_EL
, arm_debug_target_el(env
));
13377 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
13380 CPUARMTBFlags flags
= rebuild_hflags_aprofile(env
);
13381 int el
= arm_current_el(env
);
13383 if (arm_sctlr(env
, el
) & SCTLR_A
) {
13384 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
13387 if (arm_el_is_aa64(env
, 1)) {
13388 DP_TBFLAG_A32(flags
, VFPEN
, 1);
13391 if (el
< 2 && env
->cp15
.hstr_el2
&&
13392 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
13393 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
13396 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
13399 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
13402 CPUARMTBFlags flags
= rebuild_hflags_aprofile(env
);
13403 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
13404 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
13408 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
13410 /* Get control bits for tagged addresses. */
13411 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
13412 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
13414 DP_TBFLAG_A64(flags
, TBII
, tbii
);
13415 DP_TBFLAG_A64(flags
, TBID
, tbid
);
13417 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
13418 int sve_el
= sve_exception_el(env
, el
);
13422 * If SVE is disabled, but FP is enabled,
13423 * then the effective len is 0.
13425 if (sve_el
!= 0 && fp_el
== 0) {
13428 zcr_len
= sve_zcr_len_for_el(env
, el
);
13430 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
13431 DP_TBFLAG_A64(flags
, ZCR_LEN
, zcr_len
);
13434 sctlr
= regime_sctlr(env
, stage1
);
13436 if (sctlr
& SCTLR_A
) {
13437 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
13440 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
13441 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
13444 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
13446 * In order to save space in flags, we record only whether
13447 * pauth is "inactive", meaning all insns are implemented as
13448 * a nop, or "active" when some action must be performed.
13449 * The decision of which action to take is left to a helper.
13451 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
13452 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
13456 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
13457 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
13458 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
13459 DP_TBFLAG_A64(flags
, BT
, 1);
13463 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
13464 if (!(env
->pstate
& PSTATE_UAO
)) {
13466 case ARMMMUIdx_E10_1
:
13467 case ARMMMUIdx_E10_1_PAN
:
13468 case ARMMMUIdx_SE10_1
:
13469 case ARMMMUIdx_SE10_1_PAN
:
13470 /* TODO: ARMv8.3-NV */
13471 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
13473 case ARMMMUIdx_E20_2
:
13474 case ARMMMUIdx_E20_2_PAN
:
13475 case ARMMMUIdx_SE20_2
:
13476 case ARMMMUIdx_SE20_2_PAN
:
13478 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
13479 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
13481 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
13482 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
13490 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
13492 * Set MTE_ACTIVE if any access may be Checked, and leave clear
13493 * if all accesses must be Unchecked:
13494 * 1) If no TBI, then there are no tags in the address to check,
13495 * 2) If Tag Check Override, then all accesses are Unchecked,
13496 * 3) If Tag Check Fail == 0, then Checked access have no effect,
13497 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
13499 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
13500 DP_TBFLAG_A64(flags
, ATA
, 1);
13502 && !(env
->pstate
& PSTATE_TCO
)
13503 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
13504 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
13507 /* And again for unprivileged accesses, if required. */
13508 if (EX_TBFLAG_A64(flags
, UNPRIV
)
13510 && !(env
->pstate
& PSTATE_TCO
)
13511 && (sctlr
& SCTLR_TCF0
)
13512 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
13513 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
13515 /* Cache TCMA as well as TBI. */
13516 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
13519 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
13522 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
13524 int el
= arm_current_el(env
);
13525 int fp_el
= fp_exception_el(env
, el
);
13526 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13529 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
13530 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
13531 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13533 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13537 void arm_rebuild_hflags(CPUARMState
*env
)
13539 env
->hflags
= rebuild_hflags_internal(env
);
13543 * If we have triggered a EL state change we can't rely on the
13544 * translator having passed it to us, we need to recompute.
13546 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
13548 int el
= arm_current_el(env
);
13549 int fp_el
= fp_exception_el(env
, el
);
13550 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13552 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13555 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
13557 int fp_el
= fp_exception_el(env
, el
);
13558 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13560 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13564 * If we have triggered a EL state change we can't rely on the
13565 * translator having passed it to us, we need to recompute.
13567 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
13569 int el
= arm_current_el(env
);
13570 int fp_el
= fp_exception_el(env
, el
);
13571 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13572 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13575 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
13577 int fp_el
= fp_exception_el(env
, el
);
13578 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13580 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13583 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
13585 int fp_el
= fp_exception_el(env
, el
);
13586 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13588 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
13591 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
13593 #ifdef CONFIG_DEBUG_TCG
13594 CPUARMTBFlags c
= env
->hflags
;
13595 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
13597 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
13598 fprintf(stderr
, "TCG hflags mismatch "
13599 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
13600 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
13601 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
13607 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
13608 target_ulong
*cs_base
, uint32_t *pflags
)
13610 CPUARMTBFlags flags
;
13612 assert_hflags_rebuild_correctly(env
);
13613 flags
= env
->hflags
;
13615 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
13617 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
13618 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
13621 *pc
= env
->regs
[15];
13623 if (arm_feature(env
, ARM_FEATURE_M
)) {
13624 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
13625 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
13626 != env
->v7m
.secure
) {
13627 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
13630 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
13631 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
13632 (env
->v7m
.secure
&&
13633 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
13635 * ASPEN is set, but FPCA/SFPA indicate that there is no
13636 * active FP context; we must create a new FP context before
13637 * executing any FP insn.
13639 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
13642 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
13643 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
13644 DP_TBFLAG_M32(flags
, LSPACT
, 1);
13648 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
13649 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
13651 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
13652 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
13654 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
13655 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
13657 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
13658 DP_TBFLAG_A32(flags
, VFPEN
, 1);
13662 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
13663 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
13667 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13668 * states defined in the ARM ARM for software singlestep:
13669 * SS_ACTIVE PSTATE.SS State
13670 * 0 x Inactive (the TB flag for SS is always 0)
13671 * 1 0 Active-pending
13672 * 1 1 Active-not-pending
13673 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
13675 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
13676 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
13679 *pflags
= flags
.flags
;
13680 *cs_base
= flags
.flags2
;
13683 #ifdef TARGET_AARCH64
13685 * The manual says that when SVE is enabled and VQ is widened the
13686 * implementation is allowed to zero the previously inaccessible
13687 * portion of the registers. The corollary to that is that when
13688 * SVE is enabled and VQ is narrowed we are also allowed to zero
13689 * the now inaccessible portion of the registers.
13691 * The intent of this is that no predicate bit beyond VQ is ever set.
13692 * Which means that some operations on predicate registers themselves
13693 * may operate on full uint64_t or even unrolled across the maximum
13694 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13695 * may well be cheaper than conditionals to restrict the operation
13696 * to the relevant portion of a uint16_t[16].
13698 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
13703 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
13704 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
13706 /* Zap the high bits of the zregs. */
13707 for (i
= 0; i
< 32; i
++) {
13708 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
13711 /* Zap the high bits of the pregs and ffr. */
13714 pmask
= ~(-1ULL << (16 * (vq
& 3)));
13716 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
13717 for (i
= 0; i
< 17; ++i
) {
13718 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
13725 * Notice a change in SVE vector size when changing EL.
13727 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
13728 int new_el
, bool el0_a64
)
13730 ARMCPU
*cpu
= env_archcpu(env
);
13731 int old_len
, new_len
;
13732 bool old_a64
, new_a64
;
13734 /* Nothing to do if no SVE. */
13735 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
13739 /* Nothing to do if FP is disabled in either EL. */
13740 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
13745 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13746 * at ELx, or not available because the EL is in AArch32 state, then
13747 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13748 * has an effective value of 0".
13750 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13751 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13752 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13753 * we already have the correct register contents when encountering the
13754 * vq0->vq0 transition between EL0->EL1.
13756 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
13757 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
13758 ? sve_zcr_len_for_el(env
, old_el
) : 0);
13759 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
13760 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
13761 ? sve_zcr_len_for_el(env
, new_el
) : 0);
13763 /* When changing vector length, clear inaccessible state. */
13764 if (new_len
< old_len
) {
13765 aarch64_sve_narrow_vq(env
, new_len
+ 1);