hw/timer/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Contributions after 2012-01-13 are licensed under the terms of the
  11  * GNU GPL, version 2 or (at your option) any later version.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/sysbus.h"
  16 #include "qemu/timer.h"
  17 #include "sysemu/sysemu.h"
  18 #include "qemu/cutils.h"
  19 #include "qemu/log.h"
  20
  21 //#define DEBUG_PL031
  22
  23 #ifdef DEBUG_PL031
  24 #define DPRINTF(fmt, ...) \
  25 do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
  26 #else
  27 #define DPRINTF(fmt, ...) do {} while(0)
  28 #endif
  29
  30 #define RTC_DR      0x00    /* Data read register */
  31 #define RTC_MR      0x04    /* Match register */
  32 #define RTC_LR      0x08    /* Data load register */
  33 #define RTC_CR      0x0c    /* Control register */
  34 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  35 #define RTC_RIS     0x14    /* Raw interrupt status register */
  36 #define RTC_MIS     0x18    /* Masked interrupt status register */
  37 #define RTC_ICR     0x1c    /* Interrupt clear register */
  38
  39 #define TYPE_PL031 "pl031"
  40 #define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
  41
  42 typedef struct PL031State {
  43     SysBusDevice parent_obj;
  44
  45     MemoryRegion iomem;
  46     QEMUTimer *timer;
  47     qemu_irq irq;
  48
  49     /* Needed to preserve the tick_count across migration, even if the
  50      * absolute value of the rtc_clock is different on the source and
  51      * destination.
  52      */
  53     uint32_t tick_offset_vmstate;
  54     uint32_t tick_offset;
  55
  56     uint32_t mr;
  57     uint32_t lr;
  58     uint32_t cr;
  59     uint32_t im;
  60     uint32_t is;
  61 } PL031State;
  62
  63 static const unsigned char pl031_id[] = {
  64     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  65     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  66 };
  67
  68 static void pl031_update(PL031State *s)
  69 {
  70     qemu_set_irq(s->irq, s->is & s->im);
  71 }
  72
  73 static void pl031_interrupt(void * opaque)
  74 {
  75     PL031State *s = (PL031State *)opaque;
  76
  77     s->is = 1;
  78     DPRINTF("Alarm raised\n");
  79     pl031_update(s);
  80 }
  81
  82 static uint32_t pl031_get_count(PL031State *s)
  83 {
  84     int64_t now = qemu_clock_get_ns(rtc_clock);
  85     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  86 }
  87
  88 static void pl031_set_alarm(PL031State *s)
  89 {
  90     uint32_t ticks;
  91
  92     /* The timer wraps around.  This subtraction also wraps in the same way,
  93        and gives correct results when alarm < now_ticks.  */
  94     ticks = s->mr - pl031_get_count(s);
  95     DPRINTF("Alarm set in %ud ticks\n", ticks);
  96     if (ticks == 0) {
  97         timer_del(s->timer);
  98         pl031_interrupt(s);
  99     } else {
 100         int64_t now = qemu_clock_get_ns(rtc_clock);
 101         timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
 102     }
 103 }
 104
 105 static uint64_t pl031_read(void *opaque, hwaddr offset,
 106                            unsigned size)
 107 {
 108     PL031State *s = (PL031State *)opaque;
 109
 110     if (offset >= 0xfe0  &&  offset < 0x1000)
 111         return pl031_id[(offset - 0xfe0) >> 2];
 112
 113     switch (offset) {
 114     case RTC_DR:
 115         return pl031_get_count(s);
 116     case RTC_MR:
 117         return s->mr;
 118     case RTC_IMSC:
 119         return s->im;
 120     case RTC_RIS:
 121         return s->is;
 122     case RTC_LR:
 123         return s->lr;
 124     case RTC_CR:
 125         /* RTC is permanently enabled.  */
 126         return 1;
 127     case RTC_MIS:
 128         return s->is & s->im;
 129     case RTC_ICR:
 130         qemu_log_mask(LOG_GUEST_ERROR,
 131                       "pl031: read of write-only register at offset 0x%x\n",
 132                       (int)offset);
 133         break;
 134     default:
 135         qemu_log_mask(LOG_GUEST_ERROR,
 136                       "pl031_read: Bad offset 0x%x\n", (int)offset);
 137         break;
 138     }
 139
 140     return 0;
 141 }
 142
 143 static void pl031_write(void * opaque, hwaddr offset,
 144                         uint64_t value, unsigned size)
 145 {
 146     PL031State *s = (PL031State *)opaque;
 147
 148
 149     switch (offset) {
 150     case RTC_LR:
 151         s->tick_offset += value - pl031_get_count(s);
 152         pl031_set_alarm(s);
 153         break;
 154     case RTC_MR:
 155         s->mr = value;
 156         pl031_set_alarm(s);
 157         break;
 158     case RTC_IMSC:
 159         s->im = value & 1;
 160         DPRINTF("Interrupt mask %d\n", s->im);
 161         pl031_update(s);
 162         break;
 163     case RTC_ICR:
 164         /* The PL031 documentation (DDI0224B) states that the interrupt is
 165            cleared when bit 0 of the written value is set.  However the
 166            arm926e documentation (DDI0287B) states that the interrupt is
 167            cleared when any value is written.  */
 168         DPRINTF("Interrupt cleared");
 169         s->is = 0;
 170         pl031_update(s);
 171         break;
 172     case RTC_CR:
 173         /* Written value is ignored.  */
 174         break;
 175
 176     case RTC_DR:
 177     case RTC_MIS:
 178     case RTC_RIS:
 179         qemu_log_mask(LOG_GUEST_ERROR,
 180                       "pl031: write to read-only register at offset 0x%x\n",
 181                       (int)offset);
 182         break;
 183
 184     default:
 185         qemu_log_mask(LOG_GUEST_ERROR,
 186                       "pl031_write: Bad offset 0x%x\n", (int)offset);
 187         break;
 188     }
 189 }
 190
 191 static const MemoryRegionOps pl031_ops = {
 192     .read = pl031_read,
 193     .write = pl031_write,
 194     .endianness = DEVICE_NATIVE_ENDIAN,
 195 };
 196
 197 static void pl031_init(Object *obj)
 198 {
 199     PL031State *s = PL031(obj);
 200     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 201     struct tm tm;
 202
 203     memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
 204     sysbus_init_mmio(dev, &s->iomem);
 205
 206     sysbus_init_irq(dev, &s->irq);
 207     qemu_get_timedate(&tm, 0);
 208     s->tick_offset = mktimegm(&tm) -
 209         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 210
 211     s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
 212 }
 213
 214 static int pl031_pre_save(void *opaque)
 215 {
 216     PL031State *s = opaque;
 217
 218     /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
 219      * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility.  */
 220     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 221     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
 222
 223     return 0;
 224 }
 225
 226 static int pl031_post_load(void *opaque, int version_id)
 227 {
 228     PL031State *s = opaque;
 229
 230     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 231     s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
 232     pl031_set_alarm(s);
 233     return 0;
 234 }
 235
 236 static const VMStateDescription vmstate_pl031 = {
 237     .name = "pl031",
 238     .version_id = 1,
 239     .minimum_version_id = 1,
 240     .pre_save = pl031_pre_save,
 241     .post_load = pl031_post_load,
 242     .fields = (VMStateField[]) {
 243         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
 244         VMSTATE_UINT32(mr, PL031State),
 245         VMSTATE_UINT32(lr, PL031State),
 246         VMSTATE_UINT32(cr, PL031State),
 247         VMSTATE_UINT32(im, PL031State),
 248         VMSTATE_UINT32(is, PL031State),
 249         VMSTATE_END_OF_LIST()
 250     }
 251 };
 252
 253 static void pl031_class_init(ObjectClass *klass, void *data)
 254 {
 255     DeviceClass *dc = DEVICE_CLASS(klass);
 256
 257     dc->vmsd = &vmstate_pl031;
 258 }
 259
 260 static const TypeInfo pl031_info = {
 261     .name          = TYPE_PL031,
 262     .parent        = TYPE_SYS_BUS_DEVICE,
 263     .instance_size = sizeof(PL031State),
 264     .instance_init = pl031_init,
 265     .class_init    = pl031_class_init,
 266 };
 267
 268 static void pl031_register_types(void)
 269 {
 270     type_register_static(&pl031_info);
 271 }
 272
 273 type_init(pl031_register_types)