hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/units.h"
  33 #include "hw/loader.h"
  34 #include "sysemu/arch_init.h"
  35 #include "hw/i2c/smbus_eeprom.h"
  36 #include "hw/rtc/mc146818rtc.h"
  37 #include "sysemu/kvm.h"
  38 #include "hw/kvm/clock.h"
  39 #include "hw/pci-host/q35.h"
  40 #include "hw/qdev-properties.h"
  41 #include "hw/i386/x86.h"
  42 #include "hw/i386/pc.h"
  43 #include "hw/i386/ich9.h"
  44 #include "hw/i386/amd_iommu.h"
  45 #include "hw/i386/intel_iommu.h"
  46 #include "hw/display/ramfb.h"
  47 #include "hw/firmware/smbios.h"
  48 #include "hw/ide/pci.h"
  49 #include "hw/ide/ahci.h"
  50 #include "hw/usb.h"
  51 #include "qapi/error.h"
  52 #include "qemu/error-report.h"
  53 #include "sysemu/numa.h"
  54 #include "hw/hyperv/vmbus-bridge.h"
  55 #include "hw/mem/nvdimm.h"
  56 #include "hw/i386/acpi-build.h"
  57
  58 /* ICH9 AHCI has 6 ports */
  59 #define MAX_SATA_PORTS     6
  60
  61 struct ehci_companions {
  62     const char *name;
  63     int func;
  64     int port;
  65 };
  66
  67 static const struct ehci_companions ich9_1d[] = {
  68     { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
  69     { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
  70     { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
  71 };
  72
  73 static const struct ehci_companions ich9_1a[] = {
  74     { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
  75     { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
  76     { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
  77 };
  78
  79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  80 {
  81     const struct ehci_companions *comp;
  82     PCIDevice *ehci, *uhci;
  83     BusState *usbbus;
  84     const char *name;
  85     int i;
  86
  87     switch (slot) {
  88     case 0x1d:
  89         name = "ich9-usb-ehci1";
  90         comp = ich9_1d;
  91         break;
  92     case 0x1a:
  93         name = "ich9-usb-ehci2";
  94         comp = ich9_1a;
  95         break;
  96     default:
  97         return -1;
  98     }
  99
 100     ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
 101     pci_realize_and_unref(ehci, bus, &error_fatal);
 102     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 103
 104     for (i = 0; i < 3; i++) {
 105         uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
 106                                      comp[i].name);
 107         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 108         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 109         pci_realize_and_unref(uhci, bus, &error_fatal);
 110     }
 111     return 0;
 112 }
 113
 114 /* PC hardware initialisation */
 115 static void pc_q35_init(MachineState *machine)
 116 {
 117     PCMachineState *pcms = PC_MACHINE(machine);
 118     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 119     X86MachineState *x86ms = X86_MACHINE(machine);
 120     Q35PCIHost *q35_host;
 121     PCIHostState *phb;
 122     PCIBus *host_bus;
 123     PCIDevice *lpc;
 124     DeviceState *lpc_dev;
 125     BusState *idebus[MAX_SATA_PORTS];
 126     ISADevice *rtc_state;
 127     MemoryRegion *system_io = get_system_io();
 128     MemoryRegion *pci_memory;
 129     MemoryRegion *rom_memory;
 130     MemoryRegion *ram_memory;
 131     GSIState *gsi_state;
 132     ISABus *isa_bus;
 133     int i;
 134     ICH9LPCState *ich9_lpc;
 135     PCIDevice *ahci;
 136     ram_addr_t lowmem;
 137     DriveInfo *hd[MAX_SATA_PORTS];
 138     MachineClass *mc = MACHINE_GET_CLASS(machine);
 139
 140     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 141      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 142      * also known as MMCFG).
 143      * If it doesn't, we need to split it in chunks below and above 4G.
 144      * In any case, try to make sure that guest addresses aligned at
 145      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 146      */
 147     if (machine->ram_size >= 0xb0000000) {
 148         lowmem = 0x80000000;
 149     } else {
 150         lowmem = 0xb0000000;
 151     }
 152
 153     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 154      * min(qemu limit, user limit).
 155      */
 156     if (!pcms->max_ram_below_4g) {
 157         pcms->max_ram_below_4g = 4 * GiB;
 158     }
 159     if (lowmem > pcms->max_ram_below_4g) {
 160         lowmem = pcms->max_ram_below_4g;
 161         if (machine->ram_size - lowmem > lowmem &&
 162             lowmem & (1 * GiB - 1)) {
 163             warn_report("There is possibly poor performance as the ram size "
 164                         " (0x%" PRIx64 ") is more then twice the size of"
 165                         " max-ram-below-4g (%"PRIu64") and"
 166                         " max-ram-below-4g is not a multiple of 1G.",
 167                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 168         }
 169     }
 170
 171     if (machine->ram_size >= lowmem) {
 172         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 173         x86ms->below_4g_mem_size = lowmem;
 174     } else {
 175         x86ms->above_4g_mem_size = 0;
 176         x86ms->below_4g_mem_size = machine->ram_size;
 177     }
 178
 179     x86_cpus_init(x86ms, pcmc->default_cpu_version);
 180
 181     kvmclock_create(pcmc->kvmclock_create_always);
 182
 183     /* pci enabled */
 184     if (pcmc->pci_enabled) {
 185         pci_memory = g_new(MemoryRegion, 1);
 186         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 187         rom_memory = pci_memory;
 188     } else {
 189         pci_memory = NULL;
 190         rom_memory = get_system_memory();
 191     }
 192
 193     pc_guest_info_init(pcms);
 194
 195     if (pcmc->smbios_defaults) {
 196         /* These values are guest ABI, do not change */
 197         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 198                             mc->name, pcmc->smbios_legacy_mode,
 199                             pcmc->smbios_uuid_encoded,
 200                             SMBIOS_ENTRY_POINT_21);
 201     }
 202
 203     /* allocate ram and load rom/bios */
 204     pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory);
 205
 206     /* create pci host bus */
 207     q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
 208
 209     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
 210     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
 211                              OBJECT(ram_memory), NULL);
 212     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM,
 213                              OBJECT(pci_memory), NULL);
 214     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM,
 215                              OBJECT(get_system_memory()), NULL);
 216     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM,
 217                              OBJECT(system_io), NULL);
 218     object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE,
 219                             x86ms->below_4g_mem_size, NULL);
 220     object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE,
 221                             x86ms->above_4g_mem_size, NULL);
 222     /* pci */
 223     sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
 224     phb = PCI_HOST_BRIDGE(q35_host);
 225     host_bus = phb->bus;
 226     /* create ISA bus */
 227     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 228                                           ICH9_LPC_FUNC), true,
 229                                           TYPE_ICH9_LPC_DEVICE);
 230
 231     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 232                              TYPE_HOTPLUG_HANDLER,
 233                              (Object **)&x86ms->acpi_dev,
 234                              object_property_allow_set_link,
 235                              OBJ_PROP_LINK_STRONG);
 236     object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 237                              OBJECT(lpc), &error_abort);
 238
 239     /* irq lines */
 240     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 241
 242     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 243     lpc_dev = DEVICE(lpc);
 244     for (i = 0; i < GSI_NUM_PINS; i++) {
 245         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
 246     }
 247     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 248                  ICH9_LPC_NB_PIRQS);
 249     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 250     isa_bus = ich9_lpc->isa_bus;
 251
 252     pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 253
 254     if (pcmc->pci_enabled) {
 255         ioapic_init_gsi(gsi_state, "q35");
 256     }
 257
 258     if (tcg_enabled()) {
 259         x86_register_ferr_irq(x86ms->gsi[13]);
 260     }
 261
 262     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 263     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 264         pcms->vmport = ON_OFF_AUTO_ON;
 265     }
 266
 267     /* init basic PC hardware */
 268     pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
 269                          0xff0104);
 270
 271     /* connect pm stuff to lpc */
 272     ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
 273
 274     if (pcms->sata_enabled) {
 275         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 276         ahci = pci_create_simple_multifunction(host_bus,
 277                                                PCI_DEVFN(ICH9_SATA1_DEV,
 278                                                          ICH9_SATA1_FUNC),
 279                                                true, "ich9-ahci");
 280         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 281         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 282         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 283         ide_drive_get(hd, ahci_get_num_ports(ahci));
 284         ahci_ide_create_devs(ahci, hd);
 285     } else {
 286         idebus[0] = idebus[1] = NULL;
 287     }
 288
 289     if (machine_usb(machine)) {
 290         /* Should we create 6 UHCI according to ich9 spec? */
 291         ehci_create_ich9_with_companions(host_bus, 0x1d);
 292     }
 293
 294     if (pcms->smbus_enabled) {
 295         /* TODO: Populate SPD eeprom data.  */
 296         pcms->smbus = ich9_smb_init(host_bus,
 297                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 298                                     0xb100);
 299         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 300     }
 301
 302     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 303
 304     /* the rest devices to which pci devfn is automatically assigned */
 305     pc_vga_init(isa_bus, host_bus);
 306     pc_nic_init(pcmc, isa_bus, host_bus);
 307
 308     if (machine->nvdimms_state->is_enabled) {
 309         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
 310                                x86_nvdimm_acpi_dsmio,
 311                                x86ms->fw_cfg, OBJECT(pcms));
 312     }
 313 }
 314
 315 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 316     static void pc_init_##suffix(MachineState *machine) \
 317     { \
 318         void (*compat)(MachineState *m) = (compatfn); \
 319         if (compat) { \
 320             compat(machine); \
 321         } \
 322         pc_q35_init(machine); \
 323     } \
 324     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 325
 326
 327 static void pc_q35_machine_options(MachineClass *m)
 328 {
 329     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 330     pcmc->default_nic_model = "e1000e";
 331     pcmc->pci_root_uid = 0;
 332
 333     m->family = "pc_q35";
 334     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 335     m->units_per_default_bus = 1;
 336     m->default_machine_opts = "firmware=bios-256k.bin";
 337     m->default_display = "std";
 338     m->default_kernel_irqchip_split = false;
 339     m->no_floppy = 1;
 340     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 341     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 342     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 343     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
 344     m->max_cpus = 288;
 345 }
 346
 347 static void pc_q35_6_1_machine_options(MachineClass *m)
 348 {
 349     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 350     pc_q35_machine_options(m);
 351     m->alias = "q35";
 352     pcmc->default_cpu_version = 1;
 353 }
 354
 355 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
 356                    pc_q35_6_1_machine_options);
 357
 358 static void pc_q35_6_0_machine_options(MachineClass *m)
 359 {
 360     pc_q35_6_1_machine_options(m);
 361     m->alias = NULL;
 362     compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
 363     compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
 364 }
 365
 366 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
 367                    pc_q35_6_0_machine_options);
 368
 369 static void pc_q35_5_2_machine_options(MachineClass *m)
 370 {
 371     pc_q35_6_0_machine_options(m);
 372     m->alias = NULL;
 373     compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
 374     compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
 375 }
 376
 377 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
 378                    pc_q35_5_2_machine_options);
 379
 380 static void pc_q35_5_1_machine_options(MachineClass *m)
 381 {
 382     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 383
 384     pc_q35_5_2_machine_options(m);
 385     m->alias = NULL;
 386     compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
 387     compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
 388     pcmc->kvmclock_create_always = false;
 389     pcmc->pci_root_uid = 1;
 390 }
 391
 392 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
 393                    pc_q35_5_1_machine_options);
 394
 395 static void pc_q35_5_0_machine_options(MachineClass *m)
 396 {
 397     pc_q35_5_1_machine_options(m);
 398     m->alias = NULL;
 399     m->numa_mem_supported = true;
 400     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
 401     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
 402     m->auto_enable_numa_with_memdev = false;
 403 }
 404
 405 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
 406                    pc_q35_5_0_machine_options);
 407
 408 static void pc_q35_4_2_machine_options(MachineClass *m)
 409 {
 410     pc_q35_5_0_machine_options(m);
 411     m->alias = NULL;
 412     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
 413     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
 414 }
 415
 416 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
 417                    pc_q35_4_2_machine_options);
 418
 419 static void pc_q35_4_1_machine_options(MachineClass *m)
 420 {
 421     pc_q35_4_2_machine_options(m);
 422     m->alias = NULL;
 423     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
 424     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
 425 }
 426
 427 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
 428                    pc_q35_4_1_machine_options);
 429
 430 static void pc_q35_4_0_1_machine_options(MachineClass *m)
 431 {
 432     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 433     pc_q35_4_1_machine_options(m);
 434     m->alias = NULL;
 435     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
 436     /*
 437      * This is the default machine for the 4.0-stable branch. It is basically
 438      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
 439      * 4.0 compat props.
 440      */
 441     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 442     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
 443 }
 444
 445 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
 446                    pc_q35_4_0_1_machine_options);
 447
 448 static void pc_q35_4_0_machine_options(MachineClass *m)
 449 {
 450     pc_q35_4_0_1_machine_options(m);
 451     m->default_kernel_irqchip_split = true;
 452     m->alias = NULL;
 453     /* Compat props are applied by the 4.0.1 machine */
 454 }
 455
 456 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 457                    pc_q35_4_0_machine_options);
 458
 459 static void pc_q35_3_1_machine_options(MachineClass *m)
 460 {
 461     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 462
 463     pc_q35_4_0_machine_options(m);
 464     m->default_kernel_irqchip_split = false;
 465     pcmc->do_not_add_smb_acpi = true;
 466     m->smbus_no_migration_support = true;
 467     m->alias = NULL;
 468     pcmc->pvh_enabled = false;
 469     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 470     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 471 }
 472
 473 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 474                    pc_q35_3_1_machine_options);
 475
 476 static void pc_q35_3_0_machine_options(MachineClass *m)
 477 {
 478     pc_q35_3_1_machine_options(m);
 479     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 480     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 481 }
 482
 483 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 484                     pc_q35_3_0_machine_options);
 485
 486 static void pc_q35_2_12_machine_options(MachineClass *m)
 487 {
 488     pc_q35_3_0_machine_options(m);
 489     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 490     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 491 }
 492
 493 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 494                    pc_q35_2_12_machine_options);
 495
 496 static void pc_q35_2_11_machine_options(MachineClass *m)
 497 {
 498     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 499
 500     pc_q35_2_12_machine_options(m);
 501     pcmc->default_nic_model = "e1000";
 502     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 503     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 504 }
 505
 506 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 507                    pc_q35_2_11_machine_options);
 508
 509 static void pc_q35_2_10_machine_options(MachineClass *m)
 510 {
 511     pc_q35_2_11_machine_options(m);
 512     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 513     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 514     m->auto_enable_numa_with_memhp = false;
 515 }
 516
 517 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 518                    pc_q35_2_10_machine_options);
 519
 520 static void pc_q35_2_9_machine_options(MachineClass *m)
 521 {
 522     pc_q35_2_10_machine_options(m);
 523     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 524     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 525 }
 526
 527 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 528                    pc_q35_2_9_machine_options);
 529
 530 static void pc_q35_2_8_machine_options(MachineClass *m)
 531 {
 532     pc_q35_2_9_machine_options(m);
 533     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 534     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 535 }
 536
 537 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 538                    pc_q35_2_8_machine_options);
 539
 540 static void pc_q35_2_7_machine_options(MachineClass *m)
 541 {
 542     pc_q35_2_8_machine_options(m);
 543     m->max_cpus = 255;
 544     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 545     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 546 }
 547
 548 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 549                    pc_q35_2_7_machine_options);
 550
 551 static void pc_q35_2_6_machine_options(MachineClass *m)
 552 {
 553     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 554
 555     pc_q35_2_7_machine_options(m);
 556     pcmc->legacy_cpu_hotplug = true;
 557     pcmc->linuxboot_dma_enabled = false;
 558     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 559     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 560 }
 561
 562 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 563                    pc_q35_2_6_machine_options);
 564
 565 static void pc_q35_2_5_machine_options(MachineClass *m)
 566 {
 567     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 568
 569     pc_q35_2_6_machine_options(m);
 570     x86mc->save_tsc_khz = false;
 571     m->legacy_fw_cfg_order = 1;
 572     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 573     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 574 }
 575
 576 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 577                    pc_q35_2_5_machine_options);
 578
 579 static void pc_q35_2_4_machine_options(MachineClass *m)
 580 {
 581     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 582
 583     pc_q35_2_5_machine_options(m);
 584     m->hw_version = "2.4.0";
 585     pcmc->broken_reserved_end = true;
 586     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 587     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 588 }
 589
 590 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 591                    pc_q35_2_4_machine_options);