6 /* MIPSnet register offsets */
8 #define MIPSNET_DEV_ID 0x00
9 #define MIPSNET_BUSY 0x08
10 #define MIPSNET_RX_DATA_COUNT 0x0c
11 #define MIPSNET_TX_DATA_COUNT 0x10
12 #define MIPSNET_INT_CTL 0x14
13 # define MIPSNET_INTCTL_TXDONE 0x00000001
14 # define MIPSNET_INTCTL_RXDONE 0x00000002
15 # define MIPSNET_INTCTL_TESTBIT 0x80000000
16 #define MIPSNET_INTERRUPT_INFO 0x18
17 #define MIPSNET_RX_DATA_BUFFER 0x1c
18 #define MIPSNET_TX_DATA_BUFFER 0x20
20 #define MAX_ETH_FRAME_SIZE 1514
22 #define TYPE_MIPS_NET "mipsnet"
23 #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
25 typedef struct MIPSnetState
{
26 SysBusDevice parent_obj
;
34 uint8_t rx_buffer
[MAX_ETH_FRAME_SIZE
];
35 uint8_t tx_buffer
[MAX_ETH_FRAME_SIZE
];
42 static void mipsnet_reset(MIPSnetState
*s
)
50 memset(s
->rx_buffer
, 0, MAX_ETH_FRAME_SIZE
);
51 memset(s
->tx_buffer
, 0, MAX_ETH_FRAME_SIZE
);
54 static void mipsnet_update_irq(MIPSnetState
*s
)
56 int isr
= !!s
->intctl
;
57 trace_mipsnet_irq(isr
, s
->intctl
);
58 qemu_set_irq(s
->irq
, isr
);
61 static int mipsnet_buffer_full(MIPSnetState
*s
)
63 if (s
->rx_count
>= MAX_ETH_FRAME_SIZE
)
68 static int mipsnet_can_receive(NetClientState
*nc
)
70 MIPSnetState
*s
= qemu_get_nic_opaque(nc
);
74 return !mipsnet_buffer_full(s
);
77 static ssize_t
mipsnet_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
79 MIPSnetState
*s
= qemu_get_nic_opaque(nc
);
81 trace_mipsnet_receive(size
);
82 if (!mipsnet_can_receive(nc
))
87 /* Just accept everything. */
89 /* Write packet data. */
90 memcpy(s
->rx_buffer
, buf
, size
);
95 /* Now we can signal we have received something. */
96 s
->intctl
|= MIPSNET_INTCTL_RXDONE
;
97 mipsnet_update_irq(s
);
102 static uint64_t mipsnet_ioport_read(void *opaque
, hwaddr addr
,
105 MIPSnetState
*s
= opaque
;
111 ret
= be32_to_cpu(0x4d495053); /* MIPS */
113 case MIPSNET_DEV_ID
+ 4:
114 ret
= be32_to_cpu(0x4e455430); /* NET0 */
119 case MIPSNET_RX_DATA_COUNT
:
122 case MIPSNET_TX_DATA_COUNT
:
125 case MIPSNET_INT_CTL
:
127 s
->intctl
&= ~MIPSNET_INTCTL_TESTBIT
;
129 case MIPSNET_INTERRUPT_INFO
:
130 /* XXX: This seems to be a per-VPE interrupt number. */
133 case MIPSNET_RX_DATA_BUFFER
:
136 ret
= s
->rx_buffer
[s
->rx_read
++];
140 case MIPSNET_TX_DATA_BUFFER
:
144 trace_mipsnet_read(addr
, ret
);
148 static void mipsnet_ioport_write(void *opaque
, hwaddr addr
,
149 uint64_t val
, unsigned int size
)
151 MIPSnetState
*s
= opaque
;
154 trace_mipsnet_write(addr
, val
);
156 case MIPSNET_TX_DATA_COUNT
:
157 s
->tx_count
= (val
<= MAX_ETH_FRAME_SIZE
) ? val
: 0;
160 case MIPSNET_INT_CTL
:
161 if (val
& MIPSNET_INTCTL_TXDONE
) {
162 s
->intctl
&= ~MIPSNET_INTCTL_TXDONE
;
163 } else if (val
& MIPSNET_INTCTL_RXDONE
) {
164 s
->intctl
&= ~MIPSNET_INTCTL_RXDONE
;
165 } else if (val
& MIPSNET_INTCTL_TESTBIT
) {
167 s
->intctl
|= MIPSNET_INTCTL_TESTBIT
;
169 /* ACK testbit interrupt, flag was cleared on read. */
171 s
->busy
= !!s
->intctl
;
172 mipsnet_update_irq(s
);
174 case MIPSNET_TX_DATA_BUFFER
:
175 s
->tx_buffer
[s
->tx_written
++] = val
;
176 if (s
->tx_written
== s
->tx_count
) {
178 trace_mipsnet_send(s
->tx_count
);
179 qemu_send_packet(qemu_get_queue(s
->nic
), s
->tx_buffer
, s
->tx_count
);
180 s
->tx_count
= s
->tx_written
= 0;
181 s
->intctl
|= MIPSNET_INTCTL_TXDONE
;
183 mipsnet_update_irq(s
);
186 /* Read-only registers */
189 case MIPSNET_RX_DATA_COUNT
:
190 case MIPSNET_INTERRUPT_INFO
:
191 case MIPSNET_RX_DATA_BUFFER
:
197 static const VMStateDescription vmstate_mipsnet
= {
200 .minimum_version_id
= 0,
201 .minimum_version_id_old
= 0,
202 .fields
= (VMStateField
[]) {
203 VMSTATE_UINT32(busy
, MIPSnetState
),
204 VMSTATE_UINT32(rx_count
, MIPSnetState
),
205 VMSTATE_UINT32(rx_read
, MIPSnetState
),
206 VMSTATE_UINT32(tx_count
, MIPSnetState
),
207 VMSTATE_UINT32(tx_written
, MIPSnetState
),
208 VMSTATE_UINT32(intctl
, MIPSnetState
),
209 VMSTATE_BUFFER(rx_buffer
, MIPSnetState
),
210 VMSTATE_BUFFER(tx_buffer
, MIPSnetState
),
211 VMSTATE_END_OF_LIST()
215 static void mipsnet_cleanup(NetClientState
*nc
)
217 MIPSnetState
*s
= qemu_get_nic_opaque(nc
);
222 static NetClientInfo net_mipsnet_info
= {
223 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
224 .size
= sizeof(NICState
),
225 .can_receive
= mipsnet_can_receive
,
226 .receive
= mipsnet_receive
,
227 .cleanup
= mipsnet_cleanup
,
230 static const MemoryRegionOps mipsnet_ioport_ops
= {
231 .read
= mipsnet_ioport_read
,
232 .write
= mipsnet_ioport_write
,
233 .impl
.min_access_size
= 1,
234 .impl
.max_access_size
= 4,
237 static int mipsnet_sysbus_init(SysBusDevice
*sbd
)
239 DeviceState
*dev
= DEVICE(sbd
);
240 MIPSnetState
*s
= MIPS_NET(dev
);
242 memory_region_init_io(&s
->io
, OBJECT(dev
), &mipsnet_ioport_ops
, s
,
244 sysbus_init_mmio(sbd
, &s
->io
);
245 sysbus_init_irq(sbd
, &s
->irq
);
247 s
->nic
= qemu_new_nic(&net_mipsnet_info
, &s
->conf
,
248 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
249 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
254 static void mipsnet_sysbus_reset(DeviceState
*dev
)
256 MIPSnetState
*s
= MIPS_NET(dev
);
260 static Property mipsnet_properties
[] = {
261 DEFINE_NIC_PROPERTIES(MIPSnetState
, conf
),
262 DEFINE_PROP_END_OF_LIST(),
265 static void mipsnet_class_init(ObjectClass
*klass
, void *data
)
267 DeviceClass
*dc
= DEVICE_CLASS(klass
);
268 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
270 k
->init
= mipsnet_sysbus_init
;
271 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
272 dc
->desc
= "MIPS Simulator network device";
273 dc
->reset
= mipsnet_sysbus_reset
;
274 dc
->vmsd
= &vmstate_mipsnet
;
275 dc
->props
= mipsnet_properties
;
278 static const TypeInfo mipsnet_info
= {
279 .name
= TYPE_MIPS_NET
,
280 .parent
= TYPE_SYS_BUS_DEVICE
,
281 .instance_size
= sizeof(MIPSnetState
),
282 .class_init
= mipsnet_class_init
,
285 static void mipsnet_register_types(void)
287 type_register_static(&mipsnet_info
);
290 type_init(mipsnet_register_types
)