2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
38 #if defined(CONFIG_KVM)
39 #include <linux/kvm_para.h>
42 #include "sysemu/sysemu.h"
43 #include "hw/qdev-properties.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "exec/address-spaces.h"
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
52 /* Cache topology CPUID constants: */
54 /* CPUID Leaf 2 Descriptors */
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
61 /* CPUID Leaf 4 constants: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
68 #define CPUID_4_LEVEL(l) ((l) << 5)
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
78 #define ASSOC_FULL 0xFF
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
95 /* Definitions of the hardcoded cache entries we expose: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
139 /* TLB definitions: */
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
163 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
164 uint32_t vendor2
, uint32_t vendor3
)
167 for (i
= 0; i
< 4; i
++) {
168 dst
[i
] = vendor1
>> (8 * i
);
169 dst
[i
+ 4] = vendor2
>> (8 * i
);
170 dst
[i
+ 8] = vendor3
>> (8 * i
);
172 dst
[CPUID_VENDOR_SZ
] = '\0';
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
179 static const char *feature_name
[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL
, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189 static const char *ext_feature_name
[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL
,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL
, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
204 static const char *ext2_feature_name
[] = {
205 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
206 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
207 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
208 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
209 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
210 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
211 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL
, "lm|i64", "3dnowext", "3dnow",
214 static const char *ext3_feature_name
[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL
, "lwp",
219 "fma4", "tce", NULL
, "nodeid_msr",
220 NULL
, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL
, NULL
, NULL
,
222 NULL
, NULL
, NULL
, NULL
,
225 static const char *ext4_feature_name
[] = {
226 NULL
, NULL
, "xstore", "xstore-en",
227 NULL
, NULL
, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL
, NULL
,
230 NULL
, NULL
, NULL
, NULL
,
231 NULL
, NULL
, NULL
, NULL
,
232 NULL
, NULL
, NULL
, NULL
,
233 NULL
, NULL
, NULL
, NULL
,
236 static const char *kvm_feature_name
[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL
, NULL
, NULL
, NULL
,
240 NULL
, NULL
, NULL
, NULL
,
241 NULL
, NULL
, NULL
, NULL
,
242 NULL
, NULL
, NULL
, NULL
,
243 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
244 NULL
, NULL
, NULL
, NULL
,
247 static const char *svm_feature_name
[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL
, NULL
, "pause_filter", NULL
,
251 "pfthreshold", NULL
, NULL
, NULL
,
252 NULL
, NULL
, NULL
, NULL
,
253 NULL
, NULL
, NULL
, NULL
,
254 NULL
, NULL
, NULL
, NULL
,
255 NULL
, NULL
, NULL
, NULL
,
258 static const char *cpuid_7_0_ebx_feature_name
[] = {
259 "fsgsbase", "tsc_adjust", NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, "mpx", NULL
,
261 "avx512f", NULL
, "rdseed", "adx", "smap", NULL
, "pcommit", "clflushopt",
262 "clwb", NULL
, "avx512pf", "avx512er", "avx512cd", NULL
, NULL
, NULL
,
265 static const char *cpuid_7_0_ecx_feature_name
[] = {
266 NULL
, NULL
, NULL
, "pku",
267 "ospke", NULL
, NULL
, NULL
,
268 NULL
, NULL
, NULL
, NULL
,
269 NULL
, NULL
, NULL
, NULL
,
270 NULL
, NULL
, NULL
, NULL
,
271 NULL
, NULL
, NULL
, NULL
,
272 NULL
, NULL
, NULL
, NULL
,
273 NULL
, NULL
, NULL
, NULL
,
276 static const char *cpuid_apm_edx_feature_name
[] = {
277 NULL
, NULL
, NULL
, NULL
,
278 NULL
, NULL
, NULL
, NULL
,
279 "invtsc", NULL
, NULL
, NULL
,
280 NULL
, NULL
, NULL
, NULL
,
281 NULL
, NULL
, NULL
, NULL
,
282 NULL
, NULL
, NULL
, NULL
,
283 NULL
, NULL
, NULL
, NULL
,
284 NULL
, NULL
, NULL
, NULL
,
287 static const char *cpuid_xsave_feature_name
[] = {
288 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
289 NULL
, NULL
, NULL
, NULL
,
290 NULL
, NULL
, NULL
, NULL
,
291 NULL
, NULL
, NULL
, NULL
,
292 NULL
, NULL
, NULL
, NULL
,
293 NULL
, NULL
, NULL
, NULL
,
294 NULL
, NULL
, NULL
, NULL
,
295 NULL
, NULL
, NULL
, NULL
,
298 static const char *cpuid_6_feature_name
[] = {
299 NULL
, NULL
, "arat", NULL
,
300 NULL
, NULL
, NULL
, NULL
,
301 NULL
, NULL
, NULL
, NULL
,
302 NULL
, NULL
, NULL
, NULL
,
303 NULL
, NULL
, NULL
, NULL
,
304 NULL
, NULL
, NULL
, NULL
,
305 NULL
, NULL
, NULL
, NULL
,
306 NULL
, NULL
, NULL
, NULL
,
309 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
310 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
311 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
312 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
313 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
314 CPUID_PSE36 | CPUID_FXSR)
315 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
316 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
317 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
318 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
319 CPUID_PAE | CPUID_SEP | CPUID_APIC)
321 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
322 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
323 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
324 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
325 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
326 /* partly implemented:
327 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
329 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
330 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
331 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
332 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
333 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
334 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
336 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
337 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
338 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
339 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
340 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
343 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
345 #define TCG_EXT2_X86_64_FEATURES 0
348 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
349 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
350 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
351 TCG_EXT2_X86_64_FEATURES)
352 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
353 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
354 #define TCG_EXT4_FEATURES 0
355 #define TCG_SVM_FEATURES 0
356 #define TCG_KVM_FEATURES 0
357 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
358 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
359 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
360 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE)
362 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
363 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
364 CPUID_7_0_EBX_RDSEED */
365 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
366 #define TCG_APM_FEATURES 0
367 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
368 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
370 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
372 typedef struct FeatureWordInfo
{
373 const char **feat_names
;
374 uint32_t cpuid_eax
; /* Input EAX for CPUID */
375 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
376 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
377 int cpuid_reg
; /* output register (R_* constant) */
378 uint32_t tcg_features
; /* Feature flags supported by TCG */
379 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
382 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
384 .feat_names
= feature_name
,
385 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
386 .tcg_features
= TCG_FEATURES
,
389 .feat_names
= ext_feature_name
,
390 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
391 .tcg_features
= TCG_EXT_FEATURES
,
393 [FEAT_8000_0001_EDX
] = {
394 .feat_names
= ext2_feature_name
,
395 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
396 .tcg_features
= TCG_EXT2_FEATURES
,
398 [FEAT_8000_0001_ECX
] = {
399 .feat_names
= ext3_feature_name
,
400 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
401 .tcg_features
= TCG_EXT3_FEATURES
,
403 [FEAT_C000_0001_EDX
] = {
404 .feat_names
= ext4_feature_name
,
405 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
406 .tcg_features
= TCG_EXT4_FEATURES
,
409 .feat_names
= kvm_feature_name
,
410 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
411 .tcg_features
= TCG_KVM_FEATURES
,
414 .feat_names
= svm_feature_name
,
415 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
416 .tcg_features
= TCG_SVM_FEATURES
,
419 .feat_names
= cpuid_7_0_ebx_feature_name
,
421 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
423 .tcg_features
= TCG_7_0_EBX_FEATURES
,
426 .feat_names
= cpuid_7_0_ecx_feature_name
,
428 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
430 .tcg_features
= TCG_7_0_ECX_FEATURES
,
432 [FEAT_8000_0007_EDX
] = {
433 .feat_names
= cpuid_apm_edx_feature_name
,
434 .cpuid_eax
= 0x80000007,
436 .tcg_features
= TCG_APM_FEATURES
,
437 .unmigratable_flags
= CPUID_APM_INVTSC
,
440 .feat_names
= cpuid_xsave_feature_name
,
442 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
444 .tcg_features
= TCG_XSAVE_FEATURES
,
447 .feat_names
= cpuid_6_feature_name
,
448 .cpuid_eax
= 6, .cpuid_reg
= R_EAX
,
449 .tcg_features
= TCG_6_EAX_FEATURES
,
453 typedef struct X86RegisterInfo32
{
454 /* Name of register */
456 /* QAPI enum value register */
457 X86CPURegister32 qapi_enum
;
460 #define REGISTER(reg) \
461 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
462 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
474 const ExtSaveArea x86_ext_save_areas
[] = {
476 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
477 .offset
= 0x240, .size
= 0x100 },
478 [XSTATE_BNDREGS_BIT
] =
479 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
480 .offset
= 0x3c0, .size
= 0x40 },
481 [XSTATE_BNDCSR_BIT
] =
482 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
483 .offset
= 0x400, .size
= 0x40 },
484 [XSTATE_OPMASK_BIT
] =
485 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
486 .offset
= 0x440, .size
= 0x40 },
487 [XSTATE_ZMM_Hi256_BIT
] =
488 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
489 .offset
= 0x480, .size
= 0x200 },
490 [XSTATE_Hi16_ZMM_BIT
] =
491 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
492 .offset
= 0x680, .size
= 0x400 },
494 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
495 .offset
= 0xA80, .size
= 0x8 },
498 const char *get_register_name_32(unsigned int reg
)
500 if (reg
>= CPU_NB_REGS32
) {
503 return x86_reg_info_32
[reg
].name
;
507 * Returns the set of feature flags that are supported and migratable by
508 * QEMU, for a given FeatureWord.
510 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
512 FeatureWordInfo
*wi
= &feature_word_info
[w
];
516 for (i
= 0; i
< 32; i
++) {
517 uint32_t f
= 1U << i
;
518 /* If the feature name is unknown, it is not supported by QEMU yet */
519 if (!wi
->feat_names
[i
]) {
522 /* Skip features known to QEMU, but explicitly marked as unmigratable */
523 if (wi
->unmigratable_flags
& f
) {
531 void host_cpuid(uint32_t function
, uint32_t count
,
532 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
538 : "=a"(vec
[0]), "=b"(vec
[1]),
539 "=c"(vec
[2]), "=d"(vec
[3])
540 : "0"(function
), "c"(count
) : "cc");
541 #elif defined(__i386__)
542 asm volatile("pusha \n\t"
544 "mov %%eax, 0(%2) \n\t"
545 "mov %%ebx, 4(%2) \n\t"
546 "mov %%ecx, 8(%2) \n\t"
547 "mov %%edx, 12(%2) \n\t"
549 : : "a"(function
), "c"(count
), "S"(vec
)
565 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
567 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
568 * a substring. ex if !NULL points to the first char after a substring,
569 * otherwise the string is assumed to sized by a terminating nul.
570 * Return lexical ordering of *s1:*s2.
572 static int sstrcmp(const char *s1
, const char *e1
,
573 const char *s2
, const char *e2
)
576 if (!*s1
|| !*s2
|| *s1
!= *s2
)
579 if (s1
== e1
&& s2
== e2
)
588 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
589 * '|' delimited (possibly empty) strings in which case search for a match
590 * within the alternatives proceeds left to right. Return 0 for success,
591 * non-zero otherwise.
593 static int altcmp(const char *s
, const char *e
, const char *altstr
)
597 for (q
= p
= altstr
; ; ) {
598 while (*p
&& *p
!= '|')
600 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
609 /* search featureset for flag *[s..e), if found set corresponding bit in
610 * *pval and return true, otherwise return false
612 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
613 const char **featureset
)
619 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
620 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
628 static void add_flagname_to_bitmaps(const char *flagname
,
629 FeatureWordArray words
,
633 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
634 FeatureWordInfo
*wi
= &feature_word_info
[w
];
635 if (wi
->feat_names
&&
636 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
640 if (w
== FEATURE_WORDS
) {
641 error_setg(errp
, "CPU feature %s not found", flagname
);
645 /* CPU class name definitions: */
647 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
648 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
650 /* Return type name for a given CPU model name
651 * Caller is responsible for freeing the returned string.
653 static char *x86_cpu_type_name(const char *model_name
)
655 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
658 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
663 if (cpu_model
== NULL
) {
667 typename
= x86_cpu_type_name(cpu_model
);
668 oc
= object_class_by_name(typename
);
673 struct X86CPUDefinition
{
678 /* vendor is zero-terminated, 12 character ASCII string */
679 char vendor
[CPUID_VENDOR_SZ
+ 1];
683 FeatureWordArray features
;
687 static X86CPUDefinition builtin_x86_defs
[] = {
691 .vendor
= CPUID_VENDOR_AMD
,
695 .features
[FEAT_1_EDX
] =
697 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
699 .features
[FEAT_1_ECX
] =
700 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
701 .features
[FEAT_8000_0001_EDX
] =
702 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
703 .features
[FEAT_8000_0001_ECX
] =
704 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
705 .xlevel
= 0x8000000A,
710 .vendor
= CPUID_VENDOR_AMD
,
714 /* Missing: CPUID_HT */
715 .features
[FEAT_1_EDX
] =
717 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
718 CPUID_PSE36
| CPUID_VME
,
719 .features
[FEAT_1_ECX
] =
720 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
722 .features
[FEAT_8000_0001_EDX
] =
723 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
724 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
725 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
726 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
728 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
729 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
730 .features
[FEAT_8000_0001_ECX
] =
731 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
732 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
733 /* Missing: CPUID_SVM_LBRV */
734 .features
[FEAT_SVM
] =
736 .xlevel
= 0x8000001A,
737 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
742 .vendor
= CPUID_VENDOR_INTEL
,
746 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
747 .features
[FEAT_1_EDX
] =
749 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
750 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
751 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
752 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
753 .features
[FEAT_1_ECX
] =
754 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
756 .features
[FEAT_8000_0001_EDX
] =
757 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
758 .features
[FEAT_8000_0001_ECX
] =
760 .xlevel
= 0x80000008,
761 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
766 .vendor
= CPUID_VENDOR_INTEL
,
770 /* Missing: CPUID_HT */
771 .features
[FEAT_1_EDX
] =
772 PPRO_FEATURES
| CPUID_VME
|
773 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
775 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
776 .features
[FEAT_1_ECX
] =
777 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
778 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
779 .features
[FEAT_8000_0001_EDX
] =
780 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
781 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
782 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
783 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
784 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
785 .features
[FEAT_8000_0001_ECX
] =
787 .xlevel
= 0x80000008,
788 .model_id
= "Common KVM processor"
793 .vendor
= CPUID_VENDOR_INTEL
,
797 .features
[FEAT_1_EDX
] =
799 .features
[FEAT_1_ECX
] =
801 .xlevel
= 0x80000004,
806 .vendor
= CPUID_VENDOR_INTEL
,
810 .features
[FEAT_1_EDX
] =
811 PPRO_FEATURES
| CPUID_VME
|
812 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
813 .features
[FEAT_1_ECX
] =
815 .features
[FEAT_8000_0001_ECX
] =
817 .xlevel
= 0x80000008,
818 .model_id
= "Common 32-bit KVM processor"
823 .vendor
= CPUID_VENDOR_INTEL
,
827 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
828 .features
[FEAT_1_EDX
] =
829 PPRO_FEATURES
| CPUID_VME
|
830 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
832 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
833 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
834 .features
[FEAT_1_ECX
] =
835 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
836 .features
[FEAT_8000_0001_EDX
] =
838 .xlevel
= 0x80000008,
839 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
844 .vendor
= CPUID_VENDOR_INTEL
,
848 .features
[FEAT_1_EDX
] =
855 .vendor
= CPUID_VENDOR_INTEL
,
859 .features
[FEAT_1_EDX
] =
866 .vendor
= CPUID_VENDOR_INTEL
,
870 .features
[FEAT_1_EDX
] =
877 .vendor
= CPUID_VENDOR_INTEL
,
881 .features
[FEAT_1_EDX
] =
888 .vendor
= CPUID_VENDOR_AMD
,
892 .features
[FEAT_1_EDX
] =
893 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
895 .features
[FEAT_8000_0001_EDX
] =
896 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
897 .xlevel
= 0x80000008,
902 .vendor
= CPUID_VENDOR_INTEL
,
906 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
907 .features
[FEAT_1_EDX
] =
909 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
910 CPUID_ACPI
| CPUID_SS
,
911 /* Some CPUs got no CPUID_SEP */
912 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
914 .features
[FEAT_1_ECX
] =
915 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
917 .features
[FEAT_8000_0001_EDX
] =
919 .features
[FEAT_8000_0001_ECX
] =
921 .xlevel
= 0x80000008,
922 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
927 .vendor
= CPUID_VENDOR_INTEL
,
931 .features
[FEAT_1_EDX
] =
932 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
933 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
934 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
935 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
936 CPUID_DE
| CPUID_FP87
,
937 .features
[FEAT_1_ECX
] =
938 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
939 .features
[FEAT_8000_0001_EDX
] =
940 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
941 .features
[FEAT_8000_0001_ECX
] =
943 .xlevel
= 0x80000008,
944 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
949 .vendor
= CPUID_VENDOR_INTEL
,
953 .features
[FEAT_1_EDX
] =
954 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
955 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
956 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
957 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
958 CPUID_DE
| CPUID_FP87
,
959 .features
[FEAT_1_ECX
] =
960 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
962 .features
[FEAT_8000_0001_EDX
] =
963 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
964 .features
[FEAT_8000_0001_ECX
] =
966 .xlevel
= 0x80000008,
967 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
972 .vendor
= CPUID_VENDOR_INTEL
,
976 .features
[FEAT_1_EDX
] =
977 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
978 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
979 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
980 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
981 CPUID_DE
| CPUID_FP87
,
982 .features
[FEAT_1_ECX
] =
983 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
984 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
985 .features
[FEAT_8000_0001_EDX
] =
986 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
987 .features
[FEAT_8000_0001_ECX
] =
989 .xlevel
= 0x80000008,
990 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
995 .vendor
= CPUID_VENDOR_INTEL
,
999 .features
[FEAT_1_EDX
] =
1000 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1001 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1002 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1003 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1004 CPUID_DE
| CPUID_FP87
,
1005 .features
[FEAT_1_ECX
] =
1006 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1007 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1008 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1009 .features
[FEAT_8000_0001_EDX
] =
1010 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1011 .features
[FEAT_8000_0001_ECX
] =
1013 .features
[FEAT_6_EAX
] =
1015 .xlevel
= 0x80000008,
1016 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1019 .name
= "SandyBridge",
1021 .vendor
= CPUID_VENDOR_INTEL
,
1025 .features
[FEAT_1_EDX
] =
1026 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1027 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1028 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1029 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1030 CPUID_DE
| CPUID_FP87
,
1031 .features
[FEAT_1_ECX
] =
1032 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1033 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1034 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1035 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1037 .features
[FEAT_8000_0001_EDX
] =
1038 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1040 .features
[FEAT_8000_0001_ECX
] =
1042 .features
[FEAT_XSAVE
] =
1043 CPUID_XSAVE_XSAVEOPT
,
1044 .features
[FEAT_6_EAX
] =
1046 .xlevel
= 0x80000008,
1047 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1050 .name
= "IvyBridge",
1052 .vendor
= CPUID_VENDOR_INTEL
,
1056 .features
[FEAT_1_EDX
] =
1057 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1058 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1059 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1060 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1061 CPUID_DE
| CPUID_FP87
,
1062 .features
[FEAT_1_ECX
] =
1063 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1064 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1065 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1066 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1067 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1068 .features
[FEAT_7_0_EBX
] =
1069 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1071 .features
[FEAT_8000_0001_EDX
] =
1072 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1074 .features
[FEAT_8000_0001_ECX
] =
1076 .features
[FEAT_XSAVE
] =
1077 CPUID_XSAVE_XSAVEOPT
,
1078 .features
[FEAT_6_EAX
] =
1080 .xlevel
= 0x80000008,
1081 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1084 .name
= "Haswell-noTSX",
1086 .vendor
= CPUID_VENDOR_INTEL
,
1090 .features
[FEAT_1_EDX
] =
1091 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1092 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1093 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1094 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1095 CPUID_DE
| CPUID_FP87
,
1096 .features
[FEAT_1_ECX
] =
1097 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1098 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1099 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1100 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1101 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1102 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1103 .features
[FEAT_8000_0001_EDX
] =
1104 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1106 .features
[FEAT_8000_0001_ECX
] =
1107 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1108 .features
[FEAT_7_0_EBX
] =
1109 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1110 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1111 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1112 .features
[FEAT_XSAVE
] =
1113 CPUID_XSAVE_XSAVEOPT
,
1114 .features
[FEAT_6_EAX
] =
1116 .xlevel
= 0x80000008,
1117 .model_id
= "Intel Core Processor (Haswell, no TSX)",
1121 .vendor
= CPUID_VENDOR_INTEL
,
1125 .features
[FEAT_1_EDX
] =
1126 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1127 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1128 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1129 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1130 CPUID_DE
| CPUID_FP87
,
1131 .features
[FEAT_1_ECX
] =
1132 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1133 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1134 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1135 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1136 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1137 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1138 .features
[FEAT_8000_0001_EDX
] =
1139 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1141 .features
[FEAT_8000_0001_ECX
] =
1142 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1143 .features
[FEAT_7_0_EBX
] =
1144 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1145 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1146 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1148 .features
[FEAT_XSAVE
] =
1149 CPUID_XSAVE_XSAVEOPT
,
1150 .features
[FEAT_6_EAX
] =
1152 .xlevel
= 0x80000008,
1153 .model_id
= "Intel Core Processor (Haswell)",
1156 .name
= "Broadwell-noTSX",
1158 .vendor
= CPUID_VENDOR_INTEL
,
1162 .features
[FEAT_1_EDX
] =
1163 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1164 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1165 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1166 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1167 CPUID_DE
| CPUID_FP87
,
1168 .features
[FEAT_1_ECX
] =
1169 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1170 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1171 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1172 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1173 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1174 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1175 .features
[FEAT_8000_0001_EDX
] =
1176 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1178 .features
[FEAT_8000_0001_ECX
] =
1179 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1180 .features
[FEAT_7_0_EBX
] =
1181 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1182 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1183 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1184 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1186 .features
[FEAT_XSAVE
] =
1187 CPUID_XSAVE_XSAVEOPT
,
1188 .features
[FEAT_6_EAX
] =
1190 .xlevel
= 0x80000008,
1191 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
1194 .name
= "Broadwell",
1196 .vendor
= CPUID_VENDOR_INTEL
,
1200 .features
[FEAT_1_EDX
] =
1201 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1202 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1203 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1204 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1205 CPUID_DE
| CPUID_FP87
,
1206 .features
[FEAT_1_ECX
] =
1207 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1208 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1209 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1210 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1211 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1212 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1213 .features
[FEAT_8000_0001_EDX
] =
1214 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1216 .features
[FEAT_8000_0001_ECX
] =
1217 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1218 .features
[FEAT_7_0_EBX
] =
1219 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1220 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1221 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1222 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1224 .features
[FEAT_XSAVE
] =
1225 CPUID_XSAVE_XSAVEOPT
,
1226 .features
[FEAT_6_EAX
] =
1228 .xlevel
= 0x80000008,
1229 .model_id
= "Intel Core Processor (Broadwell)",
1232 .name
= "Opteron_G1",
1234 .vendor
= CPUID_VENDOR_AMD
,
1238 .features
[FEAT_1_EDX
] =
1239 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1240 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1241 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1242 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1243 CPUID_DE
| CPUID_FP87
,
1244 .features
[FEAT_1_ECX
] =
1246 .features
[FEAT_8000_0001_EDX
] =
1247 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1248 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1249 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1250 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1251 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1252 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1253 .xlevel
= 0x80000008,
1254 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1257 .name
= "Opteron_G2",
1259 .vendor
= CPUID_VENDOR_AMD
,
1263 .features
[FEAT_1_EDX
] =
1264 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1265 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1266 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1267 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1268 CPUID_DE
| CPUID_FP87
,
1269 .features
[FEAT_1_ECX
] =
1270 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1271 /* Missing: CPUID_EXT2_RDTSCP */
1272 .features
[FEAT_8000_0001_EDX
] =
1273 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
|
1274 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1275 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1276 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1277 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1278 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1279 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1280 .features
[FEAT_8000_0001_ECX
] =
1281 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1282 .xlevel
= 0x80000008,
1283 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1286 .name
= "Opteron_G3",
1288 .vendor
= CPUID_VENDOR_AMD
,
1292 .features
[FEAT_1_EDX
] =
1293 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1294 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1295 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1296 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1297 CPUID_DE
| CPUID_FP87
,
1298 .features
[FEAT_1_ECX
] =
1299 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1301 /* Missing: CPUID_EXT2_RDTSCP */
1302 .features
[FEAT_8000_0001_EDX
] =
1303 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
|
1304 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1305 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1306 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1307 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1308 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1309 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1310 .features
[FEAT_8000_0001_ECX
] =
1311 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1312 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1313 .xlevel
= 0x80000008,
1314 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1317 .name
= "Opteron_G4",
1319 .vendor
= CPUID_VENDOR_AMD
,
1323 .features
[FEAT_1_EDX
] =
1324 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1325 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1326 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1327 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1328 CPUID_DE
| CPUID_FP87
,
1329 .features
[FEAT_1_ECX
] =
1330 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1331 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1332 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1334 /* Missing: CPUID_EXT2_RDTSCP */
1335 .features
[FEAT_8000_0001_EDX
] =
1337 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1338 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1339 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1340 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1341 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1342 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1343 .features
[FEAT_8000_0001_ECX
] =
1344 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1345 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1346 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1349 .xlevel
= 0x8000001A,
1350 .model_id
= "AMD Opteron 62xx class CPU",
1353 .name
= "Opteron_G5",
1355 .vendor
= CPUID_VENDOR_AMD
,
1359 .features
[FEAT_1_EDX
] =
1360 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1361 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1362 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1363 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1364 CPUID_DE
| CPUID_FP87
,
1365 .features
[FEAT_1_ECX
] =
1366 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1367 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1368 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1369 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1370 /* Missing: CPUID_EXT2_RDTSCP */
1371 .features
[FEAT_8000_0001_EDX
] =
1373 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1374 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1375 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1376 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1377 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1378 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1379 .features
[FEAT_8000_0001_ECX
] =
1380 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1381 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1382 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1385 .xlevel
= 0x8000001A,
1386 .model_id
= "AMD Opteron 63xx class CPU",
1390 typedef struct PropValue
{
1391 const char *prop
, *value
;
1394 /* KVM-specific features that are automatically added/removed
1395 * from all CPU models when KVM is enabled.
1397 static PropValue kvm_default_props
[] = {
1398 { "kvmclock", "on" },
1399 { "kvm-nopiodelay", "on" },
1400 { "kvm-asyncpf", "on" },
1401 { "kvm-steal-time", "on" },
1402 { "kvm-pv-eoi", "on" },
1403 { "kvmclock-stable-bit", "on" },
1406 { "monitor", "off" },
1411 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
1414 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
1415 if (!strcmp(pv
->prop
, prop
)) {
1421 /* It is valid to call this function only for properties that
1422 * are already present in the kvm_default_props table.
1427 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1428 bool migratable_only
);
1432 static int cpu_x86_fill_model_id(char *str
)
1434 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1437 for (i
= 0; i
< 3; i
++) {
1438 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1439 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1440 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1441 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1442 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1447 static X86CPUDefinition host_cpudef
;
1449 static Property host_x86_cpu_properties
[] = {
1450 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1451 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
1452 DEFINE_PROP_END_OF_LIST()
1455 /* class_init for the "host" CPU model
1457 * This function may be called before KVM is initialized.
1459 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1461 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1462 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1463 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1465 xcc
->kvm_required
= true;
1467 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1468 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
1470 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1471 host_cpudef
.family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1472 host_cpudef
.model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1473 host_cpudef
.stepping
= eax
& 0x0F;
1475 cpu_x86_fill_model_id(host_cpudef
.model_id
);
1477 xcc
->cpu_def
= &host_cpudef
;
1479 /* level, xlevel, xlevel2, and the feature words are initialized on
1480 * instance_init, because they require KVM to be initialized.
1483 dc
->props
= host_x86_cpu_properties
;
1484 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1485 dc
->cannot_destroy_with_object_finalize_yet
= true;
1488 static void host_x86_cpu_initfn(Object
*obj
)
1490 X86CPU
*cpu
= X86_CPU(obj
);
1491 CPUX86State
*env
= &cpu
->env
;
1492 KVMState
*s
= kvm_state
;
1494 assert(kvm_enabled());
1496 /* We can't fill the features array here because we don't know yet if
1497 * "migratable" is true or false.
1499 cpu
->host_features
= true;
1501 env
->cpuid_level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1502 env
->cpuid_xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1503 env
->cpuid_xlevel2
= kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1505 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1508 static const TypeInfo host_x86_cpu_type_info
= {
1509 .name
= X86_CPU_TYPE_NAME("host"),
1510 .parent
= TYPE_X86_CPU
,
1511 .instance_init
= host_x86_cpu_initfn
,
1512 .class_init
= host_x86_cpu_class_init
,
1517 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1519 FeatureWordInfo
*f
= &feature_word_info
[w
];
1522 for (i
= 0; i
< 32; ++i
) {
1523 if ((1UL << i
) & mask
) {
1524 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1526 fprintf(stderr
, "warning: %s doesn't support requested feature: "
1527 "CPUID.%02XH:%s%s%s [bit %d]\n",
1528 kvm_enabled() ? "host" : "TCG",
1530 f
->feat_names
[i
] ? "." : "",
1531 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1536 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
1537 const char *name
, void *opaque
,
1540 X86CPU
*cpu
= X86_CPU(obj
);
1541 CPUX86State
*env
= &cpu
->env
;
1544 value
= (env
->cpuid_version
>> 8) & 0xf;
1546 value
+= (env
->cpuid_version
>> 20) & 0xff;
1548 visit_type_int(v
, name
, &value
, errp
);
1551 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
1552 const char *name
, void *opaque
,
1555 X86CPU
*cpu
= X86_CPU(obj
);
1556 CPUX86State
*env
= &cpu
->env
;
1557 const int64_t min
= 0;
1558 const int64_t max
= 0xff + 0xf;
1559 Error
*local_err
= NULL
;
1562 visit_type_int(v
, name
, &value
, &local_err
);
1564 error_propagate(errp
, local_err
);
1567 if (value
< min
|| value
> max
) {
1568 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1569 name
? name
: "null", value
, min
, max
);
1573 env
->cpuid_version
&= ~0xff00f00;
1575 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1577 env
->cpuid_version
|= value
<< 8;
1581 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
1582 const char *name
, void *opaque
,
1585 X86CPU
*cpu
= X86_CPU(obj
);
1586 CPUX86State
*env
= &cpu
->env
;
1589 value
= (env
->cpuid_version
>> 4) & 0xf;
1590 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1591 visit_type_int(v
, name
, &value
, errp
);
1594 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
1595 const char *name
, void *opaque
,
1598 X86CPU
*cpu
= X86_CPU(obj
);
1599 CPUX86State
*env
= &cpu
->env
;
1600 const int64_t min
= 0;
1601 const int64_t max
= 0xff;
1602 Error
*local_err
= NULL
;
1605 visit_type_int(v
, name
, &value
, &local_err
);
1607 error_propagate(errp
, local_err
);
1610 if (value
< min
|| value
> max
) {
1611 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1612 name
? name
: "null", value
, min
, max
);
1616 env
->cpuid_version
&= ~0xf00f0;
1617 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1620 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1621 const char *name
, void *opaque
,
1624 X86CPU
*cpu
= X86_CPU(obj
);
1625 CPUX86State
*env
= &cpu
->env
;
1628 value
= env
->cpuid_version
& 0xf;
1629 visit_type_int(v
, name
, &value
, errp
);
1632 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1633 const char *name
, void *opaque
,
1636 X86CPU
*cpu
= X86_CPU(obj
);
1637 CPUX86State
*env
= &cpu
->env
;
1638 const int64_t min
= 0;
1639 const int64_t max
= 0xf;
1640 Error
*local_err
= NULL
;
1643 visit_type_int(v
, name
, &value
, &local_err
);
1645 error_propagate(errp
, local_err
);
1648 if (value
< min
|| value
> max
) {
1649 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1650 name
? name
: "null", value
, min
, max
);
1654 env
->cpuid_version
&= ~0xf;
1655 env
->cpuid_version
|= value
& 0xf;
1658 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1660 X86CPU
*cpu
= X86_CPU(obj
);
1661 CPUX86State
*env
= &cpu
->env
;
1664 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
1665 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1666 env
->cpuid_vendor3
);
1670 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1673 X86CPU
*cpu
= X86_CPU(obj
);
1674 CPUX86State
*env
= &cpu
->env
;
1677 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1678 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
1682 env
->cpuid_vendor1
= 0;
1683 env
->cpuid_vendor2
= 0;
1684 env
->cpuid_vendor3
= 0;
1685 for (i
= 0; i
< 4; i
++) {
1686 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1687 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1688 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1692 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1694 X86CPU
*cpu
= X86_CPU(obj
);
1695 CPUX86State
*env
= &cpu
->env
;
1699 value
= g_malloc(48 + 1);
1700 for (i
= 0; i
< 48; i
++) {
1701 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1707 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1710 X86CPU
*cpu
= X86_CPU(obj
);
1711 CPUX86State
*env
= &cpu
->env
;
1714 if (model_id
== NULL
) {
1717 len
= strlen(model_id
);
1718 memset(env
->cpuid_model
, 0, 48);
1719 for (i
= 0; i
< 48; i
++) {
1723 c
= (uint8_t)model_id
[i
];
1725 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1729 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1730 void *opaque
, Error
**errp
)
1732 X86CPU
*cpu
= X86_CPU(obj
);
1735 value
= cpu
->env
.tsc_khz
* 1000;
1736 visit_type_int(v
, name
, &value
, errp
);
1739 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1740 void *opaque
, Error
**errp
)
1742 X86CPU
*cpu
= X86_CPU(obj
);
1743 const int64_t min
= 0;
1744 const int64_t max
= INT64_MAX
;
1745 Error
*local_err
= NULL
;
1748 visit_type_int(v
, name
, &value
, &local_err
);
1750 error_propagate(errp
, local_err
);
1753 if (value
< min
|| value
> max
) {
1754 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1755 name
? name
: "null", value
, min
, max
);
1759 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
1762 static void x86_cpuid_get_apic_id(Object
*obj
, Visitor
*v
, const char *name
,
1763 void *opaque
, Error
**errp
)
1765 X86CPU
*cpu
= X86_CPU(obj
);
1766 int64_t value
= cpu
->apic_id
;
1768 visit_type_int(v
, name
, &value
, errp
);
1771 static void x86_cpuid_set_apic_id(Object
*obj
, Visitor
*v
, const char *name
,
1772 void *opaque
, Error
**errp
)
1774 X86CPU
*cpu
= X86_CPU(obj
);
1775 DeviceState
*dev
= DEVICE(obj
);
1776 const int64_t min
= 0;
1777 const int64_t max
= UINT32_MAX
;
1778 Error
*error
= NULL
;
1781 if (dev
->realized
) {
1782 error_setg(errp
, "Attempt to set property '%s' on '%s' after "
1783 "it was realized", name
, object_get_typename(obj
));
1787 visit_type_int(v
, name
, &value
, &error
);
1789 error_propagate(errp
, error
);
1792 if (value
< min
|| value
> max
) {
1793 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1794 " (minimum: %" PRId64
", maximum: %" PRId64
")" ,
1795 object_get_typename(obj
), name
, value
, min
, max
);
1799 if ((value
!= cpu
->apic_id
) && cpu_exists(value
)) {
1800 error_setg(errp
, "CPU with APIC ID %" PRIi64
" exists", value
);
1803 cpu
->apic_id
= value
;
1806 /* Generic getter for "feature-words" and "filtered-features" properties */
1807 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
1808 const char *name
, void *opaque
,
1811 uint32_t *array
= (uint32_t *)opaque
;
1814 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
1815 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
1816 X86CPUFeatureWordInfoList
*list
= NULL
;
1818 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1819 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1820 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
1821 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
1822 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
1823 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
1824 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
1825 qwi
->features
= array
[w
];
1827 /* List will be in reverse order, but order shouldn't matter */
1828 list_entries
[w
].next
= list
;
1829 list_entries
[w
].value
= &word_infos
[w
];
1830 list
= &list_entries
[w
];
1833 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, &err
);
1834 error_propagate(errp
, err
);
1837 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
1838 void *opaque
, Error
**errp
)
1840 X86CPU
*cpu
= X86_CPU(obj
);
1841 int64_t value
= cpu
->hyperv_spinlock_attempts
;
1843 visit_type_int(v
, name
, &value
, errp
);
1846 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
1847 void *opaque
, Error
**errp
)
1849 const int64_t min
= 0xFFF;
1850 const int64_t max
= UINT_MAX
;
1851 X86CPU
*cpu
= X86_CPU(obj
);
1855 visit_type_int(v
, name
, &value
, &err
);
1857 error_propagate(errp
, err
);
1861 if (value
< min
|| value
> max
) {
1862 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1863 " (minimum: %" PRId64
", maximum: %" PRId64
")",
1864 object_get_typename(obj
), name
? name
: "null",
1868 cpu
->hyperv_spinlock_attempts
= value
;
1871 static PropertyInfo qdev_prop_spinlocks
= {
1873 .get
= x86_get_hv_spinlocks
,
1874 .set
= x86_set_hv_spinlocks
,
1877 /* Convert all '_' in a feature string option name to '-', to make feature
1878 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1880 static inline void feat2prop(char *s
)
1882 while ((s
= strchr(s
, '_'))) {
1887 /* Parse "+feature,-feature,feature=foo" CPU feature string
1889 static void x86_cpu_parse_featurestr(CPUState
*cs
, char *features
,
1892 X86CPU
*cpu
= X86_CPU(cs
);
1893 char *featurestr
; /* Single 'key=value" string being parsed */
1895 /* Features to be added */
1896 FeatureWordArray plus_features
= { 0 };
1897 /* Features to be removed */
1898 FeatureWordArray minus_features
= { 0 };
1900 CPUX86State
*env
= &cpu
->env
;
1901 Error
*local_err
= NULL
;
1903 featurestr
= features
? strtok(features
, ",") : NULL
;
1905 while (featurestr
) {
1907 if (featurestr
[0] == '+') {
1908 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
, &local_err
);
1909 } else if (featurestr
[0] == '-') {
1910 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
, &local_err
);
1911 } else if ((val
= strchr(featurestr
, '='))) {
1913 feat2prop(featurestr
);
1914 if (!strcmp(featurestr
, "xlevel")) {
1918 numvalue
= strtoul(val
, &err
, 0);
1919 if (!*val
|| *err
) {
1920 error_setg(errp
, "bad numerical value %s", val
);
1923 if (numvalue
< 0x80000000) {
1924 error_report("xlevel value shall always be >= 0x80000000"
1925 ", fixup will be removed in future versions");
1926 numvalue
+= 0x80000000;
1928 snprintf(num
, sizeof(num
), "%" PRIu32
, numvalue
);
1929 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1930 } else if (!strcmp(featurestr
, "tsc-freq")) {
1935 tsc_freq
= qemu_strtosz_suffix_unit(val
, &err
,
1936 QEMU_STRTOSZ_DEFSUFFIX_B
, 1000);
1937 if (tsc_freq
< 0 || *err
) {
1938 error_setg(errp
, "bad numerical value %s", val
);
1941 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
1942 object_property_parse(OBJECT(cpu
), num
, "tsc-frequency",
1944 } else if (!strcmp(featurestr
, "hv-spinlocks")) {
1946 const int min
= 0xFFF;
1948 numvalue
= strtoul(val
, &err
, 0);
1949 if (!*val
|| *err
) {
1950 error_setg(errp
, "bad numerical value %s", val
);
1953 if (numvalue
< min
) {
1954 error_report("hv-spinlocks value shall always be >= 0x%x"
1955 ", fixup will be removed in future versions",
1959 snprintf(num
, sizeof(num
), "%" PRId32
, numvalue
);
1960 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1962 object_property_parse(OBJECT(cpu
), val
, featurestr
, &local_err
);
1965 feat2prop(featurestr
);
1966 object_property_parse(OBJECT(cpu
), "on", featurestr
, &local_err
);
1969 error_propagate(errp
, local_err
);
1972 featurestr
= strtok(NULL
, ",");
1975 if (cpu
->host_features
) {
1976 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1978 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
1982 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1983 env
->features
[w
] |= plus_features
[w
];
1984 env
->features
[w
] &= ~minus_features
[w
];
1988 /* Print all cpuid feature names in featureset
1990 static void listflags(FILE *f
, fprintf_function print
, const char **featureset
)
1995 for (bit
= 0; bit
< 32; bit
++) {
1996 if (featureset
[bit
]) {
1997 print(f
, "%s%s", first
? "" : " ", featureset
[bit
]);
2003 /* generate CPU information. */
2004 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2006 X86CPUDefinition
*def
;
2010 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
2011 def
= &builtin_x86_defs
[i
];
2012 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
2013 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
2016 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", "host",
2017 "KVM processor with all supported host features "
2018 "(only available in KVM mode)");
2021 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
2022 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
2023 FeatureWordInfo
*fw
= &feature_word_info
[i
];
2025 (*cpu_fprintf
)(f
, " ");
2026 listflags(f
, cpu_fprintf
, fw
->feat_names
);
2027 (*cpu_fprintf
)(f
, "\n");
2031 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2033 CpuDefinitionInfoList
*cpu_list
= NULL
;
2034 X86CPUDefinition
*def
;
2037 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
2038 CpuDefinitionInfoList
*entry
;
2039 CpuDefinitionInfo
*info
;
2041 def
= &builtin_x86_defs
[i
];
2042 info
= g_malloc0(sizeof(*info
));
2043 info
->name
= g_strdup(def
->name
);
2045 entry
= g_malloc0(sizeof(*entry
));
2046 entry
->value
= info
;
2047 entry
->next
= cpu_list
;
2054 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2055 bool migratable_only
)
2057 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2060 if (kvm_enabled()) {
2061 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2064 } else if (tcg_enabled()) {
2065 r
= wi
->tcg_features
;
2069 if (migratable_only
) {
2070 r
&= x86_cpu_get_migratable_flags(w
);
2076 * Filters CPU feature words based on host availability of each feature.
2078 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2080 static int x86_cpu_filter_features(X86CPU
*cpu
)
2082 CPUX86State
*env
= &cpu
->env
;
2086 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2087 uint32_t host_feat
=
2088 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
2089 uint32_t requested_features
= env
->features
[w
];
2090 env
->features
[w
] &= host_feat
;
2091 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
2092 if (cpu
->filtered_features
[w
]) {
2093 if (cpu
->check_cpuid
|| cpu
->enforce_cpuid
) {
2094 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2103 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
2106 for (pv
= props
; pv
->prop
; pv
++) {
2110 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
2115 /* Load data from X86CPUDefinition
2117 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2119 CPUX86State
*env
= &cpu
->env
;
2121 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2124 object_property_set_int(OBJECT(cpu
), def
->level
, "level", errp
);
2125 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2126 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2127 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2128 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", errp
);
2129 object_property_set_int(OBJECT(cpu
), def
->xlevel2
, "xlevel2", errp
);
2130 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2131 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2132 env
->features
[w
] = def
->features
[w
];
2135 /* Special cases not set in the X86CPUDefinition structs: */
2136 if (kvm_enabled()) {
2137 if (!kvm_irqchip_in_kernel()) {
2138 x86_cpu_change_kvm_default("x2apic", "off");
2141 x86_cpu_apply_props(cpu
, kvm_default_props
);
2144 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2146 /* sysenter isn't supported in compatibility mode on AMD,
2147 * syscall isn't supported in compatibility mode on Intel.
2148 * Normally we advertise the actual CPU vendor, but you can
2149 * override this using the 'vendor' property if you want to use
2150 * KVM's sysenter/syscall emulation in compatibility mode and
2151 * when doing cross vendor migration
2153 vendor
= def
->vendor
;
2154 if (kvm_enabled()) {
2155 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2156 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2157 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2158 vendor
= host_vendor
;
2161 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2165 X86CPU
*cpu_x86_create(const char *cpu_model
, Error
**errp
)
2170 gchar
**model_pieces
;
2171 char *name
, *features
;
2172 Error
*error
= NULL
;
2174 model_pieces
= g_strsplit(cpu_model
, ",", 2);
2175 if (!model_pieces
[0]) {
2176 error_setg(&error
, "Invalid/empty CPU model name");
2179 name
= model_pieces
[0];
2180 features
= model_pieces
[1];
2182 oc
= x86_cpu_class_by_name(name
);
2184 error_setg(&error
, "Unable to find CPU definition: %s", name
);
2187 xcc
= X86_CPU_CLASS(oc
);
2189 if (xcc
->kvm_required
&& !kvm_enabled()) {
2190 error_setg(&error
, "CPU model '%s' requires KVM", name
);
2194 cpu
= X86_CPU(object_new(object_class_get_name(oc
)));
2196 x86_cpu_parse_featurestr(CPU(cpu
), features
, &error
);
2202 if (error
!= NULL
) {
2203 error_propagate(errp
, error
);
2205 object_unref(OBJECT(cpu
));
2209 g_strfreev(model_pieces
);
2213 X86CPU
*cpu_x86_init(const char *cpu_model
)
2215 Error
*error
= NULL
;
2218 cpu
= cpu_x86_create(cpu_model
, &error
);
2223 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
2227 error_report_err(error
);
2229 object_unref(OBJECT(cpu
));
2236 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2238 X86CPUDefinition
*cpudef
= data
;
2239 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2241 xcc
->cpu_def
= cpudef
;
2244 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2246 char *typename
= x86_cpu_type_name(def
->name
);
2249 .parent
= TYPE_X86_CPU
,
2250 .class_init
= x86_cpu_cpudef_class_init
,
2258 #if !defined(CONFIG_USER_ONLY)
2260 void cpu_clear_apic_feature(CPUX86State
*env
)
2262 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2265 #endif /* !CONFIG_USER_ONLY */
2267 /* Initialize list of CPU models, filling some non-static fields if necessary
2269 void x86_cpudef_setup(void)
2272 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
2274 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
2275 X86CPUDefinition
*def
= &builtin_x86_defs
[i
];
2277 /* Look for specific "cpudef" models that */
2278 /* have the QEMU version in .model_id */
2279 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
2280 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
2281 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
2282 "QEMU Virtual CPU version ");
2283 pstrcat(def
->model_id
, sizeof(def
->model_id
),
2291 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2292 uint32_t *eax
, uint32_t *ebx
,
2293 uint32_t *ecx
, uint32_t *edx
)
2295 X86CPU
*cpu
= x86_env_get_cpu(env
);
2296 CPUState
*cs
= CPU(cpu
);
2298 /* test if maximum index reached */
2299 if (index
& 0x80000000) {
2300 if (index
> env
->cpuid_xlevel
) {
2301 if (env
->cpuid_xlevel2
> 0) {
2302 /* Handle the Centaur's CPUID instruction. */
2303 if (index
> env
->cpuid_xlevel2
) {
2304 index
= env
->cpuid_xlevel2
;
2305 } else if (index
< 0xC0000000) {
2306 index
= env
->cpuid_xlevel
;
2309 /* Intel documentation states that invalid EAX input will
2310 * return the same information as EAX=cpuid_level
2311 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2313 index
= env
->cpuid_level
;
2317 if (index
> env
->cpuid_level
)
2318 index
= env
->cpuid_level
;
2323 *eax
= env
->cpuid_level
;
2324 *ebx
= env
->cpuid_vendor1
;
2325 *edx
= env
->cpuid_vendor2
;
2326 *ecx
= env
->cpuid_vendor3
;
2329 *eax
= env
->cpuid_version
;
2330 *ebx
= (cpu
->apic_id
<< 24) |
2331 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2332 *ecx
= env
->features
[FEAT_1_ECX
];
2333 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
2334 *ecx
|= CPUID_EXT_OSXSAVE
;
2336 *edx
= env
->features
[FEAT_1_EDX
];
2337 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2338 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2343 /* cache info: needed for Pentium Pro compatibility */
2344 if (cpu
->cache_info_passthrough
) {
2345 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2348 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2351 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2352 (L1I_DESCRIPTOR
<< 8) | \
2356 /* cache info: needed for Core compatibility */
2357 if (cpu
->cache_info_passthrough
) {
2358 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2359 *eax
&= ~0xFC000000;
2363 case 0: /* L1 dcache info */
2364 *eax
|= CPUID_4_TYPE_DCACHE
| \
2365 CPUID_4_LEVEL(1) | \
2366 CPUID_4_SELF_INIT_LEVEL
;
2367 *ebx
= (L1D_LINE_SIZE
- 1) | \
2368 ((L1D_PARTITIONS
- 1) << 12) | \
2369 ((L1D_ASSOCIATIVITY
- 1) << 22);
2370 *ecx
= L1D_SETS
- 1;
2371 *edx
= CPUID_4_NO_INVD_SHARING
;
2373 case 1: /* L1 icache info */
2374 *eax
|= CPUID_4_TYPE_ICACHE
| \
2375 CPUID_4_LEVEL(1) | \
2376 CPUID_4_SELF_INIT_LEVEL
;
2377 *ebx
= (L1I_LINE_SIZE
- 1) | \
2378 ((L1I_PARTITIONS
- 1) << 12) | \
2379 ((L1I_ASSOCIATIVITY
- 1) << 22);
2380 *ecx
= L1I_SETS
- 1;
2381 *edx
= CPUID_4_NO_INVD_SHARING
;
2383 case 2: /* L2 cache info */
2384 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2385 CPUID_4_LEVEL(2) | \
2386 CPUID_4_SELF_INIT_LEVEL
;
2387 if (cs
->nr_threads
> 1) {
2388 *eax
|= (cs
->nr_threads
- 1) << 14;
2390 *ebx
= (L2_LINE_SIZE
- 1) | \
2391 ((L2_PARTITIONS
- 1) << 12) | \
2392 ((L2_ASSOCIATIVITY
- 1) << 22);
2394 *edx
= CPUID_4_NO_INVD_SHARING
;
2396 default: /* end of info */
2405 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2406 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2407 *eax
|= (cs
->nr_cores
- 1) << 26;
2411 /* mwait info: needed for Core compatibility */
2412 *eax
= 0; /* Smallest monitor-line size in bytes */
2413 *ebx
= 0; /* Largest monitor-line size in bytes */
2414 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2418 /* Thermal and Power Leaf */
2419 *eax
= env
->features
[FEAT_6_EAX
];
2425 /* Structured Extended Feature Flags Enumeration Leaf */
2427 *eax
= 0; /* Maximum ECX value for sub-leaves */
2428 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2429 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
2430 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
2431 *ecx
|= CPUID_7_0_ECX_OSPKE
;
2433 *edx
= 0; /* Reserved */
2442 /* Direct Cache Access Information Leaf */
2443 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2449 /* Architectural Performance Monitoring Leaf */
2450 if (kvm_enabled() && cpu
->enable_pmu
) {
2451 KVMState
*s
= cs
->kvm_state
;
2453 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2454 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2455 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2456 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2465 KVMState
*s
= cs
->kvm_state
;
2469 /* Processor Extended State */
2474 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
2477 if (kvm_enabled()) {
2478 ena_mask
= kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EDX
);
2480 ena_mask
|= kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EAX
);
2487 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
2488 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
2489 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
2490 && ((ena_mask
>> i
) & 1) != 0) {
2494 *edx
|= 1u << (i
- 32);
2496 *ecx
= MAX(*ecx
, esa
->offset
+ esa
->size
);
2499 *eax
|= ena_mask
& (XSTATE_FP_MASK
| XSTATE_SSE_MASK
);
2501 } else if (count
== 1) {
2502 *eax
= env
->features
[FEAT_XSAVE
];
2503 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
2504 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
2505 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
2506 && ((ena_mask
>> count
) & 1) != 0) {
2514 *eax
= env
->cpuid_xlevel
;
2515 *ebx
= env
->cpuid_vendor1
;
2516 *edx
= env
->cpuid_vendor2
;
2517 *ecx
= env
->cpuid_vendor3
;
2520 *eax
= env
->cpuid_version
;
2522 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
2523 *edx
= env
->features
[FEAT_8000_0001_EDX
];
2525 /* The Linux kernel checks for the CMPLegacy bit and
2526 * discards multiple thread information if it is set.
2527 * So don't set it here for Intel to make Linux guests happy.
2529 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2530 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
2531 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
2532 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
2533 *ecx
|= 1 << 1; /* CmpLegacy bit */
2540 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2541 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2542 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2543 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2546 /* cache info (L1 cache) */
2547 if (cpu
->cache_info_passthrough
) {
2548 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2551 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
2552 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
2553 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
2554 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
2555 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
2556 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
2557 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
2558 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
2561 /* cache info (L2 cache) */
2562 if (cpu
->cache_info_passthrough
) {
2563 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2566 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
2567 (L2_DTLB_2M_ENTRIES
<< 16) | \
2568 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
2569 (L2_ITLB_2M_ENTRIES
);
2570 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
2571 (L2_DTLB_4K_ENTRIES
<< 16) | \
2572 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
2573 (L2_ITLB_4K_ENTRIES
);
2574 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
2575 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
2576 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
2577 *edx
= ((L3_SIZE_KB
/512) << 18) | \
2578 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
2579 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
2585 *edx
= env
->features
[FEAT_8000_0007_EDX
];
2588 /* virtual & phys address size in low 2 bytes. */
2589 /* XXX: This value must match the one used in the MMU code. */
2590 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2591 /* 64 bit processor */
2592 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2593 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2595 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
2596 *eax
= 0x00000024; /* 36 bits physical */
2598 *eax
= 0x00000020; /* 32 bits physical */
2604 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2605 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2609 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2610 *eax
= 0x00000001; /* SVM Revision */
2611 *ebx
= 0x00000010; /* nr of ASIDs */
2613 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2622 *eax
= env
->cpuid_xlevel2
;
2628 /* Support for VIA CPU's CPUID instruction */
2629 *eax
= env
->cpuid_version
;
2632 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2637 /* Reserved for the future, and now filled with zero */
2644 /* reserved values: zero */
2653 /* CPUClass::reset() */
2654 static void x86_cpu_reset(CPUState
*s
)
2656 X86CPU
*cpu
= X86_CPU(s
);
2657 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2658 CPUX86State
*env
= &cpu
->env
;
2663 xcc
->parent_reset(s
);
2665 memset(env
, 0, offsetof(CPUX86State
, cpuid_level
));
2669 env
->old_exception
= -1;
2671 /* init to reset state */
2673 #ifdef CONFIG_SOFTMMU
2674 env
->hflags
|= HF_SOFTMMU_MASK
;
2676 env
->hflags2
|= HF2_GIF_MASK
;
2678 cpu_x86_update_cr0(env
, 0x60000010);
2679 env
->a20_mask
= ~0x0;
2680 env
->smbase
= 0x30000;
2682 env
->idt
.limit
= 0xffff;
2683 env
->gdt
.limit
= 0xffff;
2684 env
->ldt
.limit
= 0xffff;
2685 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2686 env
->tr
.limit
= 0xffff;
2687 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2689 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2690 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2691 DESC_R_MASK
| DESC_A_MASK
);
2692 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2693 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2695 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2696 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2698 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2699 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2701 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2702 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2704 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2705 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2709 env
->regs
[R_EDX
] = env
->cpuid_version
;
2714 for (i
= 0; i
< 8; i
++) {
2717 cpu_set_fpuc(env
, 0x37f);
2719 env
->mxcsr
= 0x1f80;
2720 /* All units are in INIT state. */
2723 env
->pat
= 0x0007040600070406ULL
;
2724 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2726 memset(env
->dr
, 0, sizeof(env
->dr
));
2727 env
->dr
[6] = DR6_FIXED_1
;
2728 env
->dr
[7] = DR7_FIXED_1
;
2729 cpu_breakpoint_remove_all(s
, BP_CPU
);
2730 cpu_watchpoint_remove_all(s
, BP_CPU
);
2733 xcr0
= XSTATE_FP_MASK
;
2735 #ifdef CONFIG_USER_ONLY
2736 /* Enable all the features for user-mode. */
2737 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
2738 xcr0
|= XSTATE_SSE_MASK
;
2740 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
2741 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
2742 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
) {
2747 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
2748 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
2750 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
2751 cr4
|= CR4_FSGSBASE_MASK
;
2756 cpu_x86_update_cr4(env
, cr4
);
2759 * SDM 11.11.5 requires:
2760 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2761 * - IA32_MTRR_PHYSMASKn.V = 0
2762 * All other bits are undefined. For simplification, zero it all.
2764 env
->mtrr_deftype
= 0;
2765 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
2766 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
2768 #if !defined(CONFIG_USER_ONLY)
2769 /* We hard-wire the BSP to the first CPU. */
2770 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
2772 s
->halted
= !cpu_is_bsp(cpu
);
2774 if (kvm_enabled()) {
2775 kvm_arch_reset_vcpu(cpu
);
2780 #ifndef CONFIG_USER_ONLY
2781 bool cpu_is_bsp(X86CPU
*cpu
)
2783 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
2786 /* TODO: remove me, when reset over QOM tree is implemented */
2787 static void x86_cpu_machine_reset_cb(void *opaque
)
2789 X86CPU
*cpu
= opaque
;
2790 cpu_reset(CPU(cpu
));
2794 static void mce_init(X86CPU
*cpu
)
2796 CPUX86State
*cenv
= &cpu
->env
;
2799 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2800 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2801 (CPUID_MCE
| CPUID_MCA
)) {
2802 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2803 cenv
->mcg_ctl
= ~(uint64_t)0;
2804 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2805 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2810 #ifndef CONFIG_USER_ONLY
2811 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2813 APICCommonState
*apic
;
2814 const char *apic_type
= "apic";
2816 if (kvm_apic_in_kernel()) {
2817 apic_type
= "kvm-apic";
2818 } else if (xen_enabled()) {
2819 apic_type
= "xen-apic";
2822 cpu
->apic_state
= DEVICE(object_new(apic_type
));
2824 object_property_add_child(OBJECT(cpu
), "apic",
2825 OBJECT(cpu
->apic_state
), NULL
);
2826 qdev_prop_set_uint8(cpu
->apic_state
, "id", cpu
->apic_id
);
2827 /* TODO: convert to link<> */
2828 apic
= APIC_COMMON(cpu
->apic_state
);
2830 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
2833 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2835 APICCommonState
*apic
;
2836 static bool apic_mmio_map_once
;
2838 if (cpu
->apic_state
== NULL
) {
2841 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
2844 /* Map APIC MMIO area */
2845 apic
= APIC_COMMON(cpu
->apic_state
);
2846 if (!apic_mmio_map_once
) {
2847 memory_region_add_subregion_overlap(get_system_memory(),
2849 MSR_IA32_APICBASE_BASE
,
2852 apic_mmio_map_once
= true;
2856 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
2858 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
2859 MemoryRegion
*smram
=
2860 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
2863 cpu
->smram
= g_new(MemoryRegion
, 1);
2864 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
2865 smram
, 0, 1ull << 32);
2866 memory_region_set_enabled(cpu
->smram
, false);
2867 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
2871 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2877 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2878 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2879 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2880 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2881 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2882 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2883 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
2885 CPUState
*cs
= CPU(dev
);
2886 X86CPU
*cpu
= X86_CPU(dev
);
2887 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
2888 CPUX86State
*env
= &cpu
->env
;
2889 Error
*local_err
= NULL
;
2890 static bool ht_warned
;
2892 if (cpu
->apic_id
< 0) {
2893 error_setg(errp
, "apic-id property was not initialized properly");
2897 if (env
->features
[FEAT_7_0_EBX
] && env
->cpuid_level
< 7) {
2898 env
->cpuid_level
= 7;
2901 if (x86_cpu_filter_features(cpu
) && cpu
->enforce_cpuid
) {
2902 error_setg(&local_err
,
2904 "Host doesn't support requested features" :
2905 "TCG doesn't support requested features");
2909 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2912 if (IS_AMD_CPU(env
)) {
2913 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
2914 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
2915 & CPUID_EXT2_AMD_ALIASES
);
2919 #ifndef CONFIG_USER_ONLY
2920 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2922 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
2923 x86_cpu_apic_create(cpu
, &local_err
);
2924 if (local_err
!= NULL
) {
2932 #ifndef CONFIG_USER_ONLY
2933 if (tcg_enabled()) {
2934 AddressSpace
*newas
= g_new(AddressSpace
, 1);
2936 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
2937 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
2939 /* Outer container... */
2940 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
2941 memory_region_set_enabled(cpu
->cpu_as_root
, true);
2943 /* ... with two regions inside: normal system memory with low
2946 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
2947 get_system_memory(), 0, ~0ull);
2948 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
2949 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
2950 address_space_init(newas
, cpu
->cpu_as_root
, "CPU");
2952 cpu_address_space_init(cs
, newas
, 0);
2954 /* ... SMRAM with higher priority, linked from /machine/smram. */
2955 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
2956 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
2962 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2963 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2964 * based on inputs (sockets,cores,threads), it is still better to gives
2967 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2968 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2970 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
2971 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2972 " -smp options properly.");
2976 x86_cpu_apic_realize(cpu
, &local_err
);
2977 if (local_err
!= NULL
) {
2982 xcc
->parent_realize(dev
, &local_err
);
2985 if (local_err
!= NULL
) {
2986 error_propagate(errp
, local_err
);
2991 typedef struct BitProperty
{
2996 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
2997 void *opaque
, Error
**errp
)
2999 BitProperty
*fp
= opaque
;
3000 bool value
= (*fp
->ptr
& fp
->mask
) == fp
->mask
;
3001 visit_type_bool(v
, name
, &value
, errp
);
3004 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3005 void *opaque
, Error
**errp
)
3007 DeviceState
*dev
= DEVICE(obj
);
3008 BitProperty
*fp
= opaque
;
3009 Error
*local_err
= NULL
;
3012 if (dev
->realized
) {
3013 qdev_prop_set_after_realize(dev
, name
, errp
);
3017 visit_type_bool(v
, name
, &value
, &local_err
);
3019 error_propagate(errp
, local_err
);
3024 *fp
->ptr
|= fp
->mask
;
3026 *fp
->ptr
&= ~fp
->mask
;
3030 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
3033 BitProperty
*prop
= opaque
;
3037 /* Register a boolean property to get/set a single bit in a uint32_t field.
3039 * The same property name can be registered multiple times to make it affect
3040 * multiple bits in the same FeatureWord. In that case, the getter will return
3041 * true only if all bits are set.
3043 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
3044 const char *prop_name
,
3050 uint32_t mask
= (1UL << bitnr
);
3052 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
3055 assert(fp
->ptr
== field
);
3058 fp
= g_new0(BitProperty
, 1);
3061 object_property_add(OBJECT(cpu
), prop_name
, "bool",
3062 x86_cpu_get_bit_prop
,
3063 x86_cpu_set_bit_prop
,
3064 x86_cpu_release_bit_prop
, fp
, &error_abort
);
3068 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
3072 Object
*obj
= OBJECT(cpu
);
3075 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3077 if (!fi
->feat_names
) {
3080 if (!fi
->feat_names
[bitnr
]) {
3084 names
= g_strsplit(fi
->feat_names
[bitnr
], "|", 0);
3086 feat2prop(names
[0]);
3087 x86_cpu_register_bit_prop(cpu
, names
[0], &cpu
->env
.features
[w
], bitnr
);
3089 for (i
= 1; names
[i
]; i
++) {
3090 feat2prop(names
[i
]);
3091 object_property_add_alias(obj
, names
[i
], obj
, names
[0],
3098 static void x86_cpu_initfn(Object
*obj
)
3100 CPUState
*cs
= CPU(obj
);
3101 X86CPU
*cpu
= X86_CPU(obj
);
3102 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
3103 CPUX86State
*env
= &cpu
->env
;
3108 cpu_exec_init(cs
, &error_abort
);
3110 object_property_add(obj
, "family", "int",
3111 x86_cpuid_version_get_family
,
3112 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
3113 object_property_add(obj
, "model", "int",
3114 x86_cpuid_version_get_model
,
3115 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
3116 object_property_add(obj
, "stepping", "int",
3117 x86_cpuid_version_get_stepping
,
3118 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
3119 object_property_add_str(obj
, "vendor",
3120 x86_cpuid_get_vendor
,
3121 x86_cpuid_set_vendor
, NULL
);
3122 object_property_add_str(obj
, "model-id",
3123 x86_cpuid_get_model_id
,
3124 x86_cpuid_set_model_id
, NULL
);
3125 object_property_add(obj
, "tsc-frequency", "int",
3126 x86_cpuid_get_tsc_freq
,
3127 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
3128 object_property_add(obj
, "apic-id", "int",
3129 x86_cpuid_get_apic_id
,
3130 x86_cpuid_set_apic_id
, NULL
, NULL
, NULL
);
3131 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
3132 x86_cpu_get_feature_words
,
3133 NULL
, NULL
, (void *)env
->features
, NULL
);
3134 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
3135 x86_cpu_get_feature_words
,
3136 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
3138 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
3140 #ifndef CONFIG_USER_ONLY
3141 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3145 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3148 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
3149 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
3153 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
3155 /* init various static tables used in TCG mode */
3156 if (tcg_enabled() && !inited
) {
3162 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
3164 X86CPU
*cpu
= X86_CPU(cs
);
3166 return cpu
->apic_id
;
3169 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
3171 X86CPU
*cpu
= X86_CPU(cs
);
3173 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
3176 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
3178 X86CPU
*cpu
= X86_CPU(cs
);
3180 cpu
->env
.eip
= value
;
3183 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
3185 X86CPU
*cpu
= X86_CPU(cs
);
3187 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
3190 static bool x86_cpu_has_work(CPUState
*cs
)
3192 X86CPU
*cpu
= X86_CPU(cs
);
3193 CPUX86State
*env
= &cpu
->env
;
3195 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
3196 CPU_INTERRUPT_POLL
)) &&
3197 (env
->eflags
& IF_MASK
)) ||
3198 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
3199 CPU_INTERRUPT_INIT
|
3200 CPU_INTERRUPT_SIPI
|
3201 CPU_INTERRUPT_MCE
)) ||
3202 ((cs
->interrupt_request
& CPU_INTERRUPT_SMI
) &&
3203 !(env
->hflags
& HF_SMM_MASK
));
3206 static Property x86_cpu_properties
[] = {
3207 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
3208 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
3209 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
3210 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
3211 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
3212 DEFINE_PROP_BOOL("hv-crash", X86CPU
, hyperv_crash
, false),
3213 DEFINE_PROP_BOOL("hv-reset", X86CPU
, hyperv_reset
, false),
3214 DEFINE_PROP_BOOL("hv-vpindex", X86CPU
, hyperv_vpindex
, false),
3215 DEFINE_PROP_BOOL("hv-runtime", X86CPU
, hyperv_runtime
, false),
3216 DEFINE_PROP_BOOL("hv-synic", X86CPU
, hyperv_synic
, false),
3217 DEFINE_PROP_BOOL("hv-stimer", X86CPU
, hyperv_stimer
, false),
3218 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
3219 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
3220 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
3221 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, 0),
3222 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, 0),
3223 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, 0),
3224 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
3225 DEFINE_PROP_END_OF_LIST()
3228 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
3230 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3231 CPUClass
*cc
= CPU_CLASS(oc
);
3232 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3234 xcc
->parent_realize
= dc
->realize
;
3235 dc
->realize
= x86_cpu_realizefn
;
3236 dc
->props
= x86_cpu_properties
;
3238 xcc
->parent_reset
= cc
->reset
;
3239 cc
->reset
= x86_cpu_reset
;
3240 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
3242 cc
->class_by_name
= x86_cpu_class_by_name
;
3243 cc
->parse_features
= x86_cpu_parse_featurestr
;
3244 cc
->has_work
= x86_cpu_has_work
;
3245 cc
->do_interrupt
= x86_cpu_do_interrupt
;
3246 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
3247 cc
->dump_state
= x86_cpu_dump_state
;
3248 cc
->set_pc
= x86_cpu_set_pc
;
3249 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
3250 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
3251 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
3252 cc
->get_arch_id
= x86_cpu_get_arch_id
;
3253 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
3254 #ifdef CONFIG_USER_ONLY
3255 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
3257 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
3258 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
3259 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
3260 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
3261 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
3262 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
3263 cc
->vmsd
= &vmstate_x86_cpu
;
3265 cc
->gdb_num_core_regs
= CPU_NB_REGS
* 2 + 25;
3266 #ifndef CONFIG_USER_ONLY
3267 cc
->debug_excp_handler
= breakpoint_handler
;
3269 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
3270 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
3273 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3274 * object in cpus -> dangling pointer after final object_unref().
3276 dc
->cannot_destroy_with_object_finalize_yet
= true;
3279 static const TypeInfo x86_cpu_type_info
= {
3280 .name
= TYPE_X86_CPU
,
3282 .instance_size
= sizeof(X86CPU
),
3283 .instance_init
= x86_cpu_initfn
,
3285 .class_size
= sizeof(X86CPUClass
),
3286 .class_init
= x86_cpu_common_class_init
,
3289 static void x86_cpu_register_types(void)
3293 type_register_static(&x86_cpu_type_info
);
3294 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
3295 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
3298 type_register_static(&host_x86_cpu_type_info
);
3302 type_init(x86_cpu_register_types
)