hw/pci-host/xilinx-pcie.c

   1 /*
   2  * Xilinx PCIe host controller emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/pci/pci_bridge.h"
  23 #include "hw/pci-host/xilinx-pcie.h"
  24
  25 enum root_cfg_reg {
  26     /* Interrupt Decode Register */
  27     ROOTCFG_INTDEC              = 0x138,
  28
  29     /* Interrupt Mask Register */
  30     ROOTCFG_INTMASK             = 0x13c,
  31     /* INTx Interrupt Received */
  32 #define ROOTCFG_INTMASK_INTX    (1 << 16)
  33     /* MSI Interrupt Received */
  34 #define ROOTCFG_INTMASK_MSI     (1 << 17)
  35
  36     /* PHY Status/Control Register */
  37     ROOTCFG_PSCR                = 0x144,
  38     /* Link Up */
  39 #define ROOTCFG_PSCR_LINK_UP    (1 << 11)
  40
  41     /* Root Port Status/Control Register */
  42     ROOTCFG_RPSCR               = 0x148,
  43     /* Bridge Enable */
  44 #define ROOTCFG_RPSCR_BRIDGEEN  (1 << 0)
  45     /* Interrupt FIFO Not Empty */
  46 #define ROOTCFG_RPSCR_INTNEMPTY (1 << 18)
  47     /* Interrupt FIFO Overflow */
  48 #define ROOTCFG_RPSCR_INTOVF    (1 << 19)
  49
  50     /* Root Port Interrupt FIFO Read Register 1 */
  51     ROOTCFG_RPIFR1              = 0x158,
  52 #define ROOTCFG_RPIFR1_INT_LANE_SHIFT   27
  53 #define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29
  54 #define ROOTCFG_RPIFR1_INT_VALID_SHIFT  31
  55     /* Root Port Interrupt FIFO Read Register 2 */
  56     ROOTCFG_RPIFR2              = 0x15c,
  57 };
  58
  59 static void xilinx_pcie_update_intr(XilinxPCIEHost *s,
  60                                     uint32_t set, uint32_t clear)
  61 {
  62     int level;
  63
  64     s->intr |= set;
  65     s->intr &= ~clear;
  66
  67     if (s->intr_fifo_r != s->intr_fifo_w) {
  68         s->intr |= ROOTCFG_INTMASK_INTX;
  69     }
  70
  71     level = !!(s->intr & s->intr_mask);
  72     qemu_set_irq(s->irq, level);
  73 }
  74
  75 static void xilinx_pcie_queue_intr(XilinxPCIEHost *s,
  76                                    uint32_t fifo_reg1, uint32_t fifo_reg2)
  77 {
  78     XilinxPCIEInt *intr;
  79     unsigned int new_w;
  80
  81     new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo);
  82     if (new_w == s->intr_fifo_r) {
  83         s->rpscr |= ROOTCFG_RPSCR_INTOVF;
  84         return;
  85     }
  86
  87     intr = &s->intr_fifo[s->intr_fifo_w];
  88     s->intr_fifo_w = new_w;
  89
  90     intr->fifo_reg1 = fifo_reg1;
  91     intr->fifo_reg2 = fifo_reg2;
  92
  93     xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0);
  94 }
  95
  96 static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level)
  97 {
  98     XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque);
  99
 100     xilinx_pcie_queue_intr(s,
 101        (irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) |
 102            (level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) |
 103            (1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT),
 104        0);
 105 }
 106
 107 static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
 108 {
 109     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
 110     XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
 111     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 112     PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
 113
 114     snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);
 115
 116     /* PCI configuration space */
 117     pcie_host_mmcfg_init(pex, s->cfg_size);
 118
 119     /* MMIO region */
 120     memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
 121     memory_region_set_enabled(&s->mmio, false);
 122
 123     /* dummy PCI I/O region (not visible to the CPU) */
 124     memory_region_init(&s->io, OBJECT(s), "io", 16);
 125
 126     /* interrupt out */
 127     qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
 128
 129     sysbus_init_mmio(sbd, &pex->mmio);
 130     sysbus_init_mmio(sbd, &s->mmio);
 131
 132     pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq,
 133                                      pci_swizzle_map_irq_fn, s, &s->mmio,
 134                                      &s->io, 0, 4, TYPE_PCIE_BUS);
 135
 136     qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
 137     qdev_init_nofail(DEVICE(&s->root));
 138 }
 139
 140 static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge,
 141                                                   PCIBus *rootbus)
 142 {
 143     return "0000:00";
 144 }
 145
 146 static void xilinx_pcie_host_init(Object *obj)
 147 {
 148     XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
 149     XilinxPCIERoot *root = &s->root;
 150
 151     object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT);
 152     object_property_add_child(obj, "root", OBJECT(root), NULL);
 153     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
 154     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
 155 }
 156
 157 static Property xilinx_pcie_host_props[] = {
 158     DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
 159     DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
 160     DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20),
 161     DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
 162     DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20),
 163     DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
 164     DEFINE_PROP_END_OF_LIST(),
 165 };
 166
 167 static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data)
 168 {
 169     DeviceClass *dc = DEVICE_CLASS(klass);
 170     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 171
 172     hc->root_bus_path = xilinx_pcie_host_root_bus_path;
 173     dc->realize = xilinx_pcie_host_realize;
 174     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 175     dc->fw_name = "pci";
 176     dc->props = xilinx_pcie_host_props;
 177 }
 178
 179 static const TypeInfo xilinx_pcie_host_info = {
 180     .name       = TYPE_XILINX_PCIE_HOST,
 181     .parent     = TYPE_PCIE_HOST_BRIDGE,
 182     .instance_size = sizeof(XilinxPCIEHost),
 183     .instance_init = xilinx_pcie_host_init,
 184     .class_init = xilinx_pcie_host_class_init,
 185 };
 186
 187 static uint32_t xilinx_pcie_root_config_read(PCIDevice *d,
 188                                              uint32_t address, int len)
 189 {
 190     XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
 191     uint32_t val;
 192
 193     switch (address) {
 194     case ROOTCFG_INTDEC:
 195         val = s->intr;
 196         break;
 197     case ROOTCFG_INTMASK:
 198         val = s->intr_mask;
 199         break;
 200     case ROOTCFG_PSCR:
 201         val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0;
 202         break;
 203     case ROOTCFG_RPSCR:
 204         if (s->intr_fifo_r != s->intr_fifo_w) {
 205             s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY;
 206         } else {
 207             s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY;
 208         }
 209         val = s->rpscr;
 210         break;
 211     case ROOTCFG_RPIFR1:
 212         if (s->intr_fifo_w == s->intr_fifo_r) {
 213             /* FIFO empty */
 214             val = 0;
 215         } else {
 216             val = s->intr_fifo[s->intr_fifo_r].fifo_reg1;
 217         }
 218         break;
 219     case ROOTCFG_RPIFR2:
 220         if (s->intr_fifo_w == s->intr_fifo_r) {
 221             /* FIFO empty */
 222             val = 0;
 223         } else {
 224             val = s->intr_fifo[s->intr_fifo_r].fifo_reg2;
 225         }
 226         break;
 227     default:
 228         val = pci_default_read_config(d, address, len);
 229         break;
 230     }
 231     return val;
 232 }
 233
 234 static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address,
 235                                           uint32_t val, int len)
 236 {
 237     XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
 238     switch (address) {
 239     case ROOTCFG_INTDEC:
 240         xilinx_pcie_update_intr(s, 0, val);
 241         break;
 242     case ROOTCFG_INTMASK:
 243         s->intr_mask = val;
 244         xilinx_pcie_update_intr(s, 0, 0);
 245         break;
 246     case ROOTCFG_RPSCR:
 247         s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN;
 248         s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN;
 249         memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN);
 250
 251         if (val & ROOTCFG_INTMASK_INTX) {
 252             s->rpscr &= ~ROOTCFG_INTMASK_INTX;
 253         }
 254         break;
 255     case ROOTCFG_RPIFR1:
 256     case ROOTCFG_RPIFR2:
 257         if (s->intr_fifo_w == s->intr_fifo_r) {
 258             /* FIFO empty */
 259             return;
 260         } else {
 261             s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo);
 262         }
 263         break;
 264     default:
 265         pci_default_write_config(d, address, val, len);
 266         break;
 267     }
 268 }
 269
 270 static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp)
 271 {
 272     BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev));
 273     XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);
 274
 275     pci_set_word(pci_dev->config + PCI_COMMAND,
 276                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 277     pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
 278     pci_set_word(pci_dev->config + PCI_MEMORY_LIMIT,
 279                  ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0);
 280
 281     pci_bridge_initfn(pci_dev, TYPE_PCI_BUS);
 282
 283     if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) {
 284         error_setg(errp, "Failed to initialize PCIe capability");
 285     }
 286 }
 287
 288 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data)
 289 {
 290     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 291     DeviceClass *dc = DEVICE_CLASS(klass);
 292
 293     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 294     dc->desc = "Xilinx AXI-PCIe Host Bridge";
 295     k->vendor_id = PCI_VENDOR_ID_XILINX;
 296     k->device_id = 0x7021;
 297     k->revision = 0;
 298     k->class_id = PCI_CLASS_BRIDGE_HOST;
 299     k->is_bridge = true;
 300     k->realize = xilinx_pcie_root_realize;
 301     k->exit = pci_bridge_exitfn;
 302     dc->reset = pci_bridge_reset;
 303     k->config_read = xilinx_pcie_root_config_read;
 304     k->config_write = xilinx_pcie_root_config_write;
 305     /*
 306      * PCI-facing part of the host bridge, not usable without the
 307      * host-facing part, which can't be device_add'ed, yet.
 308      */
 309     dc->user_creatable = false;
 310 }
 311
 312 static const TypeInfo xilinx_pcie_root_info = {
 313     .name = TYPE_XILINX_PCIE_ROOT,
 314     .parent = TYPE_PCI_BRIDGE,
 315     .instance_size = sizeof(XilinxPCIERoot),
 316     .class_init = xilinx_pcie_root_class_init,
 317     .interfaces = (InterfaceInfo[]) {
 318         { INTERFACE_PCIE_DEVICE },
 319         { }
 320     },
 321 };
 322
 323 static void xilinx_pcie_register(void)
 324 {
 325     type_register_static(&xilinx_pcie_root_info);
 326     type_register_static(&xilinx_pcie_host_info);
 327 }
 328
 329 type_init(xilinx_pcie_register)