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Make error handling more consistent in img_create() and img_resize()
[qemu.git] / hw / pci.c
blob24e650a442e25176944554f1384c45fe2d847a5c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "msix.h"
29 #include "msi.h"
30 #include "monitor.h"
31 #include "net.h"
32 #include "sysemu.h"
33 #include "loader.h"
34 #include "qemu-objects.h"
35 #include "range.h"
36
37 //#define DEBUG_PCI
38 #ifdef DEBUG_PCI
39 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
40 #else
41 # define PCI_DPRINTF(format, ...) do { } while (0)
42 #endif
43
44 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
45 static char *pcibus_get_dev_path(DeviceState *dev);
46 static char *pcibus_get_fw_dev_path(DeviceState *dev);
47 static int pcibus_reset(BusState *qbus);
48
49 struct BusInfo pci_bus_info = {
50 .name = "PCI",
51 .size = sizeof(PCIBus),
52 .print_dev = pcibus_dev_print,
53 .get_dev_path = pcibus_get_dev_path,
54 .get_fw_dev_path = pcibus_get_fw_dev_path,
55 .reset = pcibus_reset,
56 .props = (Property[]) {
57 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
58 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
59 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
60 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
61 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 /* Update interrupt status bit in config space on interrupt
130 * state change. */
131 static void pci_update_irq_status(PCIDevice *dev)
132 {
133 if (dev->irq_state) {
134 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
135 } else {
136 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
137 }
138 }
139
140 static void pci_device_reset(PCIDevice *dev)
141 {
142 int r;
143 /* TODO: call the below unconditionally once all pci devices
144 * are qdevified */
145 if (dev->qdev.info) {
146 qdev_reset_all(&dev->qdev);
147 }
148
149 dev->irq_state = 0;
150 pci_update_irq_status(dev);
151 /* Clear all writeable bits */
152 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
153 pci_get_word(dev->wmask + PCI_COMMAND) |
154 pci_get_word(dev->w1cmask + PCI_COMMAND));
155 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
156 pci_get_word(dev->wmask + PCI_STATUS) |
157 pci_get_word(dev->w1cmask + PCI_STATUS));
158 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
159 dev->config[PCI_INTERRUPT_LINE] = 0x0;
160 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
161 PCIIORegion *region = &dev->io_regions[r];
162 if (!region->size) {
163 continue;
164 }
165
166 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
167 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
168 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
169 } else {
170 pci_set_long(dev->config + pci_bar(dev, r), region->type);
171 }
172 }
173 pci_update_mappings(dev);
174 }
175
176 /*
177 * Trigger pci bus reset under a given bus.
178 * To be called on RST# assert.
179 */
180 void pci_bus_reset(PCIBus *bus)
181 {
182 int i;
183
184 for (i = 0; i < bus->nirq; i++) {
185 bus->irq_count[i] = 0;
186 }
187 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
188 if (bus->devices[i]) {
189 pci_device_reset(bus->devices[i]);
190 }
191 }
192 }
193
194 static int pcibus_reset(BusState *qbus)
195 {
196 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
197
198 /* topology traverse is done by pci_bus_reset().
199 Tell qbus/qdev walker not to traverse the tree */
200 return 1;
201 }
202
203 static void pci_host_bus_register(int domain, PCIBus *bus)
204 {
205 struct PCIHostBus *host;
206 host = qemu_mallocz(sizeof(*host));
207 host->domain = domain;
208 host->bus = bus;
209 QLIST_INSERT_HEAD(&host_buses, host, next);
210 }
211
212 PCIBus *pci_find_root_bus(int domain)
213 {
214 struct PCIHostBus *host;
215
216 QLIST_FOREACH(host, &host_buses, next) {
217 if (host->domain == domain) {
218 return host->bus;
219 }
220 }
221
222 return NULL;
223 }
224
225 int pci_find_domain(const PCIBus *bus)
226 {
227 PCIDevice *d;
228 struct PCIHostBus *host;
229
230 /* obtain root bus */
231 while ((d = bus->parent_dev) != NULL) {
232 bus = d->bus;
233 }
234
235 QLIST_FOREACH(host, &host_buses, next) {
236 if (host->bus == bus) {
237 return host->domain;
238 }
239 }
240
241 abort(); /* should not be reached */
242 return -1;
243 }
244
245 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
246 const char *name, int devfn_min)
247 {
248 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
249 assert(PCI_FUNC(devfn_min) == 0);
250 bus->devfn_min = devfn_min;
251
252 /* host bridge */
253 QLIST_INIT(&bus->child);
254 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
255
256 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
257 }
258
259 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
260 {
261 PCIBus *bus;
262
263 bus = qemu_mallocz(sizeof(*bus));
264 bus->qbus.qdev_allocated = 1;
265 pci_bus_new_inplace(bus, parent, name, devfn_min);
266 return bus;
267 }
268
269 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
270 void *irq_opaque, int nirq)
271 {
272 bus->set_irq = set_irq;
273 bus->map_irq = map_irq;
274 bus->irq_opaque = irq_opaque;
275 bus->nirq = nirq;
276 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
277 }
278
279 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
280 {
281 bus->qbus.allow_hotplug = 1;
282 bus->hotplug = hotplug;
283 bus->hotplug_qdev = qdev;
284 }
285
286 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
287 {
288 bus->mem_base = base;
289 }
290
291 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
292 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
293 void *irq_opaque, int devfn_min, int nirq)
294 {
295 PCIBus *bus;
296
297 bus = pci_bus_new(parent, name, devfn_min);
298 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
299 return bus;
300 }
301
302 int pci_bus_num(PCIBus *s)
303 {
304 if (!s->parent_dev)
305 return 0; /* pci host bridge */
306 return s->parent_dev->config[PCI_SECONDARY_BUS];
307 }
308
309 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
310 {
311 PCIDevice *s = container_of(pv, PCIDevice, config);
312 uint8_t *config;
313 int i;
314
315 assert(size == pci_config_size(s));
316 config = qemu_malloc(size);
317
318 qemu_get_buffer(f, config, size);
319 for (i = 0; i < size; ++i) {
320 if ((config[i] ^ s->config[i]) &
321 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
322 qemu_free(config);
323 return -EINVAL;
324 }
325 }
326 memcpy(s->config, config, size);
327
328 pci_update_mappings(s);
329
330 qemu_free(config);
331 return 0;
332 }
333
334 /* just put buffer */
335 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
336 {
337 const uint8_t **v = pv;
338 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
339 qemu_put_buffer(f, *v, size);
340 }
341
342 static VMStateInfo vmstate_info_pci_config = {
343 .name = "pci config",
344 .get = get_pci_config_device,
345 .put = put_pci_config_device,
346 };
347
348 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
349 {
350 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
351 uint32_t irq_state[PCI_NUM_PINS];
352 int i;
353 for (i = 0; i < PCI_NUM_PINS; ++i) {
354 irq_state[i] = qemu_get_be32(f);
355 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
356 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
357 irq_state[i]);
358 return -EINVAL;
359 }
360 }
361
362 for (i = 0; i < PCI_NUM_PINS; ++i) {
363 pci_set_irq_state(s, i, irq_state[i]);
364 }
365
366 return 0;
367 }
368
369 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
370 {
371 int i;
372 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
373
374 for (i = 0; i < PCI_NUM_PINS; ++i) {
375 qemu_put_be32(f, pci_irq_state(s, i));
376 }
377 }
378
379 static VMStateInfo vmstate_info_pci_irq_state = {
380 .name = "pci irq state",
381 .get = get_pci_irq_state,
382 .put = put_pci_irq_state,
383 };
384
385 const VMStateDescription vmstate_pci_device = {
386 .name = "PCIDevice",
387 .version_id = 2,
388 .minimum_version_id = 1,
389 .minimum_version_id_old = 1,
390 .fields = (VMStateField []) {
391 VMSTATE_INT32_LE(version_id, PCIDevice),
392 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
393 vmstate_info_pci_config,
394 PCI_CONFIG_SPACE_SIZE),
395 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
396 vmstate_info_pci_irq_state,
397 PCI_NUM_PINS * sizeof(int32_t)),
398 VMSTATE_END_OF_LIST()
399 }
400 };
401
402 const VMStateDescription vmstate_pcie_device = {
403 .name = "PCIDevice",
404 .version_id = 2,
405 .minimum_version_id = 1,
406 .minimum_version_id_old = 1,
407 .fields = (VMStateField []) {
408 VMSTATE_INT32_LE(version_id, PCIDevice),
409 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
410 vmstate_info_pci_config,
411 PCIE_CONFIG_SPACE_SIZE),
412 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
413 vmstate_info_pci_irq_state,
414 PCI_NUM_PINS * sizeof(int32_t)),
415 VMSTATE_END_OF_LIST()
416 }
417 };
418
419 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
420 {
421 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
422 }
423
424 void pci_device_save(PCIDevice *s, QEMUFile *f)
425 {
426 /* Clear interrupt status bit: it is implicit
427 * in irq_state which we are saving.
428 * This makes us compatible with old devices
429 * which never set or clear this bit. */
430 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
431 vmstate_save_state(f, pci_get_vmstate(s), s);
432 /* Restore the interrupt status bit. */
433 pci_update_irq_status(s);
434 }
435
436 int pci_device_load(PCIDevice *s, QEMUFile *f)
437 {
438 int ret;
439 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
440 /* Restore the interrupt status bit. */
441 pci_update_irq_status(s);
442 return ret;
443 }
444
445 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
446 {
447 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
448 pci_default_sub_vendor_id);
449 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
450 pci_default_sub_device_id);
451 }
452
453 /*
454 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
455 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
456 */
457 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
458 unsigned int *slotp, unsigned int *funcp)
459 {
460 const char *p;
461 char *e;
462 unsigned long val;
463 unsigned long dom = 0, bus = 0;
464 unsigned int slot = 0;
465 unsigned int func = 0;
466
467 p = addr;
468 val = strtoul(p, &e, 16);
469 if (e == p)
470 return -1;
471 if (*e == ':') {
472 bus = val;
473 p = e + 1;
474 val = strtoul(p, &e, 16);
475 if (e == p)
476 return -1;
477 if (*e == ':') {
478 dom = bus;
479 bus = val;
480 p = e + 1;
481 val = strtoul(p, &e, 16);
482 if (e == p)
483 return -1;
484 }
485 }
486
487 slot = val;
488
489 if (funcp != NULL) {
490 if (*e != '.')
491 return -1;
492
493 p = e + 1;
494 val = strtoul(p, &e, 16);
495 if (e == p)
496 return -1;
497
498 func = val;
499 }
500
501 /* if funcp == NULL func is 0 */
502 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
503 return -1;
504
505 if (*e)
506 return -1;
507
508 /* Note: QEMU doesn't implement domains other than 0 */
509 if (!pci_find_bus(pci_find_root_bus(dom), bus))
510 return -1;
511
512 *domp = dom;
513 *busp = bus;
514 *slotp = slot;
515 if (funcp != NULL)
516 *funcp = func;
517 return 0;
518 }
519
520 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
521 unsigned *slotp)
522 {
523 /* strip legacy tag */
524 if (!strncmp(addr, "pci_addr=", 9)) {
525 addr += 9;
526 }
527 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
528 monitor_printf(mon, "Invalid pci address\n");
529 return -1;
530 }
531 return 0;
532 }
533
534 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
535 {
536 int dom, bus;
537 unsigned slot;
538
539 if (!devaddr) {
540 *devfnp = -1;
541 return pci_find_bus(pci_find_root_bus(0), 0);
542 }
543
544 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
545 return NULL;
546 }
547
548 *devfnp = slot << 3;
549 return pci_find_bus(pci_find_root_bus(dom), bus);
550 }
551
552 static void pci_init_cmask(PCIDevice *dev)
553 {
554 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
555 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
556 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
557 dev->cmask[PCI_REVISION_ID] = 0xff;
558 dev->cmask[PCI_CLASS_PROG] = 0xff;
559 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
560 dev->cmask[PCI_HEADER_TYPE] = 0xff;
561 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
562 }
563
564 static void pci_init_wmask(PCIDevice *dev)
565 {
566 int config_size = pci_config_size(dev);
567
568 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
569 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
570 pci_set_word(dev->wmask + PCI_COMMAND,
571 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
572 PCI_COMMAND_INTX_DISABLE);
573
574 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
575 config_size - PCI_CONFIG_HEADER_SIZE);
576 }
577
578 static void pci_init_w1cmask(PCIDevice *dev)
579 {
580 /*
581 * Note: It's okay to set w1cmask even for readonly bits as
582 * long as their value is hardwired to 0.
583 */
584 pci_set_word(dev->w1cmask + PCI_STATUS,
585 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
586 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
587 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
588 }
589
590 static void pci_init_wmask_bridge(PCIDevice *d)
591 {
592 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
593 PCI_SEC_LETENCY_TIMER */
594 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
595
596 /* base and limit */
597 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
598 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
599 pci_set_word(d->wmask + PCI_MEMORY_BASE,
600 PCI_MEMORY_RANGE_MASK & 0xffff);
601 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
602 PCI_MEMORY_RANGE_MASK & 0xffff);
603 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
604 PCI_PREF_RANGE_MASK & 0xffff);
605 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
606 PCI_PREF_RANGE_MASK & 0xffff);
607
608 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
609 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
610
611 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
612 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
613 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
614 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
615 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
616 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
617 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
618 PCI_BRIDGE_CTL_PARITY |
619 PCI_BRIDGE_CTL_SERR |
620 PCI_BRIDGE_CTL_ISA |
621 PCI_BRIDGE_CTL_VGA |
622 PCI_BRIDGE_CTL_VGA_16BIT |
623 PCI_BRIDGE_CTL_MASTER_ABORT |
624 PCI_BRIDGE_CTL_BUS_RESET |
625 PCI_BRIDGE_CTL_FAST_BACK |
626 PCI_BRIDGE_CTL_DISCARD |
627 PCI_BRIDGE_CTL_SEC_DISCARD |
628 PCI_BRIDGE_CTL_DISCARD_STATUS |
629 PCI_BRIDGE_CTL_DISCARD_SERR);
630 /* Below does not do anything as we never set this bit, put here for
631 * completeness. */
632 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
633 PCI_BRIDGE_CTL_DISCARD_STATUS);
634 }
635
636 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
637 {
638 uint8_t slot = PCI_SLOT(dev->devfn);
639 uint8_t func;
640
641 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
642 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
643 }
644
645 /*
646 * multifunction bit is interpreted in two ways as follows.
647 * - all functions must set the bit to 1.
648 * Example: Intel X53
649 * - function 0 must set the bit, but the rest function (> 0)
650 * is allowed to leave the bit to 0.
651 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
652 *
653 * So OS (at least Linux) checks the bit of only function 0,
654 * and doesn't see the bit of function > 0.
655 *
656 * The below check allows both interpretation.
657 */
658 if (PCI_FUNC(dev->devfn)) {
659 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
660 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
661 /* function 0 should set multifunction bit */
662 error_report("PCI: single function device can't be populated "
663 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
664 return -1;
665 }
666 return 0;
667 }
668
669 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
670 return 0;
671 }
672 /* function 0 indicates single function, so function > 0 must be NULL */
673 for (func = 1; func < PCI_FUNC_MAX; ++func) {
674 if (bus->devices[PCI_DEVFN(slot, func)]) {
675 error_report("PCI: %x.0 indicates single function, "
676 "but %x.%x is already populated.",
677 slot, slot, func);
678 return -1;
679 }
680 }
681 return 0;
682 }
683
684 static void pci_config_alloc(PCIDevice *pci_dev)
685 {
686 int config_size = pci_config_size(pci_dev);
687
688 pci_dev->config = qemu_mallocz(config_size);
689 pci_dev->cmask = qemu_mallocz(config_size);
690 pci_dev->wmask = qemu_mallocz(config_size);
691 pci_dev->w1cmask = qemu_mallocz(config_size);
692 pci_dev->used = qemu_mallocz(config_size);
693 }
694
695 static void pci_config_free(PCIDevice *pci_dev)
696 {
697 qemu_free(pci_dev->config);
698 qemu_free(pci_dev->cmask);
699 qemu_free(pci_dev->wmask);
700 qemu_free(pci_dev->w1cmask);
701 qemu_free(pci_dev->used);
702 }
703
704 /* -1 for devfn means auto assign */
705 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
706 const char *name, int devfn,
707 PCIConfigReadFunc *config_read,
708 PCIConfigWriteFunc *config_write,
709 bool is_bridge)
710 {
711 if (devfn < 0) {
712 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
713 devfn += PCI_FUNC_MAX) {
714 if (!bus->devices[devfn])
715 goto found;
716 }
717 error_report("PCI: no slot/function available for %s, all in use", name);
718 return NULL;
719 found: ;
720 } else if (bus->devices[devfn]) {
721 error_report("PCI: slot %d function %d not available for %s, in use by %s",
722 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
723 return NULL;
724 }
725 pci_dev->bus = bus;
726 pci_dev->devfn = devfn;
727 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
728 pci_dev->irq_state = 0;
729 pci_config_alloc(pci_dev);
730
731 if (!is_bridge) {
732 pci_set_default_subsystem_id(pci_dev);
733 }
734 pci_init_cmask(pci_dev);
735 pci_init_wmask(pci_dev);
736 pci_init_w1cmask(pci_dev);
737 if (is_bridge) {
738 pci_init_wmask_bridge(pci_dev);
739 }
740 if (pci_init_multifunction(bus, pci_dev)) {
741 pci_config_free(pci_dev);
742 return NULL;
743 }
744
745 if (!config_read)
746 config_read = pci_default_read_config;
747 if (!config_write)
748 config_write = pci_default_write_config;
749 pci_dev->config_read = config_read;
750 pci_dev->config_write = config_write;
751 bus->devices[devfn] = pci_dev;
752 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
753 pci_dev->version_id = 2; /* Current pci device vmstate version */
754 return pci_dev;
755 }
756
757 static void do_pci_unregister_device(PCIDevice *pci_dev)
758 {
759 qemu_free_irqs(pci_dev->irq);
760 pci_dev->bus->devices[pci_dev->devfn] = NULL;
761 pci_config_free(pci_dev);
762 }
763
764 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
765 int instance_size, int devfn,
766 PCIConfigReadFunc *config_read,
767 PCIConfigWriteFunc *config_write)
768 {
769 PCIDevice *pci_dev;
770
771 pci_dev = qemu_mallocz(instance_size);
772 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
773 config_read, config_write,
774 PCI_HEADER_TYPE_NORMAL);
775 if (pci_dev == NULL) {
776 hw_error("PCI: can't register device\n");
777 }
778 return pci_dev;
779 }
780
781 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
782 target_phys_addr_t addr)
783 {
784 return addr + bus->mem_base;
785 }
786
787 static void pci_unregister_io_regions(PCIDevice *pci_dev)
788 {
789 PCIIORegion *r;
790 int i;
791
792 for(i = 0; i < PCI_NUM_REGIONS; i++) {
793 r = &pci_dev->io_regions[i];
794 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
795 continue;
796 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
797 isa_unassign_ioport(r->addr, r->filtered_size);
798 } else {
799 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
800 r->addr),
801 r->filtered_size,
802 IO_MEM_UNASSIGNED);
803 }
804 }
805 }
806
807 static int pci_unregister_device(DeviceState *dev)
808 {
809 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
810 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
811 int ret = 0;
812
813 if (info->exit)
814 ret = info->exit(pci_dev);
815 if (ret)
816 return ret;
817
818 pci_unregister_io_regions(pci_dev);
819 pci_del_option_rom(pci_dev);
820 do_pci_unregister_device(pci_dev);
821 return 0;
822 }
823
824 void pci_register_bar(PCIDevice *pci_dev, int region_num,
825 pcibus_t size, uint8_t type,
826 PCIMapIORegionFunc *map_func)
827 {
828 PCIIORegion *r;
829 uint32_t addr;
830 uint64_t wmask;
831
832 assert(region_num >= 0);
833 assert(region_num < PCI_NUM_REGIONS);
834 if (size & (size-1)) {
835 fprintf(stderr, "ERROR: PCI region size must be pow2 "
836 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
837 exit(1);
838 }
839
840 r = &pci_dev->io_regions[region_num];
841 r->addr = PCI_BAR_UNMAPPED;
842 r->size = size;
843 r->filtered_size = size;
844 r->type = type;
845 r->map_func = map_func;
846
847 wmask = ~(size - 1);
848 addr = pci_bar(pci_dev, region_num);
849 if (region_num == PCI_ROM_SLOT) {
850 /* ROM enable bit is writeable */
851 wmask |= PCI_ROM_ADDRESS_ENABLE;
852 }
853 pci_set_long(pci_dev->config + addr, type);
854 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
855 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
856 pci_set_quad(pci_dev->wmask + addr, wmask);
857 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
858 } else {
859 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
860 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
861 }
862 }
863
864 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
865 uint8_t type)
866 {
867 pcibus_t base = *addr;
868 pcibus_t limit = *addr + *size - 1;
869 PCIDevice *br;
870
871 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
872 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
873
874 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
875 if (!(cmd & PCI_COMMAND_IO)) {
876 goto no_map;
877 }
878 } else {
879 if (!(cmd & PCI_COMMAND_MEMORY)) {
880 goto no_map;
881 }
882 }
883
884 base = MAX(base, pci_bridge_get_base(br, type));
885 limit = MIN(limit, pci_bridge_get_limit(br, type));
886 }
887
888 if (base > limit) {
889 goto no_map;
890 }
891 *addr = base;
892 *size = limit - base + 1;
893 return;
894 no_map:
895 *addr = PCI_BAR_UNMAPPED;
896 *size = 0;
897 }
898
899 static pcibus_t pci_bar_address(PCIDevice *d,
900 int reg, uint8_t type, pcibus_t size)
901 {
902 pcibus_t new_addr, last_addr;
903 int bar = pci_bar(d, reg);
904 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
905
906 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
907 if (!(cmd & PCI_COMMAND_IO)) {
908 return PCI_BAR_UNMAPPED;
909 }
910 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
911 last_addr = new_addr + size - 1;
912 /* NOTE: we have only 64K ioports on PC */
913 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
914 return PCI_BAR_UNMAPPED;
915 }
916 return new_addr;
917 }
918
919 if (!(cmd & PCI_COMMAND_MEMORY)) {
920 return PCI_BAR_UNMAPPED;
921 }
922 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
923 new_addr = pci_get_quad(d->config + bar);
924 } else {
925 new_addr = pci_get_long(d->config + bar);
926 }
927 /* the ROM slot has a specific enable bit */
928 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
929 return PCI_BAR_UNMAPPED;
930 }
931 new_addr &= ~(size - 1);
932 last_addr = new_addr + size - 1;
933 /* NOTE: we do not support wrapping */
934 /* XXX: as we cannot support really dynamic
935 mappings, we handle specific values as invalid
936 mappings. */
937 if (last_addr <= new_addr || new_addr == 0 ||
938 last_addr == PCI_BAR_UNMAPPED) {
939 return PCI_BAR_UNMAPPED;
940 }
941
942 /* Now pcibus_t is 64bit.
943 * Check if 32 bit BAR wraps around explicitly.
944 * Without this, PC ide doesn't work well.
945 * TODO: remove this work around.
946 */
947 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
948 return PCI_BAR_UNMAPPED;
949 }
950
951 /*
952 * OS is allowed to set BAR beyond its addressable
953 * bits. For example, 32 bit OS can set 64bit bar
954 * to >4G. Check it. TODO: we might need to support
955 * it in the future for e.g. PAE.
956 */
957 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
958 return PCI_BAR_UNMAPPED;
959 }
960
961 return new_addr;
962 }
963
964 static void pci_update_mappings(PCIDevice *d)
965 {
966 PCIIORegion *r;
967 int i;
968 pcibus_t new_addr, filtered_size;
969
970 for(i = 0; i < PCI_NUM_REGIONS; i++) {
971 r = &d->io_regions[i];
972
973 /* this region isn't registered */
974 if (!r->size)
975 continue;
976
977 new_addr = pci_bar_address(d, i, r->type, r->size);
978
979 /* bridge filtering */
980 filtered_size = r->size;
981 if (new_addr != PCI_BAR_UNMAPPED) {
982 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
983 }
984
985 /* This bar isn't changed */
986 if (new_addr == r->addr && filtered_size == r->filtered_size)
987 continue;
988
989 /* now do the real mapping */
990 if (r->addr != PCI_BAR_UNMAPPED) {
991 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
992 int class;
993 /* NOTE: specific hack for IDE in PC case:
994 only one byte must be mapped. */
995 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
996 if (class == 0x0101 && r->size == 4) {
997 isa_unassign_ioport(r->addr + 2, 1);
998 } else {
999 isa_unassign_ioport(r->addr, r->filtered_size);
1000 }
1001 } else {
1002 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1003 r->filtered_size,
1004 IO_MEM_UNASSIGNED);
1005 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1006 }
1007 }
1008 r->addr = new_addr;
1009 r->filtered_size = filtered_size;
1010 if (r->addr != PCI_BAR_UNMAPPED) {
1011 /*
1012 * TODO: currently almost all the map funcions assumes
1013 * filtered_size == size and addr & ~(size - 1) == addr.
1014 * However with bridge filtering, they aren't always true.
1015 * Teach them such cases, such that filtered_size < size and
1016 * addr & (size - 1) != 0.
1017 */
1018 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1019 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1020 } else {
1021 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1022 r->filtered_size, r->type);
1023 }
1024 }
1025 }
1026 }
1027
1028 static inline int pci_irq_disabled(PCIDevice *d)
1029 {
1030 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1031 }
1032
1033 /* Called after interrupt disabled field update in config space,
1034 * assert/deassert interrupts if necessary.
1035 * Gets original interrupt disable bit value (before update). */
1036 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1037 {
1038 int i, disabled = pci_irq_disabled(d);
1039 if (disabled == was_irq_disabled)
1040 return;
1041 for (i = 0; i < PCI_NUM_PINS; ++i) {
1042 int state = pci_irq_state(d, i);
1043 pci_change_irq_level(d, i, disabled ? -state : state);
1044 }
1045 }
1046
1047 uint32_t pci_default_read_config(PCIDevice *d,
1048 uint32_t address, int len)
1049 {
1050 uint32_t val = 0;
1051 assert(len == 1 || len == 2 || len == 4);
1052 len = MIN(len, pci_config_size(d) - address);
1053 memcpy(&val, d->config + address, len);
1054 return le32_to_cpu(val);
1055 }
1056
1057 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1058 {
1059 int i, was_irq_disabled = pci_irq_disabled(d);
1060 uint32_t config_size = pci_config_size(d);
1061
1062 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1063 uint8_t wmask = d->wmask[addr + i];
1064 uint8_t w1cmask = d->w1cmask[addr + i];
1065 assert(!(wmask & w1cmask));
1066 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1067 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1068 }
1069 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1070 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1071 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1072 range_covers_byte(addr, l, PCI_COMMAND))
1073 pci_update_mappings(d);
1074
1075 if (range_covers_byte(addr, l, PCI_COMMAND))
1076 pci_update_irq_disabled(d, was_irq_disabled);
1077 }
1078
1079 /***********************************************************/
1080 /* generic PCI irq support */
1081
1082 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1083 static void pci_set_irq(void *opaque, int irq_num, int level)
1084 {
1085 PCIDevice *pci_dev = opaque;
1086 int change;
1087
1088 change = level - pci_irq_state(pci_dev, irq_num);
1089 if (!change)
1090 return;
1091
1092 pci_set_irq_state(pci_dev, irq_num, level);
1093 pci_update_irq_status(pci_dev);
1094 if (pci_irq_disabled(pci_dev))
1095 return;
1096 pci_change_irq_level(pci_dev, irq_num, change);
1097 }
1098
1099 bool pci_msi_enabled(PCIDevice *dev)
1100 {
1101 return msix_enabled(dev) || msi_enabled(dev);
1102 }
1103
1104 void pci_msi_notify(PCIDevice *dev, unsigned int vector)
1105 {
1106 if (msix_enabled(dev)) {
1107 msix_notify(dev, vector);
1108 } else if (msi_enabled(dev)) {
1109 msi_notify(dev, vector);
1110 } else {
1111 /* MSI/MSI-X must be enabled */
1112 abort();
1113 }
1114 }
1115
1116 /***********************************************************/
1117 /* monitor info on PCI */
1118
1119 typedef struct {
1120 uint16_t class;
1121 const char *desc;
1122 const char *fw_name;
1123 uint16_t fw_ign_bits;
1124 } pci_class_desc;
1125
1126 static const pci_class_desc pci_class_descriptions[] =
1127 {
1128 { 0x0001, "VGA controller", "display"},
1129 { 0x0100, "SCSI controller", "scsi"},
1130 { 0x0101, "IDE controller", "ide"},
1131 { 0x0102, "Floppy controller", "fdc"},
1132 { 0x0103, "IPI controller", "ipi"},
1133 { 0x0104, "RAID controller", "raid"},
1134 { 0x0106, "SATA controller"},
1135 { 0x0107, "SAS controller"},
1136 { 0x0180, "Storage controller"},
1137 { 0x0200, "Ethernet controller", "ethernet"},
1138 { 0x0201, "Token Ring controller", "token-ring"},
1139 { 0x0202, "FDDI controller", "fddi"},
1140 { 0x0203, "ATM controller", "atm"},
1141 { 0x0280, "Network controller"},
1142 { 0x0300, "VGA controller", "display", 0x00ff},
1143 { 0x0301, "XGA controller"},
1144 { 0x0302, "3D controller"},
1145 { 0x0380, "Display controller"},
1146 { 0x0400, "Video controller", "video"},
1147 { 0x0401, "Audio controller", "sound"},
1148 { 0x0402, "Phone"},
1149 { 0x0480, "Multimedia controller"},
1150 { 0x0500, "RAM controller", "memory"},
1151 { 0x0501, "Flash controller", "flash"},
1152 { 0x0580, "Memory controller"},
1153 { 0x0600, "Host bridge", "host"},
1154 { 0x0601, "ISA bridge", "isa"},
1155 { 0x0602, "EISA bridge", "eisa"},
1156 { 0x0603, "MC bridge", "mca"},
1157 { 0x0604, "PCI bridge", "pci"},
1158 { 0x0605, "PCMCIA bridge", "pcmcia"},
1159 { 0x0606, "NUBUS bridge", "nubus"},
1160 { 0x0607, "CARDBUS bridge", "cardbus"},
1161 { 0x0608, "RACEWAY bridge"},
1162 { 0x0680, "Bridge"},
1163 { 0x0700, "Serial port", "serial"},
1164 { 0x0701, "Parallel port", "parallel"},
1165 { 0x0800, "Interrupt controller", "interrupt-controller"},
1166 { 0x0801, "DMA controller", "dma-controller"},
1167 { 0x0802, "Timer", "timer"},
1168 { 0x0803, "RTC", "rtc"},
1169 { 0x0900, "Keyboard", "keyboard"},
1170 { 0x0901, "Pen", "pen"},
1171 { 0x0902, "Mouse", "mouse"},
1172 { 0x0A00, "Dock station", "dock", 0x00ff},
1173 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1174 { 0x0c00, "Fireware contorller", "fireware"},
1175 { 0x0c01, "Access bus controller", "access-bus"},
1176 { 0x0c02, "SSA controller", "ssa"},
1177 { 0x0c03, "USB controller", "usb"},
1178 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1179 { 0, NULL}
1180 };
1181
1182 static void pci_for_each_device_under_bus(PCIBus *bus,
1183 void (*fn)(PCIBus *b, PCIDevice *d))
1184 {
1185 PCIDevice *d;
1186 int devfn;
1187
1188 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1189 d = bus->devices[devfn];
1190 if (d) {
1191 fn(bus, d);
1192 }
1193 }
1194 }
1195
1196 void pci_for_each_device(PCIBus *bus, int bus_num,
1197 void (*fn)(PCIBus *b, PCIDevice *d))
1198 {
1199 bus = pci_find_bus(bus, bus_num);
1200
1201 if (bus) {
1202 pci_for_each_device_under_bus(bus, fn);
1203 }
1204 }
1205
1206 static void pci_device_print(Monitor *mon, QDict *device)
1207 {
1208 QDict *qdict;
1209 QListEntry *entry;
1210 uint64_t addr, size;
1211
1212 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1213 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1214 qdict_get_int(device, "slot"),
1215 qdict_get_int(device, "function"));
1216 monitor_printf(mon, " ");
1217
1218 qdict = qdict_get_qdict(device, "class_info");
1219 if (qdict_haskey(qdict, "desc")) {
1220 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1221 } else {
1222 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1223 }
1224
1225 qdict = qdict_get_qdict(device, "id");
1226 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1227 qdict_get_int(qdict, "device"),
1228 qdict_get_int(qdict, "vendor"));
1229
1230 if (qdict_haskey(device, "irq")) {
1231 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1232 qdict_get_int(device, "irq"));
1233 }
1234
1235 if (qdict_haskey(device, "pci_bridge")) {
1236 QDict *info;
1237
1238 qdict = qdict_get_qdict(device, "pci_bridge");
1239
1240 info = qdict_get_qdict(qdict, "bus");
1241 monitor_printf(mon, " BUS %" PRId64 ".\n",
1242 qdict_get_int(info, "number"));
1243 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1244 qdict_get_int(info, "secondary"));
1245 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1246 qdict_get_int(info, "subordinate"));
1247
1248 info = qdict_get_qdict(qdict, "io_range");
1249 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1250 qdict_get_int(info, "base"),
1251 qdict_get_int(info, "limit"));
1252
1253 info = qdict_get_qdict(qdict, "memory_range");
1254 monitor_printf(mon,
1255 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1256 qdict_get_int(info, "base"),
1257 qdict_get_int(info, "limit"));
1258
1259 info = qdict_get_qdict(qdict, "prefetchable_range");
1260 monitor_printf(mon, " prefetchable memory range "
1261 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1262 qdict_get_int(info, "base"),
1263 qdict_get_int(info, "limit"));
1264 }
1265
1266 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1267 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1268 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1269
1270 addr = qdict_get_int(qdict, "address");
1271 size = qdict_get_int(qdict, "size");
1272
1273 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1274 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1275 " [0x%04"FMT_PCIBUS"].\n",
1276 addr, addr + size - 1);
1277 } else {
1278 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1279 " [0x%08"FMT_PCIBUS"].\n",
1280 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1281 qdict_get_bool(qdict, "prefetch") ?
1282 " prefetchable" : "", addr, addr + size - 1);
1283 }
1284 }
1285
1286 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1287
1288 if (qdict_haskey(device, "pci_bridge")) {
1289 qdict = qdict_get_qdict(device, "pci_bridge");
1290 if (qdict_haskey(qdict, "devices")) {
1291 QListEntry *dev;
1292 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1293 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1294 }
1295 }
1296 }
1297 }
1298
1299 void do_pci_info_print(Monitor *mon, const QObject *data)
1300 {
1301 QListEntry *bus, *dev;
1302
1303 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1304 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1305 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1306 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1307 }
1308 }
1309 }
1310
1311 static QObject *pci_get_dev_class(const PCIDevice *dev)
1312 {
1313 int class;
1314 const pci_class_desc *desc;
1315
1316 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1317 desc = pci_class_descriptions;
1318 while (desc->desc && class != desc->class)
1319 desc++;
1320
1321 if (desc->desc) {
1322 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1323 desc->desc, class);
1324 } else {
1325 return qobject_from_jsonf("{ 'class': %d }", class);
1326 }
1327 }
1328
1329 static QObject *pci_get_dev_id(const PCIDevice *dev)
1330 {
1331 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1332 pci_get_word(dev->config + PCI_VENDOR_ID),
1333 pci_get_word(dev->config + PCI_DEVICE_ID));
1334 }
1335
1336 static QObject *pci_get_regions_list(const PCIDevice *dev)
1337 {
1338 int i;
1339 QList *regions_list;
1340
1341 regions_list = qlist_new();
1342
1343 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1344 QObject *obj;
1345 const PCIIORegion *r = &dev->io_regions[i];
1346
1347 if (!r->size) {
1348 continue;
1349 }
1350
1351 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1352 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1353 "'address': %" PRId64 ", "
1354 "'size': %" PRId64 " }",
1355 i, r->addr, r->size);
1356 } else {
1357 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1358
1359 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1360 "'mem_type_64': %i, 'prefetch': %i, "
1361 "'address': %" PRId64 ", "
1362 "'size': %" PRId64 " }",
1363 i, mem_type_64,
1364 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1365 r->addr, r->size);
1366 }
1367
1368 qlist_append_obj(regions_list, obj);
1369 }
1370
1371 return QOBJECT(regions_list);
1372 }
1373
1374 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1375
1376 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1377 {
1378 uint8_t type;
1379 QObject *obj;
1380
1381 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1382 " 'qdev_id': %s }",
1383 bus_num,
1384 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1385 pci_get_dev_class(dev), pci_get_dev_id(dev),
1386 pci_get_regions_list(dev),
1387 dev->qdev.id ? dev->qdev.id : "");
1388
1389 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1390 QDict *qdict = qobject_to_qdict(obj);
1391 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1392 }
1393
1394 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1395 if (type == PCI_HEADER_TYPE_BRIDGE) {
1396 QDict *qdict;
1397 QObject *pci_bridge;
1398
1399 pci_bridge = qobject_from_jsonf("{ 'bus': "
1400 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1401 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1402 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1403 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1404 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1405 dev->config[PCI_SUBORDINATE_BUS],
1406 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1407 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1408 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1409 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1410 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1411 PCI_BASE_ADDRESS_MEM_PREFETCH),
1412 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1413 PCI_BASE_ADDRESS_MEM_PREFETCH));
1414
1415 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1416 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1417
1418 if (child_bus) {
1419 qdict = qobject_to_qdict(pci_bridge);
1420 qdict_put_obj(qdict, "devices",
1421 pci_get_devices_list(child_bus,
1422 dev->config[PCI_SECONDARY_BUS]));
1423 }
1424 }
1425 qdict = qobject_to_qdict(obj);
1426 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1427 }
1428
1429 return obj;
1430 }
1431
1432 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1433 {
1434 int devfn;
1435 PCIDevice *dev;
1436 QList *dev_list;
1437
1438 dev_list = qlist_new();
1439
1440 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1441 dev = bus->devices[devfn];
1442 if (dev) {
1443 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1444 }
1445 }
1446
1447 return QOBJECT(dev_list);
1448 }
1449
1450 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1451 {
1452 bus = pci_find_bus(bus, bus_num);
1453 if (bus) {
1454 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1455 bus_num, pci_get_devices_list(bus, bus_num));
1456 }
1457
1458 return NULL;
1459 }
1460
1461 void do_pci_info(Monitor *mon, QObject **ret_data)
1462 {
1463 QList *bus_list;
1464 struct PCIHostBus *host;
1465
1466 bus_list = qlist_new();
1467
1468 QLIST_FOREACH(host, &host_buses, next) {
1469 QObject *obj = pci_get_bus_dict(host->bus, 0);
1470 if (obj) {
1471 qlist_append_obj(bus_list, obj);
1472 }
1473 }
1474
1475 *ret_data = QOBJECT(bus_list);
1476 }
1477
1478 static const char * const pci_nic_models[] = {
1479 "ne2k_pci",
1480 "i82551",
1481 "i82557b",
1482 "i82559er",
1483 "rtl8139",
1484 "e1000",
1485 "pcnet",
1486 "virtio",
1487 NULL
1488 };
1489
1490 static const char * const pci_nic_names[] = {
1491 "ne2k_pci",
1492 "i82551",
1493 "i82557b",
1494 "i82559er",
1495 "rtl8139",
1496 "e1000",
1497 "pcnet",
1498 "virtio-net-pci",
1499 NULL
1500 };
1501
1502 /* Initialize a PCI NIC. */
1503 /* FIXME callers should check for failure, but don't */
1504 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1505 const char *default_devaddr)
1506 {
1507 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1508 PCIBus *bus;
1509 int devfn;
1510 PCIDevice *pci_dev;
1511 DeviceState *dev;
1512 int i;
1513
1514 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1515 if (i < 0)
1516 return NULL;
1517
1518 bus = pci_get_bus_devfn(&devfn, devaddr);
1519 if (!bus) {
1520 error_report("Invalid PCI device address %s for device %s",
1521 devaddr, pci_nic_names[i]);
1522 return NULL;
1523 }
1524
1525 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1526 dev = &pci_dev->qdev;
1527 qdev_set_nic_properties(dev, nd);
1528 if (qdev_init(dev) < 0)
1529 return NULL;
1530 return pci_dev;
1531 }
1532
1533 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1534 const char *default_devaddr)
1535 {
1536 PCIDevice *res;
1537
1538 if (qemu_show_nic_models(nd->model, pci_nic_models))
1539 exit(0);
1540
1541 res = pci_nic_init(nd, default_model, default_devaddr);
1542 if (!res)
1543 exit(1);
1544 return res;
1545 }
1546
1547 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1548 {
1549 pci_update_mappings(d);
1550 }
1551
1552 void pci_bridge_update_mappings(PCIBus *b)
1553 {
1554 PCIBus *child;
1555
1556 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1557
1558 QLIST_FOREACH(child, &b->child, sibling) {
1559 pci_bridge_update_mappings(child);
1560 }
1561 }
1562
1563 /* Whether a given bus number is in range of the secondary
1564 * bus of the given bridge device. */
1565 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1566 {
1567 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1568 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1569 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1570 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1571 }
1572
1573 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1574 {
1575 PCIBus *sec;
1576
1577 if (!bus) {
1578 return NULL;
1579 }
1580
1581 if (pci_bus_num(bus) == bus_num) {
1582 return bus;
1583 }
1584
1585 /* Consider all bus numbers in range for the host pci bridge. */
1586 if (bus->parent_dev &&
1587 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1588 return NULL;
1589 }
1590
1591 /* try child bus */
1592 for (; bus; bus = sec) {
1593 QLIST_FOREACH(sec, &bus->child, sibling) {
1594 assert(sec->parent_dev);
1595 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1596 return sec;
1597 }
1598 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1599 break;
1600 }
1601 }
1602 }
1603
1604 return NULL;
1605 }
1606
1607 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1608 {
1609 bus = pci_find_bus(bus, bus_num);
1610
1611 if (!bus)
1612 return NULL;
1613
1614 return bus->devices[PCI_DEVFN(slot, function)];
1615 }
1616
1617 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1618 {
1619 PCIDevice *pci_dev = (PCIDevice *)qdev;
1620 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1621 PCIBus *bus;
1622 int devfn, rc;
1623 bool is_default_rom;
1624
1625 /* initialize cap_present for pci_is_express() and pci_config_size() */
1626 if (info->is_express) {
1627 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1628 }
1629
1630 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1631 devfn = pci_dev->devfn;
1632 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1633 info->config_read, info->config_write,
1634 info->is_bridge);
1635 if (pci_dev == NULL)
1636 return -1;
1637 rc = info->init(pci_dev);
1638 if (rc != 0) {
1639 do_pci_unregister_device(pci_dev);
1640 return rc;
1641 }
1642
1643 /* rom loading */
1644 is_default_rom = false;
1645 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1646 pci_dev->romfile = qemu_strdup(info->romfile);
1647 is_default_rom = true;
1648 }
1649 pci_add_option_rom(pci_dev, is_default_rom);
1650
1651 if (bus->hotplug) {
1652 /* Let buses differentiate between hotplug and when device is
1653 * enabled during qemu machine creation. */
1654 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1655 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1656 PCI_COLDPLUG_ENABLED);
1657 if (rc != 0) {
1658 int r = pci_unregister_device(&pci_dev->qdev);
1659 assert(!r);
1660 return rc;
1661 }
1662 }
1663 return 0;
1664 }
1665
1666 static int pci_unplug_device(DeviceState *qdev)
1667 {
1668 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1669
1670 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1671 PCI_HOTPLUG_DISABLED);
1672 }
1673
1674 void pci_qdev_register(PCIDeviceInfo *info)
1675 {
1676 info->qdev.init = pci_qdev_init;
1677 info->qdev.unplug = pci_unplug_device;
1678 info->qdev.exit = pci_unregister_device;
1679 info->qdev.bus_info = &pci_bus_info;
1680 qdev_register(&info->qdev);
1681 }
1682
1683 void pci_qdev_register_many(PCIDeviceInfo *info)
1684 {
1685 while (info->qdev.name) {
1686 pci_qdev_register(info);
1687 info++;
1688 }
1689 }
1690
1691 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1692 const char *name)
1693 {
1694 DeviceState *dev;
1695
1696 dev = qdev_create(&bus->qbus, name);
1697 qdev_prop_set_uint32(dev, "addr", devfn);
1698 qdev_prop_set_bit(dev, "multifunction", multifunction);
1699 return DO_UPCAST(PCIDevice, qdev, dev);
1700 }
1701
1702 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1703 bool multifunction,
1704 const char *name)
1705 {
1706 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1707 qdev_init_nofail(&dev->qdev);
1708 return dev;
1709 }
1710
1711 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1712 {
1713 return pci_create_multifunction(bus, devfn, false, name);
1714 }
1715
1716 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1717 {
1718 return pci_create_simple_multifunction(bus, devfn, false, name);
1719 }
1720
1721 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1722 {
1723 int config_size = pci_config_size(pdev);
1724 int offset = PCI_CONFIG_HEADER_SIZE;
1725 int i;
1726 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1727 if (pdev->used[i])
1728 offset = i + 1;
1729 else if (i - offset + 1 == size)
1730 return offset;
1731 return 0;
1732 }
1733
1734 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1735 uint8_t *prev_p)
1736 {
1737 uint8_t next, prev;
1738
1739 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1740 return 0;
1741
1742 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1743 prev = next + PCI_CAP_LIST_NEXT)
1744 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1745 break;
1746
1747 if (prev_p)
1748 *prev_p = prev;
1749 return next;
1750 }
1751
1752 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1753 {
1754 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1755 }
1756
1757 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1758 This is needed for an option rom which is used for more than one device. */
1759 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1760 {
1761 uint16_t vendor_id;
1762 uint16_t device_id;
1763 uint16_t rom_vendor_id;
1764 uint16_t rom_device_id;
1765 uint16_t rom_magic;
1766 uint16_t pcir_offset;
1767 uint8_t checksum;
1768
1769 /* Words in rom data are little endian (like in PCI configuration),
1770 so they can be read / written with pci_get_word / pci_set_word. */
1771
1772 /* Only a valid rom will be patched. */
1773 rom_magic = pci_get_word(ptr);
1774 if (rom_magic != 0xaa55) {
1775 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1776 return;
1777 }
1778 pcir_offset = pci_get_word(ptr + 0x18);
1779 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1780 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1781 return;
1782 }
1783
1784 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1785 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1786 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1787 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1788
1789 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1790 vendor_id, device_id, rom_vendor_id, rom_device_id);
1791
1792 checksum = ptr[6];
1793
1794 if (vendor_id != rom_vendor_id) {
1795 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1796 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1797 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1798 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1799 ptr[6] = checksum;
1800 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1801 }
1802
1803 if (device_id != rom_device_id) {
1804 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1805 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1806 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1807 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1808 ptr[6] = checksum;
1809 pci_set_word(ptr + pcir_offset + 6, device_id);
1810 }
1811 }
1812
1813 /* Add an option rom for the device */
1814 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1815 {
1816 int size;
1817 char *path;
1818 void *ptr;
1819 char name[32];
1820
1821 if (!pdev->romfile)
1822 return 0;
1823 if (strlen(pdev->romfile) == 0)
1824 return 0;
1825
1826 if (!pdev->rom_bar) {
1827 /*
1828 * Load rom via fw_cfg instead of creating a rom bar,
1829 * for 0.11 compatibility.
1830 */
1831 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1832 if (class == 0x0300) {
1833 rom_add_vga(pdev->romfile);
1834 } else {
1835 rom_add_option(pdev->romfile, -1);
1836 }
1837 return 0;
1838 }
1839
1840 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1841 if (path == NULL) {
1842 path = qemu_strdup(pdev->romfile);
1843 }
1844
1845 size = get_image_size(path);
1846 if (size < 0) {
1847 error_report("%s: failed to find romfile \"%s\"",
1848 __FUNCTION__, pdev->romfile);
1849 return -1;
1850 }
1851 if (size & (size - 1)) {
1852 size = 1 << qemu_fls(size);
1853 }
1854
1855 if (pdev->qdev.info->vmsd)
1856 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1857 else
1858 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1859 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1860
1861 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1862 load_image(path, ptr);
1863 qemu_free(path);
1864
1865 if (is_default_rom) {
1866 /* Only the default rom images will be patched (if needed). */
1867 pci_patch_ids(pdev, ptr, size);
1868 }
1869
1870 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1871 0, pci_map_option_rom);
1872
1873 return 0;
1874 }
1875
1876 static void pci_del_option_rom(PCIDevice *pdev)
1877 {
1878 if (!pdev->rom_offset)
1879 return;
1880
1881 qemu_ram_free(pdev->rom_offset);
1882 pdev->rom_offset = 0;
1883 }
1884
1885 /*
1886 * if !offset
1887 * Reserve space and add capability to the linked list in pci config space
1888 *
1889 * if offset = 0,
1890 * Find and reserve space and add capability to the linked list
1891 * in pci config space */
1892 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1893 uint8_t offset, uint8_t size)
1894 {
1895 uint8_t *config;
1896 if (!offset) {
1897 offset = pci_find_space(pdev, size);
1898 if (!offset) {
1899 return -ENOSPC;
1900 }
1901 }
1902
1903 config = pdev->config + offset;
1904 config[PCI_CAP_LIST_ID] = cap_id;
1905 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1906 pdev->config[PCI_CAPABILITY_LIST] = offset;
1907 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1908 memset(pdev->used + offset, 0xFF, size);
1909 /* Make capability read-only by default */
1910 memset(pdev->wmask + offset, 0, size);
1911 /* Check capability by default */
1912 memset(pdev->cmask + offset, 0xFF, size);
1913 return offset;
1914 }
1915
1916 /* Unlink capability from the pci config space. */
1917 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1918 {
1919 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1920 if (!offset)
1921 return;
1922 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1923 /* Make capability writeable again */
1924 memset(pdev->wmask + offset, 0xff, size);
1925 memset(pdev->w1cmask + offset, 0, size);
1926 /* Clear cmask as device-specific registers can't be checked */
1927 memset(pdev->cmask + offset, 0, size);
1928 memset(pdev->used + offset, 0, size);
1929
1930 if (!pdev->config[PCI_CAPABILITY_LIST])
1931 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1932 }
1933
1934 /* Reserve space for capability at a known offset (to call after load). */
1935 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1936 {
1937 memset(pdev->used + offset, 0xff, size);
1938 }
1939
1940 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1941 {
1942 return pci_find_capability_list(pdev, cap_id, NULL);
1943 }
1944
1945 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1946 {
1947 PCIDevice *d = (PCIDevice *)dev;
1948 const pci_class_desc *desc;
1949 char ctxt[64];
1950 PCIIORegion *r;
1951 int i, class;
1952
1953 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1954 desc = pci_class_descriptions;
1955 while (desc->desc && class != desc->class)
1956 desc++;
1957 if (desc->desc) {
1958 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1959 } else {
1960 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1961 }
1962
1963 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1964 "pci id %04x:%04x (sub %04x:%04x)\n",
1965 indent, "", ctxt, pci_bus_num(d->bus),
1966 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1967 pci_get_word(d->config + PCI_VENDOR_ID),
1968 pci_get_word(d->config + PCI_DEVICE_ID),
1969 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1970 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1971 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1972 r = &d->io_regions[i];
1973 if (!r->size)
1974 continue;
1975 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1976 " [0x%"FMT_PCIBUS"]\n",
1977 indent, "",
1978 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1979 r->addr, r->addr + r->size - 1);
1980 }
1981 }
1982
1983 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1984 {
1985 PCIDevice *d = (PCIDevice *)dev;
1986 const char *name = NULL;
1987 const pci_class_desc *desc = pci_class_descriptions;
1988 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1989
1990 while (desc->desc &&
1991 (class & ~desc->fw_ign_bits) !=
1992 (desc->class & ~desc->fw_ign_bits)) {
1993 desc++;
1994 }
1995
1996 if (desc->desc) {
1997 name = desc->fw_name;
1998 }
1999
2000 if (name) {
2001 pstrcpy(buf, len, name);
2002 } else {
2003 snprintf(buf, len, "pci%04x,%04x",
2004 pci_get_word(d->config + PCI_VENDOR_ID),
2005 pci_get_word(d->config + PCI_DEVICE_ID));
2006 }
2007
2008 return buf;
2009 }
2010
2011 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2012 {
2013 PCIDevice *d = (PCIDevice *)dev;
2014 char path[50], name[33];
2015 int off;
2016
2017 off = snprintf(path, sizeof(path), "%s@%x",
2018 pci_dev_fw_name(dev, name, sizeof name),
2019 PCI_SLOT(d->devfn));
2020 if (PCI_FUNC(d->devfn))
2021 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2022 return strdup(path);
2023 }
2024
2025 static char *pcibus_get_dev_path(DeviceState *dev)
2026 {
2027 PCIDevice *d = (PCIDevice *)dev;
2028 char path[16];
2029
2030 snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
2031 pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
2032 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
2033
2034 return strdup(path);
2035 }
2036
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