4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
34 #include "fpu/softfloat.h"
35 #include "qemu/module.h"
36 #include "migration/vmstate.h"
37 #include "hw/qdev-clock.h"
40 static void xtensa_cpu_set_pc(CPUState
*cs
, vaddr value
)
42 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
47 static vaddr
xtensa_cpu_get_pc(CPUState
*cs
)
49 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
54 static void xtensa_restore_state_to_opc(CPUState
*cs
,
55 const TranslationBlock
*tb
,
58 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
60 cpu
->env
.pc
= data
[0];
63 static bool xtensa_cpu_has_work(CPUState
*cs
)
65 #ifndef CONFIG_USER_ONLY
66 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
68 return !cpu
->env
.runstall
&& cpu
->env
.pending_irq_level
;
74 #ifdef CONFIG_USER_ONLY
75 static bool abi_call0
;
77 void xtensa_set_abi_call0(void)
82 bool xtensa_abi_call0(void)
88 static void xtensa_cpu_reset(DeviceState
*dev
)
90 CPUState
*s
= CPU(dev
);
91 XtensaCPU
*cpu
= XTENSA_CPU(s
);
92 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(cpu
);
93 CPUXtensaState
*env
= &cpu
->env
;
94 bool dfpu
= xtensa_option_enabled(env
->config
,
95 XTENSA_OPTION_DFP_COPROCESSOR
);
97 xcc
->parent_reset(dev
);
99 env
->pc
= env
->config
->exception_vector
[EXC_RESET0
+ env
->static_vectors
];
100 env
->sregs
[LITBASE
] &= ~1;
101 #ifndef CONFIG_USER_ONLY
102 env
->sregs
[PS
] = xtensa_option_enabled(env
->config
,
103 XTENSA_OPTION_INTERRUPT
) ? 0x1f : 0x10;
104 env
->pending_irq_level
= 0;
106 env
->sregs
[PS
] = PS_UM
| (3 << PS_RING_SHIFT
);
107 if (xtensa_option_enabled(env
->config
,
108 XTENSA_OPTION_WINDOWED_REGISTER
) &&
109 !xtensa_abi_call0()) {
110 env
->sregs
[PS
] |= PS_WOE
;
112 env
->sregs
[CPENABLE
] = 0xff;
114 env
->sregs
[VECBASE
] = env
->config
->vecbase
;
115 env
->sregs
[IBREAKENABLE
] = 0;
116 env
->sregs
[MEMCTL
] = MEMCTL_IL0EN
& env
->config
->memctl_mask
;
117 env
->sregs
[ATOMCTL
] = xtensa_option_enabled(env
->config
,
118 XTENSA_OPTION_ATOMCTL
) ? 0x28 : 0x15;
119 env
->sregs
[CONFIGID0
] = env
->config
->configid
[0];
120 env
->sregs
[CONFIGID1
] = env
->config
->configid
[1];
121 env
->exclusive_addr
= -1;
123 #ifndef CONFIG_USER_ONLY
125 s
->halted
= env
->runstall
;
127 set_no_signaling_nans(!dfpu
, &env
->fp_status
);
128 set_use_first_nan(!dfpu
, &env
->fp_status
);
131 static ObjectClass
*xtensa_cpu_class_by_name(const char *cpu_model
)
136 typename
= g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model
);
137 oc
= object_class_by_name(typename
);
139 if (oc
== NULL
|| !object_class_dynamic_cast(oc
, TYPE_XTENSA_CPU
) ||
140 object_class_is_abstract(oc
)) {
146 static void xtensa_cpu_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
148 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
150 info
->private_data
= cpu
->env
.config
->isa
;
151 info
->print_insn
= print_insn_xtensa
;
154 static void xtensa_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
156 CPUState
*cs
= CPU(dev
);
157 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(dev
);
158 Error
*local_err
= NULL
;
160 #ifndef CONFIG_USER_ONLY
161 xtensa_irq_init(&XTENSA_CPU(dev
)->env
);
164 cpu_exec_realizefn(cs
, &local_err
);
165 if (local_err
!= NULL
) {
166 error_propagate(errp
, local_err
);
170 cs
->gdb_num_regs
= xcc
->config
->gdb_regmap
.num_regs
;
174 xcc
->parent_realize(dev
, errp
);
177 static void xtensa_cpu_initfn(Object
*obj
)
179 XtensaCPU
*cpu
= XTENSA_CPU(obj
);
180 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(obj
);
181 CPUXtensaState
*env
= &cpu
->env
;
183 cpu_set_cpustate_pointers(cpu
);
184 env
->config
= xcc
->config
;
186 #ifndef CONFIG_USER_ONLY
187 env
->address_space_er
= g_malloc(sizeof(*env
->address_space_er
));
188 env
->system_er
= g_malloc(sizeof(*env
->system_er
));
189 memory_region_init_io(env
->system_er
, obj
, NULL
, env
, "er",
190 UINT64_C(0x100000000));
191 address_space_init(env
->address_space_er
, env
->system_er
, "ER");
193 cpu
->clock
= qdev_init_clock_in(DEVICE(obj
), "clk-in", NULL
, cpu
, 0);
194 clock_set_hz(cpu
->clock
, env
->config
->clock_freq_khz
* 1000);
198 XtensaCPU
*xtensa_cpu_create_with_clock(const char *cpu_type
, Clock
*cpu_refclk
)
202 cpu
= DEVICE(object_new(cpu_type
));
203 qdev_connect_clock_in(cpu
, "clk-in", cpu_refclk
);
204 qdev_realize(cpu
, NULL
, &error_abort
);
206 return XTENSA_CPU(cpu
);
209 #ifndef CONFIG_USER_ONLY
210 static const VMStateDescription vmstate_xtensa_cpu
= {
215 #include "hw/core/sysemu-cpu-ops.h"
217 static const struct SysemuCPUOps xtensa_sysemu_ops
= {
218 .get_phys_page_debug
= xtensa_cpu_get_phys_page_debug
,
222 #include "hw/core/tcg-cpu-ops.h"
224 static const struct TCGCPUOps xtensa_tcg_ops
= {
225 .initialize
= xtensa_translate_init
,
226 .debug_excp_handler
= xtensa_breakpoint_handler
,
227 .restore_state_to_opc
= xtensa_restore_state_to_opc
,
229 #ifndef CONFIG_USER_ONLY
230 .tlb_fill
= xtensa_cpu_tlb_fill
,
231 .cpu_exec_interrupt
= xtensa_cpu_exec_interrupt
,
232 .do_interrupt
= xtensa_cpu_do_interrupt
,
233 .do_transaction_failed
= xtensa_cpu_do_transaction_failed
,
234 .do_unaligned_access
= xtensa_cpu_do_unaligned_access
,
235 #endif /* !CONFIG_USER_ONLY */
238 static void xtensa_cpu_class_init(ObjectClass
*oc
, void *data
)
240 DeviceClass
*dc
= DEVICE_CLASS(oc
);
241 CPUClass
*cc
= CPU_CLASS(oc
);
242 XtensaCPUClass
*xcc
= XTENSA_CPU_CLASS(cc
);
244 device_class_set_parent_realize(dc
, xtensa_cpu_realizefn
,
245 &xcc
->parent_realize
);
247 device_class_set_parent_reset(dc
, xtensa_cpu_reset
, &xcc
->parent_reset
);
249 cc
->class_by_name
= xtensa_cpu_class_by_name
;
250 cc
->has_work
= xtensa_cpu_has_work
;
251 cc
->dump_state
= xtensa_cpu_dump_state
;
252 cc
->set_pc
= xtensa_cpu_set_pc
;
253 cc
->get_pc
= xtensa_cpu_get_pc
;
254 cc
->gdb_read_register
= xtensa_cpu_gdb_read_register
;
255 cc
->gdb_write_register
= xtensa_cpu_gdb_write_register
;
256 cc
->gdb_stop_before_watchpoint
= true;
257 #ifndef CONFIG_USER_ONLY
258 cc
->sysemu_ops
= &xtensa_sysemu_ops
;
259 dc
->vmsd
= &vmstate_xtensa_cpu
;
261 cc
->disas_set_info
= xtensa_cpu_disas_set_info
;
262 cc
->tcg_ops
= &xtensa_tcg_ops
;
265 static const TypeInfo xtensa_cpu_type_info
= {
266 .name
= TYPE_XTENSA_CPU
,
268 .instance_size
= sizeof(XtensaCPU
),
269 .instance_init
= xtensa_cpu_initfn
,
271 .class_size
= sizeof(XtensaCPUClass
),
272 .class_init
= xtensa_cpu_class_init
,
275 static void xtensa_cpu_register_types(void)
277 type_register_static(&xtensa_cpu_type_info
);
280 type_init(xtensa_cpu_register_types
)