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json-streamer: limit the maximum recursion depth and maximum token count
[qemu.git] / hw / qxl.c
blob2bb36c660ff5851105540b8fbc6047954271f355
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <pthread.h>
22
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
26 #include "monitor.h"
27 #include "sysemu.h"
28
29 #include "qxl.h"
30
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
38 abort(); \
39 } \
40 ret = &m_item->el; \
41 }
42
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 abort(); \
51 } \
52 ret = &m_item->el; \
53 }
54
55 #undef ALIGN
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
59
60 #define QXL_MODE(_x, _y, _b, _o) \
61 { .x_res = _x, \
62 .y_res = _y, \
63 .bits = _b, \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
67 .orientation = _o, \
68 }
69
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
73
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
79
80 static QXLMode qxl_modes[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
111 #endif
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
117 #endif
118 };
119
120 static PCIQXLDevice *qxl0;
121
122 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123 static void qxl_destroy_primary(PCIQXLDevice *d);
124 static void qxl_reset_memslots(PCIQXLDevice *d);
125 static void qxl_reset_surfaces(PCIQXLDevice *d);
126 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127
128 static inline uint32_t msb_mask(uint32_t val)
129 {
130 uint32_t mask;
131
132 do {
133 mask = ~(val - 1) & val;
134 val &= ~mask;
135 } while (mask < val);
136
137 return mask;
138 }
139
140 static ram_addr_t qxl_rom_size(void)
141 {
142 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
143 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
144 rom_size = msb_mask(rom_size * 2 - 1);
145 return rom_size;
146 }
147
148 static void init_qxl_rom(PCIQXLDevice *d)
149 {
150 QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
151 QXLModes *modes = (QXLModes *)(rom + 1);
152 uint32_t ram_header_size;
153 uint32_t surface0_area_size;
154 uint32_t num_pages;
155 uint32_t fb, maxfb = 0;
156 int i;
157
158 memset(rom, 0, d->rom_size);
159
160 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
161 rom->id = cpu_to_le32(d->id);
162 rom->log_level = cpu_to_le32(d->guestdebug);
163 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
164
165 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
166 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
167 rom->slots_start = 1;
168 rom->slots_end = NUM_MEMSLOTS - 1;
169 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
170
171 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
172 for (i = 0; i < modes->n_modes; i++) {
173 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
174 if (maxfb < fb) {
175 maxfb = fb;
176 }
177 modes->modes[i].id = cpu_to_le32(i);
178 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
179 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
180 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
181 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
182 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
183 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
184 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
185 }
186 if (maxfb < VGA_RAM_SIZE && d->id == 0)
187 maxfb = VGA_RAM_SIZE;
188
189 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
190 surface0_area_size = ALIGN(maxfb, 4096);
191 num_pages = d->vga.vram_size;
192 num_pages -= ram_header_size;
193 num_pages -= surface0_area_size;
194 num_pages = num_pages / TARGET_PAGE_SIZE;
195
196 rom->draw_area_offset = cpu_to_le32(0);
197 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
198 rom->pages_offset = cpu_to_le32(surface0_area_size);
199 rom->num_pages = cpu_to_le32(num_pages);
200 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
201
202 d->shadow_rom = *rom;
203 d->rom = rom;
204 d->modes = modes;
205 }
206
207 static void init_qxl_ram(PCIQXLDevice *d)
208 {
209 uint8_t *buf;
210 uint64_t *item;
211
212 buf = d->vga.vram_ptr;
213 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
214 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
215 d->ram->int_pending = cpu_to_le32(0);
216 d->ram->int_mask = cpu_to_le32(0);
217 SPICE_RING_INIT(&d->ram->cmd_ring);
218 SPICE_RING_INIT(&d->ram->cursor_ring);
219 SPICE_RING_INIT(&d->ram->release_ring);
220 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
221 *item = 0;
222 qxl_ring_set_dirty(d);
223 }
224
225 /* can be called from spice server thread context */
226 static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
227 {
228 while (addr < end) {
229 cpu_physical_memory_set_dirty(addr);
230 addr += TARGET_PAGE_SIZE;
231 }
232 }
233
234 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
235 {
236 ram_addr_t addr = qxl->rom_offset;
237 qxl_set_dirty(addr, addr + qxl->rom_size);
238 }
239
240 /* called from spice server thread context only */
241 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
242 {
243 ram_addr_t addr = qxl->vga.vram_offset;
244 void *base = qxl->vga.vram_ptr;
245 intptr_t offset;
246
247 offset = ptr - base;
248 offset &= ~(TARGET_PAGE_SIZE-1);
249 assert(offset < qxl->vga.vram_size);
250 qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
251 }
252
253 /* can be called from spice server thread context */
254 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
255 {
256 ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
257 ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size;
258 qxl_set_dirty(addr, end);
259 }
260
261 /*
262 * keep track of some command state, for savevm/loadvm.
263 * called from spice server thread context only
264 */
265 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
266 {
267 switch (le32_to_cpu(ext->cmd.type)) {
268 case QXL_CMD_SURFACE:
269 {
270 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
271 uint32_t id = le32_to_cpu(cmd->surface_id);
272 PANIC_ON(id >= NUM_SURFACES);
273 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
274 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
275 qxl->guest_surfaces.count++;
276 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
277 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
278 }
279 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
280 qxl->guest_surfaces.cmds[id] = 0;
281 qxl->guest_surfaces.count--;
282 }
283 break;
284 }
285 case QXL_CMD_CURSOR:
286 {
287 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
288 if (cmd->type == QXL_CURSOR_SET) {
289 qxl->guest_cursor = ext->cmd.data;
290 }
291 break;
292 }
293 }
294 }
295
296 /* spice display interface callbacks */
297
298 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
299 {
300 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
301
302 dprint(qxl, 1, "%s:\n", __FUNCTION__);
303 qxl->ssd.worker = qxl_worker;
304 }
305
306 static void interface_set_compression_level(QXLInstance *sin, int level)
307 {
308 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
309
310 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
311 qxl->shadow_rom.compression_level = cpu_to_le32(level);
312 qxl->rom->compression_level = cpu_to_le32(level);
313 qxl_rom_set_dirty(qxl);
314 }
315
316 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
317 {
318 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
319
320 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
321 qxl->rom->mm_clock = cpu_to_le32(mm_time);
322 qxl_rom_set_dirty(qxl);
323 }
324
325 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
326 {
327 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
328
329 dprint(qxl, 1, "%s:\n", __FUNCTION__);
330 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
331 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
332 info->num_memslots = NUM_MEMSLOTS;
333 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
334 info->internal_groupslot_id = 0;
335 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
336 info->n_surfaces = NUM_SURFACES;
337 }
338
339 /* called from spice server thread context only */
340 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
341 {
342 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
343 SimpleSpiceUpdate *update;
344 QXLCommandRing *ring;
345 QXLCommand *cmd;
346 int notify, ret;
347
348 switch (qxl->mode) {
349 case QXL_MODE_VGA:
350 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
351 ret = false;
352 qemu_mutex_lock(&qxl->ssd.lock);
353 if (qxl->ssd.update != NULL) {
354 update = qxl->ssd.update;
355 qxl->ssd.update = NULL;
356 *ext = update->ext;
357 ret = true;
358 }
359 qemu_mutex_unlock(&qxl->ssd.lock);
360 qxl_log_command(qxl, "vga", ext);
361 return ret;
362 case QXL_MODE_COMPAT:
363 case QXL_MODE_NATIVE:
364 case QXL_MODE_UNDEFINED:
365 dprint(qxl, 2, "%s: %s\n", __FUNCTION__,
366 qxl->cmdflags ? "compat" : "native");
367 ring = &qxl->ram->cmd_ring;
368 if (SPICE_RING_IS_EMPTY(ring)) {
369 return false;
370 }
371 SPICE_RING_CONS_ITEM(ring, cmd);
372 ext->cmd = *cmd;
373 ext->group_id = MEMSLOT_GROUP_GUEST;
374 ext->flags = qxl->cmdflags;
375 SPICE_RING_POP(ring, notify);
376 qxl_ring_set_dirty(qxl);
377 if (notify) {
378 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
379 }
380 qxl->guest_primary.commands++;
381 qxl_track_command(qxl, ext);
382 qxl_log_command(qxl, "cmd", ext);
383 return true;
384 default:
385 return false;
386 }
387 }
388
389 /* called from spice server thread context only */
390 static int interface_req_cmd_notification(QXLInstance *sin)
391 {
392 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
393 int wait = 1;
394
395 switch (qxl->mode) {
396 case QXL_MODE_COMPAT:
397 case QXL_MODE_NATIVE:
398 case QXL_MODE_UNDEFINED:
399 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
400 qxl_ring_set_dirty(qxl);
401 break;
402 default:
403 /* nothing */
404 break;
405 }
406 return wait;
407 }
408
409 /* called from spice server thread context only */
410 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
411 {
412 QXLReleaseRing *ring = &d->ram->release_ring;
413 uint64_t *item;
414 int notify;
415
416 #define QXL_FREE_BUNCH_SIZE 32
417
418 if (ring->prod - ring->cons + 1 == ring->num_items) {
419 /* ring full -- can't push */
420 return;
421 }
422 if (!flush && d->oom_running) {
423 /* collect everything from oom handler before pushing */
424 return;
425 }
426 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
427 /* collect a bit more before pushing */
428 return;
429 }
430
431 SPICE_RING_PUSH(ring, notify);
432 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
433 d->num_free_res, notify ? "yes" : "no",
434 ring->prod - ring->cons, ring->num_items,
435 ring->prod, ring->cons);
436 if (notify) {
437 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
438 }
439 SPICE_RING_PROD_ITEM(ring, item);
440 *item = 0;
441 d->num_free_res = 0;
442 d->last_release = NULL;
443 qxl_ring_set_dirty(d);
444 }
445
446 /* called from spice server thread context only */
447 static void interface_release_resource(QXLInstance *sin,
448 struct QXLReleaseInfoExt ext)
449 {
450 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
451 QXLReleaseRing *ring;
452 uint64_t *item, id;
453
454 if (ext.group_id == MEMSLOT_GROUP_HOST) {
455 /* host group -> vga mode update request */
456 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
457 return;
458 }
459
460 /*
461 * ext->info points into guest-visible memory
462 * pci bar 0, $command.release_info
463 */
464 ring = &qxl->ram->release_ring;
465 SPICE_RING_PROD_ITEM(ring, item);
466 if (*item == 0) {
467 /* stick head into the ring */
468 id = ext.info->id;
469 ext.info->next = 0;
470 qxl_ram_set_dirty(qxl, &ext.info->next);
471 *item = id;
472 qxl_ring_set_dirty(qxl);
473 } else {
474 /* append item to the list */
475 qxl->last_release->next = ext.info->id;
476 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
477 ext.info->next = 0;
478 qxl_ram_set_dirty(qxl, &ext.info->next);
479 }
480 qxl->last_release = ext.info;
481 qxl->num_free_res++;
482 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
483 qxl_push_free_res(qxl, 0);
484 }
485
486 /* called from spice server thread context only */
487 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
488 {
489 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
490 QXLCursorRing *ring;
491 QXLCommand *cmd;
492 int notify;
493
494 switch (qxl->mode) {
495 case QXL_MODE_COMPAT:
496 case QXL_MODE_NATIVE:
497 case QXL_MODE_UNDEFINED:
498 ring = &qxl->ram->cursor_ring;
499 if (SPICE_RING_IS_EMPTY(ring)) {
500 return false;
501 }
502 SPICE_RING_CONS_ITEM(ring, cmd);
503 ext->cmd = *cmd;
504 ext->group_id = MEMSLOT_GROUP_GUEST;
505 ext->flags = qxl->cmdflags;
506 SPICE_RING_POP(ring, notify);
507 qxl_ring_set_dirty(qxl);
508 if (notify) {
509 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
510 }
511 qxl->guest_primary.commands++;
512 qxl_track_command(qxl, ext);
513 qxl_log_command(qxl, "csr", ext);
514 if (qxl->id == 0) {
515 qxl_render_cursor(qxl, ext);
516 }
517 return true;
518 default:
519 return false;
520 }
521 }
522
523 /* called from spice server thread context only */
524 static int interface_req_cursor_notification(QXLInstance *sin)
525 {
526 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
527 int wait = 1;
528
529 switch (qxl->mode) {
530 case QXL_MODE_COMPAT:
531 case QXL_MODE_NATIVE:
532 case QXL_MODE_UNDEFINED:
533 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
534 qxl_ring_set_dirty(qxl);
535 break;
536 default:
537 /* nothing */
538 break;
539 }
540 return wait;
541 }
542
543 /* called from spice server thread context */
544 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
545 {
546 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
547 abort();
548 }
549
550 /* called from spice server thread context only */
551 static int interface_flush_resources(QXLInstance *sin)
552 {
553 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
554 int ret;
555
556 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
557 ret = qxl->num_free_res;
558 if (ret) {
559 qxl_push_free_res(qxl, 1);
560 }
561 return ret;
562 }
563
564 static const QXLInterface qxl_interface = {
565 .base.type = SPICE_INTERFACE_QXL,
566 .base.description = "qxl gpu",
567 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
568 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
569
570 .attache_worker = interface_attach_worker,
571 .set_compression_level = interface_set_compression_level,
572 .set_mm_time = interface_set_mm_time,
573 .get_init_info = interface_get_init_info,
574
575 /* the callbacks below are called from spice server thread context */
576 .get_command = interface_get_command,
577 .req_cmd_notification = interface_req_cmd_notification,
578 .release_resource = interface_release_resource,
579 .get_cursor_command = interface_get_cursor_command,
580 .req_cursor_notification = interface_req_cursor_notification,
581 .notify_update = interface_notify_update,
582 .flush_resources = interface_flush_resources,
583 };
584
585 static void qxl_enter_vga_mode(PCIQXLDevice *d)
586 {
587 if (d->mode == QXL_MODE_VGA) {
588 return;
589 }
590 dprint(d, 1, "%s\n", __FUNCTION__);
591 qemu_spice_create_host_primary(&d->ssd);
592 d->mode = QXL_MODE_VGA;
593 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
594 }
595
596 static void qxl_exit_vga_mode(PCIQXLDevice *d)
597 {
598 if (d->mode != QXL_MODE_VGA) {
599 return;
600 }
601 dprint(d, 1, "%s\n", __FUNCTION__);
602 qxl_destroy_primary(d);
603 }
604
605 static void qxl_set_irq(PCIQXLDevice *d)
606 {
607 uint32_t pending = le32_to_cpu(d->ram->int_pending);
608 uint32_t mask = le32_to_cpu(d->ram->int_mask);
609 int level = !!(pending & mask);
610 qemu_set_irq(d->pci.irq[0], level);
611 qxl_ring_set_dirty(d);
612 }
613
614 static void qxl_write_config(PCIDevice *d, uint32_t address,
615 uint32_t val, int len)
616 {
617 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
618 VGACommonState *vga = &qxl->vga;
619
620 vga_dirty_log_stop(vga);
621 pci_default_write_config(d, address, val, len);
622 if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
623 vga->map_addr = 0;
624 }
625 vga_dirty_log_start(vga);
626 }
627
628 static void qxl_check_state(PCIQXLDevice *d)
629 {
630 QXLRam *ram = d->ram;
631
632 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
633 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
634 }
635
636 static void qxl_reset_state(PCIQXLDevice *d)
637 {
638 QXLRam *ram = d->ram;
639 QXLRom *rom = d->rom;
640
641 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
642 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
643 d->shadow_rom.update_id = cpu_to_le32(0);
644 *rom = d->shadow_rom;
645 qxl_rom_set_dirty(d);
646 init_qxl_ram(d);
647 d->num_free_res = 0;
648 d->last_release = NULL;
649 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
650 }
651
652 static void qxl_soft_reset(PCIQXLDevice *d)
653 {
654 dprint(d, 1, "%s:\n", __FUNCTION__);
655 qxl_check_state(d);
656
657 if (d->id == 0) {
658 qxl_enter_vga_mode(d);
659 } else {
660 d->mode = QXL_MODE_UNDEFINED;
661 }
662 }
663
664 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
665 {
666 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
667 loadvm ? " (loadvm)" : "");
668
669 d->ssd.worker->reset_cursor(d->ssd.worker);
670 d->ssd.worker->reset_image_cache(d->ssd.worker);
671 qxl_reset_surfaces(d);
672 qxl_reset_memslots(d);
673
674 /* pre loadvm reset must not touch QXLRam. This lives in
675 * device memory, is migrated together with RAM and thus
676 * already loaded at this point */
677 if (!loadvm) {
678 qxl_reset_state(d);
679 }
680 qemu_spice_create_host_memslot(&d->ssd);
681 qxl_soft_reset(d);
682
683 dprint(d, 1, "%s: done\n", __FUNCTION__);
684 }
685
686 static void qxl_reset_handler(DeviceState *dev)
687 {
688 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
689 qxl_hard_reset(d, 0);
690 }
691
692 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
693 {
694 VGACommonState *vga = opaque;
695 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
696
697 if (qxl->mode != QXL_MODE_VGA) {
698 dprint(qxl, 1, "%s\n", __FUNCTION__);
699 qxl_destroy_primary(qxl);
700 qxl_soft_reset(qxl);
701 }
702 vga_ioport_write(opaque, addr, val);
703 }
704
705 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta)
706 {
707 static const int regions[] = {
708 QXL_RAM_RANGE_INDEX,
709 QXL_VRAM_RANGE_INDEX,
710 };
711 uint64_t guest_start;
712 uint64_t guest_end;
713 int pci_region;
714 pcibus_t pci_start;
715 pcibus_t pci_end;
716 intptr_t virt_start;
717 QXLDevMemSlot memslot;
718 int i;
719
720 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
721 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
722
723 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
724 __FUNCTION__, slot_id,
725 guest_start, guest_end);
726
727 PANIC_ON(slot_id >= NUM_MEMSLOTS);
728 PANIC_ON(guest_start > guest_end);
729
730 for (i = 0; i < ARRAY_SIZE(regions); i++) {
731 pci_region = regions[i];
732 pci_start = d->pci.io_regions[pci_region].addr;
733 pci_end = pci_start + d->pci.io_regions[pci_region].size;
734 /* mapped? */
735 if (pci_start == -1) {
736 continue;
737 }
738 /* start address in range ? */
739 if (guest_start < pci_start || guest_start > pci_end) {
740 continue;
741 }
742 /* end address in range ? */
743 if (guest_end > pci_end) {
744 continue;
745 }
746 /* passed */
747 break;
748 }
749 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
750
751 switch (pci_region) {
752 case QXL_RAM_RANGE_INDEX:
753 virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
754 break;
755 case QXL_VRAM_RANGE_INDEX:
756 virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
757 break;
758 default:
759 /* should not happen */
760 abort();
761 }
762
763 memslot.slot_id = slot_id;
764 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
765 memslot.virt_start = virt_start + (guest_start - pci_start);
766 memslot.virt_end = virt_start + (guest_end - pci_start);
767 memslot.addr_delta = memslot.virt_start - delta;
768 memslot.generation = d->rom->slot_generation = 0;
769 qxl_rom_set_dirty(d);
770
771 dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
772 __FUNCTION__, memslot.slot_id,
773 memslot.virt_start, memslot.virt_end);
774
775 d->ssd.worker->add_memslot(d->ssd.worker, &memslot);
776 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
777 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
778 d->guest_slots[slot_id].delta = delta;
779 d->guest_slots[slot_id].active = 1;
780 }
781
782 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
783 {
784 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
785 d->ssd.worker->del_memslot(d->ssd.worker, MEMSLOT_GROUP_HOST, slot_id);
786 d->guest_slots[slot_id].active = 0;
787 }
788
789 static void qxl_reset_memslots(PCIQXLDevice *d)
790 {
791 dprint(d, 1, "%s:\n", __FUNCTION__);
792 d->ssd.worker->reset_memslots(d->ssd.worker);
793 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
794 }
795
796 static void qxl_reset_surfaces(PCIQXLDevice *d)
797 {
798 dprint(d, 1, "%s:\n", __FUNCTION__);
799 d->mode = QXL_MODE_UNDEFINED;
800 d->ssd.worker->destroy_surfaces(d->ssd.worker);
801 memset(&d->guest_surfaces.cmds, 0, sizeof(d->guest_surfaces.cmds));
802 }
803
804 /* called from spice server thread context only */
805 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
806 {
807 uint64_t phys = le64_to_cpu(pqxl);
808 uint32_t slot = (phys >> (64 - 8)) & 0xff;
809 uint64_t offset = phys & 0xffffffffffff;
810
811 switch (group_id) {
812 case MEMSLOT_GROUP_HOST:
813 return (void*)offset;
814 case MEMSLOT_GROUP_GUEST:
815 PANIC_ON(slot > NUM_MEMSLOTS);
816 PANIC_ON(!qxl->guest_slots[slot].active);
817 PANIC_ON(offset < qxl->guest_slots[slot].delta);
818 offset -= qxl->guest_slots[slot].delta;
819 PANIC_ON(offset > qxl->guest_slots[slot].size)
820 return qxl->guest_slots[slot].ptr + offset;
821 default:
822 PANIC_ON(1);
823 }
824 }
825
826 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm)
827 {
828 QXLDevSurfaceCreate surface;
829 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
830
831 assert(qxl->mode != QXL_MODE_NATIVE);
832 qxl_exit_vga_mode(qxl);
833
834 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
835 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
836
837 surface.format = le32_to_cpu(sc->format);
838 surface.height = le32_to_cpu(sc->height);
839 surface.mem = le64_to_cpu(sc->mem);
840 surface.position = le32_to_cpu(sc->position);
841 surface.stride = le32_to_cpu(sc->stride);
842 surface.width = le32_to_cpu(sc->width);
843 surface.type = le32_to_cpu(sc->type);
844 surface.flags = le32_to_cpu(sc->flags);
845
846 surface.mouse_mode = true;
847 surface.group_id = MEMSLOT_GROUP_GUEST;
848 if (loadvm) {
849 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
850 }
851
852 qxl->mode = QXL_MODE_NATIVE;
853 qxl->cmdflags = 0;
854 qxl->ssd.worker->create_primary_surface(qxl->ssd.worker, 0, &surface);
855
856 /* for local rendering */
857 qxl_render_resize(qxl);
858 }
859
860 static void qxl_destroy_primary(PCIQXLDevice *d)
861 {
862 if (d->mode == QXL_MODE_UNDEFINED) {
863 return;
864 }
865
866 dprint(d, 1, "%s\n", __FUNCTION__);
867
868 d->mode = QXL_MODE_UNDEFINED;
869 d->ssd.worker->destroy_primary_surface(d->ssd.worker, 0);
870 }
871
872 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
873 {
874 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
875 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
876 QXLMode *mode = d->modes->modes + modenr;
877 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
878 QXLMemSlot slot = {
879 .mem_start = start,
880 .mem_end = end
881 };
882 QXLSurfaceCreate surface = {
883 .width = mode->x_res,
884 .height = mode->y_res,
885 .stride = -mode->x_res * 4,
886 .format = SPICE_SURFACE_FMT_32_xRGB,
887 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
888 .mouse_mode = true,
889 .mem = devmem + d->shadow_rom.draw_area_offset,
890 };
891
892 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
893 modenr, mode->x_res, mode->y_res, mode->bits, devmem);
894 if (!loadvm) {
895 qxl_hard_reset(d, 0);
896 }
897
898 d->guest_slots[0].slot = slot;
899 qxl_add_memslot(d, 0, devmem);
900
901 d->guest_primary.surface = surface;
902 qxl_create_guest_primary(d, 0);
903
904 d->mode = QXL_MODE_COMPAT;
905 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
906 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
907 if (mode->bits == 16) {
908 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
909 }
910 #endif
911 d->shadow_rom.mode = cpu_to_le32(modenr);
912 d->rom->mode = cpu_to_le32(modenr);
913 qxl_rom_set_dirty(d);
914 }
915
916 static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
917 {
918 PCIQXLDevice *d = opaque;
919 uint32_t io_port = addr - d->io_base;
920
921 switch (io_port) {
922 case QXL_IO_RESET:
923 case QXL_IO_SET_MODE:
924 case QXL_IO_MEMSLOT_ADD:
925 case QXL_IO_MEMSLOT_DEL:
926 case QXL_IO_CREATE_PRIMARY:
927 break;
928 default:
929 if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT)
930 break;
931 dprint(d, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__, io_port);
932 return;
933 }
934
935 switch (io_port) {
936 case QXL_IO_UPDATE_AREA:
937 {
938 QXLRect update = d->ram->update_area;
939 d->ssd.worker->update_area(d->ssd.worker, d->ram->update_surface,
940 &update, NULL, 0, 0);
941 break;
942 }
943 case QXL_IO_NOTIFY_CMD:
944 d->ssd.worker->wakeup(d->ssd.worker);
945 break;
946 case QXL_IO_NOTIFY_CURSOR:
947 d->ssd.worker->wakeup(d->ssd.worker);
948 break;
949 case QXL_IO_UPDATE_IRQ:
950 qxl_set_irq(d);
951 break;
952 case QXL_IO_NOTIFY_OOM:
953 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
954 break;
955 }
956 pthread_yield();
957 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
958 break;
959 }
960 d->oom_running = 1;
961 d->ssd.worker->oom(d->ssd.worker);
962 d->oom_running = 0;
963 break;
964 case QXL_IO_SET_MODE:
965 dprint(d, 1, "QXL_SET_MODE %d\n", val);
966 qxl_set_mode(d, val, 0);
967 break;
968 case QXL_IO_LOG:
969 if (d->guestdebug) {
970 fprintf(stderr, "qxl/guest: %s", d->ram->log_buf);
971 }
972 break;
973 case QXL_IO_RESET:
974 dprint(d, 1, "QXL_IO_RESET\n");
975 qxl_hard_reset(d, 0);
976 break;
977 case QXL_IO_MEMSLOT_ADD:
978 PANIC_ON(val >= NUM_MEMSLOTS);
979 PANIC_ON(d->guest_slots[val].active);
980 d->guest_slots[val].slot = d->ram->mem_slot;
981 qxl_add_memslot(d, val, 0);
982 break;
983 case QXL_IO_MEMSLOT_DEL:
984 qxl_del_memslot(d, val);
985 break;
986 case QXL_IO_CREATE_PRIMARY:
987 PANIC_ON(val != 0);
988 dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n");
989 d->guest_primary.surface = d->ram->create_surface;
990 qxl_create_guest_primary(d, 0);
991 break;
992 case QXL_IO_DESTROY_PRIMARY:
993 PANIC_ON(val != 0);
994 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY\n");
995 qxl_destroy_primary(d);
996 break;
997 case QXL_IO_DESTROY_SURFACE_WAIT:
998 d->ssd.worker->destroy_surface_wait(d->ssd.worker, val);
999 break;
1000 case QXL_IO_DESTROY_ALL_SURFACES:
1001 d->ssd.worker->destroy_surfaces(d->ssd.worker);
1002 break;
1003 default:
1004 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1005 abort();
1006 }
1007 }
1008
1009 static uint32_t ioport_read(void *opaque, uint32_t addr)
1010 {
1011 PCIQXLDevice *d = opaque;
1012
1013 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1014 return 0xff;
1015 }
1016
1017 static void qxl_map(PCIDevice *pci, int region_num,
1018 pcibus_t addr, pcibus_t size, int type)
1019 {
1020 static const char *names[] = {
1021 [ QXL_IO_RANGE_INDEX ] = "ioports",
1022 [ QXL_RAM_RANGE_INDEX ] = "devram",
1023 [ QXL_ROM_RANGE_INDEX ] = "rom",
1024 [ QXL_VRAM_RANGE_INDEX ] = "vram",
1025 };
1026 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
1027
1028 dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
1029 region_num, names[region_num], addr, size);
1030
1031 switch (region_num) {
1032 case QXL_IO_RANGE_INDEX:
1033 register_ioport_write(addr, size, 1, ioport_write, pci);
1034 register_ioport_read(addr, size, 1, ioport_read, pci);
1035 qxl->io_base = addr;
1036 break;
1037 case QXL_RAM_RANGE_INDEX:
1038 cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
1039 qxl->vga.map_addr = addr;
1040 qxl->vga.map_end = addr + size;
1041 if (qxl->id == 0) {
1042 vga_dirty_log_start(&qxl->vga);
1043 }
1044 break;
1045 case QXL_ROM_RANGE_INDEX:
1046 cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
1047 break;
1048 case QXL_VRAM_RANGE_INDEX:
1049 cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
1050 break;
1051 }
1052 }
1053
1054 static void pipe_read(void *opaque)
1055 {
1056 PCIQXLDevice *d = opaque;
1057 char dummy;
1058 int len;
1059
1060 do {
1061 len = read(d->pipe[0], &dummy, sizeof(dummy));
1062 } while (len == sizeof(dummy));
1063 qxl_set_irq(d);
1064 }
1065
1066 /* called from spice server thread context only */
1067 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1068 {
1069 uint32_t old_pending;
1070 uint32_t le_events = cpu_to_le32(events);
1071
1072 assert(d->ssd.running);
1073 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1074 if ((old_pending & le_events) == le_events) {
1075 return;
1076 }
1077 if (pthread_self() == d->main) {
1078 qxl_set_irq(d);
1079 } else {
1080 if (write(d->pipe[1], d, 1) != 1) {
1081 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1082 }
1083 }
1084 }
1085
1086 static void init_pipe_signaling(PCIQXLDevice *d)
1087 {
1088 if (pipe(d->pipe) < 0) {
1089 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1090 return;
1091 }
1092 #ifdef CONFIG_IOTHREAD
1093 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1094 #else
1095 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1096 #endif
1097 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1098 fcntl(d->pipe[0], F_SETOWN, getpid());
1099
1100 d->main = pthread_self();
1101 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1102 }
1103
1104 /* graphics console */
1105
1106 static void qxl_hw_update(void *opaque)
1107 {
1108 PCIQXLDevice *qxl = opaque;
1109 VGACommonState *vga = &qxl->vga;
1110
1111 switch (qxl->mode) {
1112 case QXL_MODE_VGA:
1113 vga->update(vga);
1114 break;
1115 case QXL_MODE_COMPAT:
1116 case QXL_MODE_NATIVE:
1117 qxl_render_update(qxl);
1118 break;
1119 default:
1120 break;
1121 }
1122 }
1123
1124 static void qxl_hw_invalidate(void *opaque)
1125 {
1126 PCIQXLDevice *qxl = opaque;
1127 VGACommonState *vga = &qxl->vga;
1128
1129 vga->invalidate(vga);
1130 }
1131
1132 static void qxl_hw_screen_dump(void *opaque, const char *filename)
1133 {
1134 PCIQXLDevice *qxl = opaque;
1135 VGACommonState *vga = &qxl->vga;
1136
1137 switch (qxl->mode) {
1138 case QXL_MODE_COMPAT:
1139 case QXL_MODE_NATIVE:
1140 qxl_render_update(qxl);
1141 ppm_save(filename, qxl->ssd.ds->surface);
1142 break;
1143 case QXL_MODE_VGA:
1144 vga->screen_dump(vga, filename);
1145 break;
1146 default:
1147 break;
1148 }
1149 }
1150
1151 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1152 {
1153 PCIQXLDevice *qxl = opaque;
1154 VGACommonState *vga = &qxl->vga;
1155
1156 if (qxl->mode == QXL_MODE_VGA) {
1157 vga->text_update(vga, chardata);
1158 return;
1159 }
1160 }
1161
1162 static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1163 {
1164 PCIQXLDevice *qxl = opaque;
1165 qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1166
1167 if (!running && qxl->mode == QXL_MODE_NATIVE) {
1168 /* dirty all vram (which holds surfaces) to make sure it is saved */
1169 /* FIXME #1: should go out during "live" stage */
1170 /* FIXME #2: we only need to save the areas which are actually used */
1171 ram_addr_t addr = qxl->vram_offset;
1172 qxl_set_dirty(addr, addr + qxl->vram_size);
1173 }
1174 }
1175
1176 /* display change listener */
1177
1178 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1179 {
1180 if (qxl0->mode == QXL_MODE_VGA) {
1181 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1182 }
1183 }
1184
1185 static void display_resize(struct DisplayState *ds)
1186 {
1187 if (qxl0->mode == QXL_MODE_VGA) {
1188 qemu_spice_display_resize(&qxl0->ssd);
1189 }
1190 }
1191
1192 static void display_refresh(struct DisplayState *ds)
1193 {
1194 if (qxl0->mode == QXL_MODE_VGA) {
1195 qemu_spice_display_refresh(&qxl0->ssd);
1196 }
1197 }
1198
1199 static DisplayChangeListener display_listener = {
1200 .dpy_update = display_update,
1201 .dpy_resize = display_resize,
1202 .dpy_refresh = display_refresh,
1203 };
1204
1205 static int qxl_init_common(PCIQXLDevice *qxl)
1206 {
1207 uint8_t* config = qxl->pci.config;
1208 uint32_t pci_device_id;
1209 uint32_t pci_device_rev;
1210 uint32_t io_size;
1211
1212 qxl->mode = QXL_MODE_UNDEFINED;
1213 qxl->generation = 1;
1214 qxl->num_memslots = NUM_MEMSLOTS;
1215 qxl->num_surfaces = NUM_SURFACES;
1216
1217 switch (qxl->revision) {
1218 case 1: /* spice 0.4 -- qxl-1 */
1219 pci_device_id = QXL_DEVICE_ID_STABLE;
1220 pci_device_rev = QXL_REVISION_STABLE_V04;
1221 break;
1222 case 2: /* spice 0.6 -- qxl-2 */
1223 pci_device_id = QXL_DEVICE_ID_STABLE;
1224 pci_device_rev = QXL_REVISION_STABLE_V06;
1225 break;
1226 default: /* experimental */
1227 pci_device_id = QXL_DEVICE_ID_DEVEL;
1228 pci_device_rev = 1;
1229 break;
1230 }
1231
1232 pci_config_set_vendor_id(config, REDHAT_PCI_VENDOR_ID);
1233 pci_config_set_device_id(config, pci_device_id);
1234 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1235 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1236
1237 qxl->rom_size = qxl_rom_size();
1238 qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
1239 init_qxl_rom(qxl);
1240 init_qxl_ram(qxl);
1241
1242 if (qxl->vram_size < 16 * 1024 * 1024) {
1243 qxl->vram_size = 16 * 1024 * 1024;
1244 }
1245 if (qxl->revision == 1) {
1246 qxl->vram_size = 4096;
1247 }
1248 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1249 qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
1250
1251 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1252 if (qxl->revision == 1) {
1253 io_size = 8;
1254 }
1255
1256 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1257 io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
1258
1259 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1260 qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1261 qxl_map);
1262
1263 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1264 qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1265 qxl_map);
1266
1267 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
1268 PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
1269
1270 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1271 qxl->ssd.qxl.id = qxl->id;
1272 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1273 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1274
1275 init_pipe_signaling(qxl);
1276 qxl_reset_state(qxl);
1277
1278 return 0;
1279 }
1280
1281 static int qxl_init_primary(PCIDevice *dev)
1282 {
1283 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1284 VGACommonState *vga = &qxl->vga;
1285 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1286
1287 qxl->id = 0;
1288
1289 if (ram_size < 32 * 1024 * 1024) {
1290 ram_size = 32 * 1024 * 1024;
1291 }
1292 vga_common_init(vga, ram_size);
1293 vga_init(vga);
1294 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1295 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
1296 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
1297 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga);
1298 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga);
1299
1300 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1301 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1302 qxl->ssd.ds = vga->ds;
1303 qemu_mutex_init(&qxl->ssd.lock);
1304 qxl->ssd.mouse_x = -1;
1305 qxl->ssd.mouse_y = -1;
1306 qxl->ssd.bufsize = (16 * 1024 * 1024);
1307 qxl->ssd.buf = qemu_malloc(qxl->ssd.bufsize);
1308
1309 qxl0 = qxl;
1310 register_displaychangelistener(vga->ds, &display_listener);
1311
1312 pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_VGA);
1313 return qxl_init_common(qxl);
1314 }
1315
1316 static int qxl_init_secondary(PCIDevice *dev)
1317 {
1318 static int device_id = 1;
1319 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1320 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1321
1322 qxl->id = device_id++;
1323
1324 if (ram_size < 16 * 1024 * 1024) {
1325 ram_size = 16 * 1024 * 1024;
1326 }
1327 qxl->vga.vram_size = ram_size;
1328 qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
1329 qxl->vga.vram_size);
1330 qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
1331
1332 pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_OTHER);
1333 return qxl_init_common(qxl);
1334 }
1335
1336 static void qxl_pre_save(void *opaque)
1337 {
1338 PCIQXLDevice* d = opaque;
1339 uint8_t *ram_start = d->vga.vram_ptr;
1340
1341 dprint(d, 1, "%s:\n", __FUNCTION__);
1342 if (d->last_release == NULL) {
1343 d->last_release_offset = 0;
1344 } else {
1345 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1346 }
1347 assert(d->last_release_offset < d->vga.vram_size);
1348 }
1349
1350 static int qxl_pre_load(void *opaque)
1351 {
1352 PCIQXLDevice* d = opaque;
1353
1354 dprint(d, 1, "%s: start\n", __FUNCTION__);
1355 qxl_hard_reset(d, 1);
1356 qxl_exit_vga_mode(d);
1357 dprint(d, 1, "%s: done\n", __FUNCTION__);
1358 return 0;
1359 }
1360
1361 static int qxl_post_load(void *opaque, int version)
1362 {
1363 PCIQXLDevice* d = opaque;
1364 uint8_t *ram_start = d->vga.vram_ptr;
1365 QXLCommandExt *cmds;
1366 int in, out, i, newmode;
1367
1368 dprint(d, 1, "%s: start\n", __FUNCTION__);
1369
1370 assert(d->last_release_offset < d->vga.vram_size);
1371 if (d->last_release_offset == 0) {
1372 d->last_release = NULL;
1373 } else {
1374 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1375 }
1376
1377 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1378
1379 dprint(d, 1, "%s: restore mode\n", __FUNCTION__);
1380 newmode = d->mode;
1381 d->mode = QXL_MODE_UNDEFINED;
1382 switch (newmode) {
1383 case QXL_MODE_UNDEFINED:
1384 break;
1385 case QXL_MODE_VGA:
1386 qxl_enter_vga_mode(d);
1387 break;
1388 case QXL_MODE_NATIVE:
1389 for (i = 0; i < NUM_MEMSLOTS; i++) {
1390 if (!d->guest_slots[i].active) {
1391 continue;
1392 }
1393 qxl_add_memslot(d, i, 0);
1394 }
1395 qxl_create_guest_primary(d, 1);
1396
1397 /* replay surface-create and cursor-set commands */
1398 cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1399 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1400 if (d->guest_surfaces.cmds[in] == 0) {
1401 continue;
1402 }
1403 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1404 cmds[out].cmd.type = QXL_CMD_SURFACE;
1405 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1406 out++;
1407 }
1408 cmds[out].cmd.data = d->guest_cursor;
1409 cmds[out].cmd.type = QXL_CMD_CURSOR;
1410 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1411 out++;
1412 d->ssd.worker->loadvm_commands(d->ssd.worker, cmds, out);
1413 qemu_free(cmds);
1414
1415 break;
1416 case QXL_MODE_COMPAT:
1417 qxl_set_mode(d, d->shadow_rom.mode, 1);
1418 break;
1419 }
1420 dprint(d, 1, "%s: done\n", __FUNCTION__);
1421
1422 return 0;
1423 }
1424
1425 #define QXL_SAVE_VERSION 21
1426
1427 static VMStateDescription qxl_memslot = {
1428 .name = "qxl-memslot",
1429 .version_id = QXL_SAVE_VERSION,
1430 .minimum_version_id = QXL_SAVE_VERSION,
1431 .fields = (VMStateField[]) {
1432 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1433 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1434 VMSTATE_UINT32(active, struct guest_slots),
1435 VMSTATE_END_OF_LIST()
1436 }
1437 };
1438
1439 static VMStateDescription qxl_surface = {
1440 .name = "qxl-surface",
1441 .version_id = QXL_SAVE_VERSION,
1442 .minimum_version_id = QXL_SAVE_VERSION,
1443 .fields = (VMStateField[]) {
1444 VMSTATE_UINT32(width, QXLSurfaceCreate),
1445 VMSTATE_UINT32(height, QXLSurfaceCreate),
1446 VMSTATE_INT32(stride, QXLSurfaceCreate),
1447 VMSTATE_UINT32(format, QXLSurfaceCreate),
1448 VMSTATE_UINT32(position, QXLSurfaceCreate),
1449 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1450 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1451 VMSTATE_UINT32(type, QXLSurfaceCreate),
1452 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1453 VMSTATE_END_OF_LIST()
1454 }
1455 };
1456
1457 static VMStateDescription qxl_vmstate = {
1458 .name = "qxl",
1459 .version_id = QXL_SAVE_VERSION,
1460 .minimum_version_id = QXL_SAVE_VERSION,
1461 .pre_save = qxl_pre_save,
1462 .pre_load = qxl_pre_load,
1463 .post_load = qxl_post_load,
1464 .fields = (VMStateField []) {
1465 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1466 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1467 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1468 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1469 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1470 VMSTATE_UINT32(mode, PCIQXLDevice),
1471 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1472 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1473 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1474 qxl_memslot, struct guest_slots),
1475 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1476 qxl_surface, QXLSurfaceCreate),
1477 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1478 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1479 vmstate_info_uint64, uint64_t),
1480 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1481 VMSTATE_END_OF_LIST()
1482 },
1483 };
1484
1485 static PCIDeviceInfo qxl_info_primary = {
1486 .qdev.name = "qxl-vga",
1487 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1488 .qdev.size = sizeof(PCIQXLDevice),
1489 .qdev.reset = qxl_reset_handler,
1490 .qdev.vmsd = &qxl_vmstate,
1491 .no_hotplug = 1,
1492 .init = qxl_init_primary,
1493 .config_write = qxl_write_config,
1494 .romfile = "vgabios-qxl.bin",
1495 .qdev.props = (Property[]) {
1496 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1497 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1498 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1499 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1500 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1501 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1502 DEFINE_PROP_END_OF_LIST(),
1503 }
1504 };
1505
1506 static PCIDeviceInfo qxl_info_secondary = {
1507 .qdev.name = "qxl",
1508 .qdev.desc = "Spice QXL GPU (secondary)",
1509 .qdev.size = sizeof(PCIQXLDevice),
1510 .qdev.reset = qxl_reset_handler,
1511 .qdev.vmsd = &qxl_vmstate,
1512 .init = qxl_init_secondary,
1513 .qdev.props = (Property[]) {
1514 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1515 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1516 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1517 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1518 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1519 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1520 DEFINE_PROP_END_OF_LIST(),
1521 }
1522 };
1523
1524 static void qxl_register(void)
1525 {
1526 pci_qdev_register(&qxl_info_primary);
1527 pci_qdev_register(&qxl_info_secondary);
1528 }
1529
1530 device_init(qxl_register);
QEmu