hw/pci-host/apb.c

   1 /*
   2  * QEMU Ultrasparc APB PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2012,2013 Artyom Tarasenko
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 /* XXX This file and most of its contents are somewhat misnamed.  The
  27    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
  28    the secondary PCI bridge.  */
  29
  30 #include "hw/sysbus.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/pci/pci_host.h"
  33 #include "hw/pci/pci_bridge.h"
  34 #include "hw/pci/pci_bus.h"
  35 #include "hw/pci-host/apb.h"
  36 #include "sysemu/sysemu.h"
  37 #include "exec/address-spaces.h"
  38
  39 /* debug APB */
  40 //#define DEBUG_APB
  41
  42 #ifdef DEBUG_APB
  43 #define APB_DPRINTF(fmt, ...) \
  44 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
  45 #else
  46 #define APB_DPRINTF(fmt, ...)
  47 #endif
  48
  49 /*
  50  * Chipset docs:
  51  * PBM: "UltraSPARC IIi User's Manual",
  52  * http://www.sun.com/processors/manuals/805-0087.pdf
  53  *
  54  * APB: "Advanced PCI Bridge (APB) User's Manual",
  55  * http://www.sun.com/processors/manuals/805-1251.pdf
  56  */
  57
  58 #define PBM_PCI_IMR_MASK    0x7fffffff
  59 #define PBM_PCI_IMR_ENABLED 0x80000000
  60
  61 #define POR          (1 << 31)
  62 #define SOFT_POR     (1 << 30)
  63 #define SOFT_XIR     (1 << 29)
  64 #define BTN_POR      (1 << 28)
  65 #define BTN_XIR      (1 << 27)
  66 #define RESET_MASK   0xf8000000
  67 #define RESET_WCMASK 0x98000000
  68 #define RESET_WMASK  0x60000000
  69
  70 #define MAX_IVEC 0x40
  71 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
  72
  73 #define TYPE_APB "pbm"
  74
  75 #define APB_DEVICE(obj) \
  76     OBJECT_CHECK(APBState, (obj), TYPE_APB)
  77
  78 typedef struct APBState {
  79     PCIHostState parent_obj;
  80
  81     MemoryRegion apb_config;
  82     MemoryRegion pci_config;
  83     MemoryRegion pci_mmio;
  84     MemoryRegion pci_ioport;
  85     uint64_t pci_irq_in;
  86     uint32_t iommu[4];
  87     uint32_t pci_control[16];
  88     uint32_t pci_irq_map[8];
  89     uint32_t obio_irq_map[32];
  90     qemu_irq *pbm_irqs;
  91     qemu_irq *ivec_irqs;
  92     unsigned int irq_request;
  93     uint32_t reset_control;
  94     unsigned int nr_resets;
  95 } APBState;
  96
  97 static inline void pbm_set_request(APBState *s, unsigned int irq_num)
  98 {
  99     APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
 100
 101     s->irq_request = irq_num;
 102     qemu_set_irq(s->ivec_irqs[irq_num], 1);
 103 }
 104
 105 static inline void pbm_check_irqs(APBState *s)
 106 {
 107
 108     unsigned int i;
 109
 110     /* Previous request is not acknowledged, resubmit */
 111     if (s->irq_request != NO_IRQ_REQUEST) {
 112         pbm_set_request(s, s->irq_request);
 113         return;
 114     }
 115     /* no request pending */
 116     if (s->pci_irq_in == 0ULL) {
 117         return;
 118     }
 119     for (i = 0; i < 32; i++) {
 120         if (s->pci_irq_in & (1ULL << i)) {
 121             if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
 122                 pbm_set_request(s, i);
 123                 return;
 124             }
 125         }
 126     }
 127     for (i = 32; i < 64; i++) {
 128         if (s->pci_irq_in & (1ULL << i)) {
 129             if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
 130                 pbm_set_request(s, i);
 131                 break;
 132             }
 133         }
 134     }
 135 }
 136
 137 static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
 138 {
 139     APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
 140     qemu_set_irq(s->ivec_irqs[irq_num], 0);
 141     s->irq_request = NO_IRQ_REQUEST;
 142 }
 143
 144 static void apb_config_writel (void *opaque, hwaddr addr,
 145                                uint64_t val, unsigned size)
 146 {
 147     APBState *s = opaque;
 148
 149     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 150
 151     switch (addr & 0xffff) {
 152     case 0x30 ... 0x4f: /* DMA error registers */
 153         /* XXX: not implemented yet */
 154         break;
 155     case 0x200 ... 0x20b: /* IOMMU */
 156         s->iommu[(addr & 0xf) >> 2] = val;
 157         break;
 158     case 0x20c ... 0x3ff: /* IOMMU flush */
 159         break;
 160     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 161         if (addr & 4) {
 162             unsigned int ino = (addr & 0x3f) >> 3;
 163             s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
 164             s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 165             if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
 166                 pbm_clear_request(s, ino);
 167             }
 168             pbm_check_irqs(s);
 169         }
 170         break;
 171     case 0x1000 ... 0x1080: /* OBIO interrupt control */
 172         if (addr & 4) {
 173             unsigned int ino = ((addr & 0xff) >> 3);
 174             s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
 175             s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 176             if ((s->irq_request == (ino | 0x20))
 177                  && !(val & ~PBM_PCI_IMR_MASK)) {
 178                 pbm_clear_request(s, ino | 0x20);
 179             }
 180             pbm_check_irqs(s);
 181         }
 182         break;
 183     case 0x1400 ... 0x14ff: /* PCI interrupt clear */
 184         if (addr & 4) {
 185             unsigned int ino = (addr & 0xff) >> 5;
 186             if ((s->irq_request / 4)  == ino) {
 187                 pbm_clear_request(s, s->irq_request);
 188                 pbm_check_irqs(s);
 189             }
 190         }
 191         break;
 192     case 0x1800 ... 0x1860: /* OBIO interrupt clear */
 193         if (addr & 4) {
 194             unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
 195             if (s->irq_request == ino) {
 196                 pbm_clear_request(s, ino);
 197                 pbm_check_irqs(s);
 198             }
 199         }
 200         break;
 201     case 0x2000 ... 0x202f: /* PCI control */
 202         s->pci_control[(addr & 0x3f) >> 2] = val;
 203         break;
 204     case 0xf020 ... 0xf027: /* Reset control */
 205         if (addr & 4) {
 206             val &= RESET_MASK;
 207             s->reset_control &= ~(val & RESET_WCMASK);
 208             s->reset_control |= val & RESET_WMASK;
 209             if (val & SOFT_POR) {
 210                 s->nr_resets = 0;
 211                 qemu_system_reset_request();
 212             } else if (val & SOFT_XIR) {
 213                 qemu_system_reset_request();
 214             }
 215         }
 216         break;
 217     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 218     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 219     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 220     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 221         /* we don't care */
 222     default:
 223         break;
 224     }
 225 }
 226
 227 static uint64_t apb_config_readl (void *opaque,
 228                                   hwaddr addr, unsigned size)
 229 {
 230     APBState *s = opaque;
 231     uint32_t val;
 232
 233     switch (addr & 0xffff) {
 234     case 0x30 ... 0x4f: /* DMA error registers */
 235         val = 0;
 236         /* XXX: not implemented yet */
 237         break;
 238     case 0x200 ... 0x20b: /* IOMMU */
 239         val = s->iommu[(addr & 0xf) >> 2];
 240         break;
 241     case 0x20c ... 0x3ff: /* IOMMU flush */
 242         val = 0;
 243         break;
 244     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 245         if (addr & 4) {
 246             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 247         } else {
 248             val = 0;
 249         }
 250         break;
 251     case 0x1000 ... 0x1080: /* OBIO interrupt control */
 252         if (addr & 4) {
 253             val = s->obio_irq_map[(addr & 0xff) >> 3];
 254         } else {
 255             val = 0;
 256         }
 257         break;
 258     case 0x2000 ... 0x202f: /* PCI control */
 259         val = s->pci_control[(addr & 0x3f) >> 2];
 260         break;
 261     case 0xf020 ... 0xf027: /* Reset control */
 262         if (addr & 4) {
 263             val = s->reset_control;
 264         } else {
 265             val = 0;
 266         }
 267         break;
 268     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 269     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 270     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 271     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 272         /* we don't care */
 273     default:
 274         val = 0;
 275         break;
 276     }
 277     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
 278
 279     return val;
 280 }
 281
 282 static const MemoryRegionOps apb_config_ops = {
 283     .read = apb_config_readl,
 284     .write = apb_config_writel,
 285     .endianness = DEVICE_NATIVE_ENDIAN,
 286 };
 287
 288 static void apb_pci_config_write(void *opaque, hwaddr addr,
 289                                  uint64_t val, unsigned size)
 290 {
 291     APBState *s = opaque;
 292     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 293
 294     val = qemu_bswap_len(val, size);
 295     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 296     pci_data_write(phb->bus, addr, val, size);
 297 }
 298
 299 static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
 300                                     unsigned size)
 301 {
 302     uint32_t ret;
 303     APBState *s = opaque;
 304     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 305
 306     ret = pci_data_read(phb->bus, addr, size);
 307     ret = qemu_bswap_len(ret, size);
 308     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
 309     return ret;
 310 }
 311
 312 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 313 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
 314 {
 315     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 316 }
 317
 318 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
 319 {
 320     int bus_offset;
 321     if (pci_dev->devfn & 1)
 322         bus_offset = 16;
 323     else
 324         bus_offset = 0;
 325     return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
 326 }
 327
 328 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 329 {
 330     APBState *s = opaque;
 331
 332     APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
 333     /* PCI IRQ map onto the first 32 INO.  */
 334     if (irq_num < 32) {
 335         if (level) {
 336             s->pci_irq_in |= 1ULL << irq_num;
 337             if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 338                 pbm_set_request(s, irq_num);
 339             }
 340         } else {
 341             s->pci_irq_in &= ~(1ULL << irq_num);
 342         }
 343     } else {
 344         /* OBIO IRQ map onto the next 32 INO.  */
 345         if (level) {
 346             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
 347             s->pci_irq_in |= 1ULL << irq_num;
 348             if ((s->irq_request == NO_IRQ_REQUEST)
 349                 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
 350                 pbm_set_request(s, irq_num);
 351             }
 352         } else {
 353             s->pci_irq_in &= ~(1ULL << irq_num);
 354         }
 355     }
 356 }
 357
 358 static int apb_pci_bridge_initfn(PCIDevice *dev)
 359 {
 360     int rc;
 361
 362     rc = pci_bridge_initfn(dev, TYPE_PCI_BUS);
 363     if (rc < 0) {
 364         return rc;
 365     }
 366
 367     /*
 368      * command register:
 369      * According to PCI bridge spec, after reset
 370      *   bus master bit is off
 371      *   memory space enable bit is off
 372      * According to manual (805-1251.pdf).
 373      *   the reset value should be zero unless the boot pin is tied high
 374      *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
 375      */
 376     pci_set_word(dev->config + PCI_COMMAND,
 377                  PCI_COMMAND_MEMORY);
 378     pci_set_word(dev->config + PCI_STATUS,
 379                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 380                  PCI_STATUS_DEVSEL_MEDIUM);
 381     return 0;
 382 }
 383
 384 PCIBus *pci_apb_init(hwaddr special_base,
 385                      hwaddr mem_base,
 386                      qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
 387                      qemu_irq **pbm_irqs)
 388 {
 389     DeviceState *dev;
 390     SysBusDevice *s;
 391     PCIHostState *phb;
 392     APBState *d;
 393     PCIDevice *pci_dev;
 394     PCIBridge *br;
 395
 396     /* Ultrasparc PBM main bus */
 397     dev = qdev_create(NULL, TYPE_APB);
 398     qdev_init_nofail(dev);
 399     s = SYS_BUS_DEVICE(dev);
 400     /* apb_config */
 401     sysbus_mmio_map(s, 0, special_base);
 402     /* PCI configuration space */
 403     sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
 404     /* pci_ioport */
 405     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
 406     d = APB_DEVICE(dev);
 407
 408     memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
 409     memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
 410
 411     phb = PCI_HOST_BRIDGE(dev);
 412     phb->bus = pci_register_bus(DEVICE(phb), "pci",
 413                                 pci_apb_set_irq, pci_pbm_map_irq, d,
 414                                 &d->pci_mmio,
 415                                 get_system_io(),
 416                                 0, 32, TYPE_PCI_BUS);
 417
 418     *pbm_irqs = d->pbm_irqs;
 419     d->ivec_irqs = ivec_irqs;
 420
 421     pci_create_simple(phb->bus, 0, "pbm-pci");
 422
 423     /* APB secondary busses */
 424     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
 425                                    "pbm-bridge");
 426     br = PCI_BRIDGE(pci_dev);
 427     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
 428                        pci_apb_map_irq);
 429     qdev_init_nofail(&pci_dev->qdev);
 430     *bus2 = pci_bridge_get_sec_bus(br);
 431
 432     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
 433                                    "pbm-bridge");
 434     br = PCI_BRIDGE(pci_dev);
 435     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
 436                        pci_apb_map_irq);
 437     qdev_init_nofail(&pci_dev->qdev);
 438     *bus3 = pci_bridge_get_sec_bus(br);
 439
 440     return phb->bus;
 441 }
 442
 443 static void pci_pbm_reset(DeviceState *d)
 444 {
 445     unsigned int i;
 446     APBState *s = APB_DEVICE(d);
 447
 448     for (i = 0; i < 8; i++) {
 449         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 450     }
 451     for (i = 0; i < 32; i++) {
 452         s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
 453     }
 454
 455     s->irq_request = NO_IRQ_REQUEST;
 456     s->pci_irq_in = 0ULL;
 457
 458     if (s->nr_resets++ == 0) {
 459         /* Power on reset */
 460         s->reset_control = POR;
 461     }
 462 }
 463
 464 static const MemoryRegionOps pci_config_ops = {
 465     .read = apb_pci_config_read,
 466     .write = apb_pci_config_write,
 467     .endianness = DEVICE_NATIVE_ENDIAN,
 468 };
 469
 470 static int pci_pbm_init_device(SysBusDevice *dev)
 471 {
 472     APBState *s;
 473     unsigned int i;
 474
 475     s = APB_DEVICE(dev);
 476     for (i = 0; i < 8; i++) {
 477         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 478     }
 479     for (i = 0; i < 32; i++) {
 480         s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
 481     }
 482     s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
 483     s->irq_request = NO_IRQ_REQUEST;
 484     s->pci_irq_in = 0ULL;
 485
 486     /* apb_config */
 487     memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
 488                           "apb-config", 0x10000);
 489     /* at region 0 */
 490     sysbus_init_mmio(dev, &s->apb_config);
 491
 492     memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
 493                           "apb-pci-config", 0x1000000);
 494     /* at region 1 */
 495     sysbus_init_mmio(dev, &s->pci_config);
 496
 497     /* pci_ioport */
 498     memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
 499                              get_system_io(), 0, 0x10000);
 500     /* at region 2 */
 501     sysbus_init_mmio(dev, &s->pci_ioport);
 502
 503     return 0;
 504 }
 505
 506 static int pbm_pci_host_init(PCIDevice *d)
 507 {
 508     pci_set_word(d->config + PCI_COMMAND,
 509                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 510     pci_set_word(d->config + PCI_STATUS,
 511                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 512                  PCI_STATUS_DEVSEL_MEDIUM);
 513     return 0;
 514 }
 515
 516 static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
 517 {
 518     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 519
 520     k->init = pbm_pci_host_init;
 521     k->vendor_id = PCI_VENDOR_ID_SUN;
 522     k->device_id = PCI_DEVICE_ID_SUN_SABRE;
 523     k->class_id = PCI_CLASS_BRIDGE_HOST;
 524 }
 525
 526 static const TypeInfo pbm_pci_host_info = {
 527     .name          = "pbm-pci",
 528     .parent        = TYPE_PCI_DEVICE,
 529     .instance_size = sizeof(PCIDevice),
 530     .class_init    = pbm_pci_host_class_init,
 531 };
 532
 533 static void pbm_host_class_init(ObjectClass *klass, void *data)
 534 {
 535     DeviceClass *dc = DEVICE_CLASS(klass);
 536     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 537
 538     k->init = pci_pbm_init_device;
 539     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 540     dc->reset = pci_pbm_reset;
 541 }
 542
 543 static const TypeInfo pbm_host_info = {
 544     .name          = TYPE_APB,
 545     .parent        = TYPE_PCI_HOST_BRIDGE,
 546     .instance_size = sizeof(APBState),
 547     .class_init    = pbm_host_class_init,
 548 };
 549
 550 static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
 551 {
 552     DeviceClass *dc = DEVICE_CLASS(klass);
 553     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 554
 555     k->init = apb_pci_bridge_initfn;
 556     k->exit = pci_bridge_exitfn;
 557     k->vendor_id = PCI_VENDOR_ID_SUN;
 558     k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
 559     k->revision = 0x11;
 560     k->config_write = pci_bridge_write_config;
 561     k->is_bridge = 1;
 562     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 563     dc->reset = pci_bridge_reset;
 564     dc->vmsd = &vmstate_pci_device;
 565 }
 566
 567 static const TypeInfo pbm_pci_bridge_info = {
 568     .name          = "pbm-bridge",
 569     .parent        = TYPE_PCI_BRIDGE,
 570     .class_init    = pbm_pci_bridge_class_init,
 571 };
 572
 573 static void pbm_register_types(void)
 574 {
 575     type_register_static(&pbm_host_info);
 576     type_register_static(&pbm_pci_host_info);
 577     type_register_static(&pbm_pci_bridge_info);
 578 }
 579
 580 type_init(pbm_register_types)