hw/intc/arm_gicv3_common.c

   1 /*
   2  * ARM GICv3 support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Copyright (c) 2015 Huawei.
   6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   7  * Written by Peter Maydell
   8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation, either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qom/cpu.h"
  27 #include "hw/intc/arm_gicv3_common.h"
  28 #include "gicv3_internal.h"
  29 #include "hw/arm/linux-boot-if.h"
  30
  31 static void gicv3_pre_save(void *opaque)
  32 {
  33     GICv3State *s = (GICv3State *)opaque;
  34     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
  35
  36     if (c->pre_save) {
  37         c->pre_save(s);
  38     }
  39 }
  40
  41 static int gicv3_post_load(void *opaque, int version_id)
  42 {
  43     GICv3State *s = (GICv3State *)opaque;
  44     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
  45
  46     if (c->post_load) {
  47         c->post_load(s);
  48     }
  49     return 0;
  50 }
  51
  52 static bool virt_state_needed(void *opaque)
  53 {
  54     GICv3CPUState *cs = opaque;
  55
  56     return cs->num_list_regs != 0;
  57 }
  58
  59 static const VMStateDescription vmstate_gicv3_cpu_virt = {
  60     .name = "arm_gicv3_cpu/virt",
  61     .version_id = 1,
  62     .minimum_version_id = 1,
  63     .needed = virt_state_needed,
  64     .fields = (VMStateField[]) {
  65         VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4),
  66         VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState),
  67         VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX),
  68         VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState),
  69         VMSTATE_END_OF_LIST()
  70     }
  71 };
  72
  73 static int icc_sre_el1_reg_pre_load(void *opaque)
  74 {
  75     GICv3CPUState *cs = opaque;
  76
  77    /*
  78     * If the sre_el1 subsection is not transferred this
  79     * means SRE_EL1 is 0x7 (which might not be the same as
  80     * our reset value).
  81     */
  82     cs->icc_sre_el1 = 0x7;
  83     return 0;
  84 }
  85
  86 static bool icc_sre_el1_reg_needed(void *opaque)
  87 {
  88     GICv3CPUState *cs = opaque;
  89
  90     return cs->icc_sre_el1 != 7;
  91 }
  92
  93 const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
  94     .name = "arm_gicv3_cpu/sre_el1",
  95     .version_id = 1,
  96     .minimum_version_id = 1,
  97     .pre_load = icc_sre_el1_reg_pre_load,
  98     .needed = icc_sre_el1_reg_needed,
  99     .fields = (VMStateField[]) {
 100         VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
 101         VMSTATE_END_OF_LIST()
 102     }
 103 };
 104
 105 static const VMStateDescription vmstate_gicv3_cpu = {
 106     .name = "arm_gicv3_cpu",
 107     .version_id = 1,
 108     .minimum_version_id = 1,
 109     .fields = (VMStateField[]) {
 110         VMSTATE_UINT32(level, GICv3CPUState),
 111         VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
 112         VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
 113         VMSTATE_UINT32(gicr_waker, GICv3CPUState),
 114         VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
 115         VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
 116         VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
 117         VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
 118         VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
 119         VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
 120         VMSTATE_UINT32(edge_trigger, GICv3CPUState),
 121         VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
 122         VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
 123         VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
 124         VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
 125         VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
 126         VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
 127         VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
 128         VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
 129         VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
 130         VMSTATE_END_OF_LIST()
 131     },
 132     .subsections = (const VMStateDescription * []) {
 133         &vmstate_gicv3_cpu_virt,
 134         NULL
 135     },
 136     .subsections = (const VMStateDescription * []) {
 137         &vmstate_gicv3_cpu_sre_el1,
 138         NULL
 139     }
 140 };
 141
 142 static const VMStateDescription vmstate_gicv3 = {
 143     .name = "arm_gicv3",
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .pre_save = gicv3_pre_save,
 147     .post_load = gicv3_post_load,
 148     .priority = MIG_PRI_GICV3,
 149     .fields = (VMStateField[]) {
 150         VMSTATE_UINT32(gicd_ctlr, GICv3State),
 151         VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
 152         VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
 153         VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
 154         VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
 155         VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
 156         VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
 157         VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
 158         VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
 159         VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
 160         VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
 161         VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
 162                              DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
 163         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
 164                                              vmstate_gicv3_cpu, GICv3CPUState),
 165         VMSTATE_END_OF_LIST()
 166     }
 167 };
 168
 169 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 170                               const MemoryRegionOps *ops)
 171 {
 172     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 173     int i;
 174
 175     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 176      * GPIO array layout is thus:
 177      *  [0..N-1] spi
 178      *  [N..N+31] PPIs for CPU 0
 179      *  [N+32..N+63] PPIs for CPU 1
 180      *   ...
 181      */
 182     i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
 183     qdev_init_gpio_in(DEVICE(s), handler, i);
 184
 185     for (i = 0; i < s->num_cpu; i++) {
 186         sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
 187     }
 188     for (i = 0; i < s->num_cpu; i++) {
 189         sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
 190     }
 191     for (i = 0; i < s->num_cpu; i++) {
 192         sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
 193     }
 194     for (i = 0; i < s->num_cpu; i++) {
 195         sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
 196     }
 197
 198     memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
 199                           "gicv3_dist", 0x10000);
 200     memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
 201                           "gicv3_redist", 0x20000 * s->num_cpu);
 202
 203     sysbus_init_mmio(sbd, &s->iomem_dist);
 204     sysbus_init_mmio(sbd, &s->iomem_redist);
 205 }
 206
 207 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
 208 {
 209     GICv3State *s = ARM_GICV3_COMMON(dev);
 210     int i;
 211
 212     /* revision property is actually reserved and currently used only in order
 213      * to keep the interface compatible with GICv2 code, avoiding extra
 214      * conditions. However, in future it could be used, for example, if we
 215      * implement GICv4.
 216      */
 217     if (s->revision != 3) {
 218         error_setg(errp, "unsupported GIC revision %d", s->revision);
 219         return;
 220     }
 221
 222     if (s->num_irq > GICV3_MAXIRQ) {
 223         error_setg(errp,
 224                    "requested %u interrupt lines exceeds GIC maximum %d",
 225                    s->num_irq, GICV3_MAXIRQ);
 226         return;
 227     }
 228     if (s->num_irq < GIC_INTERNAL) {
 229         error_setg(errp,
 230                    "requested %u interrupt lines is below GIC minimum %d",
 231                    s->num_irq, GIC_INTERNAL);
 232         return;
 233     }
 234
 235     /* ITLinesNumber is represented as (N / 32) - 1, so this is an
 236      * implementation imposed restriction, not an architectural one,
 237      * so we don't have to deal with bitfields where only some of the
 238      * bits in a 32-bit word should be valid.
 239      */
 240     if (s->num_irq % 32) {
 241         error_setg(errp,
 242                    "%d interrupt lines unsupported: not divisible by 32",
 243                    s->num_irq);
 244         return;
 245     }
 246
 247     s->cpu = g_new0(GICv3CPUState, s->num_cpu);
 248
 249     for (i = 0; i < s->num_cpu; i++) {
 250         CPUState *cpu = qemu_get_cpu(i);
 251         uint64_t cpu_affid;
 252         int last;
 253
 254         s->cpu[i].cpu = cpu;
 255         s->cpu[i].gic = s;
 256         /* Store GICv3CPUState in CPUARMState gicv3state pointer */
 257         gicv3_set_gicv3state(cpu, &s->cpu[i]);
 258
 259         /* Pre-construct the GICR_TYPER:
 260          * For our implementation:
 261          *  Top 32 bits are the affinity value of the associated CPU
 262          *  CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
 263          *  Processor_Number == CPU index starting from 0
 264          *  DPGS == 0 (GICR_CTLR.DPG* not supported)
 265          *  Last == 1 if this is the last redistributor in a series of
 266          *            contiguous redistributor pages
 267          *  DirectLPI == 0 (direct injection of LPIs not supported)
 268          *  VLPIS == 0 (virtual LPIs not supported)
 269          *  PLPIS == 0 (physical LPIs not supported)
 270          */
 271         cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
 272         last = (i == s->num_cpu - 1);
 273
 274         /* The CPU mp-affinity property is in MPIDR register format; squash
 275          * the affinity bytes into 32 bits as the GICR_TYPER has them.
 276          */
 277         cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
 278                      (cpu_affid & 0xFFFFFF);
 279         s->cpu[i].gicr_typer = (cpu_affid << 32) |
 280             (1 << 24) |
 281             (i << 8) |
 282             (last << 4);
 283     }
 284 }
 285
 286 static void arm_gicv3_common_reset(DeviceState *dev)
 287 {
 288     GICv3State *s = ARM_GICV3_COMMON(dev);
 289     int i;
 290
 291     for (i = 0; i < s->num_cpu; i++) {
 292         GICv3CPUState *cs = &s->cpu[i];
 293
 294         cs->level = 0;
 295         cs->gicr_ctlr = 0;
 296         cs->gicr_statusr[GICV3_S] = 0;
 297         cs->gicr_statusr[GICV3_NS] = 0;
 298         cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
 299         cs->gicr_propbaser = 0;
 300         cs->gicr_pendbaser = 0;
 301         /* If we're resetting a TZ-aware GIC as if secure firmware
 302          * had set it up ready to start a kernel in non-secure, we
 303          * need to set interrupts to group 1 so the kernel can use them.
 304          * Otherwise they reset to group 0 like the hardware.
 305          */
 306         if (s->irq_reset_nonsecure) {
 307             cs->gicr_igroupr0 = 0xffffffff;
 308         } else {
 309             cs->gicr_igroupr0 = 0;
 310         }
 311
 312         cs->gicr_ienabler0 = 0;
 313         cs->gicr_ipendr0 = 0;
 314         cs->gicr_iactiver0 = 0;
 315         cs->edge_trigger = 0xffff;
 316         cs->gicr_igrpmodr0 = 0;
 317         cs->gicr_nsacr = 0;
 318         memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
 319
 320         cs->hppi.prio = 0xff;
 321
 322         /* State in the CPU interface must *not* be reset here, because it
 323          * is part of the CPU's reset domain, not the GIC device's.
 324          */
 325     }
 326
 327     /* For our implementation affinity routing is always enabled */
 328     if (s->security_extn) {
 329         s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
 330     } else {
 331         s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
 332     }
 333
 334     s->gicd_statusr[GICV3_S] = 0;
 335     s->gicd_statusr[GICV3_NS] = 0;
 336
 337     memset(s->group, 0, sizeof(s->group));
 338     memset(s->grpmod, 0, sizeof(s->grpmod));
 339     memset(s->enabled, 0, sizeof(s->enabled));
 340     memset(s->pending, 0, sizeof(s->pending));
 341     memset(s->active, 0, sizeof(s->active));
 342     memset(s->level, 0, sizeof(s->level));
 343     memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
 344     memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
 345     memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
 346     memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
 347     /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must
 348      * write these to get sane behaviour and we need not populate the
 349      * pointer cache here; however having the cache be different for
 350      * "happened to be 0 from reset" and "guest wrote 0" would be
 351      * too confusing.
 352      */
 353     gicv3_cache_all_target_cpustates(s);
 354
 355     if (s->irq_reset_nonsecure) {
 356         /* If we're resetting a TZ-aware GIC as if secure firmware
 357          * had set it up ready to start a kernel in non-secure, we
 358          * need to set interrupts to group 1 so the kernel can use them.
 359          * Otherwise they reset to group 0 like the hardware.
 360          */
 361         for (i = GIC_INTERNAL; i < s->num_irq; i++) {
 362             gicv3_gicd_group_set(s, i);
 363         }
 364     }
 365 }
 366
 367 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
 368                                       bool secure_boot)
 369 {
 370     GICv3State *s = ARM_GICV3_COMMON(obj);
 371
 372     if (s->security_extn && !secure_boot) {
 373         /* We're directly booting a kernel into NonSecure. If this GIC
 374          * implements the security extensions then we must configure it
 375          * to have all the interrupts be NonSecure (this is a job that
 376          * is done by the Secure boot firmware in real hardware, and in
 377          * this mode QEMU is acting as a minimalist firmware-and-bootloader
 378          * equivalent).
 379          */
 380         s->irq_reset_nonsecure = true;
 381     }
 382 }
 383
 384 static Property arm_gicv3_common_properties[] = {
 385     DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
 386     DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
 387     DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
 388     DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
 389     DEFINE_PROP_END_OF_LIST(),
 390 };
 391
 392 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
 393 {
 394     DeviceClass *dc = DEVICE_CLASS(klass);
 395     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 396
 397     dc->reset = arm_gicv3_common_reset;
 398     dc->realize = arm_gicv3_common_realize;
 399     dc->props = arm_gicv3_common_properties;
 400     dc->vmsd = &vmstate_gicv3;
 401     albifc->arm_linux_init = arm_gic_common_linux_init;
 402 }
 403
 404 static const TypeInfo arm_gicv3_common_type = {
 405     .name = TYPE_ARM_GICV3_COMMON,
 406     .parent = TYPE_SYS_BUS_DEVICE,
 407     .instance_size = sizeof(GICv3State),
 408     .class_size = sizeof(ARMGICv3CommonClass),
 409     .class_init = arm_gicv3_common_class_init,
 410     .abstract = true,
 411     .interfaces = (InterfaceInfo []) {
 412         { TYPE_ARM_LINUX_BOOT_IF },
 413         { },
 414     },
 415 };
 416
 417 static void register_types(void)
 418 {
 419     type_register_static(&arm_gicv3_common_type);
 420 }
 421
 422 type_init(register_types)