hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw/hw.h"
  22 #include "hw/i386/pc.h"
  23 #include "hw/isa/apm.h"
  24 #include "hw/i2c/pm_smbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/acpi/acpi.h"
  27 #include "sysemu/sysemu.h"
  28 #include "qemu/range.h"
  29 #include "exec/ioport.h"
  30 #include "hw/nvram/fw_cfg.h"
  31 #include "exec/address-spaces.h"
  32 #include "hw/acpi/piix4.h"
  33 #include "hw/acpi/pcihp.h"
  34 #include "hw/acpi/cpu_hotplug.h"
  35
  36 //#define DEBUG
  37
  38 #ifdef DEBUG
  39 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  40 #else
  41 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  42 #endif
  43
  44 #define GPE_BASE 0xafe0
  45 #define GPE_LEN 4
  46
  47 #define PIIX4_PCI_HOTPLUG_STATUS 2
  48
  49 struct pci_status {
  50     uint32_t up; /* deprecated, maintained for migration compatibility */
  51     uint32_t down;
  52 };
  53
  54 typedef struct PIIX4PMState {
  55     /*< private >*/
  56     PCIDevice parent_obj;
  57     /*< public >*/
  58
  59     MemoryRegion io;
  60     uint32_t io_base;
  61
  62     MemoryRegion io_gpe;
  63     ACPIREGS ar;
  64
  65     APMState apm;
  66
  67     PMSMBus smb;
  68     uint32_t smb_io_base;
  69
  70     qemu_irq irq;
  71     qemu_irq smi_irq;
  72     int kvm_enabled;
  73     Notifier machine_ready;
  74     Notifier powerdown_notifier;
  75
  76     AcpiPciHpState acpi_pci_hotplug;
  77     bool use_acpi_pci_hotplug;
  78
  79     uint8_t disable_s3;
  80     uint8_t disable_s4;
  81     uint8_t s4_val;
  82
  83     AcpiCpuHotplug gpe_cpu;
  84     Notifier cpu_added_notifier;
  85 } PIIX4PMState;
  86
  87 #define TYPE_PIIX4_PM "PIIX4_PM"
  88
  89 #define PIIX4_PM(obj) \
  90     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  91
  92 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  93                                            PCIBus *bus, PIIX4PMState *s);
  94
  95 #define ACPI_ENABLE 0xf1
  96 #define ACPI_DISABLE 0xf0
  97
  98 static void pm_tmr_timer(ACPIREGS *ar)
  99 {
 100     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 101     acpi_update_sci(&s->ar, s->irq);
 102 }
 103
 104 static void apm_ctrl_changed(uint32_t val, void *arg)
 105 {
 106     PIIX4PMState *s = arg;
 107     PCIDevice *d = PCI_DEVICE(s);
 108
 109     /* ACPI specs 3.0, 4.7.2.5 */
 110     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 111
 112     if (d->config[0x5b] & (1 << 1)) {
 113         if (s->smi_irq) {
 114             qemu_irq_raise(s->smi_irq);
 115         }
 116     }
 117 }
 118
 119 static void pm_io_space_update(PIIX4PMState *s)
 120 {
 121     PCIDevice *d = PCI_DEVICE(s);
 122
 123     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 124     s->io_base &= 0xffc0;
 125
 126     memory_region_transaction_begin();
 127     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 128     memory_region_set_address(&s->io, s->io_base);
 129     memory_region_transaction_commit();
 130 }
 131
 132 static void smbus_io_space_update(PIIX4PMState *s)
 133 {
 134     PCIDevice *d = PCI_DEVICE(s);
 135
 136     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 137     s->smb_io_base &= 0xffc0;
 138
 139     memory_region_transaction_begin();
 140     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 141     memory_region_set_address(&s->smb.io, s->smb_io_base);
 142     memory_region_transaction_commit();
 143 }
 144
 145 static void pm_write_config(PCIDevice *d,
 146                             uint32_t address, uint32_t val, int len)
 147 {
 148     pci_default_write_config(d, address, val, len);
 149     if (range_covers_byte(address, len, 0x80) ||
 150         ranges_overlap(address, len, 0x40, 4)) {
 151         pm_io_space_update((PIIX4PMState *)d);
 152     }
 153     if (range_covers_byte(address, len, 0xd2) ||
 154         ranges_overlap(address, len, 0x90, 4)) {
 155         smbus_io_space_update((PIIX4PMState *)d);
 156     }
 157 }
 158
 159 static int vmstate_acpi_post_load(void *opaque, int version_id)
 160 {
 161     PIIX4PMState *s = opaque;
 162
 163     pm_io_space_update(s);
 164     return 0;
 165 }
 166
 167 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 168  {                                                                   \
 169      .name       = (stringify(_field)),                              \
 170      .version_id = 0,                                                \
 171      .info       = &vmstate_info_uint16,                             \
 172      .size       = sizeof(uint16_t),                                 \
 173      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 174      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 175  }
 176
 177 static const VMStateDescription vmstate_gpe = {
 178     .name = "gpe",
 179     .version_id = 1,
 180     .minimum_version_id = 1,
 181     .minimum_version_id_old = 1,
 182     .fields      = (VMStateField []) {
 183         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 184         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 185         VMSTATE_END_OF_LIST()
 186     }
 187 };
 188
 189 static const VMStateDescription vmstate_pci_status = {
 190     .name = "pci_status",
 191     .version_id = 1,
 192     .minimum_version_id = 1,
 193     .minimum_version_id_old = 1,
 194     .fields      = (VMStateField []) {
 195         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 196         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 197         VMSTATE_END_OF_LIST()
 198     }
 199 };
 200
 201 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 202 {
 203     PIIX4PMState *s = opaque;
 204     int ret, i;
 205     uint16_t temp;
 206
 207     ret = pci_device_load(PCI_DEVICE(s), f);
 208     if (ret < 0) {
 209         return ret;
 210     }
 211     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 212     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 213     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 214
 215     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 216     if (ret) {
 217         return ret;
 218     }
 219
 220     timer_get(f, s->ar.tmr.timer);
 221     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 222
 223     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 224     for (i = 0; i < 3; i++) {
 225         qemu_get_be16s(f, &temp);
 226     }
 227
 228     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 229     for (i = 0; i < 3; i++) {
 230         qemu_get_be16s(f, &temp);
 231     }
 232
 233     ret = vmstate_load_state(f, &vmstate_pci_status,
 234         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 235     return ret;
 236 }
 237
 238 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 239 {
 240     PIIX4PMState *s = opaque;
 241     return s->use_acpi_pci_hotplug;
 242 }
 243
 244 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 245 {
 246     PIIX4PMState *s = opaque;
 247     return !s->use_acpi_pci_hotplug;
 248 }
 249
 250 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 251  * To support incoming qemu-kvm 1.2 migration, change version_id
 252  * and minimum_version_id to 2 below (which breaks migration from
 253  * qemu 1.2).
 254  *
 255  */
 256 static const VMStateDescription vmstate_acpi = {
 257     .name = "piix4_pm",
 258     .version_id = 3,
 259     .minimum_version_id = 3,
 260     .minimum_version_id_old = 1,
 261     .load_state_old = acpi_load_old,
 262     .post_load = vmstate_acpi_post_load,
 263     .fields      = (VMStateField []) {
 264         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 265         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 266         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 267         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 268         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 269         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 270         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 271         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 272         VMSTATE_STRUCT_TEST(
 273             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 274             PIIX4PMState,
 275             vmstate_test_no_use_acpi_pci_hotplug,
 276             2, vmstate_pci_status,
 277             struct AcpiPciHpPciStatus),
 278         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 279                             vmstate_test_use_acpi_pci_hotplug),
 280         VMSTATE_END_OF_LIST()
 281     }
 282 };
 283
 284 static void piix4_reset(void *opaque)
 285 {
 286     PIIX4PMState *s = opaque;
 287     PCIDevice *d = PCI_DEVICE(s);
 288     uint8_t *pci_conf = d->config;
 289
 290     pci_conf[0x58] = 0;
 291     pci_conf[0x59] = 0;
 292     pci_conf[0x5a] = 0;
 293     pci_conf[0x5b] = 0;
 294
 295     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 296     pci_conf[0x80] = 0;
 297
 298     if (s->kvm_enabled) {
 299         /* Mark SMM as already inited (until KVM supports SMM). */
 300         pci_conf[0x5B] = 0x02;
 301     }
 302     pm_io_space_update(s);
 303     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 304 }
 305
 306 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 307 {
 308     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 309
 310     assert(s != NULL);
 311     acpi_pm1_evt_power_down(&s->ar);
 312 }
 313
 314 static int piix4_acpi_pci_hotplug(DeviceState *qdev, PCIDevice *dev,
 315                                   PCIHotplugState state)
 316 {
 317     PIIX4PMState *s = PIIX4_PM(qdev);
 318     int ret = acpi_pcihp_device_hotplug(&s->acpi_pci_hotplug, dev, state);
 319     if (ret < 0) {
 320         return ret;
 321     }
 322     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 323
 324     acpi_update_sci(&s->ar, s->irq);
 325     return 0;
 326 }
 327
 328 static void piix4_update_bus_hotplug(PCIBus *bus, void *opaque)
 329 {
 330     PIIX4PMState *s = opaque;
 331     pci_bus_hotplug(bus, piix4_acpi_pci_hotplug, DEVICE(s));
 332 }
 333
 334 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 335 {
 336     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 337     PCIDevice *d = PCI_DEVICE(s);
 338     MemoryRegion *io_as = pci_address_space_io(d);
 339     uint8_t *pci_conf;
 340
 341     pci_conf = d->config;
 342     pci_conf[0x5f] = 0x10 |
 343         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 344     pci_conf[0x63] = 0x60;
 345     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 346         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 347
 348     if (s->use_acpi_pci_hotplug) {
 349         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 350     } else {
 351         piix4_update_bus_hotplug(d->bus, s);
 352     }
 353 }
 354
 355 static void piix4_pm_add_propeties(PIIX4PMState *s)
 356 {
 357     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 358     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 359     static const uint32_t gpe0_blk = GPE_BASE;
 360     static const uint32_t gpe0_blk_len = GPE_LEN;
 361     static const uint16_t sci_int = 9;
 362
 363     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 364                                   &acpi_enable_cmd, NULL);
 365     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 366                                   &acpi_disable_cmd, NULL);
 367     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 368                                   &gpe0_blk, NULL);
 369     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 370                                   &gpe0_blk_len, NULL);
 371     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 372                                   &sci_int, NULL);
 373     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 374                                   &s->io_base, NULL);
 375 }
 376
 377 static int piix4_pm_initfn(PCIDevice *dev)
 378 {
 379     PIIX4PMState *s = PIIX4_PM(dev);
 380     uint8_t *pci_conf;
 381
 382     pci_conf = dev->config;
 383     pci_conf[0x06] = 0x80;
 384     pci_conf[0x07] = 0x02;
 385     pci_conf[0x09] = 0x00;
 386     pci_conf[0x3d] = 0x01; // interrupt pin 1
 387
 388     /* APM */
 389     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 390
 391     if (s->kvm_enabled) {
 392         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 393          * support SMM mode. */
 394         pci_conf[0x5B] = 0x02;
 395     }
 396
 397     /* XXX: which specification is used ? The i82731AB has different
 398        mappings */
 399     pci_conf[0x90] = s->smb_io_base | 1;
 400     pci_conf[0x91] = s->smb_io_base >> 8;
 401     pci_conf[0xd2] = 0x09;
 402     pm_smbus_init(DEVICE(dev), &s->smb);
 403     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 404     memory_region_add_subregion(pci_address_space_io(dev),
 405                                 s->smb_io_base, &s->smb.io);
 406
 407     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 408     memory_region_set_enabled(&s->io, false);
 409     memory_region_add_subregion(pci_address_space_io(dev),
 410                                 0, &s->io);
 411
 412     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 413     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 414     acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val);
 415     acpi_gpe_init(&s->ar, GPE_LEN);
 416
 417     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 418     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 419
 420     s->machine_ready.notify = piix4_pm_machine_ready;
 421     qemu_add_machine_init_done_notifier(&s->machine_ready);
 422     qemu_register_reset(piix4_reset, s);
 423
 424     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 425
 426     piix4_pm_add_propeties(s);
 427     return 0;
 428 }
 429
 430 Object *piix4_pm_find(void)
 431 {
 432     bool ambig;
 433     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 434
 435     if (ambig || !o) {
 436         return NULL;
 437     }
 438     return o;
 439 }
 440
 441 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 442                        qemu_irq sci_irq, qemu_irq smi_irq,
 443                        int kvm_enabled, FWCfgState *fw_cfg)
 444 {
 445     DeviceState *dev;
 446     PIIX4PMState *s;
 447
 448     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 449     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 450
 451     s = PIIX4_PM(dev);
 452     s->irq = sci_irq;
 453     s->smi_irq = smi_irq;
 454     s->kvm_enabled = kvm_enabled;
 455
 456     qdev_init_nofail(dev);
 457
 458     if (fw_cfg) {
 459         uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 460         suspend[3] = 1 | ((!s->disable_s3) << 7);
 461         suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 462
 463         fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 464     }
 465
 466     return s->smb.smbus;
 467 }
 468
 469 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 470 {
 471     PIIX4PMState *s = opaque;
 472     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 473
 474     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 475     return val;
 476 }
 477
 478 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 479                        unsigned width)
 480 {
 481     PIIX4PMState *s = opaque;
 482
 483     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 484     acpi_update_sci(&s->ar, s->irq);
 485
 486     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 487 }
 488
 489 static const MemoryRegionOps piix4_gpe_ops = {
 490     .read = gpe_readb,
 491     .write = gpe_writeb,
 492     .valid.min_access_size = 1,
 493     .valid.max_access_size = 4,
 494     .impl.min_access_size = 1,
 495     .impl.max_access_size = 1,
 496     .endianness = DEVICE_LITTLE_ENDIAN,
 497 };
 498
 499 static void piix4_cpu_added_req(Notifier *n, void *opaque)
 500 {
 501     PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier);
 502
 503     assert(s != NULL);
 504     AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque));
 505     acpi_update_sci(&s->ar, s->irq);
 506 }
 507
 508 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 509                                            PCIBus *bus, PIIX4PMState *s)
 510 {
 511     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 512                           "acpi-gpe0", GPE_LEN);
 513     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 514
 515     acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
 516                     s->use_acpi_pci_hotplug);
 517
 518     AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 519                         PIIX4_CPU_HOTPLUG_IO_BASE);
 520     s->cpu_added_notifier.notify = piix4_cpu_added_req;
 521     qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
 522 }
 523
 524 static Property piix4_pm_properties[] = {
 525     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 526     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 527     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 528     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 529     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 530                      use_acpi_pci_hotplug, true),
 531     DEFINE_PROP_END_OF_LIST(),
 532 };
 533
 534 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 535 {
 536     DeviceClass *dc = DEVICE_CLASS(klass);
 537     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 538
 539     k->init = piix4_pm_initfn;
 540     k->config_write = pm_write_config;
 541     k->vendor_id = PCI_VENDOR_ID_INTEL;
 542     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 543     k->revision = 0x03;
 544     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 545     dc->desc = "PM";
 546     dc->vmsd = &vmstate_acpi;
 547     dc->props = piix4_pm_properties;
 548     /*
 549      * Reason: part of PIIX4 southbridge, needs to be wired up,
 550      * e.g. by mips_malta_init()
 551      */
 552     dc->cannot_instantiate_with_device_add_yet = true;
 553     dc->hotpluggable = false;
 554 }
 555
 556 static const TypeInfo piix4_pm_info = {
 557     .name          = TYPE_PIIX4_PM,
 558     .parent        = TYPE_PCI_DEVICE,
 559     .instance_size = sizeof(PIIX4PMState),
 560     .class_init    = piix4_pm_class_init,
 561 };
 562
 563 static void piix4_pm_register_types(void)
 564 {
 565     type_register_static(&piix4_pm_info);
 566 }
 567
 568 type_init(piix4_pm_register_types)