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target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
[qemu.git] / target-arm / helper.c
blobd0b7c27749115fc4f9d0416047e006f128c8a927
1 #include "cpu.h"
2 #include "exec/gdbstub.h"
3 #include "helper.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
8
9 #ifndef CONFIG_USER_ONLY
10 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
11 int access_type, int is_user,
12 hwaddr *phys_ptr, int *prot,
13 target_ulong *page_size);
14 #endif
15
16 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
17 {
18 int nregs;
19
20 /* VFP data registers are always little-endian. */
21 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
22 if (reg < nregs) {
23 stfq_le_p(buf, env->vfp.regs[reg]);
24 return 8;
25 }
26 if (arm_feature(env, ARM_FEATURE_NEON)) {
27 /* Aliases for Q regs. */
28 nregs += 16;
29 if (reg < nregs) {
30 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
31 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
32 return 16;
33 }
34 }
35 switch (reg - nregs) {
36 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
37 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
38 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
39 }
40 return 0;
41 }
42
43 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
44 {
45 int nregs;
46
47 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
48 if (reg < nregs) {
49 env->vfp.regs[reg] = ldfq_le_p(buf);
50 return 8;
51 }
52 if (arm_feature(env, ARM_FEATURE_NEON)) {
53 nregs += 16;
54 if (reg < nregs) {
55 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
56 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
57 return 16;
58 }
59 }
60 switch (reg - nregs) {
61 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
62 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
63 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
64 }
65 return 0;
66 }
67
68 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
69 {
70 switch (reg) {
71 case 0 ... 31:
72 /* 128 bit FP register */
73 stfq_le_p(buf, env->vfp.regs[reg * 2]);
74 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
75 return 16;
76 case 32:
77 /* FPSR */
78 stl_p(buf, vfp_get_fpsr(env));
79 return 4;
80 case 33:
81 /* FPCR */
82 stl_p(buf, vfp_get_fpcr(env));
83 return 4;
84 default:
85 return 0;
86 }
87 }
88
89 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
90 {
91 switch (reg) {
92 case 0 ... 31:
93 /* 128 bit FP register */
94 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
95 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
96 return 16;
97 case 32:
98 /* FPSR */
99 vfp_set_fpsr(env, ldl_p(buf));
100 return 4;
101 case 33:
102 /* FPCR */
103 vfp_set_fpcr(env, ldl_p(buf));
104 return 4;
105 default:
106 return 0;
107 }
108 }
109
110 static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
111 uint64_t *value)
112 {
113 if (ri->type & ARM_CP_64BIT) {
114 *value = CPREG_FIELD64(env, ri);
115 } else {
116 *value = CPREG_FIELD32(env, ri);
117 }
118 return 0;
119 }
120
121 static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
122 uint64_t value)
123 {
124 if (ri->type & ARM_CP_64BIT) {
125 CPREG_FIELD64(env, ri) = value;
126 } else {
127 CPREG_FIELD32(env, ri) = value;
128 }
129 return 0;
130 }
131
132 static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
133 uint64_t *v)
134 {
135 /* Raw read of a coprocessor register (as needed for migration, etc)
136 * return true on success, false if the read is impossible for some reason.
137 */
138 if (ri->type & ARM_CP_CONST) {
139 *v = ri->resetvalue;
140 } else if (ri->raw_readfn) {
141 return (ri->raw_readfn(env, ri, v) == 0);
142 } else if (ri->readfn) {
143 return (ri->readfn(env, ri, v) == 0);
144 } else {
145 if (ri->type & ARM_CP_64BIT) {
146 *v = CPREG_FIELD64(env, ri);
147 } else {
148 *v = CPREG_FIELD32(env, ri);
149 }
150 }
151 return true;
152 }
153
154 static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
155 int64_t v)
156 {
157 /* Raw write of a coprocessor register (as needed for migration, etc).
158 * Return true on success, false if the write is impossible for some reason.
159 * Note that constant registers are treated as write-ignored; the
160 * caller should check for success by whether a readback gives the
161 * value written.
162 */
163 if (ri->type & ARM_CP_CONST) {
164 return true;
165 } else if (ri->raw_writefn) {
166 return (ri->raw_writefn(env, ri, v) == 0);
167 } else if (ri->writefn) {
168 return (ri->writefn(env, ri, v) == 0);
169 } else {
170 if (ri->type & ARM_CP_64BIT) {
171 CPREG_FIELD64(env, ri) = v;
172 } else {
173 CPREG_FIELD32(env, ri) = v;
174 }
175 }
176 return true;
177 }
178
179 bool write_cpustate_to_list(ARMCPU *cpu)
180 {
181 /* Write the coprocessor state from cpu->env to the (index,value) list. */
182 int i;
183 bool ok = true;
184
185 for (i = 0; i < cpu->cpreg_array_len; i++) {
186 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
187 const ARMCPRegInfo *ri;
188 uint64_t v;
189 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
190 if (!ri) {
191 ok = false;
192 continue;
193 }
194 if (ri->type & ARM_CP_NO_MIGRATE) {
195 continue;
196 }
197 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
198 ok = false;
199 continue;
200 }
201 cpu->cpreg_values[i] = v;
202 }
203 return ok;
204 }
205
206 bool write_list_to_cpustate(ARMCPU *cpu)
207 {
208 int i;
209 bool ok = true;
210
211 for (i = 0; i < cpu->cpreg_array_len; i++) {
212 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
213 uint64_t v = cpu->cpreg_values[i];
214 uint64_t readback;
215 const ARMCPRegInfo *ri;
216
217 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
218 if (!ri) {
219 ok = false;
220 continue;
221 }
222 if (ri->type & ARM_CP_NO_MIGRATE) {
223 continue;
224 }
225 /* Write value and confirm it reads back as written
226 * (to catch read-only registers and partially read-only
227 * registers where the incoming migration value doesn't match)
228 */
229 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
230 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
231 readback != v) {
232 ok = false;
233 }
234 }
235 return ok;
236 }
237
238 static void add_cpreg_to_list(gpointer key, gpointer opaque)
239 {
240 ARMCPU *cpu = opaque;
241 uint64_t regidx;
242 const ARMCPRegInfo *ri;
243
244 regidx = *(uint32_t *)key;
245 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
246
247 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
248 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
249 /* The value array need not be initialized at this point */
250 cpu->cpreg_array_len++;
251 }
252 }
253
254 static void count_cpreg(gpointer key, gpointer opaque)
255 {
256 ARMCPU *cpu = opaque;
257 uint64_t regidx;
258 const ARMCPRegInfo *ri;
259
260 regidx = *(uint32_t *)key;
261 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
262
263 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
264 cpu->cpreg_array_len++;
265 }
266 }
267
268 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
269 {
270 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
271 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
272
273 if (aidx > bidx) {
274 return 1;
275 }
276 if (aidx < bidx) {
277 return -1;
278 }
279 return 0;
280 }
281
282 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
283 {
284 GList **plist = udata;
285
286 *plist = g_list_prepend(*plist, key);
287 }
288
289 void init_cpreg_list(ARMCPU *cpu)
290 {
291 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
292 * Note that we require cpreg_tuples[] to be sorted by key ID.
293 */
294 GList *keys = NULL;
295 int arraylen;
296
297 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
298
299 keys = g_list_sort(keys, cpreg_key_compare);
300
301 cpu->cpreg_array_len = 0;
302
303 g_list_foreach(keys, count_cpreg, cpu);
304
305 arraylen = cpu->cpreg_array_len;
306 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
307 cpu->cpreg_values = g_new(uint64_t, arraylen);
308 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
309 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
310 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
311 cpu->cpreg_array_len = 0;
312
313 g_list_foreach(keys, add_cpreg_to_list, cpu);
314
315 assert(cpu->cpreg_array_len == arraylen);
316
317 g_list_free(keys);
318 }
319
320 static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
321 {
322 env->cp15.c3 = value;
323 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
324 return 0;
325 }
326
327 static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
328 {
329 if (env->cp15.c13_fcse != value) {
330 /* Unlike real hardware the qemu TLB uses virtual addresses,
331 * not modified virtual addresses, so this causes a TLB flush.
332 */
333 tlb_flush(env, 1);
334 env->cp15.c13_fcse = value;
335 }
336 return 0;
337 }
338 static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
339 uint64_t value)
340 {
341 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
342 /* For VMSA (when not using the LPAE long descriptor page table
343 * format) this register includes the ASID, so do a TLB flush.
344 * For PMSA it is purely a process ID and no action is needed.
345 */
346 tlb_flush(env, 1);
347 }
348 env->cp15.c13_context = value;
349 return 0;
350 }
351
352 static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
353 uint64_t value)
354 {
355 /* Invalidate all (TLBIALL) */
356 tlb_flush(env, 1);
357 return 0;
358 }
359
360 static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
361 uint64_t value)
362 {
363 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
364 tlb_flush_page(env, value & TARGET_PAGE_MASK);
365 return 0;
366 }
367
368 static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
369 uint64_t value)
370 {
371 /* Invalidate by ASID (TLBIASID) */
372 tlb_flush(env, value == 0);
373 return 0;
374 }
375
376 static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
377 uint64_t value)
378 {
379 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
380 tlb_flush_page(env, value & TARGET_PAGE_MASK);
381 return 0;
382 }
383
384 static const ARMCPRegInfo cp_reginfo[] = {
385 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
386 * version" bits will read as a reserved value, which should cause
387 * Linux to not try to use the debug hardware.
388 */
389 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
390 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
391 /* MMU Domain access control / MPU write buffer control */
392 { .name = "DACR", .cp = 15,
393 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
394 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
395 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
396 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
397 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
398 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
399 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
400 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
401 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
402 /* ??? This covers not just the impdef TLB lockdown registers but also
403 * some v7VMSA registers relating to TEX remap, so it is overly broad.
404 */
405 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
406 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
407 /* MMU TLB control. Note that the wildcarding means we cover not just
408 * the unified TLB ops but also the dside/iside/inner-shareable variants.
409 */
410 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
411 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
412 .type = ARM_CP_NO_MIGRATE },
413 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
414 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
415 .type = ARM_CP_NO_MIGRATE },
416 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
417 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
418 .type = ARM_CP_NO_MIGRATE },
419 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
420 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
421 .type = ARM_CP_NO_MIGRATE },
422 /* Cache maintenance ops; some of this space may be overridden later. */
423 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
424 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
425 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
426 REGINFO_SENTINEL
427 };
428
429 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
430 /* Not all pre-v6 cores implemented this WFI, so this is slightly
431 * over-broad.
432 */
433 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
434 .access = PL1_W, .type = ARM_CP_WFI },
435 REGINFO_SENTINEL
436 };
437
438 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
439 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
440 * is UNPREDICTABLE; we choose to NOP as most implementations do).
441 */
442 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
443 .access = PL1_W, .type = ARM_CP_WFI },
444 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
445 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
446 * OMAPCP will override this space.
447 */
448 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
449 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
450 .resetvalue = 0 },
451 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
452 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
453 .resetvalue = 0 },
454 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
455 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
456 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
457 .resetvalue = 0 },
458 REGINFO_SENTINEL
459 };
460
461 static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
462 {
463 if (env->cp15.c1_coproc != value) {
464 env->cp15.c1_coproc = value;
465 /* ??? Is this safe when called from within a TB? */
466 tb_flush(env);
467 }
468 return 0;
469 }
470
471 static const ARMCPRegInfo v6_cp_reginfo[] = {
472 /* prefetch by MVA in v6, NOP in v7 */
473 { .name = "MVA_prefetch",
474 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
475 .access = PL1_W, .type = ARM_CP_NOP },
476 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
477 .access = PL0_W, .type = ARM_CP_NOP },
478 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
479 .access = PL0_W, .type = ARM_CP_NOP },
480 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
481 .access = PL0_W, .type = ARM_CP_NOP },
482 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
483 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
484 .resetvalue = 0, },
485 /* Watchpoint Fault Address Register : should actually only be present
486 * for 1136, 1176, 11MPCore.
487 */
488 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
489 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
490 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
491 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
492 .resetvalue = 0, .writefn = cpacr_write },
493 REGINFO_SENTINEL
494 };
495
496
497 static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
498 uint64_t *value)
499 {
500 /* Generic performance monitor register read function for where
501 * user access may be allowed by PMUSERENR.
502 */
503 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
504 return EXCP_UDEF;
505 }
506 *value = CPREG_FIELD32(env, ri);
507 return 0;
508 }
509
510 static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
511 uint64_t value)
512 {
513 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
514 return EXCP_UDEF;
515 }
516 /* only the DP, X, D and E bits are writable */
517 env->cp15.c9_pmcr &= ~0x39;
518 env->cp15.c9_pmcr |= (value & 0x39);
519 return 0;
520 }
521
522 static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
523 uint64_t value)
524 {
525 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
526 return EXCP_UDEF;
527 }
528 value &= (1 << 31);
529 env->cp15.c9_pmcnten |= value;
530 return 0;
531 }
532
533 static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
534 uint64_t value)
535 {
536 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
537 return EXCP_UDEF;
538 }
539 value &= (1 << 31);
540 env->cp15.c9_pmcnten &= ~value;
541 return 0;
542 }
543
544 static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
545 uint64_t value)
546 {
547 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
548 return EXCP_UDEF;
549 }
550 env->cp15.c9_pmovsr &= ~value;
551 return 0;
552 }
553
554 static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
555 uint64_t value)
556 {
557 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
558 return EXCP_UDEF;
559 }
560 env->cp15.c9_pmxevtyper = value & 0xff;
561 return 0;
562 }
563
564 static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
565 uint64_t value)
566 {
567 env->cp15.c9_pmuserenr = value & 1;
568 return 0;
569 }
570
571 static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
572 uint64_t value)
573 {
574 /* We have no event counters so only the C bit can be changed */
575 value &= (1 << 31);
576 env->cp15.c9_pminten |= value;
577 return 0;
578 }
579
580 static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
581 uint64_t value)
582 {
583 value &= (1 << 31);
584 env->cp15.c9_pminten &= ~value;
585 return 0;
586 }
587
588 static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
589 uint64_t value)
590 {
591 env->cp15.c12_vbar = value & ~0x1Ful;
592 return 0;
593 }
594
595 static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
596 uint64_t *value)
597 {
598 ARMCPU *cpu = arm_env_get_cpu(env);
599 *value = cpu->ccsidr[env->cp15.c0_cssel];
600 return 0;
601 }
602
603 static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
604 uint64_t value)
605 {
606 env->cp15.c0_cssel = value & 0xf;
607 return 0;
608 }
609
610 static const ARMCPRegInfo v7_cp_reginfo[] = {
611 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
612 * debug components
613 */
614 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
615 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
616 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
617 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
618 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
619 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
620 .access = PL1_W, .type = ARM_CP_NOP },
621 /* Performance monitors are implementation defined in v7,
622 * but with an ARM recommended set of registers, which we
623 * follow (although we don't actually implement any counters)
624 *
625 * Performance registers fall into three categories:
626 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
627 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
628 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
629 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
630 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
631 */
632 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
633 .access = PL0_RW, .resetvalue = 0,
634 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
635 .readfn = pmreg_read, .writefn = pmcntenset_write,
636 .raw_readfn = raw_read, .raw_writefn = raw_write },
637 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
638 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
639 .readfn = pmreg_read, .writefn = pmcntenclr_write,
640 .type = ARM_CP_NO_MIGRATE },
641 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
642 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
643 .readfn = pmreg_read, .writefn = pmovsr_write,
644 .raw_readfn = raw_read, .raw_writefn = raw_write },
645 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
646 * respect PMUSERENR.
647 */
648 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
649 .access = PL0_W, .type = ARM_CP_NOP },
650 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
651 * We choose to RAZ/WI. XXX should respect PMUSERENR.
652 */
653 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
654 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
655 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
656 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
657 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
658 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
659 .access = PL0_RW,
660 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
661 .readfn = pmreg_read, .writefn = pmxevtyper_write,
662 .raw_readfn = raw_read, .raw_writefn = raw_write },
663 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
664 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
665 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
666 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
667 .access = PL0_R | PL1_RW,
668 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
669 .resetvalue = 0,
670 .writefn = pmuserenr_write, .raw_writefn = raw_write },
671 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
672 .access = PL1_RW,
673 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
674 .resetvalue = 0,
675 .writefn = pmintenset_write, .raw_writefn = raw_write },
676 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
677 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
678 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
679 .resetvalue = 0, .writefn = pmintenclr_write, },
680 { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
681 .access = PL1_RW, .writefn = vbar_write,
682 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
683 .resetvalue = 0 },
684 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
685 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
686 .resetvalue = 0, },
687 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
688 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
689 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
690 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
691 .writefn = csselr_write, .resetvalue = 0 },
692 /* Auxiliary ID register: this actually has an IMPDEF value but for now
693 * just RAZ for all cores:
694 */
695 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
696 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
697 REGINFO_SENTINEL
698 };
699
700 static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
701 {
702 value &= 1;
703 env->teecr = value;
704 return 0;
705 }
706
707 static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
708 uint64_t *value)
709 {
710 /* This is a helper function because the user access rights
711 * depend on the value of the TEECR.
712 */
713 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
714 return EXCP_UDEF;
715 }
716 *value = env->teehbr;
717 return 0;
718 }
719
720 static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
721 uint64_t value)
722 {
723 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
724 return EXCP_UDEF;
725 }
726 env->teehbr = value;
727 return 0;
728 }
729
730 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
731 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
732 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
733 .resetvalue = 0,
734 .writefn = teecr_write },
735 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
736 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
737 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
738 .readfn = teehbr_read, .writefn = teehbr_write },
739 REGINFO_SENTINEL
740 };
741
742 static const ARMCPRegInfo v6k_cp_reginfo[] = {
743 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
744 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
745 .access = PL0_RW,
746 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
747 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
748 .access = PL0_RW,
749 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
750 .resetfn = arm_cp_reset_ignore },
751 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
752 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
753 .access = PL0_R|PL1_W,
754 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
755 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
756 .access = PL0_R|PL1_W,
757 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
758 .resetfn = arm_cp_reset_ignore },
759 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
760 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
761 .access = PL1_RW,
762 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
763 REGINFO_SENTINEL
764 };
765
766 #ifndef CONFIG_USER_ONLY
767
768 static uint64_t gt_get_countervalue(CPUARMState *env)
769 {
770 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
771 }
772
773 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
774 {
775 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
776
777 if (gt->ctl & 1) {
778 /* Timer enabled: calculate and set current ISTATUS, irq, and
779 * reset timer to when ISTATUS next has to change
780 */
781 uint64_t count = gt_get_countervalue(&cpu->env);
782 /* Note that this must be unsigned 64 bit arithmetic: */
783 int istatus = count >= gt->cval;
784 uint64_t nexttick;
785
786 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
787 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
788 (istatus && !(gt->ctl & 2)));
789 if (istatus) {
790 /* Next transition is when count rolls back over to zero */
791 nexttick = UINT64_MAX;
792 } else {
793 /* Next transition is when we hit cval */
794 nexttick = gt->cval;
795 }
796 /* Note that the desired next expiry time might be beyond the
797 * signed-64-bit range of a QEMUTimer -- in this case we just
798 * set the timer for as far in the future as possible. When the
799 * timer expires we will reset the timer for any remaining period.
800 */
801 if (nexttick > INT64_MAX / GTIMER_SCALE) {
802 nexttick = INT64_MAX / GTIMER_SCALE;
803 }
804 timer_mod(cpu->gt_timer[timeridx], nexttick);
805 } else {
806 /* Timer disabled: ISTATUS and timer output always clear */
807 gt->ctl &= ~4;
808 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
809 timer_del(cpu->gt_timer[timeridx]);
810 }
811 }
812
813 static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
814 uint64_t *value)
815 {
816 /* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
817 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
818 return EXCP_UDEF;
819 }
820 *value = env->cp15.c14_cntfrq;
821 return 0;
822 }
823
824 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
825 {
826 ARMCPU *cpu = arm_env_get_cpu(env);
827 int timeridx = ri->opc1 & 1;
828
829 timer_del(cpu->gt_timer[timeridx]);
830 }
831
832 static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
833 uint64_t *value)
834 {
835 int timeridx = ri->opc1 & 1;
836
837 if (arm_current_pl(env) == 0 &&
838 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
839 return EXCP_UDEF;
840 }
841 *value = gt_get_countervalue(env);
842 return 0;
843 }
844
845 static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
846 uint64_t *value)
847 {
848 int timeridx = ri->opc1 & 1;
849
850 if (arm_current_pl(env) == 0 &&
851 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
852 return EXCP_UDEF;
853 }
854 *value = env->cp15.c14_timer[timeridx].cval;
855 return 0;
856 }
857
858 static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
859 uint64_t value)
860 {
861 int timeridx = ri->opc1 & 1;
862
863 env->cp15.c14_timer[timeridx].cval = value;
864 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
865 return 0;
866 }
867 static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
868 uint64_t *value)
869 {
870 int timeridx = ri->crm & 1;
871
872 if (arm_current_pl(env) == 0 &&
873 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
874 return EXCP_UDEF;
875 }
876 *value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
877 gt_get_countervalue(env));
878 return 0;
879 }
880
881 static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
882 uint64_t value)
883 {
884 int timeridx = ri->crm & 1;
885
886 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
887 + sextract64(value, 0, 32);
888 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
889 return 0;
890 }
891
892 static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
893 uint64_t *value)
894 {
895 int timeridx = ri->crm & 1;
896
897 if (arm_current_pl(env) == 0 &&
898 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
899 return EXCP_UDEF;
900 }
901 *value = env->cp15.c14_timer[timeridx].ctl;
902 return 0;
903 }
904
905 static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
906 uint64_t value)
907 {
908 ARMCPU *cpu = arm_env_get_cpu(env);
909 int timeridx = ri->crm & 1;
910 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
911
912 env->cp15.c14_timer[timeridx].ctl = value & 3;
913 if ((oldval ^ value) & 1) {
914 /* Enable toggled */
915 gt_recalc_timer(cpu, timeridx);
916 } else if ((oldval & value) & 2) {
917 /* IMASK toggled: don't need to recalculate,
918 * just set the interrupt line based on ISTATUS
919 */
920 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
921 (oldval & 4) && (value & 2));
922 }
923 return 0;
924 }
925
926 void arm_gt_ptimer_cb(void *opaque)
927 {
928 ARMCPU *cpu = opaque;
929
930 gt_recalc_timer(cpu, GTIMER_PHYS);
931 }
932
933 void arm_gt_vtimer_cb(void *opaque)
934 {
935 ARMCPU *cpu = opaque;
936
937 gt_recalc_timer(cpu, GTIMER_VIRT);
938 }
939
940 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
941 /* Note that CNTFRQ is purely reads-as-written for the benefit
942 * of software; writing it doesn't actually change the timer frequency.
943 * Our reset value matches the fixed frequency we implement the timer at.
944 */
945 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
946 .access = PL1_RW | PL0_R,
947 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
948 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
949 .readfn = gt_cntfrq_read, .raw_readfn = raw_read,
950 },
951 /* overall control: mostly access permissions */
952 { .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
953 .access = PL1_RW,
954 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
955 .resetvalue = 0,
956 },
957 /* per-timer control */
958 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
959 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
960 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
961 .resetvalue = 0,
962 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
963 .raw_readfn = raw_read, .raw_writefn = raw_write,
964 },
965 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
966 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
967 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
968 .resetvalue = 0,
969 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
970 .raw_readfn = raw_read, .raw_writefn = raw_write,
971 },
972 /* TimerValue views: a 32 bit downcounting view of the underlying state */
973 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
974 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
975 .readfn = gt_tval_read, .writefn = gt_tval_write,
976 },
977 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
978 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
979 .readfn = gt_tval_read, .writefn = gt_tval_write,
980 },
981 /* The counter itself */
982 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
983 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
984 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
985 },
986 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
987 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
988 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
989 },
990 /* Comparison value, indicating when the timer goes off */
991 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
992 .access = PL1_RW | PL0_R,
993 .type = ARM_CP_64BIT | ARM_CP_IO,
994 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
995 .resetvalue = 0,
996 .readfn = gt_cval_read, .writefn = gt_cval_write,
997 .raw_readfn = raw_read, .raw_writefn = raw_write,
998 },
999 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1000 .access = PL1_RW | PL0_R,
1001 .type = ARM_CP_64BIT | ARM_CP_IO,
1002 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1003 .resetvalue = 0,
1004 .readfn = gt_cval_read, .writefn = gt_cval_write,
1005 .raw_readfn = raw_read, .raw_writefn = raw_write,
1006 },
1007 REGINFO_SENTINEL
1008 };
1009
1010 #else
1011 /* In user-mode none of the generic timer registers are accessible,
1012 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1013 * so instead just don't register any of them.
1014 */
1015 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1016 REGINFO_SENTINEL
1017 };
1018
1019 #endif
1020
1021 static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1022 {
1023 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1024 env->cp15.c7_par = value;
1025 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1026 env->cp15.c7_par = value & 0xfffff6ff;
1027 } else {
1028 env->cp15.c7_par = value & 0xfffff1ff;
1029 }
1030 return 0;
1031 }
1032
1033 #ifndef CONFIG_USER_ONLY
1034 /* get_phys_addr() isn't present for user-mode-only targets */
1035
1036 /* Return true if extended addresses are enabled, ie this is an
1037 * LPAE implementation and we are using the long-descriptor translation
1038 * table format because the TTBCR EAE bit is set.
1039 */
1040 static inline bool extended_addresses_enabled(CPUARMState *env)
1041 {
1042 return arm_feature(env, ARM_FEATURE_LPAE)
1043 && (env->cp15.c2_control & (1U << 31));
1044 }
1045
1046 static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1047 {
1048 hwaddr phys_addr;
1049 target_ulong page_size;
1050 int prot;
1051 int ret, is_user = ri->opc2 & 2;
1052 int access_type = ri->opc2 & 1;
1053
1054 if (ri->opc2 & 4) {
1055 /* Other states are only available with TrustZone */
1056 return EXCP_UDEF;
1057 }
1058 ret = get_phys_addr(env, value, access_type, is_user,
1059 &phys_addr, &prot, &page_size);
1060 if (extended_addresses_enabled(env)) {
1061 /* ret is a DFSR/IFSR value for the long descriptor
1062 * translation table format, but with WnR always clear.
1063 * Convert it to a 64-bit PAR.
1064 */
1065 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1066 if (ret == 0) {
1067 par64 |= phys_addr & ~0xfffULL;
1068 /* We don't set the ATTR or SH fields in the PAR. */
1069 } else {
1070 par64 |= 1; /* F */
1071 par64 |= (ret & 0x3f) << 1; /* FS */
1072 /* Note that S2WLK and FSTAGE are always zero, because we don't
1073 * implement virtualization and therefore there can't be a stage 2
1074 * fault.
1075 */
1076 }
1077 env->cp15.c7_par = par64;
1078 env->cp15.c7_par_hi = par64 >> 32;
1079 } else {
1080 /* ret is a DFSR/IFSR value for the short descriptor
1081 * translation table format (with WnR always clear).
1082 * Convert it to a 32-bit PAR.
1083 */
1084 if (ret == 0) {
1085 /* We do not set any attribute bits in the PAR */
1086 if (page_size == (1 << 24)
1087 && arm_feature(env, ARM_FEATURE_V7)) {
1088 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1089 } else {
1090 env->cp15.c7_par = phys_addr & 0xfffff000;
1091 }
1092 } else {
1093 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1094 ((ret & (12 << 1)) >> 6) |
1095 ((ret & 0xf) << 1) | 1;
1096 }
1097 env->cp15.c7_par_hi = 0;
1098 }
1099 return 0;
1100 }
1101 #endif
1102
1103 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1104 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1105 .access = PL1_RW, .resetvalue = 0,
1106 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1107 .writefn = par_write },
1108 #ifndef CONFIG_USER_ONLY
1109 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1110 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1111 #endif
1112 REGINFO_SENTINEL
1113 };
1114
1115 /* Return basic MPU access permission bits. */
1116 static uint32_t simple_mpu_ap_bits(uint32_t val)
1117 {
1118 uint32_t ret;
1119 uint32_t mask;
1120 int i;
1121 ret = 0;
1122 mask = 3;
1123 for (i = 0; i < 16; i += 2) {
1124 ret |= (val >> i) & mask;
1125 mask <<= 2;
1126 }
1127 return ret;
1128 }
1129
1130 /* Pad basic MPU access permission bits to extended format. */
1131 static uint32_t extended_mpu_ap_bits(uint32_t val)
1132 {
1133 uint32_t ret;
1134 uint32_t mask;
1135 int i;
1136 ret = 0;
1137 mask = 3;
1138 for (i = 0; i < 16; i += 2) {
1139 ret |= (val & mask) << i;
1140 mask <<= 2;
1141 }
1142 return ret;
1143 }
1144
1145 static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1146 uint64_t value)
1147 {
1148 env->cp15.c5_data = extended_mpu_ap_bits(value);
1149 return 0;
1150 }
1151
1152 static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1153 uint64_t *value)
1154 {
1155 *value = simple_mpu_ap_bits(env->cp15.c5_data);
1156 return 0;
1157 }
1158
1159 static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1160 uint64_t value)
1161 {
1162 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1163 return 0;
1164 }
1165
1166 static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1167 uint64_t *value)
1168 {
1169 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
1170 return 0;
1171 }
1172
1173 static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1174 uint64_t *value)
1175 {
1176 if (ri->crm >= 8) {
1177 return EXCP_UDEF;
1178 }
1179 *value = env->cp15.c6_region[ri->crm];
1180 return 0;
1181 }
1182
1183 static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1184 uint64_t value)
1185 {
1186 if (ri->crm >= 8) {
1187 return EXCP_UDEF;
1188 }
1189 env->cp15.c6_region[ri->crm] = value;
1190 return 0;
1191 }
1192
1193 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1194 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1195 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1196 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1197 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1198 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1199 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1200 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1201 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1202 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1203 .access = PL1_RW,
1204 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1205 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1206 .access = PL1_RW,
1207 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1208 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1209 .access = PL1_RW,
1210 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1211 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1212 .access = PL1_RW,
1213 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1214 /* Protection region base and size registers */
1215 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1216 .opc2 = CP_ANY, .access = PL1_RW,
1217 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
1218 REGINFO_SENTINEL
1219 };
1220
1221 static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1222 uint64_t value)
1223 {
1224 int maskshift = extract32(value, 0, 3);
1225
1226 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1227 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1228 } else {
1229 value &= 7;
1230 }
1231 /* Note that we always calculate c2_mask and c2_base_mask, but
1232 * they are only used for short-descriptor tables (ie if EAE is 0);
1233 * for long-descriptor tables the TTBCR fields are used differently
1234 * and the c2_mask and c2_base_mask values are meaningless.
1235 */
1236 env->cp15.c2_control = value;
1237 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1238 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1239 return 0;
1240 }
1241
1242 static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1243 uint64_t value)
1244 {
1245 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1246 /* With LPAE the TTBCR could result in a change of ASID
1247 * via the TTBCR.A1 bit, so do a TLB flush.
1248 */
1249 tlb_flush(env, 1);
1250 }
1251 return vmsa_ttbcr_raw_write(env, ri, value);
1252 }
1253
1254 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1255 {
1256 env->cp15.c2_base_mask = 0xffffc000u;
1257 env->cp15.c2_control = 0;
1258 env->cp15.c2_mask = 0;
1259 }
1260
1261 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1262 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1263 .access = PL1_RW,
1264 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1265 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1266 .access = PL1_RW,
1267 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1268 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1269 .access = PL1_RW,
1270 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1271 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1272 .access = PL1_RW,
1273 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
1274 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1275 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
1276 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
1277 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1278 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1279 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1280 .resetvalue = 0, },
1281 REGINFO_SENTINEL
1282 };
1283
1284 static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1285 uint64_t value)
1286 {
1287 env->cp15.c15_ticonfig = value & 0xe7;
1288 /* The OS_TYPE bit in this register changes the reported CPUID! */
1289 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1290 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1291 return 0;
1292 }
1293
1294 static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1295 uint64_t value)
1296 {
1297 env->cp15.c15_threadid = value & 0xffff;
1298 return 0;
1299 }
1300
1301 static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1302 uint64_t value)
1303 {
1304 /* Wait-for-interrupt (deprecated) */
1305 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1306 return 0;
1307 }
1308
1309 static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1310 uint64_t value)
1311 {
1312 /* On OMAP there are registers indicating the max/min index of dcache lines
1313 * containing a dirty line; cache flush operations have to reset these.
1314 */
1315 env->cp15.c15_i_max = 0x000;
1316 env->cp15.c15_i_min = 0xff0;
1317 return 0;
1318 }
1319
1320 static const ARMCPRegInfo omap_cp_reginfo[] = {
1321 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1322 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1323 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1324 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1325 .access = PL1_RW, .type = ARM_CP_NOP },
1326 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1327 .access = PL1_RW,
1328 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1329 .writefn = omap_ticonfig_write },
1330 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1331 .access = PL1_RW,
1332 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1333 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1334 .access = PL1_RW, .resetvalue = 0xff0,
1335 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1336 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1337 .access = PL1_RW,
1338 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1339 .writefn = omap_threadid_write },
1340 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1341 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1342 .type = ARM_CP_NO_MIGRATE,
1343 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1344 /* TODO: Peripheral port remap register:
1345 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1346 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1347 * when MMU is off.
1348 */
1349 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1350 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1351 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1352 .writefn = omap_cachemaint_write },
1353 { .name = "C9", .cp = 15, .crn = 9,
1354 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1355 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1356 REGINFO_SENTINEL
1357 };
1358
1359 static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1360 uint64_t value)
1361 {
1362 value &= 0x3fff;
1363 if (env->cp15.c15_cpar != value) {
1364 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1365 tb_flush(env);
1366 env->cp15.c15_cpar = value;
1367 }
1368 return 0;
1369 }
1370
1371 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1372 { .name = "XSCALE_CPAR",
1373 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1374 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1375 .writefn = xscale_cpar_write, },
1376 { .name = "XSCALE_AUXCR",
1377 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1378 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1379 .resetvalue = 0, },
1380 REGINFO_SENTINEL
1381 };
1382
1383 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1384 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1385 * implementation of this implementation-defined space.
1386 * Ideally this should eventually disappear in favour of actually
1387 * implementing the correct behaviour for all cores.
1388 */
1389 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1390 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1391 .access = PL1_RW,
1392 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1393 .resetvalue = 0 },
1394 REGINFO_SENTINEL
1395 };
1396
1397 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1398 /* Cache status: RAZ because we have no cache so it's always clean */
1399 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1400 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1401 .resetvalue = 0 },
1402 REGINFO_SENTINEL
1403 };
1404
1405 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1406 /* We never have a a block transfer operation in progress */
1407 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1408 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1409 .resetvalue = 0 },
1410 /* The cache ops themselves: these all NOP for QEMU */
1411 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1412 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1413 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1414 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1415 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1416 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1417 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1418 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1419 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1420 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1421 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1422 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1423 REGINFO_SENTINEL
1424 };
1425
1426 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1427 /* The cache test-and-clean instructions always return (1 << 30)
1428 * to indicate that there are no dirty cache lines.
1429 */
1430 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1431 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1432 .resetvalue = (1 << 30) },
1433 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1434 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1435 .resetvalue = (1 << 30) },
1436 REGINFO_SENTINEL
1437 };
1438
1439 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1440 /* Ignore ReadBuffer accesses */
1441 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1442 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1443 .access = PL1_RW, .resetvalue = 0,
1444 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1445 REGINFO_SENTINEL
1446 };
1447
1448 static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1449 uint64_t *value)
1450 {
1451 CPUState *cs = CPU(arm_env_get_cpu(env));
1452 uint32_t mpidr = cs->cpu_index;
1453 /* We don't support setting cluster ID ([8..11])
1454 * so these bits always RAZ.
1455 */
1456 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1457 mpidr |= (1U << 31);
1458 /* Cores which are uniprocessor (non-coherent)
1459 * but still implement the MP extensions set
1460 * bit 30. (For instance, A9UP.) However we do
1461 * not currently model any of those cores.
1462 */
1463 }
1464 *value = mpidr;
1465 return 0;
1466 }
1467
1468 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1469 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1470 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1471 REGINFO_SENTINEL
1472 };
1473
1474 static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1475 {
1476 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1477 return 0;
1478 }
1479
1480 static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1481 {
1482 env->cp15.c7_par_hi = value >> 32;
1483 env->cp15.c7_par = value;
1484 return 0;
1485 }
1486
1487 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1488 {
1489 env->cp15.c7_par_hi = 0;
1490 env->cp15.c7_par = 0;
1491 }
1492
1493 static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1494 uint64_t *value)
1495 {
1496 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1497 return 0;
1498 }
1499
1500 static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1501 uint64_t value)
1502 {
1503 env->cp15.c2_base0_hi = value >> 32;
1504 env->cp15.c2_base0 = value;
1505 return 0;
1506 }
1507
1508 static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1509 uint64_t value)
1510 {
1511 /* Writes to the 64 bit format TTBRs may change the ASID */
1512 tlb_flush(env, 1);
1513 return ttbr064_raw_write(env, ri, value);
1514 }
1515
1516 static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1517 {
1518 env->cp15.c2_base0_hi = 0;
1519 env->cp15.c2_base0 = 0;
1520 }
1521
1522 static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1523 uint64_t *value)
1524 {
1525 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1526 return 0;
1527 }
1528
1529 static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1530 uint64_t value)
1531 {
1532 env->cp15.c2_base1_hi = value >> 32;
1533 env->cp15.c2_base1 = value;
1534 return 0;
1535 }
1536
1537 static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1538 {
1539 env->cp15.c2_base1_hi = 0;
1540 env->cp15.c2_base1 = 0;
1541 }
1542
1543 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1544 /* NOP AMAIR0/1: the override is because these clash with the rather
1545 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1546 */
1547 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1548 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1549 .resetvalue = 0 },
1550 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1551 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1552 .resetvalue = 0 },
1553 /* 64 bit access versions of the (dummy) debug registers */
1554 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1555 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1556 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1557 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1558 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1559 .access = PL1_RW, .type = ARM_CP_64BIT,
1560 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1561 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1562 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1563 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1564 .resetfn = ttbr064_reset },
1565 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1566 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1567 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
1568 REGINFO_SENTINEL
1569 };
1570
1571 static int aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1572 uint64_t *value)
1573 {
1574 *value = vfp_get_fpcr(env);
1575 return 0;
1576 }
1577
1578 static int aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1579 uint64_t value)
1580 {
1581 vfp_set_fpcr(env, value);
1582 return 0;
1583 }
1584
1585 static int aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1586 uint64_t *value)
1587 {
1588 *value = vfp_get_fpsr(env);
1589 return 0;
1590 }
1591
1592 static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1593 uint64_t value)
1594 {
1595 vfp_set_fpsr(env, value);
1596 return 0;
1597 }
1598
1599 static const ARMCPRegInfo v8_cp_reginfo[] = {
1600 /* Minimal set of EL0-visible registers. This will need to be expanded
1601 * significantly for system emulation of AArch64 CPUs.
1602 */
1603 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1604 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1605 .access = PL0_RW, .type = ARM_CP_NZCV },
1606 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1607 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1608 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1609 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1610 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1611 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1612 /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.
1613 * It will eventually need to have a CPU-specified reset value.
1614 */
1615 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
1616 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
1617 .access = PL0_R, .type = ARM_CP_CONST,
1618 .resetvalue = 0x80030003 },
1619 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1620 * For system mode the DZP bit here will need to be computed, not constant.
1621 */
1622 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1623 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1624 .access = PL0_R, .type = ARM_CP_CONST,
1625 .resetvalue = 0x10 },
1626 REGINFO_SENTINEL
1627 };
1628
1629 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1630 {
1631 env->cp15.c1_sys = value;
1632 /* ??? Lots of these bits are not implemented. */
1633 /* This may enable/disable the MMU, so do a TLB flush. */
1634 tlb_flush(env, 1);
1635 return 0;
1636 }
1637
1638 void register_cp_regs_for_features(ARMCPU *cpu)
1639 {
1640 /* Register all the coprocessor registers based on feature bits */
1641 CPUARMState *env = &cpu->env;
1642 if (arm_feature(env, ARM_FEATURE_M)) {
1643 /* M profile has no coprocessor registers */
1644 return;
1645 }
1646
1647 define_arm_cp_regs(cpu, cp_reginfo);
1648 if (arm_feature(env, ARM_FEATURE_V6)) {
1649 /* The ID registers all have impdef reset values */
1650 ARMCPRegInfo v6_idregs[] = {
1651 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1652 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1653 .resetvalue = cpu->id_pfr0 },
1654 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1655 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1656 .resetvalue = cpu->id_pfr1 },
1657 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1658 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1659 .resetvalue = cpu->id_dfr0 },
1660 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1661 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1662 .resetvalue = cpu->id_afr0 },
1663 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1664 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1665 .resetvalue = cpu->id_mmfr0 },
1666 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1667 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1668 .resetvalue = cpu->id_mmfr1 },
1669 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1670 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1671 .resetvalue = cpu->id_mmfr2 },
1672 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1673 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1674 .resetvalue = cpu->id_mmfr3 },
1675 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1676 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1677 .resetvalue = cpu->id_isar0 },
1678 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1679 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1680 .resetvalue = cpu->id_isar1 },
1681 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1682 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1683 .resetvalue = cpu->id_isar2 },
1684 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1685 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1686 .resetvalue = cpu->id_isar3 },
1687 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1688 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1689 .resetvalue = cpu->id_isar4 },
1690 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1691 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1692 .resetvalue = cpu->id_isar5 },
1693 /* 6..7 are as yet unallocated and must RAZ */
1694 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1695 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1696 .resetvalue = 0 },
1697 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1698 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1699 .resetvalue = 0 },
1700 REGINFO_SENTINEL
1701 };
1702 define_arm_cp_regs(cpu, v6_idregs);
1703 define_arm_cp_regs(cpu, v6_cp_reginfo);
1704 } else {
1705 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1706 }
1707 if (arm_feature(env, ARM_FEATURE_V6K)) {
1708 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1709 }
1710 if (arm_feature(env, ARM_FEATURE_V7)) {
1711 /* v7 performance monitor control register: same implementor
1712 * field as main ID register, and we implement no event counters.
1713 */
1714 ARMCPRegInfo pmcr = {
1715 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1716 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1717 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1718 .readfn = pmreg_read, .writefn = pmcr_write,
1719 .raw_readfn = raw_read, .raw_writefn = raw_write,
1720 };
1721 ARMCPRegInfo clidr = {
1722 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1723 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1724 };
1725 define_one_arm_cp_reg(cpu, &pmcr);
1726 define_one_arm_cp_reg(cpu, &clidr);
1727 define_arm_cp_regs(cpu, v7_cp_reginfo);
1728 } else {
1729 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1730 }
1731 if (arm_feature(env, ARM_FEATURE_V8)) {
1732 define_arm_cp_regs(cpu, v8_cp_reginfo);
1733 }
1734 if (arm_feature(env, ARM_FEATURE_MPU)) {
1735 /* These are the MPU registers prior to PMSAv6. Any new
1736 * PMSA core later than the ARM946 will require that we
1737 * implement the PMSAv6 or PMSAv7 registers, which are
1738 * completely different.
1739 */
1740 assert(!arm_feature(env, ARM_FEATURE_V6));
1741 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1742 } else {
1743 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1744 }
1745 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1746 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1747 }
1748 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1749 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1750 }
1751 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1752 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1753 }
1754 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1755 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1756 }
1757 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1758 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1759 }
1760 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1761 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1762 }
1763 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1764 define_arm_cp_regs(cpu, omap_cp_reginfo);
1765 }
1766 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1767 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1768 }
1769 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1770 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1771 }
1772 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1773 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1774 }
1775 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1776 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1777 }
1778 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1779 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1780 * be read-only (ie write causes UNDEF exception).
1781 */
1782 {
1783 ARMCPRegInfo id_cp_reginfo[] = {
1784 /* Note that the MIDR isn't a simple constant register because
1785 * of the TI925 behaviour where writes to another register can
1786 * cause the MIDR value to change.
1787 *
1788 * Unimplemented registers in the c15 0 0 0 space default to
1789 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1790 * and friends override accordingly.
1791 */
1792 { .name = "MIDR",
1793 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
1794 .access = PL1_R, .resetvalue = cpu->midr,
1795 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
1796 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1797 .type = ARM_CP_OVERRIDE },
1798 { .name = "CTR",
1799 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1800 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1801 { .name = "TCMTR",
1802 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1803 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1804 { .name = "TLBTR",
1805 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1806 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1807 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1808 { .name = "DUMMY",
1809 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1810 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1811 { .name = "DUMMY",
1812 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1813 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1814 { .name = "DUMMY",
1815 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1816 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1817 { .name = "DUMMY",
1818 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1819 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1820 { .name = "DUMMY",
1821 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1822 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1823 REGINFO_SENTINEL
1824 };
1825 ARMCPRegInfo crn0_wi_reginfo = {
1826 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1827 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1828 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1829 };
1830 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1831 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1832 ARMCPRegInfo *r;
1833 /* Register the blanket "writes ignored" value first to cover the
1834 * whole space. Then update the specific ID registers to allow write
1835 * access, so that they ignore writes rather than causing them to
1836 * UNDEF.
1837 */
1838 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1839 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1840 r->access = PL1_RW;
1841 }
1842 }
1843 define_arm_cp_regs(cpu, id_cp_reginfo);
1844 }
1845
1846 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1847 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1848 }
1849
1850 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1851 ARMCPRegInfo auxcr = {
1852 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1853 .access = PL1_RW, .type = ARM_CP_CONST,
1854 .resetvalue = cpu->reset_auxcr
1855 };
1856 define_one_arm_cp_reg(cpu, &auxcr);
1857 }
1858
1859 if (arm_feature(env, ARM_FEATURE_CBAR)) {
1860 ARMCPRegInfo cbar = {
1861 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
1862 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
1863 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
1864 };
1865 define_one_arm_cp_reg(cpu, &cbar);
1866 }
1867
1868 /* Generic registers whose values depend on the implementation */
1869 {
1870 ARMCPRegInfo sctlr = {
1871 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1872 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1873 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1874 .raw_writefn = raw_write,
1875 };
1876 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1877 /* Normally we would always end the TB on an SCTLR write, but Linux
1878 * arch/arm/mach-pxa/sleep.S expects two instructions following
1879 * an MMU enable to execute from cache. Imitate this behaviour.
1880 */
1881 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1882 }
1883 define_one_arm_cp_reg(cpu, &sctlr);
1884 }
1885 }
1886
1887 ARMCPU *cpu_arm_init(const char *cpu_model)
1888 {
1889 ARMCPU *cpu;
1890 ObjectClass *oc;
1891
1892 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1893 if (!oc) {
1894 return NULL;
1895 }
1896 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1897
1898 /* TODO this should be set centrally, once possible */
1899 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1900
1901 return cpu;
1902 }
1903
1904 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1905 {
1906 CPUState *cs = CPU(cpu);
1907 CPUARMState *env = &cpu->env;
1908
1909 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1910 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
1911 aarch64_fpu_gdb_set_reg,
1912 34, "aarch64-fpu.xml", 0);
1913 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
1914 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1915 51, "arm-neon.xml", 0);
1916 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1917 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1918 35, "arm-vfp3.xml", 0);
1919 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1920 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1921 19, "arm-vfp.xml", 0);
1922 }
1923 }
1924
1925 /* Sort alphabetically by type name, except for "any". */
1926 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1927 {
1928 ObjectClass *class_a = (ObjectClass *)a;
1929 ObjectClass *class_b = (ObjectClass *)b;
1930 const char *name_a, *name_b;
1931
1932 name_a = object_class_get_name(class_a);
1933 name_b = object_class_get_name(class_b);
1934 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1935 return 1;
1936 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1937 return -1;
1938 } else {
1939 return strcmp(name_a, name_b);
1940 }
1941 }
1942
1943 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1944 {
1945 ObjectClass *oc = data;
1946 CPUListState *s = user_data;
1947 const char *typename;
1948 char *name;
1949
1950 typename = object_class_get_name(oc);
1951 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1952 (*s->cpu_fprintf)(s->file, " %s\n",
1953 name);
1954 g_free(name);
1955 }
1956
1957 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1958 {
1959 CPUListState s = {
1960 .file = f,
1961 .cpu_fprintf = cpu_fprintf,
1962 };
1963 GSList *list;
1964
1965 list = object_class_get_list(TYPE_ARM_CPU, false);
1966 list = g_slist_sort(list, arm_cpu_list_compare);
1967 (*cpu_fprintf)(f, "Available CPUs:\n");
1968 g_slist_foreach(list, arm_cpu_list_entry, &s);
1969 g_slist_free(list);
1970 #ifdef CONFIG_KVM
1971 /* The 'host' CPU type is dynamically registered only if KVM is
1972 * enabled, so we have to special-case it here:
1973 */
1974 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
1975 #endif
1976 }
1977
1978 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
1979 {
1980 ObjectClass *oc = data;
1981 CpuDefinitionInfoList **cpu_list = user_data;
1982 CpuDefinitionInfoList *entry;
1983 CpuDefinitionInfo *info;
1984 const char *typename;
1985
1986 typename = object_class_get_name(oc);
1987 info = g_malloc0(sizeof(*info));
1988 info->name = g_strndup(typename,
1989 strlen(typename) - strlen("-" TYPE_ARM_CPU));
1990
1991 entry = g_malloc0(sizeof(*entry));
1992 entry->value = info;
1993 entry->next = *cpu_list;
1994 *cpu_list = entry;
1995 }
1996
1997 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1998 {
1999 CpuDefinitionInfoList *cpu_list = NULL;
2000 GSList *list;
2001
2002 list = object_class_get_list(TYPE_ARM_CPU, false);
2003 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2004 g_slist_free(list);
2005
2006 return cpu_list;
2007 }
2008
2009 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2010 void *opaque, int state,
2011 int crm, int opc1, int opc2)
2012 {
2013 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2014 * add a single reginfo struct to the hash table.
2015 */
2016 uint32_t *key = g_new(uint32_t, 1);
2017 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2018 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2019 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2020 /* The AArch32 view of a shared register sees the lower 32 bits
2021 * of a 64 bit backing field. It is not migratable as the AArch64
2022 * view handles that. AArch64 also handles reset.
2023 * We assume it is a cp15 register.
2024 */
2025 r2->cp = 15;
2026 r2->type |= ARM_CP_NO_MIGRATE;
2027 r2->resetfn = arm_cp_reset_ignore;
2028 #ifdef HOST_WORDS_BIGENDIAN
2029 if (r2->fieldoffset) {
2030 r2->fieldoffset += sizeof(uint32_t);
2031 }
2032 #endif
2033 }
2034 if (state == ARM_CP_STATE_AA64) {
2035 /* To allow abbreviation of ARMCPRegInfo
2036 * definitions, we treat cp == 0 as equivalent to
2037 * the value for "standard guest-visible sysreg".
2038 */
2039 if (r->cp == 0) {
2040 r2->cp = CP_REG_ARM64_SYSREG_CP;
2041 }
2042 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2043 r2->opc0, opc1, opc2);
2044 } else {
2045 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2046 }
2047 if (opaque) {
2048 r2->opaque = opaque;
2049 }
2050 /* Make sure reginfo passed to helpers for wildcarded regs
2051 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2052 */
2053 r2->crm = crm;
2054 r2->opc1 = opc1;
2055 r2->opc2 = opc2;
2056 /* By convention, for wildcarded registers only the first
2057 * entry is used for migration; the others are marked as
2058 * NO_MIGRATE so we don't try to transfer the register
2059 * multiple times. Special registers (ie NOP/WFI) are
2060 * never migratable.
2061 */
2062 if ((r->type & ARM_CP_SPECIAL) ||
2063 ((r->crm == CP_ANY) && crm != 0) ||
2064 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2065 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2066 r2->type |= ARM_CP_NO_MIGRATE;
2067 }
2068
2069 /* Overriding of an existing definition must be explicitly
2070 * requested.
2071 */
2072 if (!(r->type & ARM_CP_OVERRIDE)) {
2073 ARMCPRegInfo *oldreg;
2074 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2075 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2076 fprintf(stderr, "Register redefined: cp=%d %d bit "
2077 "crn=%d crm=%d opc1=%d opc2=%d, "
2078 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2079 r2->crn, r2->crm, r2->opc1, r2->opc2,
2080 oldreg->name, r2->name);
2081 g_assert_not_reached();
2082 }
2083 }
2084 g_hash_table_insert(cpu->cp_regs, key, r2);
2085 }
2086
2087
2088 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2089 const ARMCPRegInfo *r, void *opaque)
2090 {
2091 /* Define implementations of coprocessor registers.
2092 * We store these in a hashtable because typically
2093 * there are less than 150 registers in a space which
2094 * is 16*16*16*8*8 = 262144 in size.
2095 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2096 * If a register is defined twice then the second definition is
2097 * used, so this can be used to define some generic registers and
2098 * then override them with implementation specific variations.
2099 * At least one of the original and the second definition should
2100 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2101 * against accidental use.
2102 *
2103 * The state field defines whether the register is to be
2104 * visible in the AArch32 or AArch64 execution state. If the
2105 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2106 * reginfo structure for the AArch32 view, which sees the lower
2107 * 32 bits of the 64 bit register.
2108 *
2109 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2110 * be wildcarded. AArch64 registers are always considered to be 64
2111 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2112 * the register, if any.
2113 */
2114 int crm, opc1, opc2, state;
2115 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2116 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2117 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2118 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2119 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2120 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2121 /* 64 bit registers have only CRm and Opc1 fields */
2122 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2123 /* op0 only exists in the AArch64 encodings */
2124 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2125 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2126 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2127 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2128 * encodes a minimum access level for the register. We roll this
2129 * runtime check into our general permission check code, so check
2130 * here that the reginfo's specified permissions are strict enough
2131 * to encompass the generic architectural permission check.
2132 */
2133 if (r->state != ARM_CP_STATE_AA32) {
2134 int mask = 0;
2135 switch (r->opc1) {
2136 case 0: case 1: case 2:
2137 /* min_EL EL1 */
2138 mask = PL1_RW;
2139 break;
2140 case 3:
2141 /* min_EL EL0 */
2142 mask = PL0_RW;
2143 break;
2144 case 4:
2145 /* min_EL EL2 */
2146 mask = PL2_RW;
2147 break;
2148 case 5:
2149 /* unallocated encoding, so not possible */
2150 assert(false);
2151 break;
2152 case 6:
2153 /* min_EL EL3 */
2154 mask = PL3_RW;
2155 break;
2156 case 7:
2157 /* min_EL EL1, secure mode only (we don't check the latter) */
2158 mask = PL1_RW;
2159 break;
2160 default:
2161 /* broken reginfo with out-of-range opc1 */
2162 assert(false);
2163 break;
2164 }
2165 /* assert our permissions are not too lax (stricter is fine) */
2166 assert((r->access & ~mask) == 0);
2167 }
2168
2169 /* Check that the register definition has enough info to handle
2170 * reads and writes if they are permitted.
2171 */
2172 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2173 if (r->access & PL3_R) {
2174 assert(r->fieldoffset || r->readfn);
2175 }
2176 if (r->access & PL3_W) {
2177 assert(r->fieldoffset || r->writefn);
2178 }
2179 }
2180 /* Bad type field probably means missing sentinel at end of reg list */
2181 assert(cptype_valid(r->type));
2182 for (crm = crmmin; crm <= crmmax; crm++) {
2183 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2184 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2185 for (state = ARM_CP_STATE_AA32;
2186 state <= ARM_CP_STATE_AA64; state++) {
2187 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2188 continue;
2189 }
2190 add_cpreg_to_hashtable(cpu, r, opaque, state,
2191 crm, opc1, opc2);
2192 }
2193 }
2194 }
2195 }
2196 }
2197
2198 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2199 const ARMCPRegInfo *regs, void *opaque)
2200 {
2201 /* Define a whole list of registers */
2202 const ARMCPRegInfo *r;
2203 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2204 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2205 }
2206 }
2207
2208 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2209 {
2210 return g_hash_table_lookup(cpregs, &encoded_cp);
2211 }
2212
2213 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2214 uint64_t value)
2215 {
2216 /* Helper coprocessor write function for write-ignore registers */
2217 return 0;
2218 }
2219
2220 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
2221 {
2222 /* Helper coprocessor write function for read-as-zero registers */
2223 *value = 0;
2224 return 0;
2225 }
2226
2227 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2228 {
2229 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2230 }
2231
2232 static int bad_mode_switch(CPUARMState *env, int mode)
2233 {
2234 /* Return true if it is not valid for us to switch to
2235 * this CPU mode (ie all the UNPREDICTABLE cases in
2236 * the ARM ARM CPSRWriteByInstr pseudocode).
2237 */
2238 switch (mode) {
2239 case ARM_CPU_MODE_USR:
2240 case ARM_CPU_MODE_SYS:
2241 case ARM_CPU_MODE_SVC:
2242 case ARM_CPU_MODE_ABT:
2243 case ARM_CPU_MODE_UND:
2244 case ARM_CPU_MODE_IRQ:
2245 case ARM_CPU_MODE_FIQ:
2246 return 0;
2247 default:
2248 return 1;
2249 }
2250 }
2251
2252 uint32_t cpsr_read(CPUARMState *env)
2253 {
2254 int ZF;
2255 ZF = (env->ZF == 0);
2256 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2257 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2258 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2259 | ((env->condexec_bits & 0xfc) << 8)
2260 | (env->GE << 16);
2261 }
2262
2263 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2264 {
2265 if (mask & CPSR_NZCV) {
2266 env->ZF = (~val) & CPSR_Z;
2267 env->NF = val;
2268 env->CF = (val >> 29) & 1;
2269 env->VF = (val << 3) & 0x80000000;
2270 }
2271 if (mask & CPSR_Q)
2272 env->QF = ((val & CPSR_Q) != 0);
2273 if (mask & CPSR_T)
2274 env->thumb = ((val & CPSR_T) != 0);
2275 if (mask & CPSR_IT_0_1) {
2276 env->condexec_bits &= ~3;
2277 env->condexec_bits |= (val >> 25) & 3;
2278 }
2279 if (mask & CPSR_IT_2_7) {
2280 env->condexec_bits &= 3;
2281 env->condexec_bits |= (val >> 8) & 0xfc;
2282 }
2283 if (mask & CPSR_GE) {
2284 env->GE = (val >> 16) & 0xf;
2285 }
2286
2287 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2288 if (bad_mode_switch(env, val & CPSR_M)) {
2289 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2290 * We choose to ignore the attempt and leave the CPSR M field
2291 * untouched.
2292 */
2293 mask &= ~CPSR_M;
2294 } else {
2295 switch_mode(env, val & CPSR_M);
2296 }
2297 }
2298 mask &= ~CACHED_CPSR_BITS;
2299 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2300 }
2301
2302 /* Sign/zero extend */
2303 uint32_t HELPER(sxtb16)(uint32_t x)
2304 {
2305 uint32_t res;
2306 res = (uint16_t)(int8_t)x;
2307 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2308 return res;
2309 }
2310
2311 uint32_t HELPER(uxtb16)(uint32_t x)
2312 {
2313 uint32_t res;
2314 res = (uint16_t)(uint8_t)x;
2315 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2316 return res;
2317 }
2318
2319 uint32_t HELPER(clz)(uint32_t x)
2320 {
2321 return clz32(x);
2322 }
2323
2324 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2325 {
2326 if (den == 0)
2327 return 0;
2328 if (num == INT_MIN && den == -1)
2329 return INT_MIN;
2330 return num / den;
2331 }
2332
2333 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2334 {
2335 if (den == 0)
2336 return 0;
2337 return num / den;
2338 }
2339
2340 uint32_t HELPER(rbit)(uint32_t x)
2341 {
2342 x = ((x & 0xff000000) >> 24)
2343 | ((x & 0x00ff0000) >> 8)
2344 | ((x & 0x0000ff00) << 8)
2345 | ((x & 0x000000ff) << 24);
2346 x = ((x & 0xf0f0f0f0) >> 4)
2347 | ((x & 0x0f0f0f0f) << 4);
2348 x = ((x & 0x88888888) >> 3)
2349 | ((x & 0x44444444) >> 1)
2350 | ((x & 0x22222222) << 1)
2351 | ((x & 0x11111111) << 3);
2352 return x;
2353 }
2354
2355 #if defined(CONFIG_USER_ONLY)
2356
2357 void arm_cpu_do_interrupt(CPUState *cs)
2358 {
2359 ARMCPU *cpu = ARM_CPU(cs);
2360 CPUARMState *env = &cpu->env;
2361
2362 env->exception_index = -1;
2363 }
2364
2365 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2366 int mmu_idx)
2367 {
2368 if (rw == 2) {
2369 env->exception_index = EXCP_PREFETCH_ABORT;
2370 env->cp15.c6_insn = address;
2371 } else {
2372 env->exception_index = EXCP_DATA_ABORT;
2373 env->cp15.c6_data = address;
2374 }
2375 return 1;
2376 }
2377
2378 /* These should probably raise undefined insn exceptions. */
2379 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2380 {
2381 cpu_abort(env, "v7m_mrs %d\n", reg);
2382 }
2383
2384 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2385 {
2386 cpu_abort(env, "v7m_mrs %d\n", reg);
2387 return 0;
2388 }
2389
2390 void switch_mode(CPUARMState *env, int mode)
2391 {
2392 if (mode != ARM_CPU_MODE_USR)
2393 cpu_abort(env, "Tried to switch out of user mode\n");
2394 }
2395
2396 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2397 {
2398 cpu_abort(env, "banked r13 write\n");
2399 }
2400
2401 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2402 {
2403 cpu_abort(env, "banked r13 read\n");
2404 return 0;
2405 }
2406
2407 #else
2408
2409 /* Map CPU modes onto saved register banks. */
2410 int bank_number(int mode)
2411 {
2412 switch (mode) {
2413 case ARM_CPU_MODE_USR:
2414 case ARM_CPU_MODE_SYS:
2415 return 0;
2416 case ARM_CPU_MODE_SVC:
2417 return 1;
2418 case ARM_CPU_MODE_ABT:
2419 return 2;
2420 case ARM_CPU_MODE_UND:
2421 return 3;
2422 case ARM_CPU_MODE_IRQ:
2423 return 4;
2424 case ARM_CPU_MODE_FIQ:
2425 return 5;
2426 }
2427 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2428 }
2429
2430 void switch_mode(CPUARMState *env, int mode)
2431 {
2432 int old_mode;
2433 int i;
2434
2435 old_mode = env->uncached_cpsr & CPSR_M;
2436 if (mode == old_mode)
2437 return;
2438
2439 if (old_mode == ARM_CPU_MODE_FIQ) {
2440 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2441 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2442 } else if (mode == ARM_CPU_MODE_FIQ) {
2443 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2444 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2445 }
2446
2447 i = bank_number(old_mode);
2448 env->banked_r13[i] = env->regs[13];
2449 env->banked_r14[i] = env->regs[14];
2450 env->banked_spsr[i] = env->spsr;
2451
2452 i = bank_number(mode);
2453 env->regs[13] = env->banked_r13[i];
2454 env->regs[14] = env->banked_r14[i];
2455 env->spsr = env->banked_spsr[i];
2456 }
2457
2458 static void v7m_push(CPUARMState *env, uint32_t val)
2459 {
2460 env->regs[13] -= 4;
2461 stl_phys(env->regs[13], val);
2462 }
2463
2464 static uint32_t v7m_pop(CPUARMState *env)
2465 {
2466 uint32_t val;
2467 val = ldl_phys(env->regs[13]);
2468 env->regs[13] += 4;
2469 return val;
2470 }
2471
2472 /* Switch to V7M main or process stack pointer. */
2473 static void switch_v7m_sp(CPUARMState *env, int process)
2474 {
2475 uint32_t tmp;
2476 if (env->v7m.current_sp != process) {
2477 tmp = env->v7m.other_sp;
2478 env->v7m.other_sp = env->regs[13];
2479 env->regs[13] = tmp;
2480 env->v7m.current_sp = process;
2481 }
2482 }
2483
2484 static void do_v7m_exception_exit(CPUARMState *env)
2485 {
2486 uint32_t type;
2487 uint32_t xpsr;
2488
2489 type = env->regs[15];
2490 if (env->v7m.exception != 0)
2491 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2492
2493 /* Switch to the target stack. */
2494 switch_v7m_sp(env, (type & 4) != 0);
2495 /* Pop registers. */
2496 env->regs[0] = v7m_pop(env);
2497 env->regs[1] = v7m_pop(env);
2498 env->regs[2] = v7m_pop(env);
2499 env->regs[3] = v7m_pop(env);
2500 env->regs[12] = v7m_pop(env);
2501 env->regs[14] = v7m_pop(env);
2502 env->regs[15] = v7m_pop(env);
2503 xpsr = v7m_pop(env);
2504 xpsr_write(env, xpsr, 0xfffffdff);
2505 /* Undo stack alignment. */
2506 if (xpsr & 0x200)
2507 env->regs[13] |= 4;
2508 /* ??? The exception return type specifies Thread/Handler mode. However
2509 this is also implied by the xPSR value. Not sure what to do
2510 if there is a mismatch. */
2511 /* ??? Likewise for mismatches between the CONTROL register and the stack
2512 pointer. */
2513 }
2514
2515 /* Exception names for debug logging; note that not all of these
2516 * precisely correspond to architectural exceptions.
2517 */
2518 static const char * const excnames[] = {
2519 [EXCP_UDEF] = "Undefined Instruction",
2520 [EXCP_SWI] = "SVC",
2521 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2522 [EXCP_DATA_ABORT] = "Data Abort",
2523 [EXCP_IRQ] = "IRQ",
2524 [EXCP_FIQ] = "FIQ",
2525 [EXCP_BKPT] = "Breakpoint",
2526 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2527 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2528 [EXCP_STREX] = "QEMU intercept of STREX",
2529 };
2530
2531 static inline void arm_log_exception(int idx)
2532 {
2533 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2534 const char *exc = NULL;
2535
2536 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2537 exc = excnames[idx];
2538 }
2539 if (!exc) {
2540 exc = "unknown";
2541 }
2542 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2543 }
2544 }
2545
2546 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2547 {
2548 ARMCPU *cpu = ARM_CPU(cs);
2549 CPUARMState *env = &cpu->env;
2550 uint32_t xpsr = xpsr_read(env);
2551 uint32_t lr;
2552 uint32_t addr;
2553
2554 arm_log_exception(env->exception_index);
2555
2556 lr = 0xfffffff1;
2557 if (env->v7m.current_sp)
2558 lr |= 4;
2559 if (env->v7m.exception == 0)
2560 lr |= 8;
2561
2562 /* For exceptions we just mark as pending on the NVIC, and let that
2563 handle it. */
2564 /* TODO: Need to escalate if the current priority is higher than the
2565 one we're raising. */
2566 switch (env->exception_index) {
2567 case EXCP_UDEF:
2568 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2569 return;
2570 case EXCP_SWI:
2571 /* The PC already points to the next instruction. */
2572 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2573 return;
2574 case EXCP_PREFETCH_ABORT:
2575 case EXCP_DATA_ABORT:
2576 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2577 return;
2578 case EXCP_BKPT:
2579 if (semihosting_enabled) {
2580 int nr;
2581 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2582 if (nr == 0xab) {
2583 env->regs[15] += 2;
2584 env->regs[0] = do_arm_semihosting(env);
2585 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2586 return;
2587 }
2588 }
2589 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2590 return;
2591 case EXCP_IRQ:
2592 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2593 break;
2594 case EXCP_EXCEPTION_EXIT:
2595 do_v7m_exception_exit(env);
2596 return;
2597 default:
2598 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2599 return; /* Never happens. Keep compiler happy. */
2600 }
2601
2602 /* Align stack pointer. */
2603 /* ??? Should only do this if Configuration Control Register
2604 STACKALIGN bit is set. */
2605 if (env->regs[13] & 4) {
2606 env->regs[13] -= 4;
2607 xpsr |= 0x200;
2608 }
2609 /* Switch to the handler mode. */
2610 v7m_push(env, xpsr);
2611 v7m_push(env, env->regs[15]);
2612 v7m_push(env, env->regs[14]);
2613 v7m_push(env, env->regs[12]);
2614 v7m_push(env, env->regs[3]);
2615 v7m_push(env, env->regs[2]);
2616 v7m_push(env, env->regs[1]);
2617 v7m_push(env, env->regs[0]);
2618 switch_v7m_sp(env, 0);
2619 /* Clear IT bits */
2620 env->condexec_bits = 0;
2621 env->regs[14] = lr;
2622 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2623 env->regs[15] = addr & 0xfffffffe;
2624 env->thumb = addr & 1;
2625 }
2626
2627 /* Handle a CPU exception. */
2628 void arm_cpu_do_interrupt(CPUState *cs)
2629 {
2630 ARMCPU *cpu = ARM_CPU(cs);
2631 CPUARMState *env = &cpu->env;
2632 uint32_t addr;
2633 uint32_t mask;
2634 int new_mode;
2635 uint32_t offset;
2636
2637 assert(!IS_M(env));
2638
2639 arm_log_exception(env->exception_index);
2640
2641 /* TODO: Vectored interrupt controller. */
2642 switch (env->exception_index) {
2643 case EXCP_UDEF:
2644 new_mode = ARM_CPU_MODE_UND;
2645 addr = 0x04;
2646 mask = CPSR_I;
2647 if (env->thumb)
2648 offset = 2;
2649 else
2650 offset = 4;
2651 break;
2652 case EXCP_SWI:
2653 if (semihosting_enabled) {
2654 /* Check for semihosting interrupt. */
2655 if (env->thumb) {
2656 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2657 & 0xff;
2658 } else {
2659 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2660 & 0xffffff;
2661 }
2662 /* Only intercept calls from privileged modes, to provide some
2663 semblance of security. */
2664 if (((mask == 0x123456 && !env->thumb)
2665 || (mask == 0xab && env->thumb))
2666 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2667 env->regs[0] = do_arm_semihosting(env);
2668 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2669 return;
2670 }
2671 }
2672 new_mode = ARM_CPU_MODE_SVC;
2673 addr = 0x08;
2674 mask = CPSR_I;
2675 /* The PC already points to the next instruction. */
2676 offset = 0;
2677 break;
2678 case EXCP_BKPT:
2679 /* See if this is a semihosting syscall. */
2680 if (env->thumb && semihosting_enabled) {
2681 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2682 if (mask == 0xab
2683 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2684 env->regs[15] += 2;
2685 env->regs[0] = do_arm_semihosting(env);
2686 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2687 return;
2688 }
2689 }
2690 env->cp15.c5_insn = 2;
2691 /* Fall through to prefetch abort. */
2692 case EXCP_PREFETCH_ABORT:
2693 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2694 env->cp15.c5_insn, env->cp15.c6_insn);
2695 new_mode = ARM_CPU_MODE_ABT;
2696 addr = 0x0c;
2697 mask = CPSR_A | CPSR_I;
2698 offset = 4;
2699 break;
2700 case EXCP_DATA_ABORT:
2701 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2702 env->cp15.c5_data, env->cp15.c6_data);
2703 new_mode = ARM_CPU_MODE_ABT;
2704 addr = 0x10;
2705 mask = CPSR_A | CPSR_I;
2706 offset = 8;
2707 break;
2708 case EXCP_IRQ:
2709 new_mode = ARM_CPU_MODE_IRQ;
2710 addr = 0x18;
2711 /* Disable IRQ and imprecise data aborts. */
2712 mask = CPSR_A | CPSR_I;
2713 offset = 4;
2714 break;
2715 case EXCP_FIQ:
2716 new_mode = ARM_CPU_MODE_FIQ;
2717 addr = 0x1c;
2718 /* Disable FIQ, IRQ and imprecise data aborts. */
2719 mask = CPSR_A | CPSR_I | CPSR_F;
2720 offset = 4;
2721 break;
2722 default:
2723 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2724 return; /* Never happens. Keep compiler happy. */
2725 }
2726 /* High vectors. */
2727 if (env->cp15.c1_sys & (1 << 13)) {
2728 /* when enabled, base address cannot be remapped. */
2729 addr += 0xffff0000;
2730 } else {
2731 /* ARM v7 architectures provide a vector base address register to remap
2732 * the interrupt vector table.
2733 * This register is only followed in non-monitor mode, and has a secure
2734 * and un-secure copy. Since the cpu is always in a un-secure operation
2735 * and is never in monitor mode this feature is always active.
2736 * Note: only bits 31:5 are valid.
2737 */
2738 addr += env->cp15.c12_vbar;
2739 }
2740 switch_mode (env, new_mode);
2741 env->spsr = cpsr_read(env);
2742 /* Clear IT bits. */
2743 env->condexec_bits = 0;
2744 /* Switch to the new mode, and to the correct instruction set. */
2745 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2746 env->uncached_cpsr |= mask;
2747 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2748 * and we should just guard the thumb mode on V4 */
2749 if (arm_feature(env, ARM_FEATURE_V4T)) {
2750 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2751 }
2752 env->regs[14] = env->regs[15] + offset;
2753 env->regs[15] = addr;
2754 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2755 }
2756
2757 /* Check section/page access permissions.
2758 Returns the page protection flags, or zero if the access is not
2759 permitted. */
2760 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2761 int access_type, int is_user)
2762 {
2763 int prot_ro;
2764
2765 if (domain_prot == 3) {
2766 return PAGE_READ | PAGE_WRITE;
2767 }
2768
2769 if (access_type == 1)
2770 prot_ro = 0;
2771 else
2772 prot_ro = PAGE_READ;
2773
2774 switch (ap) {
2775 case 0:
2776 if (access_type == 1)
2777 return 0;
2778 switch ((env->cp15.c1_sys >> 8) & 3) {
2779 case 1:
2780 return is_user ? 0 : PAGE_READ;
2781 case 2:
2782 return PAGE_READ;
2783 default:
2784 return 0;
2785 }
2786 case 1:
2787 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2788 case 2:
2789 if (is_user)
2790 return prot_ro;
2791 else
2792 return PAGE_READ | PAGE_WRITE;
2793 case 3:
2794 return PAGE_READ | PAGE_WRITE;
2795 case 4: /* Reserved. */
2796 return 0;
2797 case 5:
2798 return is_user ? 0 : prot_ro;
2799 case 6:
2800 return prot_ro;
2801 case 7:
2802 if (!arm_feature (env, ARM_FEATURE_V6K))
2803 return 0;
2804 return prot_ro;
2805 default:
2806 abort();
2807 }
2808 }
2809
2810 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
2811 {
2812 uint32_t table;
2813
2814 if (address & env->cp15.c2_mask)
2815 table = env->cp15.c2_base1 & 0xffffc000;
2816 else
2817 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2818
2819 table |= (address >> 18) & 0x3ffc;
2820 return table;
2821 }
2822
2823 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
2824 int is_user, hwaddr *phys_ptr,
2825 int *prot, target_ulong *page_size)
2826 {
2827 int code;
2828 uint32_t table;
2829 uint32_t desc;
2830 int type;
2831 int ap;
2832 int domain;
2833 int domain_prot;
2834 hwaddr phys_addr;
2835
2836 /* Pagetable walk. */
2837 /* Lookup l1 descriptor. */
2838 table = get_level1_table_address(env, address);
2839 desc = ldl_phys(table);
2840 type = (desc & 3);
2841 domain = (desc >> 5) & 0x0f;
2842 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2843 if (type == 0) {
2844 /* Section translation fault. */
2845 code = 5;
2846 goto do_fault;
2847 }
2848 if (domain_prot == 0 || domain_prot == 2) {
2849 if (type == 2)
2850 code = 9; /* Section domain fault. */
2851 else
2852 code = 11; /* Page domain fault. */
2853 goto do_fault;
2854 }
2855 if (type == 2) {
2856 /* 1Mb section. */
2857 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2858 ap = (desc >> 10) & 3;
2859 code = 13;
2860 *page_size = 1024 * 1024;
2861 } else {
2862 /* Lookup l2 entry. */
2863 if (type == 1) {
2864 /* Coarse pagetable. */
2865 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2866 } else {
2867 /* Fine pagetable. */
2868 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2869 }
2870 desc = ldl_phys(table);
2871 switch (desc & 3) {
2872 case 0: /* Page translation fault. */
2873 code = 7;
2874 goto do_fault;
2875 case 1: /* 64k page. */
2876 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2877 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2878 *page_size = 0x10000;
2879 break;
2880 case 2: /* 4k page. */
2881 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2882 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2883 *page_size = 0x1000;
2884 break;
2885 case 3: /* 1k page. */
2886 if (type == 1) {
2887 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2888 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2889 } else {
2890 /* Page translation fault. */
2891 code = 7;
2892 goto do_fault;
2893 }
2894 } else {
2895 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2896 }
2897 ap = (desc >> 4) & 3;
2898 *page_size = 0x400;
2899 break;
2900 default:
2901 /* Never happens, but compiler isn't smart enough to tell. */
2902 abort();
2903 }
2904 code = 15;
2905 }
2906 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2907 if (!*prot) {
2908 /* Access permission fault. */
2909 goto do_fault;
2910 }
2911 *prot |= PAGE_EXEC;
2912 *phys_ptr = phys_addr;
2913 return 0;
2914 do_fault:
2915 return code | (domain << 4);
2916 }
2917
2918 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2919 int is_user, hwaddr *phys_ptr,
2920 int *prot, target_ulong *page_size)
2921 {
2922 int code;
2923 uint32_t table;
2924 uint32_t desc;
2925 uint32_t xn;
2926 uint32_t pxn = 0;
2927 int type;
2928 int ap;
2929 int domain = 0;
2930 int domain_prot;
2931 hwaddr phys_addr;
2932
2933 /* Pagetable walk. */
2934 /* Lookup l1 descriptor. */
2935 table = get_level1_table_address(env, address);
2936 desc = ldl_phys(table);
2937 type = (desc & 3);
2938 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2939 /* Section translation fault, or attempt to use the encoding
2940 * which is Reserved on implementations without PXN.
2941 */
2942 code = 5;
2943 goto do_fault;
2944 }
2945 if ((type == 1) || !(desc & (1 << 18))) {
2946 /* Page or Section. */
2947 domain = (desc >> 5) & 0x0f;
2948 }
2949 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2950 if (domain_prot == 0 || domain_prot == 2) {
2951 if (type != 1) {
2952 code = 9; /* Section domain fault. */
2953 } else {
2954 code = 11; /* Page domain fault. */
2955 }
2956 goto do_fault;
2957 }
2958 if (type != 1) {
2959 if (desc & (1 << 18)) {
2960 /* Supersection. */
2961 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2962 *page_size = 0x1000000;
2963 } else {
2964 /* Section. */
2965 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2966 *page_size = 0x100000;
2967 }
2968 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2969 xn = desc & (1 << 4);
2970 pxn = desc & 1;
2971 code = 13;
2972 } else {
2973 if (arm_feature(env, ARM_FEATURE_PXN)) {
2974 pxn = (desc >> 2) & 1;
2975 }
2976 /* Lookup l2 entry. */
2977 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2978 desc = ldl_phys(table);
2979 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2980 switch (desc & 3) {
2981 case 0: /* Page translation fault. */
2982 code = 7;
2983 goto do_fault;
2984 case 1: /* 64k page. */
2985 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2986 xn = desc & (1 << 15);
2987 *page_size = 0x10000;
2988 break;
2989 case 2: case 3: /* 4k page. */
2990 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2991 xn = desc & 1;
2992 *page_size = 0x1000;
2993 break;
2994 default:
2995 /* Never happens, but compiler isn't smart enough to tell. */
2996 abort();
2997 }
2998 code = 15;
2999 }
3000 if (domain_prot == 3) {
3001 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3002 } else {
3003 if (pxn && !is_user) {
3004 xn = 1;
3005 }
3006 if (xn && access_type == 2)
3007 goto do_fault;
3008
3009 /* The simplified model uses AP[0] as an access control bit. */
3010 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
3011 /* Access flag fault. */
3012 code = (code == 15) ? 6 : 3;
3013 goto do_fault;
3014 }
3015 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3016 if (!*prot) {
3017 /* Access permission fault. */
3018 goto do_fault;
3019 }
3020 if (!xn) {
3021 *prot |= PAGE_EXEC;
3022 }
3023 }
3024 *phys_ptr = phys_addr;
3025 return 0;
3026 do_fault:
3027 return code | (domain << 4);
3028 }
3029
3030 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3031 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3032 */
3033 typedef enum {
3034 translation_fault = 1,
3035 access_fault = 2,
3036 permission_fault = 3,
3037 } MMUFaultType;
3038
3039 static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
3040 int access_type, int is_user,
3041 hwaddr *phys_ptr, int *prot,
3042 target_ulong *page_size_ptr)
3043 {
3044 /* Read an LPAE long-descriptor translation table. */
3045 MMUFaultType fault_type = translation_fault;
3046 uint32_t level = 1;
3047 uint32_t epd;
3048 uint32_t tsz;
3049 uint64_t ttbr;
3050 int ttbr_select;
3051 int n;
3052 hwaddr descaddr;
3053 uint32_t tableattrs;
3054 target_ulong page_size;
3055 uint32_t attrs;
3056
3057 /* Determine whether this address is in the region controlled by
3058 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3059 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3060 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3061 */
3062 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
3063 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
3064 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
3065 /* there is a ttbr0 region and we are in it (high bits all zero) */
3066 ttbr_select = 0;
3067 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
3068 /* there is a ttbr1 region and we are in it (high bits all one) */
3069 ttbr_select = 1;
3070 } else if (!t0sz) {
3071 /* ttbr0 region is "everything not in the ttbr1 region" */
3072 ttbr_select = 0;
3073 } else if (!t1sz) {
3074 /* ttbr1 region is "everything not in the ttbr0 region" */
3075 ttbr_select = 1;
3076 } else {
3077 /* in the gap between the two regions, this is a Translation fault */
3078 fault_type = translation_fault;
3079 goto do_fault;
3080 }
3081
3082 /* Note that QEMU ignores shareability and cacheability attributes,
3083 * so we don't need to do anything with the SH, ORGN, IRGN fields
3084 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3085 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3086 * implement any ASID-like capability so we can ignore it (instead
3087 * we will always flush the TLB any time the ASID is changed).
3088 */
3089 if (ttbr_select == 0) {
3090 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
3091 epd = extract32(env->cp15.c2_control, 7, 1);
3092 tsz = t0sz;
3093 } else {
3094 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
3095 epd = extract32(env->cp15.c2_control, 23, 1);
3096 tsz = t1sz;
3097 }
3098
3099 if (epd) {
3100 /* Translation table walk disabled => Translation fault on TLB miss */
3101 goto do_fault;
3102 }
3103
3104 /* If the region is small enough we will skip straight to a 2nd level
3105 * lookup. This affects the number of bits of the address used in
3106 * combination with the TTBR to find the first descriptor. ('n' here
3107 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3108 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3109 */
3110 if (tsz > 1) {
3111 level = 2;
3112 n = 14 - tsz;
3113 } else {
3114 n = 5 - tsz;
3115 }
3116
3117 /* Clear the vaddr bits which aren't part of the within-region address,
3118 * so that we don't have to special case things when calculating the
3119 * first descriptor address.
3120 */
3121 address &= (0xffffffffU >> tsz);
3122
3123 /* Now we can extract the actual base address from the TTBR */
3124 descaddr = extract64(ttbr, 0, 40);
3125 descaddr &= ~((1ULL << n) - 1);
3126
3127 tableattrs = 0;
3128 for (;;) {
3129 uint64_t descriptor;
3130
3131 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3132 descriptor = ldq_phys(descaddr);
3133 if (!(descriptor & 1) ||
3134 (!(descriptor & 2) && (level == 3))) {
3135 /* Invalid, or the Reserved level 3 encoding */
3136 goto do_fault;
3137 }
3138 descaddr = descriptor & 0xfffffff000ULL;
3139
3140 if ((descriptor & 2) && (level < 3)) {
3141 /* Table entry. The top five bits are attributes which may
3142 * propagate down through lower levels of the table (and
3143 * which are all arranged so that 0 means "no effect", so
3144 * we can gather them up by ORing in the bits at each level).
3145 */
3146 tableattrs |= extract64(descriptor, 59, 5);
3147 level++;
3148 continue;
3149 }
3150 /* Block entry at level 1 or 2, or page entry at level 3.
3151 * These are basically the same thing, although the number
3152 * of bits we pull in from the vaddr varies.
3153 */
3154 page_size = (1 << (39 - (9 * level)));
3155 descaddr |= (address & (page_size - 1));
3156 /* Extract attributes from the descriptor and merge with table attrs */
3157 attrs = extract64(descriptor, 2, 10)
3158 | (extract64(descriptor, 52, 12) << 10);
3159 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3160 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3161 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3162 * means "force PL1 access only", which means forcing AP[1] to 0.
3163 */
3164 if (extract32(tableattrs, 2, 1)) {
3165 attrs &= ~(1 << 4);
3166 }
3167 /* Since we're always in the Non-secure state, NSTable is ignored. */
3168 break;
3169 }
3170 /* Here descaddr is the final physical address, and attributes
3171 * are all in attrs.
3172 */
3173 fault_type = access_fault;
3174 if ((attrs & (1 << 8)) == 0) {
3175 /* Access flag */
3176 goto do_fault;
3177 }
3178 fault_type = permission_fault;
3179 if (is_user && !(attrs & (1 << 4))) {
3180 /* Unprivileged access not enabled */
3181 goto do_fault;
3182 }
3183 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3184 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3185 /* XN or PXN */
3186 if (access_type == 2) {
3187 goto do_fault;
3188 }
3189 *prot &= ~PAGE_EXEC;
3190 }
3191 if (attrs & (1 << 5)) {
3192 /* Write access forbidden */
3193 if (access_type == 1) {
3194 goto do_fault;
3195 }
3196 *prot &= ~PAGE_WRITE;
3197 }
3198
3199 *phys_ptr = descaddr;
3200 *page_size_ptr = page_size;
3201 return 0;
3202
3203 do_fault:
3204 /* Long-descriptor format IFSR/DFSR value */
3205 return (1 << 9) | (fault_type << 2) | level;
3206 }
3207
3208 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3209 int access_type, int is_user,
3210 hwaddr *phys_ptr, int *prot)
3211 {
3212 int n;
3213 uint32_t mask;
3214 uint32_t base;
3215
3216 *phys_ptr = address;
3217 for (n = 7; n >= 0; n--) {
3218 base = env->cp15.c6_region[n];
3219 if ((base & 1) == 0)
3220 continue;
3221 mask = 1 << ((base >> 1) & 0x1f);
3222 /* Keep this shift separate from the above to avoid an
3223 (undefined) << 32. */
3224 mask = (mask << 1) - 1;
3225 if (((base ^ address) & ~mask) == 0)
3226 break;
3227 }
3228 if (n < 0)
3229 return 2;
3230
3231 if (access_type == 2) {
3232 mask = env->cp15.c5_insn;
3233 } else {
3234 mask = env->cp15.c5_data;
3235 }
3236 mask = (mask >> (n * 4)) & 0xf;
3237 switch (mask) {
3238 case 0:
3239 return 1;
3240 case 1:
3241 if (is_user)
3242 return 1;
3243 *prot = PAGE_READ | PAGE_WRITE;
3244 break;
3245 case 2:
3246 *prot = PAGE_READ;
3247 if (!is_user)
3248 *prot |= PAGE_WRITE;
3249 break;
3250 case 3:
3251 *prot = PAGE_READ | PAGE_WRITE;
3252 break;
3253 case 5:
3254 if (is_user)
3255 return 1;
3256 *prot = PAGE_READ;
3257 break;
3258 case 6:
3259 *prot = PAGE_READ;
3260 break;
3261 default:
3262 /* Bad permission. */
3263 return 1;
3264 }
3265 *prot |= PAGE_EXEC;
3266 return 0;
3267 }
3268
3269 /* get_phys_addr - get the physical address for this virtual address
3270 *
3271 * Find the physical address corresponding to the given virtual address,
3272 * by doing a translation table walk on MMU based systems or using the
3273 * MPU state on MPU based systems.
3274 *
3275 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3276 * prot and page_size are not filled in, and the return value provides
3277 * information on why the translation aborted, in the format of a
3278 * DFSR/IFSR fault register, with the following caveats:
3279 * * we honour the short vs long DFSR format differences.
3280 * * the WnR bit is never set (the caller must do this).
3281 * * for MPU based systems we don't bother to return a full FSR format
3282 * value.
3283 *
3284 * @env: CPUARMState
3285 * @address: virtual address to get physical address for
3286 * @access_type: 0 for read, 1 for write, 2 for execute
3287 * @is_user: 0 for privileged access, 1 for user
3288 * @phys_ptr: set to the physical address corresponding to the virtual address
3289 * @prot: set to the permissions for the page containing phys_ptr
3290 * @page_size: set to the size of the page containing phys_ptr
3291 */
3292 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
3293 int access_type, int is_user,
3294 hwaddr *phys_ptr, int *prot,
3295 target_ulong *page_size)
3296 {
3297 /* Fast Context Switch Extension. */
3298 if (address < 0x02000000)
3299 address += env->cp15.c13_fcse;
3300
3301 if ((env->cp15.c1_sys & 1) == 0) {
3302 /* MMU/MPU disabled. */
3303 *phys_ptr = address;
3304 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3305 *page_size = TARGET_PAGE_SIZE;
3306 return 0;
3307 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
3308 *page_size = TARGET_PAGE_SIZE;
3309 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3310 prot);
3311 } else if (extended_addresses_enabled(env)) {
3312 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3313 prot, page_size);
3314 } else if (env->cp15.c1_sys & (1 << 23)) {
3315 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3316 prot, page_size);
3317 } else {
3318 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3319 prot, page_size);
3320 }
3321 }
3322
3323 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
3324 int access_type, int mmu_idx)
3325 {
3326 hwaddr phys_addr;
3327 target_ulong page_size;
3328 int prot;
3329 int ret, is_user;
3330
3331 is_user = mmu_idx == MMU_USER_IDX;
3332 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3333 &page_size);
3334 if (ret == 0) {
3335 /* Map a single [sub]page. */
3336 phys_addr &= ~(hwaddr)0x3ff;
3337 address &= ~(uint32_t)0x3ff;
3338 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
3339 return 0;
3340 }
3341
3342 if (access_type == 2) {
3343 env->cp15.c5_insn = ret;
3344 env->cp15.c6_insn = address;
3345 env->exception_index = EXCP_PREFETCH_ABORT;
3346 } else {
3347 env->cp15.c5_data = ret;
3348 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3349 env->cp15.c5_data |= (1 << 11);
3350 env->cp15.c6_data = address;
3351 env->exception_index = EXCP_DATA_ABORT;
3352 }
3353 return 1;
3354 }
3355
3356 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3357 {
3358 ARMCPU *cpu = ARM_CPU(cs);
3359 hwaddr phys_addr;
3360 target_ulong page_size;
3361 int prot;
3362 int ret;
3363
3364 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3365
3366 if (ret != 0) {
3367 return -1;
3368 }
3369
3370 return phys_addr;
3371 }
3372
3373 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3374 {
3375 if ((env->uncached_cpsr & CPSR_M) == mode) {
3376 env->regs[13] = val;
3377 } else {
3378 env->banked_r13[bank_number(mode)] = val;
3379 }
3380 }
3381
3382 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3383 {
3384 if ((env->uncached_cpsr & CPSR_M) == mode) {
3385 return env->regs[13];
3386 } else {
3387 return env->banked_r13[bank_number(mode)];
3388 }
3389 }
3390
3391 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3392 {
3393 switch (reg) {
3394 case 0: /* APSR */
3395 return xpsr_read(env) & 0xf8000000;
3396 case 1: /* IAPSR */
3397 return xpsr_read(env) & 0xf80001ff;
3398 case 2: /* EAPSR */
3399 return xpsr_read(env) & 0xff00fc00;
3400 case 3: /* xPSR */
3401 return xpsr_read(env) & 0xff00fdff;
3402 case 5: /* IPSR */
3403 return xpsr_read(env) & 0x000001ff;
3404 case 6: /* EPSR */
3405 return xpsr_read(env) & 0x0700fc00;
3406 case 7: /* IEPSR */
3407 return xpsr_read(env) & 0x0700edff;
3408 case 8: /* MSP */
3409 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3410 case 9: /* PSP */
3411 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3412 case 16: /* PRIMASK */
3413 return (env->uncached_cpsr & CPSR_I) != 0;
3414 case 17: /* BASEPRI */
3415 case 18: /* BASEPRI_MAX */
3416 return env->v7m.basepri;
3417 case 19: /* FAULTMASK */
3418 return (env->uncached_cpsr & CPSR_F) != 0;
3419 case 20: /* CONTROL */
3420 return env->v7m.control;
3421 default:
3422 /* ??? For debugging only. */
3423 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3424 return 0;
3425 }
3426 }
3427
3428 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3429 {
3430 switch (reg) {
3431 case 0: /* APSR */
3432 xpsr_write(env, val, 0xf8000000);
3433 break;
3434 case 1: /* IAPSR */
3435 xpsr_write(env, val, 0xf8000000);
3436 break;
3437 case 2: /* EAPSR */
3438 xpsr_write(env, val, 0xfe00fc00);
3439 break;
3440 case 3: /* xPSR */
3441 xpsr_write(env, val, 0xfe00fc00);
3442 break;
3443 case 5: /* IPSR */
3444 /* IPSR bits are readonly. */
3445 break;
3446 case 6: /* EPSR */
3447 xpsr_write(env, val, 0x0600fc00);
3448 break;
3449 case 7: /* IEPSR */
3450 xpsr_write(env, val, 0x0600fc00);
3451 break;
3452 case 8: /* MSP */
3453 if (env->v7m.current_sp)
3454 env->v7m.other_sp = val;
3455 else
3456 env->regs[13] = val;
3457 break;
3458 case 9: /* PSP */
3459 if (env->v7m.current_sp)
3460 env->regs[13] = val;
3461 else
3462 env->v7m.other_sp = val;
3463 break;
3464 case 16: /* PRIMASK */
3465 if (val & 1)
3466 env->uncached_cpsr |= CPSR_I;
3467 else
3468 env->uncached_cpsr &= ~CPSR_I;
3469 break;
3470 case 17: /* BASEPRI */
3471 env->v7m.basepri = val & 0xff;
3472 break;
3473 case 18: /* BASEPRI_MAX */
3474 val &= 0xff;
3475 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3476 env->v7m.basepri = val;
3477 break;
3478 case 19: /* FAULTMASK */
3479 if (val & 1)
3480 env->uncached_cpsr |= CPSR_F;
3481 else
3482 env->uncached_cpsr &= ~CPSR_F;
3483 break;
3484 case 20: /* CONTROL */
3485 env->v7m.control = val & 3;
3486 switch_v7m_sp(env, (val & 2) != 0);
3487 break;
3488 default:
3489 /* ??? For debugging only. */
3490 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3491 return;
3492 }
3493 }
3494
3495 #endif
3496
3497 /* Note that signed overflow is undefined in C. The following routines are
3498 careful to use unsigned types where modulo arithmetic is required.
3499 Failure to do so _will_ break on newer gcc. */
3500
3501 /* Signed saturating arithmetic. */
3502
3503 /* Perform 16-bit signed saturating addition. */
3504 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3505 {
3506 uint16_t res;
3507
3508 res = a + b;
3509 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3510 if (a & 0x8000)
3511 res = 0x8000;
3512 else
3513 res = 0x7fff;
3514 }
3515 return res;
3516 }
3517
3518 /* Perform 8-bit signed saturating addition. */
3519 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3520 {
3521 uint8_t res;
3522
3523 res = a + b;
3524 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3525 if (a & 0x80)
3526 res = 0x80;
3527 else
3528 res = 0x7f;
3529 }
3530 return res;
3531 }
3532
3533 /* Perform 16-bit signed saturating subtraction. */
3534 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3535 {
3536 uint16_t res;
3537
3538 res = a - b;
3539 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3540 if (a & 0x8000)
3541 res = 0x8000;
3542 else
3543 res = 0x7fff;
3544 }
3545 return res;
3546 }
3547
3548 /* Perform 8-bit signed saturating subtraction. */
3549 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3550 {
3551 uint8_t res;
3552
3553 res = a - b;
3554 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3555 if (a & 0x80)
3556 res = 0x80;
3557 else
3558 res = 0x7f;
3559 }
3560 return res;
3561 }
3562
3563 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3564 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3565 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3566 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3567 #define PFX q
3568
3569 #include "op_addsub.h"
3570
3571 /* Unsigned saturating arithmetic. */
3572 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
3573 {
3574 uint16_t res;
3575 res = a + b;
3576 if (res < a)
3577 res = 0xffff;
3578 return res;
3579 }
3580
3581 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
3582 {
3583 if (a > b)
3584 return a - b;
3585 else
3586 return 0;
3587 }
3588
3589 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3590 {
3591 uint8_t res;
3592 res = a + b;
3593 if (res < a)
3594 res = 0xff;
3595 return res;
3596 }
3597
3598 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3599 {
3600 if (a > b)
3601 return a - b;
3602 else
3603 return 0;
3604 }
3605
3606 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3607 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3608 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3609 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3610 #define PFX uq
3611
3612 #include "op_addsub.h"
3613
3614 /* Signed modulo arithmetic. */
3615 #define SARITH16(a, b, n, op) do { \
3616 int32_t sum; \
3617 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3618 RESULT(sum, n, 16); \
3619 if (sum >= 0) \
3620 ge |= 3 << (n * 2); \
3621 } while(0)
3622
3623 #define SARITH8(a, b, n, op) do { \
3624 int32_t sum; \
3625 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3626 RESULT(sum, n, 8); \
3627 if (sum >= 0) \
3628 ge |= 1 << n; \
3629 } while(0)
3630
3631
3632 #define ADD16(a, b, n) SARITH16(a, b, n, +)
3633 #define SUB16(a, b, n) SARITH16(a, b, n, -)
3634 #define ADD8(a, b, n) SARITH8(a, b, n, +)
3635 #define SUB8(a, b, n) SARITH8(a, b, n, -)
3636 #define PFX s
3637 #define ARITH_GE
3638
3639 #include "op_addsub.h"
3640
3641 /* Unsigned modulo arithmetic. */
3642 #define ADD16(a, b, n) do { \
3643 uint32_t sum; \
3644 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3645 RESULT(sum, n, 16); \
3646 if ((sum >> 16) == 1) \
3647 ge |= 3 << (n * 2); \
3648 } while(0)
3649
3650 #define ADD8(a, b, n) do { \
3651 uint32_t sum; \
3652 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3653 RESULT(sum, n, 8); \
3654 if ((sum >> 8) == 1) \
3655 ge |= 1 << n; \
3656 } while(0)
3657
3658 #define SUB16(a, b, n) do { \
3659 uint32_t sum; \
3660 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3661 RESULT(sum, n, 16); \
3662 if ((sum >> 16) == 0) \
3663 ge |= 3 << (n * 2); \
3664 } while(0)
3665
3666 #define SUB8(a, b, n) do { \
3667 uint32_t sum; \
3668 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3669 RESULT(sum, n, 8); \
3670 if ((sum >> 8) == 0) \
3671 ge |= 1 << n; \
3672 } while(0)
3673
3674 #define PFX u
3675 #define ARITH_GE
3676
3677 #include "op_addsub.h"
3678
3679 /* Halved signed arithmetic. */
3680 #define ADD16(a, b, n) \
3681 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3682 #define SUB16(a, b, n) \
3683 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3684 #define ADD8(a, b, n) \
3685 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3686 #define SUB8(a, b, n) \
3687 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3688 #define PFX sh
3689
3690 #include "op_addsub.h"
3691
3692 /* Halved unsigned arithmetic. */
3693 #define ADD16(a, b, n) \
3694 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3695 #define SUB16(a, b, n) \
3696 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3697 #define ADD8(a, b, n) \
3698 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3699 #define SUB8(a, b, n) \
3700 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3701 #define PFX uh
3702
3703 #include "op_addsub.h"
3704
3705 static inline uint8_t do_usad(uint8_t a, uint8_t b)
3706 {
3707 if (a > b)
3708 return a - b;
3709 else
3710 return b - a;
3711 }
3712
3713 /* Unsigned sum of absolute byte differences. */
3714 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3715 {
3716 uint32_t sum;
3717 sum = do_usad(a, b);
3718 sum += do_usad(a >> 8, b >> 8);
3719 sum += do_usad(a >> 16, b >>16);
3720 sum += do_usad(a >> 24, b >> 24);
3721 return sum;
3722 }
3723
3724 /* For ARMv6 SEL instruction. */
3725 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3726 {
3727 uint32_t mask;
3728
3729 mask = 0;
3730 if (flags & 1)
3731 mask |= 0xff;
3732 if (flags & 2)
3733 mask |= 0xff00;
3734 if (flags & 4)
3735 mask |= 0xff0000;
3736 if (flags & 8)
3737 mask |= 0xff000000;
3738 return (a & mask) | (b & ~mask);
3739 }
3740
3741 /* VFP support. We follow the convention used for VFP instructions:
3742 Single precision routines have a "s" suffix, double precision a
3743 "d" suffix. */
3744
3745 /* Convert host exception flags to vfp form. */
3746 static inline int vfp_exceptbits_from_host(int host_bits)
3747 {
3748 int target_bits = 0;
3749
3750 if (host_bits & float_flag_invalid)
3751 target_bits |= 1;
3752 if (host_bits & float_flag_divbyzero)
3753 target_bits |= 2;
3754 if (host_bits & float_flag_overflow)
3755 target_bits |= 4;
3756 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
3757 target_bits |= 8;
3758 if (host_bits & float_flag_inexact)
3759 target_bits |= 0x10;
3760 if (host_bits & float_flag_input_denormal)
3761 target_bits |= 0x80;
3762 return target_bits;
3763 }
3764
3765 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
3766 {
3767 int i;
3768 uint32_t fpscr;
3769
3770 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3771 | (env->vfp.vec_len << 16)
3772 | (env->vfp.vec_stride << 20);
3773 i = get_float_exception_flags(&env->vfp.fp_status);
3774 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
3775 fpscr |= vfp_exceptbits_from_host(i);
3776 return fpscr;
3777 }
3778
3779 uint32_t vfp_get_fpscr(CPUARMState *env)
3780 {
3781 return HELPER(vfp_get_fpscr)(env);
3782 }
3783
3784 /* Convert vfp exception flags to target form. */
3785 static inline int vfp_exceptbits_to_host(int target_bits)
3786 {
3787 int host_bits = 0;
3788
3789 if (target_bits & 1)
3790 host_bits |= float_flag_invalid;
3791 if (target_bits & 2)
3792 host_bits |= float_flag_divbyzero;
3793 if (target_bits & 4)
3794 host_bits |= float_flag_overflow;
3795 if (target_bits & 8)
3796 host_bits |= float_flag_underflow;
3797 if (target_bits & 0x10)
3798 host_bits |= float_flag_inexact;
3799 if (target_bits & 0x80)
3800 host_bits |= float_flag_input_denormal;
3801 return host_bits;
3802 }
3803
3804 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
3805 {
3806 int i;
3807 uint32_t changed;
3808
3809 changed = env->vfp.xregs[ARM_VFP_FPSCR];
3810 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3811 env->vfp.vec_len = (val >> 16) & 7;
3812 env->vfp.vec_stride = (val >> 20) & 3;
3813
3814 changed ^= val;
3815 if (changed & (3 << 22)) {
3816 i = (val >> 22) & 3;
3817 switch (i) {
3818 case 0:
3819 i = float_round_nearest_even;
3820 break;
3821 case 1:
3822 i = float_round_up;
3823 break;
3824 case 2:
3825 i = float_round_down;
3826 break;
3827 case 3:
3828 i = float_round_to_zero;
3829 break;
3830 }
3831 set_float_rounding_mode(i, &env->vfp.fp_status);
3832 }
3833 if (changed & (1 << 24)) {
3834 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3835 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3836 }
3837 if (changed & (1 << 25))
3838 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
3839
3840 i = vfp_exceptbits_to_host(val);
3841 set_float_exception_flags(i, &env->vfp.fp_status);
3842 set_float_exception_flags(0, &env->vfp.standard_fp_status);
3843 }
3844
3845 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
3846 {
3847 HELPER(vfp_set_fpscr)(env, val);
3848 }
3849
3850 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3851
3852 #define VFP_BINOP(name) \
3853 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3854 { \
3855 float_status *fpst = fpstp; \
3856 return float32_ ## name(a, b, fpst); \
3857 } \
3858 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3859 { \
3860 float_status *fpst = fpstp; \
3861 return float64_ ## name(a, b, fpst); \
3862 }
3863 VFP_BINOP(add)
3864 VFP_BINOP(sub)
3865 VFP_BINOP(mul)
3866 VFP_BINOP(div)
3867 VFP_BINOP(min)
3868 VFP_BINOP(max)
3869 VFP_BINOP(minnum)
3870 VFP_BINOP(maxnum)
3871 #undef VFP_BINOP
3872
3873 float32 VFP_HELPER(neg, s)(float32 a)
3874 {
3875 return float32_chs(a);
3876 }
3877
3878 float64 VFP_HELPER(neg, d)(float64 a)
3879 {
3880 return float64_chs(a);
3881 }
3882
3883 float32 VFP_HELPER(abs, s)(float32 a)
3884 {
3885 return float32_abs(a);
3886 }
3887
3888 float64 VFP_HELPER(abs, d)(float64 a)
3889 {
3890 return float64_abs(a);
3891 }
3892
3893 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
3894 {
3895 return float32_sqrt(a, &env->vfp.fp_status);
3896 }
3897
3898 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
3899 {
3900 return float64_sqrt(a, &env->vfp.fp_status);
3901 }
3902
3903 /* XXX: check quiet/signaling case */
3904 #define DO_VFP_cmp(p, type) \
3905 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3906 { \
3907 uint32_t flags; \
3908 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3909 case 0: flags = 0x6; break; \
3910 case -1: flags = 0x8; break; \
3911 case 1: flags = 0x2; break; \
3912 default: case 2: flags = 0x3; break; \
3913 } \
3914 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3915 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3916 } \
3917 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3918 { \
3919 uint32_t flags; \
3920 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3921 case 0: flags = 0x6; break; \
3922 case -1: flags = 0x8; break; \
3923 case 1: flags = 0x2; break; \
3924 default: case 2: flags = 0x3; break; \
3925 } \
3926 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3927 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3928 }
3929 DO_VFP_cmp(s, float32)
3930 DO_VFP_cmp(d, float64)
3931 #undef DO_VFP_cmp
3932
3933 /* Integer to float and float to integer conversions */
3934
3935 #define CONV_ITOF(name, fsz, sign) \
3936 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3937 { \
3938 float_status *fpst = fpstp; \
3939 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3940 }
3941
3942 #define CONV_FTOI(name, fsz, sign, round) \
3943 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3944 { \
3945 float_status *fpst = fpstp; \
3946 if (float##fsz##_is_any_nan(x)) { \
3947 float_raise(float_flag_invalid, fpst); \
3948 return 0; \
3949 } \
3950 return float##fsz##_to_##sign##int32##round(x, fpst); \
3951 }
3952
3953 #define FLOAT_CONVS(name, p, fsz, sign) \
3954 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3955 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3956 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3957
3958 FLOAT_CONVS(si, s, 32, )
3959 FLOAT_CONVS(si, d, 64, )
3960 FLOAT_CONVS(ui, s, 32, u)
3961 FLOAT_CONVS(ui, d, 64, u)
3962
3963 #undef CONV_ITOF
3964 #undef CONV_FTOI
3965 #undef FLOAT_CONVS
3966
3967 /* floating point conversion */
3968 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
3969 {
3970 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3971 /* ARM requires that S<->D conversion of any kind of NaN generates
3972 * a quiet NaN by forcing the most significant frac bit to 1.
3973 */
3974 return float64_maybe_silence_nan(r);
3975 }
3976
3977 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
3978 {
3979 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3980 /* ARM requires that S<->D conversion of any kind of NaN generates
3981 * a quiet NaN by forcing the most significant frac bit to 1.
3982 */
3983 return float32_maybe_silence_nan(r);
3984 }
3985
3986 /* VFP3 fixed point conversion. */
3987 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3988 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3989 void *fpstp) \
3990 { \
3991 float_status *fpst = fpstp; \
3992 float##fsz tmp; \
3993 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3994 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3995 } \
3996 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3997 void *fpstp) \
3998 { \
3999 float_status *fpst = fpstp; \
4000 float##fsz tmp; \
4001 if (float##fsz##_is_any_nan(x)) { \
4002 float_raise(float_flag_invalid, fpst); \
4003 return 0; \
4004 } \
4005 tmp = float##fsz##_scalbn(x, shift, fpst); \
4006 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
4007 }
4008
4009 VFP_CONV_FIX(sh, d, 64, int16, )
4010 VFP_CONV_FIX(sl, d, 64, int32, )
4011 VFP_CONV_FIX(uh, d, 64, uint16, u)
4012 VFP_CONV_FIX(ul, d, 64, uint32, u)
4013 VFP_CONV_FIX(sh, s, 32, int16, )
4014 VFP_CONV_FIX(sl, s, 32, int32, )
4015 VFP_CONV_FIX(uh, s, 32, uint16, u)
4016 VFP_CONV_FIX(ul, s, 32, uint32, u)
4017 #undef VFP_CONV_FIX
4018
4019 /* Half precision conversions. */
4020 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4021 {
4022 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4023 float32 r = float16_to_float32(make_float16(a), ieee, s);
4024 if (ieee) {
4025 return float32_maybe_silence_nan(r);
4026 }
4027 return r;
4028 }
4029
4030 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4031 {
4032 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4033 float16 r = float32_to_float16(a, ieee, s);
4034 if (ieee) {
4035 r = float16_maybe_silence_nan(r);
4036 }
4037 return float16_val(r);
4038 }
4039
4040 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4041 {
4042 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4043 }
4044
4045 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4046 {
4047 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4048 }
4049
4050 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4051 {
4052 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4053 }
4054
4055 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4056 {
4057 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4058 }
4059
4060 #define float32_two make_float32(0x40000000)
4061 #define float32_three make_float32(0x40400000)
4062 #define float32_one_point_five make_float32(0x3fc00000)
4063
4064 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4065 {
4066 float_status *s = &env->vfp.standard_fp_status;
4067 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4068 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4069 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4070 float_raise(float_flag_input_denormal, s);
4071 }
4072 return float32_two;
4073 }
4074 return float32_sub(float32_two, float32_mul(a, b, s), s);
4075 }
4076
4077 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4078 {
4079 float_status *s = &env->vfp.standard_fp_status;
4080 float32 product;
4081 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4082 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4083 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4084 float_raise(float_flag_input_denormal, s);
4085 }
4086 return float32_one_point_five;
4087 }
4088 product = float32_mul(a, b, s);
4089 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4090 }
4091
4092 /* NEON helpers. */
4093
4094 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4095 * int->float conversions at run-time. */
4096 #define float64_256 make_float64(0x4070000000000000LL)
4097 #define float64_512 make_float64(0x4080000000000000LL)
4098
4099 /* The algorithm that must be used to calculate the estimate
4100 * is specified by the ARM ARM.
4101 */
4102 static float64 recip_estimate(float64 a, CPUARMState *env)
4103 {
4104 /* These calculations mustn't set any fp exception flags,
4105 * so we use a local copy of the fp_status.
4106 */
4107 float_status dummy_status = env->vfp.standard_fp_status;
4108 float_status *s = &dummy_status;
4109 /* q = (int)(a * 512.0) */
4110 float64 q = float64_mul(float64_512, a, s);
4111 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4112
4113 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4114 q = int64_to_float64(q_int, s);
4115 q = float64_add(q, float64_half, s);
4116 q = float64_div(q, float64_512, s);
4117 q = float64_div(float64_one, q, s);
4118
4119 /* s = (int)(256.0 * r + 0.5) */
4120 q = float64_mul(q, float64_256, s);
4121 q = float64_add(q, float64_half, s);
4122 q_int = float64_to_int64_round_to_zero(q, s);
4123
4124 /* return (double)s / 256.0 */
4125 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4126 }
4127
4128 float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4129 {
4130 float_status *s = &env->vfp.standard_fp_status;
4131 float64 f64;
4132 uint32_t val32 = float32_val(a);
4133
4134 int result_exp;
4135 int a_exp = (val32 & 0x7f800000) >> 23;
4136 int sign = val32 & 0x80000000;
4137
4138 if (float32_is_any_nan(a)) {
4139 if (float32_is_signaling_nan(a)) {
4140 float_raise(float_flag_invalid, s);
4141 }
4142 return float32_default_nan;
4143 } else if (float32_is_infinity(a)) {
4144 return float32_set_sign(float32_zero, float32_is_neg(a));
4145 } else if (float32_is_zero_or_denormal(a)) {
4146 if (!float32_is_zero(a)) {
4147 float_raise(float_flag_input_denormal, s);
4148 }
4149 float_raise(float_flag_divbyzero, s);
4150 return float32_set_sign(float32_infinity, float32_is_neg(a));
4151 } else if (a_exp >= 253) {
4152 float_raise(float_flag_underflow, s);
4153 return float32_set_sign(float32_zero, float32_is_neg(a));
4154 }
4155
4156 f64 = make_float64((0x3feULL << 52)
4157 | ((int64_t)(val32 & 0x7fffff) << 29));
4158
4159 result_exp = 253 - a_exp;
4160
4161 f64 = recip_estimate(f64, env);
4162
4163 val32 = sign
4164 | ((result_exp & 0xff) << 23)
4165 | ((float64_val(f64) >> 29) & 0x7fffff);
4166 return make_float32(val32);
4167 }
4168
4169 /* The algorithm that must be used to calculate the estimate
4170 * is specified by the ARM ARM.
4171 */
4172 static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
4173 {
4174 /* These calculations mustn't set any fp exception flags,
4175 * so we use a local copy of the fp_status.
4176 */
4177 float_status dummy_status = env->vfp.standard_fp_status;
4178 float_status *s = &dummy_status;
4179 float64 q;
4180 int64_t q_int;
4181
4182 if (float64_lt(a, float64_half, s)) {
4183 /* range 0.25 <= a < 0.5 */
4184
4185 /* a in units of 1/512 rounded down */
4186 /* q0 = (int)(a * 512.0); */
4187 q = float64_mul(float64_512, a, s);
4188 q_int = float64_to_int64_round_to_zero(q, s);
4189
4190 /* reciprocal root r */
4191 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4192 q = int64_to_float64(q_int, s);
4193 q = float64_add(q, float64_half, s);
4194 q = float64_div(q, float64_512, s);
4195 q = float64_sqrt(q, s);
4196 q = float64_div(float64_one, q, s);
4197 } else {
4198 /* range 0.5 <= a < 1.0 */
4199
4200 /* a in units of 1/256 rounded down */
4201 /* q1 = (int)(a * 256.0); */
4202 q = float64_mul(float64_256, a, s);
4203 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4204
4205 /* reciprocal root r */
4206 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4207 q = int64_to_float64(q_int, s);
4208 q = float64_add(q, float64_half, s);
4209 q = float64_div(q, float64_256, s);
4210 q = float64_sqrt(q, s);
4211 q = float64_div(float64_one, q, s);
4212 }
4213 /* r in units of 1/256 rounded to nearest */
4214 /* s = (int)(256.0 * r + 0.5); */
4215
4216 q = float64_mul(q, float64_256,s );
4217 q = float64_add(q, float64_half, s);
4218 q_int = float64_to_int64_round_to_zero(q, s);
4219
4220 /* return (double)s / 256.0;*/
4221 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4222 }
4223
4224 float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4225 {
4226 float_status *s = &env->vfp.standard_fp_status;
4227 int result_exp;
4228 float64 f64;
4229 uint32_t val;
4230 uint64_t val64;
4231
4232 val = float32_val(a);
4233
4234 if (float32_is_any_nan(a)) {
4235 if (float32_is_signaling_nan(a)) {
4236 float_raise(float_flag_invalid, s);
4237 }
4238 return float32_default_nan;
4239 } else if (float32_is_zero_or_denormal(a)) {
4240 if (!float32_is_zero(a)) {
4241 float_raise(float_flag_input_denormal, s);
4242 }
4243 float_raise(float_flag_divbyzero, s);
4244 return float32_set_sign(float32_infinity, float32_is_neg(a));
4245 } else if (float32_is_neg(a)) {
4246 float_raise(float_flag_invalid, s);
4247 return float32_default_nan;
4248 } else if (float32_is_infinity(a)) {
4249 return float32_zero;
4250 }
4251
4252 /* Normalize to a double-precision value between 0.25 and 1.0,
4253 * preserving the parity of the exponent. */
4254 if ((val & 0x800000) == 0) {
4255 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4256 | (0x3feULL << 52)
4257 | ((uint64_t)(val & 0x7fffff) << 29));
4258 } else {
4259 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4260 | (0x3fdULL << 52)
4261 | ((uint64_t)(val & 0x7fffff) << 29));
4262 }
4263
4264 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
4265
4266 f64 = recip_sqrt_estimate(f64, env);
4267
4268 val64 = float64_val(f64);
4269
4270 val = ((result_exp & 0xff) << 23)
4271 | ((val64 >> 29) & 0x7fffff);
4272 return make_float32(val);
4273 }
4274
4275 uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4276 {
4277 float64 f64;
4278
4279 if ((a & 0x80000000) == 0) {
4280 return 0xffffffff;
4281 }
4282
4283 f64 = make_float64((0x3feULL << 52)
4284 | ((int64_t)(a & 0x7fffffff) << 21));
4285
4286 f64 = recip_estimate (f64, env);
4287
4288 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4289 }
4290
4291 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4292 {
4293 float64 f64;
4294
4295 if ((a & 0xc0000000) == 0) {
4296 return 0xffffffff;
4297 }
4298
4299 if (a & 0x80000000) {
4300 f64 = make_float64((0x3feULL << 52)
4301 | ((uint64_t)(a & 0x7fffffff) << 21));
4302 } else { /* bits 31-30 == '01' */
4303 f64 = make_float64((0x3fdULL << 52)
4304 | ((uint64_t)(a & 0x3fffffff) << 22));
4305 }
4306
4307 f64 = recip_sqrt_estimate(f64, env);
4308
4309 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4310 }
4311
4312 /* VFPv4 fused multiply-accumulate */
4313 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4314 {
4315 float_status *fpst = fpstp;
4316 return float32_muladd(a, b, c, 0, fpst);
4317 }
4318
4319 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4320 {
4321 float_status *fpst = fpstp;
4322 return float64_muladd(a, b, c, 0, fpst);
4323 }
QEmu