target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 /*****************************************************************************/
  27 /* Exceptions processing helpers */
  28
  29 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  30                                 int error_code)
  31 {
  32     do_raise_exception_err(env, exception, error_code, 0);
  33 }
  34
  35 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  36 {
  37     do_raise_exception(env, exception, GETPC());
  38 }
  39
  40 void helper_raise_exception_debug(CPUMIPSState *env)
  41 {
  42     do_raise_exception(env, EXCP_DEBUG, 0);
  43 }
  44
  45 static void raise_exception(CPUMIPSState *env, uint32_t exception)
  46 {
  47     do_raise_exception(env, exception, 0);
  48 }
  49
  50 #if defined(CONFIG_USER_ONLY)
  51 #define HELPER_LD(name, insn, type)                                     \
  52 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  53                              int mem_idx, uintptr_t retaddr)            \
  54 {                                                                       \
  55     return (type) cpu_##insn##_data_ra(env, addr, retaddr);             \
  56 }
  57 #else
  58 #define HELPER_LD(name, insn, type)                                     \
  59 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  60                              int mem_idx, uintptr_t retaddr)            \
  61 {                                                                       \
  62     switch (mem_idx)                                                    \
  63     {                                                                   \
  64     case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr);   \
  65     case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr);    \
  66     default:                                                            \
  67     case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr);     \
  68     }                                                                   \
  69 }
  70 #endif
  71 HELPER_LD(lw, ldl, int32_t)
  72 #if defined(TARGET_MIPS64)
  73 HELPER_LD(ld, ldq, int64_t)
  74 #endif
  75 #undef HELPER_LD
  76
  77 #if defined(CONFIG_USER_ONLY)
  78 #define HELPER_ST(name, insn, type)                                     \
  79 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  80                              type val, int mem_idx, uintptr_t retaddr)  \
  81 {                                                                       \
  82     cpu_##insn##_data_ra(env, addr, val, retaddr);                      \
  83 }
  84 #else
  85 #define HELPER_ST(name, insn, type)                                     \
  86 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  87                              type val, int mem_idx, uintptr_t retaddr)  \
  88 {                                                                       \
  89     switch (mem_idx)                                                    \
  90     {                                                                   \
  91     case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break;     \
  92     case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break;      \
  93     default:                                                            \
  94     case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break;       \
  95     }                                                                   \
  96 }
  97 #endif
  98 HELPER_ST(sb, stb, uint8_t)
  99 HELPER_ST(sw, stl, uint32_t)
 100 #if defined(TARGET_MIPS64)
 101 HELPER_ST(sd, stq, uint64_t)
 102 #endif
 103 #undef HELPER_ST
 104
 105 target_ulong helper_clo (target_ulong arg1)
 106 {
 107     return clo32(arg1);
 108 }
 109
 110 target_ulong helper_clz (target_ulong arg1)
 111 {
 112     return clz32(arg1);
 113 }
 114
 115 #if defined(TARGET_MIPS64)
 116 target_ulong helper_dclo (target_ulong arg1)
 117 {
 118     return clo64(arg1);
 119 }
 120
 121 target_ulong helper_dclz (target_ulong arg1)
 122 {
 123     return clz64(arg1);
 124 }
 125 #endif /* TARGET_MIPS64 */
 126
 127 /* 64 bits arithmetic for 32 bits hosts */
 128 static inline uint64_t get_HILO(CPUMIPSState *env)
 129 {
 130     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 131 }
 132
 133 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 134 {
 135     target_ulong tmp;
 136     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 137     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 138     return tmp;
 139 }
 140
 141 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 142 {
 143     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 144     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 145     return tmp;
 146 }
 147
 148 /* Multiplication variants of the vr54xx. */
 149 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 150                          target_ulong arg2)
 151 {
 152     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 153                                  (int64_t)(int32_t)arg2));
 154 }
 155
 156 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 157                           target_ulong arg2)
 158 {
 159     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 160                        (uint64_t)(uint32_t)arg2);
 161 }
 162
 163 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 164                          target_ulong arg2)
 165 {
 166     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 167                        (int64_t)(int32_t)arg2);
 168 }
 169
 170 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 171                            target_ulong arg2)
 172 {
 173     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 174                        (int64_t)(int32_t)arg2);
 175 }
 176
 177 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 178                           target_ulong arg2)
 179 {
 180     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 181                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 182 }
 183
 184 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 185                             target_ulong arg2)
 186 {
 187     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 188                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 189 }
 190
 191 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 192                          target_ulong arg2)
 193 {
 194     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 195                        (int64_t)(int32_t)arg2);
 196 }
 197
 198 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 199                            target_ulong arg2)
 200 {
 201     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 202                        (int64_t)(int32_t)arg2);
 203 }
 204
 205 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 206                           target_ulong arg2)
 207 {
 208     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 209                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 210 }
 211
 212 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 213                             target_ulong arg2)
 214 {
 215     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 216                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 217 }
 218
 219 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 220                           target_ulong arg2)
 221 {
 222     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 223 }
 224
 225 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 226                            target_ulong arg2)
 227 {
 228     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 229                        (uint64_t)(uint32_t)arg2);
 230 }
 231
 232 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 233                            target_ulong arg2)
 234 {
 235     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 236                        (int64_t)(int32_t)arg2);
 237 }
 238
 239 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 240                             target_ulong arg2)
 241 {
 242     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 243                        (uint64_t)(uint32_t)arg2);
 244 }
 245
 246 static inline target_ulong bitswap(target_ulong v)
 247 {
 248     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 249               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 250     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 251               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 252     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 253               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 254     return v;
 255 }
 256
 257 #ifdef TARGET_MIPS64
 258 target_ulong helper_dbitswap(target_ulong rt)
 259 {
 260     return bitswap(rt);
 261 }
 262 #endif
 263
 264 target_ulong helper_bitswap(target_ulong rt)
 265 {
 266     return (int32_t)bitswap(rt);
 267 }
 268
 269 #ifndef CONFIG_USER_ONLY
 270
 271 static inline hwaddr do_translate_address(CPUMIPSState *env,
 272                                                       target_ulong address,
 273                                                       int rw, uintptr_t retaddr)
 274 {
 275     hwaddr lladdr;
 276     CPUState *cs = CPU(mips_env_get_cpu(env));
 277
 278     lladdr = cpu_mips_translate_address(env, address, rw);
 279
 280     if (lladdr == -1LL) {
 281         cpu_loop_exit_restore(cs, retaddr);
 282     } else {
 283         return lladdr;
 284     }
 285 }
 286
 287 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 288 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 289 {                                                                             \
 290     if (arg & almask) {                                                       \
 291         env->CP0_BadVAddr = arg;                                              \
 292         do_raise_exception(env, EXCP_AdEL, GETPC());                          \
 293     }                                                                         \
 294     env->lladdr = do_translate_address(env, arg, 0, GETPC());                 \
 295     env->llval = do_##insn(env, arg, mem_idx, GETPC());                       \
 296     return env->llval;                                                        \
 297 }
 298 HELPER_LD_ATOMIC(ll, lw, 0x3)
 299 #ifdef TARGET_MIPS64
 300 HELPER_LD_ATOMIC(lld, ld, 0x7)
 301 #endif
 302 #undef HELPER_LD_ATOMIC
 303
 304 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 305 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 306                            target_ulong arg2, int mem_idx)                    \
 307 {                                                                             \
 308     target_long tmp;                                                          \
 309                                                                               \
 310     if (arg2 & almask) {                                                      \
 311         env->CP0_BadVAddr = arg2;                                             \
 312         do_raise_exception(env, EXCP_AdES, GETPC());                          \
 313     }                                                                         \
 314     if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) {         \
 315         tmp = do_##ld_insn(env, arg2, mem_idx, GETPC());                      \
 316         if (tmp == env->llval) {                                              \
 317             do_##st_insn(env, arg2, arg1, mem_idx, GETPC());                  \
 318             return 1;                                                         \
 319         }                                                                     \
 320     }                                                                         \
 321     return 0;                                                                 \
 322 }
 323 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 324 #ifdef TARGET_MIPS64
 325 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 326 #endif
 327 #undef HELPER_ST_ATOMIC
 328 #endif
 329
 330 #ifdef TARGET_WORDS_BIGENDIAN
 331 #define GET_LMASK(v) ((v) & 3)
 332 #define GET_OFFSET(addr, offset) (addr + (offset))
 333 #else
 334 #define GET_LMASK(v) (((v) & 3) ^ 3)
 335 #define GET_OFFSET(addr, offset) (addr - (offset))
 336 #endif
 337
 338 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 339                 int mem_idx)
 340 {
 341     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
 342
 343     if (GET_LMASK(arg2) <= 2) {
 344         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
 345               GETPC());
 346     }
 347
 348     if (GET_LMASK(arg2) <= 1) {
 349         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
 350               GETPC());
 351     }
 352
 353     if (GET_LMASK(arg2) == 0) {
 354         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
 355               GETPC());
 356     }
 357 }
 358
 359 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 360                 int mem_idx)
 361 {
 362     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 363
 364     if (GET_LMASK(arg2) >= 1) {
 365         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 366               GETPC());
 367     }
 368
 369     if (GET_LMASK(arg2) >= 2) {
 370         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 371               GETPC());
 372     }
 373
 374     if (GET_LMASK(arg2) == 3) {
 375         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 376               GETPC());
 377     }
 378 }
 379
 380 #if defined(TARGET_MIPS64)
 381 /* "half" load and stores.  We must do the memory access inline,
 382    or fault handling won't work.  */
 383
 384 #ifdef TARGET_WORDS_BIGENDIAN
 385 #define GET_LMASK64(v) ((v) & 7)
 386 #else
 387 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 388 #endif
 389
 390 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 391                 int mem_idx)
 392 {
 393     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
 394
 395     if (GET_LMASK64(arg2) <= 6) {
 396         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
 397               GETPC());
 398     }
 399
 400     if (GET_LMASK64(arg2) <= 5) {
 401         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
 402               GETPC());
 403     }
 404
 405     if (GET_LMASK64(arg2) <= 4) {
 406         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
 407               GETPC());
 408     }
 409
 410     if (GET_LMASK64(arg2) <= 3) {
 411         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
 412               GETPC());
 413     }
 414
 415     if (GET_LMASK64(arg2) <= 2) {
 416         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
 417               GETPC());
 418     }
 419
 420     if (GET_LMASK64(arg2) <= 1) {
 421         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
 422               GETPC());
 423     }
 424
 425     if (GET_LMASK64(arg2) <= 0) {
 426         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
 427               GETPC());
 428     }
 429 }
 430
 431 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 432                 int mem_idx)
 433 {
 434     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 435
 436     if (GET_LMASK64(arg2) >= 1) {
 437         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 438               GETPC());
 439     }
 440
 441     if (GET_LMASK64(arg2) >= 2) {
 442         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 443               GETPC());
 444     }
 445
 446     if (GET_LMASK64(arg2) >= 3) {
 447         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 448               GETPC());
 449     }
 450
 451     if (GET_LMASK64(arg2) >= 4) {
 452         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
 453               GETPC());
 454     }
 455
 456     if (GET_LMASK64(arg2) >= 5) {
 457         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
 458               GETPC());
 459     }
 460
 461     if (GET_LMASK64(arg2) >= 6) {
 462         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
 463               GETPC());
 464     }
 465
 466     if (GET_LMASK64(arg2) == 7) {
 467         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
 468               GETPC());
 469     }
 470 }
 471 #endif /* TARGET_MIPS64 */
 472
 473 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 474
 475 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 476                 uint32_t mem_idx)
 477 {
 478     target_ulong base_reglist = reglist & 0xf;
 479     target_ulong do_r31 = reglist & 0x10;
 480
 481     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 482         target_ulong i;
 483
 484         for (i = 0; i < base_reglist; i++) {
 485             env->active_tc.gpr[multiple_regs[i]] =
 486                 (target_long)do_lw(env, addr, mem_idx, GETPC());
 487             addr += 4;
 488         }
 489     }
 490
 491     if (do_r31) {
 492         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
 493                                                     GETPC());
 494     }
 495 }
 496
 497 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 498                 uint32_t mem_idx)
 499 {
 500     target_ulong base_reglist = reglist & 0xf;
 501     target_ulong do_r31 = reglist & 0x10;
 502
 503     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 504         target_ulong i;
 505
 506         for (i = 0; i < base_reglist; i++) {
 507             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 508                   GETPC());
 509             addr += 4;
 510         }
 511     }
 512
 513     if (do_r31) {
 514         do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 515     }
 516 }
 517
 518 #if defined(TARGET_MIPS64)
 519 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 520                 uint32_t mem_idx)
 521 {
 522     target_ulong base_reglist = reglist & 0xf;
 523     target_ulong do_r31 = reglist & 0x10;
 524
 525     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 526         target_ulong i;
 527
 528         for (i = 0; i < base_reglist; i++) {
 529             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
 530                                                          GETPC());
 531             addr += 8;
 532         }
 533     }
 534
 535     if (do_r31) {
 536         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
 537     }
 538 }
 539
 540 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 541                 uint32_t mem_idx)
 542 {
 543     target_ulong base_reglist = reglist & 0xf;
 544     target_ulong do_r31 = reglist & 0x10;
 545
 546     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 547         target_ulong i;
 548
 549         for (i = 0; i < base_reglist; i++) {
 550             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 551                   GETPC());
 552             addr += 8;
 553         }
 554     }
 555
 556     if (do_r31) {
 557         do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 558     }
 559 }
 560 #endif
 561
 562 #ifndef CONFIG_USER_ONLY
 563 /* SMP helpers.  */
 564 static bool mips_vpe_is_wfi(MIPSCPU *c)
 565 {
 566     CPUState *cpu = CPU(c);
 567     CPUMIPSState *env = &c->env;
 568
 569     /* If the VPE is halted but otherwise active, it means it's waiting for
 570        an interrupt.  */
 571     return cpu->halted && mips_vpe_active(env);
 572 }
 573
 574 static bool mips_vp_is_wfi(MIPSCPU *c)
 575 {
 576     CPUState *cpu = CPU(c);
 577     CPUMIPSState *env = &c->env;
 578
 579     return cpu->halted && mips_vp_active(env);
 580 }
 581
 582 static inline void mips_vpe_wake(MIPSCPU *c)
 583 {
 584     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 585        because there might be other conditions that state that c should
 586        be sleeping.  */
 587     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 588 }
 589
 590 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 591 {
 592     CPUState *cs = CPU(cpu);
 593
 594     /* The VPE was shut off, really go to bed.
 595        Reset any old _WAKE requests.  */
 596     cs->halted = 1;
 597     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 598 }
 599
 600 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 601 {
 602     CPUMIPSState *c = &cpu->env;
 603
 604     /* FIXME: TC reschedule.  */
 605     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 606         mips_vpe_wake(cpu);
 607     }
 608 }
 609
 610 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 611 {
 612     CPUMIPSState *c = &cpu->env;
 613
 614     /* FIXME: TC reschedule.  */
 615     if (!mips_vpe_active(c)) {
 616         mips_vpe_sleep(cpu);
 617     }
 618 }
 619
 620 /**
 621  * mips_cpu_map_tc:
 622  * @env: CPU from which mapping is performed.
 623  * @tc: Should point to an int with the value of the global TC index.
 624  *
 625  * This function will transform @tc into a local index within the
 626  * returned #CPUMIPSState.
 627  */
 628 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 629           which depends on runtime setup. Can probably be fixed by
 630           walking the list of CPUMIPSStates.  */
 631 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 632 {
 633     MIPSCPU *cpu;
 634     CPUState *cs;
 635     CPUState *other_cs;
 636     int vpe_idx;
 637     int tc_idx = *tc;
 638
 639     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 640         /* Not allowed to address other CPUs.  */
 641         *tc = env->current_tc;
 642         return env;
 643     }
 644
 645     cs = CPU(mips_env_get_cpu(env));
 646     vpe_idx = tc_idx / cs->nr_threads;
 647     *tc = tc_idx % cs->nr_threads;
 648     other_cs = qemu_get_cpu(vpe_idx);
 649     if (other_cs == NULL) {
 650         return env;
 651     }
 652     cpu = MIPS_CPU(other_cs);
 653     return &cpu->env;
 654 }
 655
 656 /* The per VPE CP0_Status register shares some fields with the per TC
 657    CP0_TCStatus registers. These fields are wired to the same registers,
 658    so changes to either of them should be reflected on both registers.
 659
 660    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 661
 662    These helper call synchronizes the regs for a given cpu.  */
 663
 664 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 665 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 666                                      int tc);  */
 667
 668 /* Called for updates to CP0_TCStatus.  */
 669 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 670                              target_ulong v)
 671 {
 672     uint32_t status;
 673     uint32_t tcu, tmx, tasid, tksu;
 674     uint32_t mask = ((1U << CP0St_CU3)
 675                        | (1 << CP0St_CU2)
 676                        | (1 << CP0St_CU1)
 677                        | (1 << CP0St_CU0)
 678                        | (1 << CP0St_MX)
 679                        | (3 << CP0St_KSU));
 680
 681     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 682     tmx = (v >> CP0TCSt_TMX) & 0x1;
 683     tasid = v & 0xff;
 684     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 685
 686     status = tcu << CP0St_CU0;
 687     status |= tmx << CP0St_MX;
 688     status |= tksu << CP0St_KSU;
 689
 690     cpu->CP0_Status &= ~mask;
 691     cpu->CP0_Status |= status;
 692
 693     /* Sync the TASID with EntryHi.  */
 694     cpu->CP0_EntryHi &= ~0xff;
 695     cpu->CP0_EntryHi |= tasid;
 696
 697     compute_hflags(cpu);
 698 }
 699
 700 /* Called for updates to CP0_EntryHi.  */
 701 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 702 {
 703     int32_t *tcst;
 704     uint32_t asid, v = cpu->CP0_EntryHi;
 705
 706     asid = v & 0xff;
 707
 708     if (tc == cpu->current_tc) {
 709         tcst = &cpu->active_tc.CP0_TCStatus;
 710     } else {
 711         tcst = &cpu->tcs[tc].CP0_TCStatus;
 712     }
 713
 714     *tcst &= ~0xff;
 715     *tcst |= asid;
 716 }
 717
 718 /* CP0 helpers */
 719 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 720 {
 721     return env->mvp->CP0_MVPControl;
 722 }
 723
 724 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 725 {
 726     return env->mvp->CP0_MVPConf0;
 727 }
 728
 729 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 730 {
 731     return env->mvp->CP0_MVPConf1;
 732 }
 733
 734 target_ulong helper_mfc0_random(CPUMIPSState *env)
 735 {
 736     return (int32_t)cpu_mips_get_random(env);
 737 }
 738
 739 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 740 {
 741     return env->active_tc.CP0_TCStatus;
 742 }
 743
 744 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 745 {
 746     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 747     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 748
 749     if (other_tc == other->current_tc)
 750         return other->active_tc.CP0_TCStatus;
 751     else
 752         return other->tcs[other_tc].CP0_TCStatus;
 753 }
 754
 755 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 756 {
 757     return env->active_tc.CP0_TCBind;
 758 }
 759
 760 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 761 {
 762     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 763     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 764
 765     if (other_tc == other->current_tc)
 766         return other->active_tc.CP0_TCBind;
 767     else
 768         return other->tcs[other_tc].CP0_TCBind;
 769 }
 770
 771 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 772 {
 773     return env->active_tc.PC;
 774 }
 775
 776 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 777 {
 778     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 779     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 780
 781     if (other_tc == other->current_tc)
 782         return other->active_tc.PC;
 783     else
 784         return other->tcs[other_tc].PC;
 785 }
 786
 787 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 788 {
 789     return env->active_tc.CP0_TCHalt;
 790 }
 791
 792 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 793 {
 794     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 795     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 796
 797     if (other_tc == other->current_tc)
 798         return other->active_tc.CP0_TCHalt;
 799     else
 800         return other->tcs[other_tc].CP0_TCHalt;
 801 }
 802
 803 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 804 {
 805     return env->active_tc.CP0_TCContext;
 806 }
 807
 808 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 809 {
 810     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 811     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 812
 813     if (other_tc == other->current_tc)
 814         return other->active_tc.CP0_TCContext;
 815     else
 816         return other->tcs[other_tc].CP0_TCContext;
 817 }
 818
 819 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 820 {
 821     return env->active_tc.CP0_TCSchedule;
 822 }
 823
 824 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 825 {
 826     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 827     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 828
 829     if (other_tc == other->current_tc)
 830         return other->active_tc.CP0_TCSchedule;
 831     else
 832         return other->tcs[other_tc].CP0_TCSchedule;
 833 }
 834
 835 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 836 {
 837     return env->active_tc.CP0_TCScheFBack;
 838 }
 839
 840 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 841 {
 842     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 843     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 844
 845     if (other_tc == other->current_tc)
 846         return other->active_tc.CP0_TCScheFBack;
 847     else
 848         return other->tcs[other_tc].CP0_TCScheFBack;
 849 }
 850
 851 target_ulong helper_mfc0_count(CPUMIPSState *env)
 852 {
 853     return (int32_t)cpu_mips_get_count(env);
 854 }
 855
 856 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 857 {
 858     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 859     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 860
 861     return other->CP0_EntryHi;
 862 }
 863
 864 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 865 {
 866     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 867     int32_t tccause;
 868     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 869
 870     if (other_tc == other->current_tc) {
 871         tccause = other->CP0_Cause;
 872     } else {
 873         tccause = other->CP0_Cause;
 874     }
 875
 876     return tccause;
 877 }
 878
 879 target_ulong helper_mftc0_status(CPUMIPSState *env)
 880 {
 881     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 882     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 883
 884     return other->CP0_Status;
 885 }
 886
 887 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 888 {
 889     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 890 }
 891
 892 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 893 {
 894     return (int32_t)env->CP0_WatchLo[sel];
 895 }
 896
 897 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 898 {
 899     return env->CP0_WatchHi[sel];
 900 }
 901
 902 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 903 {
 904     target_ulong t0 = env->CP0_Debug;
 905     if (env->hflags & MIPS_HFLAG_DM)
 906         t0 |= 1 << CP0DB_DM;
 907
 908     return t0;
 909 }
 910
 911 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 912 {
 913     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 914     int32_t tcstatus;
 915     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 916
 917     if (other_tc == other->current_tc)
 918         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 919     else
 920         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 921
 922     /* XXX: Might be wrong, check with EJTAG spec. */
 923     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 924             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 925 }
 926
 927 #if defined(TARGET_MIPS64)
 928 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 929 {
 930     return env->active_tc.PC;
 931 }
 932
 933 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 934 {
 935     return env->active_tc.CP0_TCHalt;
 936 }
 937
 938 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 939 {
 940     return env->active_tc.CP0_TCContext;
 941 }
 942
 943 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 944 {
 945     return env->active_tc.CP0_TCSchedule;
 946 }
 947
 948 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 949 {
 950     return env->active_tc.CP0_TCScheFBack;
 951 }
 952
 953 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 954 {
 955     return env->lladdr >> env->CP0_LLAddr_shift;
 956 }
 957
 958 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 959 {
 960     return env->CP0_WatchLo[sel];
 961 }
 962 #endif /* TARGET_MIPS64 */
 963
 964 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 965 {
 966     uint32_t index_p = env->CP0_Index & 0x80000000;
 967     uint32_t tlb_index = arg1 & 0x7fffffff;
 968     if (tlb_index < env->tlb->nb_tlb) {
 969         if (env->insn_flags & ISA_MIPS32R6) {
 970             index_p |= arg1 & 0x80000000;
 971         }
 972         env->CP0_Index = index_p | tlb_index;
 973     }
 974 }
 975
 976 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 977 {
 978     uint32_t mask = 0;
 979     uint32_t newval;
 980
 981     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 982         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 983                 (1 << CP0MVPCo_EVP);
 984     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 985         mask |= (1 << CP0MVPCo_STLB);
 986     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 987
 988     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 989
 990     env->mvp->CP0_MVPControl = newval;
 991 }
 992
 993 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 994 {
 995     uint32_t mask;
 996     uint32_t newval;
 997
 998     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 999            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1000     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1001
1002     /* Yield scheduler intercept not implemented. */
1003     /* Gating storage scheduler intercept not implemented. */
1004
1005     // TODO: Enable/disable TCs.
1006
1007     env->CP0_VPEControl = newval;
1008 }
1009
1010 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1011 {
1012     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1013     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1014     uint32_t mask;
1015     uint32_t newval;
1016
1017     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1018            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1019     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1020
1021     /* TODO: Enable/disable TCs.  */
1022
1023     other->CP0_VPEControl = newval;
1024 }
1025
1026 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1027 {
1028     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1029     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1030     /* FIXME: Mask away return zero on read bits.  */
1031     return other->CP0_VPEControl;
1032 }
1033
1034 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1035 {
1036     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1037     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1038
1039     return other->CP0_VPEConf0;
1040 }
1041
1042 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1043 {
1044     uint32_t mask = 0;
1045     uint32_t newval;
1046
1047     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1048         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1049             mask |= (0xff << CP0VPEC0_XTC);
1050         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1051     }
1052     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1053
1054     // TODO: TC exclusive handling due to ERL/EXL.
1055
1056     env->CP0_VPEConf0 = newval;
1057 }
1058
1059 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1060 {
1061     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1062     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1063     uint32_t mask = 0;
1064     uint32_t newval;
1065
1066     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1067     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1068
1069     /* TODO: TC exclusive handling due to ERL/EXL.  */
1070     other->CP0_VPEConf0 = newval;
1071 }
1072
1073 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1074 {
1075     uint32_t mask = 0;
1076     uint32_t newval;
1077
1078     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1079         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1080                 (0xff << CP0VPEC1_NCP1);
1081     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1082
1083     /* UDI not implemented. */
1084     /* CP2 not implemented. */
1085
1086     // TODO: Handle FPU (CP1) binding.
1087
1088     env->CP0_VPEConf1 = newval;
1089 }
1090
1091 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1092 {
1093     /* Yield qualifier inputs not implemented. */
1094     env->CP0_YQMask = 0x00000000;
1095 }
1096
1097 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1098 {
1099     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1100 }
1101
1102 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1103
1104 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1105 {
1106     /* 1k pages not implemented */
1107     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1108     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1109                         | (rxi << (CP0EnLo_XI - 30));
1110 }
1111
1112 #if defined(TARGET_MIPS64)
1113 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1114
1115 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1116 {
1117     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1118     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1119 }
1120 #endif
1121
1122 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1123 {
1124     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1125     uint32_t newval;
1126
1127     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1128
1129     env->active_tc.CP0_TCStatus = newval;
1130     sync_c0_tcstatus(env, env->current_tc, newval);
1131 }
1132
1133 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1134 {
1135     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1136     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1137
1138     if (other_tc == other->current_tc)
1139         other->active_tc.CP0_TCStatus = arg1;
1140     else
1141         other->tcs[other_tc].CP0_TCStatus = arg1;
1142     sync_c0_tcstatus(other, other_tc, arg1);
1143 }
1144
1145 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1146 {
1147     uint32_t mask = (1 << CP0TCBd_TBE);
1148     uint32_t newval;
1149
1150     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1151         mask |= (1 << CP0TCBd_CurVPE);
1152     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1153     env->active_tc.CP0_TCBind = newval;
1154 }
1155
1156 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1157 {
1158     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1159     uint32_t mask = (1 << CP0TCBd_TBE);
1160     uint32_t newval;
1161     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1162
1163     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1164         mask |= (1 << CP0TCBd_CurVPE);
1165     if (other_tc == other->current_tc) {
1166         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1167         other->active_tc.CP0_TCBind = newval;
1168     } else {
1169         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1170         other->tcs[other_tc].CP0_TCBind = newval;
1171     }
1172 }
1173
1174 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1175 {
1176     env->active_tc.PC = arg1;
1177     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1178     env->lladdr = 0ULL;
1179     /* MIPS16 not implemented. */
1180 }
1181
1182 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1183 {
1184     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1185     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1186
1187     if (other_tc == other->current_tc) {
1188         other->active_tc.PC = arg1;
1189         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1190         other->lladdr = 0ULL;
1191         /* MIPS16 not implemented. */
1192     } else {
1193         other->tcs[other_tc].PC = arg1;
1194         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1195         other->lladdr = 0ULL;
1196         /* MIPS16 not implemented. */
1197     }
1198 }
1199
1200 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1201 {
1202     MIPSCPU *cpu = mips_env_get_cpu(env);
1203
1204     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1205
1206     // TODO: Halt TC / Restart (if allocated+active) TC.
1207     if (env->active_tc.CP0_TCHalt & 1) {
1208         mips_tc_sleep(cpu, env->current_tc);
1209     } else {
1210         mips_tc_wake(cpu, env->current_tc);
1211     }
1212 }
1213
1214 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1215 {
1216     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1217     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1218     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1219
1220     // TODO: Halt TC / Restart (if allocated+active) TC.
1221
1222     if (other_tc == other->current_tc)
1223         other->active_tc.CP0_TCHalt = arg1;
1224     else
1225         other->tcs[other_tc].CP0_TCHalt = arg1;
1226
1227     if (arg1 & 1) {
1228         mips_tc_sleep(other_cpu, other_tc);
1229     } else {
1230         mips_tc_wake(other_cpu, other_tc);
1231     }
1232 }
1233
1234 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1235 {
1236     env->active_tc.CP0_TCContext = arg1;
1237 }
1238
1239 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1240 {
1241     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1242     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1243
1244     if (other_tc == other->current_tc)
1245         other->active_tc.CP0_TCContext = arg1;
1246     else
1247         other->tcs[other_tc].CP0_TCContext = arg1;
1248 }
1249
1250 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1251 {
1252     env->active_tc.CP0_TCSchedule = arg1;
1253 }
1254
1255 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1256 {
1257     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1258     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1259
1260     if (other_tc == other->current_tc)
1261         other->active_tc.CP0_TCSchedule = arg1;
1262     else
1263         other->tcs[other_tc].CP0_TCSchedule = arg1;
1264 }
1265
1266 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1267 {
1268     env->active_tc.CP0_TCScheFBack = arg1;
1269 }
1270
1271 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1272 {
1273     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1274     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1275
1276     if (other_tc == other->current_tc)
1277         other->active_tc.CP0_TCScheFBack = arg1;
1278     else
1279         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1280 }
1281
1282 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1283 {
1284     /* 1k pages not implemented */
1285     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1286     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1287                         | (rxi << (CP0EnLo_XI - 30));
1288 }
1289
1290 #if defined(TARGET_MIPS64)
1291 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1292 {
1293     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1294     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1295 }
1296 #endif
1297
1298 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1299 {
1300     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1301 }
1302
1303 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1304 {
1305     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1306     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1307         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1308          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1309          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1310         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1311     }
1312 }
1313
1314 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1315 {
1316     /* SmartMIPS not implemented */
1317     /* 1k pages not implemented */
1318     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1319                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1320     compute_hflags(env);
1321     restore_pamask(env);
1322 }
1323
1324 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1325 {
1326     if (env->insn_flags & ISA_MIPS32R6) {
1327         if (arg1 < env->tlb->nb_tlb) {
1328             env->CP0_Wired = arg1;
1329         }
1330     } else {
1331         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1332     }
1333 }
1334
1335 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1336 {
1337     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1338 }
1339
1340 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1341 {
1342     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1343 }
1344
1345 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1346 {
1347     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1348 }
1349
1350 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1351 {
1352     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1353 }
1354
1355 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1356 {
1357     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1358 }
1359
1360 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1361 {
1362     uint32_t mask = 0x0000000F;
1363
1364     if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1365         (env->insn_flags & ISA_MIPS32R6)) {
1366         mask |= (1 << 4);
1367     }
1368     if (env->insn_flags & ISA_MIPS32R6) {
1369         mask |= (1 << 5);
1370     }
1371     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1372         mask |= (1 << 29);
1373
1374         if (arg1 & (1 << 29)) {
1375             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1376         } else {
1377             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1378         }
1379     }
1380
1381     env->CP0_HWREna = arg1 & mask;
1382 }
1383
1384 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1385 {
1386     cpu_mips_store_count(env, arg1);
1387 }
1388
1389 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1390 {
1391     target_ulong old, val, mask;
1392     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1393     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1394         mask |= 1 << CP0EnHi_EHINV;
1395     }
1396
1397     /* 1k pages not implemented */
1398 #if defined(TARGET_MIPS64)
1399     if (env->insn_flags & ISA_MIPS32R6) {
1400         int entryhi_r = extract64(arg1, 62, 2);
1401         int config0_at = extract32(env->CP0_Config0, 13, 2);
1402         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1403         if ((entryhi_r == 2) ||
1404             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1405             /* skip EntryHi.R field if new value is reserved */
1406             mask &= ~(0x3ull << 62);
1407         }
1408     }
1409     mask &= env->SEGMask;
1410 #endif
1411     old = env->CP0_EntryHi;
1412     val = (arg1 & mask) | (old & ~mask);
1413     env->CP0_EntryHi = val;
1414     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1415         sync_c0_entryhi(env, env->current_tc);
1416     }
1417     /* If the ASID changes, flush qemu's TLB.  */
1418     if ((old & 0xFF) != (val & 0xFF))
1419         cpu_mips_tlb_flush(env, 1);
1420 }
1421
1422 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1423 {
1424     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1425     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1426
1427     other->CP0_EntryHi = arg1;
1428     sync_c0_entryhi(other, other_tc);
1429 }
1430
1431 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1432 {
1433     cpu_mips_store_compare(env, arg1);
1434 }
1435
1436 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1437 {
1438     MIPSCPU *cpu = mips_env_get_cpu(env);
1439     uint32_t val, old;
1440
1441     old = env->CP0_Status;
1442     cpu_mips_store_status(env, arg1);
1443     val = env->CP0_Status;
1444
1445     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1446         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1447                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1448                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1449                 env->CP0_Cause);
1450         switch (env->hflags & MIPS_HFLAG_KSU) {
1451         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1452         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1453         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1454         default:
1455             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1456             break;
1457         }
1458     }
1459 }
1460
1461 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1462 {
1463     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1464     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1465     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1466
1467     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1468     sync_c0_status(env, other, other_tc);
1469 }
1470
1471 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1472 {
1473     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1474 }
1475
1476 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1477 {
1478     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1479     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1480 }
1481
1482 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1483 {
1484     cpu_mips_store_cause(env, arg1);
1485 }
1486
1487 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1488 {
1489     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1490     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1491
1492     cpu_mips_store_cause(other, arg1);
1493 }
1494
1495 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1496 {
1497     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1498     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1499
1500     return other->CP0_EPC;
1501 }
1502
1503 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1504 {
1505     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1506     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1507
1508     return other->CP0_EBase;
1509 }
1510
1511 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1512 {
1513     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1514 }
1515
1516 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1517 {
1518     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1519     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1520     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1521 }
1522
1523 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1524 {
1525     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1526     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1527
1528     switch (idx) {
1529     case 0: return other->CP0_Config0;
1530     case 1: return other->CP0_Config1;
1531     case 2: return other->CP0_Config2;
1532     case 3: return other->CP0_Config3;
1533     /* 4 and 5 are reserved.  */
1534     case 6: return other->CP0_Config6;
1535     case 7: return other->CP0_Config7;
1536     default:
1537         break;
1538     }
1539     return 0;
1540 }
1541
1542 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1543 {
1544     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1545 }
1546
1547 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1548 {
1549     /* tertiary/secondary caches not implemented */
1550     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1551 }
1552
1553 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1554 {
1555     if (env->insn_flags & ASE_MICROMIPS) {
1556         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1557                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1558     }
1559 }
1560
1561 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1562 {
1563     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1564                        (arg1 & env->CP0_Config4_rw_bitmask);
1565 }
1566
1567 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1568 {
1569     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1570                        (arg1 & env->CP0_Config5_rw_bitmask);
1571     compute_hflags(env);
1572 }
1573
1574 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1575 {
1576     target_long mask = env->CP0_LLAddr_rw_bitmask;
1577     arg1 = arg1 << env->CP0_LLAddr_shift;
1578     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1579 }
1580
1581 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1582 {
1583     /* Watch exceptions for instructions, data loads, data stores
1584        not implemented. */
1585     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1586 }
1587
1588 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1589 {
1590     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1591     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1592 }
1593
1594 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1595 {
1596     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1597     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1598 }
1599
1600 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1601 {
1602     env->CP0_Framemask = arg1; /* XXX */
1603 }
1604
1605 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1606 {
1607     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1608     if (arg1 & (1 << CP0DB_DM))
1609         env->hflags |= MIPS_HFLAG_DM;
1610     else
1611         env->hflags &= ~MIPS_HFLAG_DM;
1612 }
1613
1614 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1615 {
1616     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1617     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1618     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1619
1620     /* XXX: Might be wrong, check with EJTAG spec. */
1621     if (other_tc == other->current_tc)
1622         other->active_tc.CP0_Debug_tcstatus = val;
1623     else
1624         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1625     other->CP0_Debug = (other->CP0_Debug &
1626                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1627                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1628 }
1629
1630 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1631 {
1632     env->CP0_Performance0 = arg1 & 0x000007ff;
1633 }
1634
1635 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1636 {
1637     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1638 }
1639
1640 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1641 {
1642     env->CP0_DataLo = arg1; /* XXX */
1643 }
1644
1645 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1646 {
1647     env->CP0_TagHi = arg1; /* XXX */
1648 }
1649
1650 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1651 {
1652     env->CP0_DataHi = arg1; /* XXX */
1653 }
1654
1655 /* MIPS MT functions */
1656 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1657 {
1658     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1659     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1660
1661     if (other_tc == other->current_tc)
1662         return other->active_tc.gpr[sel];
1663     else
1664         return other->tcs[other_tc].gpr[sel];
1665 }
1666
1667 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1668 {
1669     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1670     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1671
1672     if (other_tc == other->current_tc)
1673         return other->active_tc.LO[sel];
1674     else
1675         return other->tcs[other_tc].LO[sel];
1676 }
1677
1678 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1679 {
1680     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1681     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1682
1683     if (other_tc == other->current_tc)
1684         return other->active_tc.HI[sel];
1685     else
1686         return other->tcs[other_tc].HI[sel];
1687 }
1688
1689 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1690 {
1691     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1692     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1693
1694     if (other_tc == other->current_tc)
1695         return other->active_tc.ACX[sel];
1696     else
1697         return other->tcs[other_tc].ACX[sel];
1698 }
1699
1700 target_ulong helper_mftdsp(CPUMIPSState *env)
1701 {
1702     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1703     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1704
1705     if (other_tc == other->current_tc)
1706         return other->active_tc.DSPControl;
1707     else
1708         return other->tcs[other_tc].DSPControl;
1709 }
1710
1711 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1712 {
1713     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1714     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1715
1716     if (other_tc == other->current_tc)
1717         other->active_tc.gpr[sel] = arg1;
1718     else
1719         other->tcs[other_tc].gpr[sel] = arg1;
1720 }
1721
1722 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1723 {
1724     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1725     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1726
1727     if (other_tc == other->current_tc)
1728         other->active_tc.LO[sel] = arg1;
1729     else
1730         other->tcs[other_tc].LO[sel] = arg1;
1731 }
1732
1733 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1734 {
1735     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1736     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1737
1738     if (other_tc == other->current_tc)
1739         other->active_tc.HI[sel] = arg1;
1740     else
1741         other->tcs[other_tc].HI[sel] = arg1;
1742 }
1743
1744 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1745 {
1746     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1747     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1748
1749     if (other_tc == other->current_tc)
1750         other->active_tc.ACX[sel] = arg1;
1751     else
1752         other->tcs[other_tc].ACX[sel] = arg1;
1753 }
1754
1755 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1756 {
1757     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1758     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1759
1760     if (other_tc == other->current_tc)
1761         other->active_tc.DSPControl = arg1;
1762     else
1763         other->tcs[other_tc].DSPControl = arg1;
1764 }
1765
1766 /* MIPS MT functions */
1767 target_ulong helper_dmt(void)
1768 {
1769     // TODO
1770      return 0;
1771 }
1772
1773 target_ulong helper_emt(void)
1774 {
1775     // TODO
1776     return 0;
1777 }
1778
1779 target_ulong helper_dvpe(CPUMIPSState *env)
1780 {
1781     CPUState *other_cs = first_cpu;
1782     target_ulong prev = env->mvp->CP0_MVPControl;
1783
1784     CPU_FOREACH(other_cs) {
1785         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1786         /* Turn off all VPEs except the one executing the dvpe.  */
1787         if (&other_cpu->env != env) {
1788             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1789             mips_vpe_sleep(other_cpu);
1790         }
1791     }
1792     return prev;
1793 }
1794
1795 target_ulong helper_evpe(CPUMIPSState *env)
1796 {
1797     CPUState *other_cs = first_cpu;
1798     target_ulong prev = env->mvp->CP0_MVPControl;
1799
1800     CPU_FOREACH(other_cs) {
1801         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1802
1803         if (&other_cpu->env != env
1804             /* If the VPE is WFI, don't disturb its sleep.  */
1805             && !mips_vpe_is_wfi(other_cpu)) {
1806             /* Enable the VPE.  */
1807             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1808             mips_vpe_wake(other_cpu); /* And wake it up.  */
1809         }
1810     }
1811     return prev;
1812 }
1813 #endif /* !CONFIG_USER_ONLY */
1814
1815 void helper_fork(target_ulong arg1, target_ulong arg2)
1816 {
1817     // arg1 = rt, arg2 = rs
1818     // TODO: store to TC register
1819 }
1820
1821 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1822 {
1823     target_long arg1 = arg;
1824
1825     if (arg1 < 0) {
1826         /* No scheduling policy implemented. */
1827         if (arg1 != -2) {
1828             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1829                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1830                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1831                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1832                 do_raise_exception(env, EXCP_THREAD, GETPC());
1833             }
1834         }
1835     } else if (arg1 == 0) {
1836         if (0 /* TODO: TC underflow */) {
1837             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1838             do_raise_exception(env, EXCP_THREAD, GETPC());
1839         } else {
1840             // TODO: Deallocate TC
1841         }
1842     } else if (arg1 > 0) {
1843         /* Yield qualifier inputs not implemented. */
1844         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1845         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1846         do_raise_exception(env, EXCP_THREAD, GETPC());
1847     }
1848     return env->CP0_YQMask;
1849 }
1850
1851 /* R6 Multi-threading */
1852 #ifndef CONFIG_USER_ONLY
1853 target_ulong helper_dvp(CPUMIPSState *env)
1854 {
1855     CPUState *other_cs = first_cpu;
1856     target_ulong prev = env->CP0_VPControl;
1857
1858     if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1859         CPU_FOREACH(other_cs) {
1860             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1861             /* Turn off all VPs except the one executing the dvp. */
1862             if (&other_cpu->env != env) {
1863                 mips_vpe_sleep(other_cpu);
1864             }
1865         }
1866         env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1867     }
1868     return prev;
1869 }
1870
1871 target_ulong helper_evp(CPUMIPSState *env)
1872 {
1873     CPUState *other_cs = first_cpu;
1874     target_ulong prev = env->CP0_VPControl;
1875
1876     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1877         CPU_FOREACH(other_cs) {
1878             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1879             if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1880                 /* If the VP is WFI, don't disturb its sleep.
1881                  * Otherwise, wake it up. */
1882                 mips_vpe_wake(other_cpu);
1883             }
1884         }
1885         env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1886     }
1887     return prev;
1888 }
1889 #endif /* !CONFIG_USER_ONLY */
1890
1891 #ifndef CONFIG_USER_ONLY
1892 /* TLB management */
1893 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1894 {
1895     /* Discard entries from env->tlb[first] onwards.  */
1896     while (env->tlb->tlb_in_use > first) {
1897         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1898     }
1899 }
1900
1901 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1902 {
1903 #if defined(TARGET_MIPS64)
1904     return extract64(entrylo, 6, 54);
1905 #else
1906     return extract64(entrylo, 6, 24) | /* PFN */
1907            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1908 #endif
1909 }
1910
1911 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1912 {
1913     r4k_tlb_t *tlb;
1914
1915     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1916     tlb = &env->tlb->mmu.r4k.tlb[idx];
1917     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1918         tlb->EHINV = 1;
1919         return;
1920     }
1921     tlb->EHINV = 0;
1922     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1923 #if defined(TARGET_MIPS64)
1924     tlb->VPN &= env->SEGMask;
1925 #endif
1926     tlb->ASID = env->CP0_EntryHi & 0xFF;
1927     tlb->PageMask = env->CP0_PageMask;
1928     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1929     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1930     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1931     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1932     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1933     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1934     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1935     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1936     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1937     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1938     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1939     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1940     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1941 }
1942
1943 void r4k_helper_tlbinv(CPUMIPSState *env)
1944 {
1945     int idx;
1946     r4k_tlb_t *tlb;
1947     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1948
1949     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1950         tlb = &env->tlb->mmu.r4k.tlb[idx];
1951         if (!tlb->G && tlb->ASID == ASID) {
1952             tlb->EHINV = 1;
1953         }
1954     }
1955     cpu_mips_tlb_flush(env, 1);
1956 }
1957
1958 void r4k_helper_tlbinvf(CPUMIPSState *env)
1959 {
1960     int idx;
1961
1962     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1963         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1964     }
1965     cpu_mips_tlb_flush(env, 1);
1966 }
1967
1968 void r4k_helper_tlbwi(CPUMIPSState *env)
1969 {
1970     r4k_tlb_t *tlb;
1971     int idx;
1972     target_ulong VPN;
1973     uint8_t ASID;
1974     bool G, V0, D0, V1, D1;
1975
1976     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1977     tlb = &env->tlb->mmu.r4k.tlb[idx];
1978     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1979 #if defined(TARGET_MIPS64)
1980     VPN &= env->SEGMask;
1981 #endif
1982     ASID = env->CP0_EntryHi & 0xff;
1983     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1984     V0 = (env->CP0_EntryLo0 & 2) != 0;
1985     D0 = (env->CP0_EntryLo0 & 4) != 0;
1986     V1 = (env->CP0_EntryLo1 & 2) != 0;
1987     D1 = (env->CP0_EntryLo1 & 4) != 0;
1988
1989     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1990        permissions on the current entry. */
1991     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1992         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1993         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1994         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1995     }
1996
1997     r4k_invalidate_tlb(env, idx, 0);
1998     r4k_fill_tlb(env, idx);
1999 }
2000
2001 void r4k_helper_tlbwr(CPUMIPSState *env)
2002 {
2003     int r = cpu_mips_get_random(env);
2004
2005     r4k_invalidate_tlb(env, r, 1);
2006     r4k_fill_tlb(env, r);
2007 }
2008
2009 void r4k_helper_tlbp(CPUMIPSState *env)
2010 {
2011     r4k_tlb_t *tlb;
2012     target_ulong mask;
2013     target_ulong tag;
2014     target_ulong VPN;
2015     uint8_t ASID;
2016     int i;
2017
2018     ASID = env->CP0_EntryHi & 0xFF;
2019     for (i = 0; i < env->tlb->nb_tlb; i++) {
2020         tlb = &env->tlb->mmu.r4k.tlb[i];
2021         /* 1k pages are not supported. */
2022         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2023         tag = env->CP0_EntryHi & ~mask;
2024         VPN = tlb->VPN & ~mask;
2025 #if defined(TARGET_MIPS64)
2026         tag &= env->SEGMask;
2027 #endif
2028         /* Check ASID, virtual page number & size */
2029         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2030             /* TLB match */
2031             env->CP0_Index = i;
2032             break;
2033         }
2034     }
2035     if (i == env->tlb->nb_tlb) {
2036         /* No match.  Discard any shadow entries, if any of them match.  */
2037         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2038             tlb = &env->tlb->mmu.r4k.tlb[i];
2039             /* 1k pages are not supported. */
2040             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2041             tag = env->CP0_EntryHi & ~mask;
2042             VPN = tlb->VPN & ~mask;
2043 #if defined(TARGET_MIPS64)
2044             tag &= env->SEGMask;
2045 #endif
2046             /* Check ASID, virtual page number & size */
2047             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2048                 r4k_mips_tlb_flush_extra (env, i);
2049                 break;
2050             }
2051         }
2052
2053         env->CP0_Index |= 0x80000000;
2054     }
2055 }
2056
2057 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2058 {
2059 #if defined(TARGET_MIPS64)
2060     return tlb_pfn << 6;
2061 #else
2062     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2063            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2064 #endif
2065 }
2066
2067 void r4k_helper_tlbr(CPUMIPSState *env)
2068 {
2069     r4k_tlb_t *tlb;
2070     uint8_t ASID;
2071     int idx;
2072
2073     ASID = env->CP0_EntryHi & 0xFF;
2074     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2075     tlb = &env->tlb->mmu.r4k.tlb[idx];
2076
2077     /* If this will change the current ASID, flush qemu's TLB.  */
2078     if (ASID != tlb->ASID)
2079         cpu_mips_tlb_flush (env, 1);
2080
2081     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2082
2083     if (tlb->EHINV) {
2084         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2085         env->CP0_PageMask = 0;
2086         env->CP0_EntryLo0 = 0;
2087         env->CP0_EntryLo1 = 0;
2088     } else {
2089         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2090         env->CP0_PageMask = tlb->PageMask;
2091         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2092                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2093                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2094                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2095         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2096                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2097                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2098                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2099     }
2100 }
2101
2102 void helper_tlbwi(CPUMIPSState *env)
2103 {
2104     env->tlb->helper_tlbwi(env);
2105 }
2106
2107 void helper_tlbwr(CPUMIPSState *env)
2108 {
2109     env->tlb->helper_tlbwr(env);
2110 }
2111
2112 void helper_tlbp(CPUMIPSState *env)
2113 {
2114     env->tlb->helper_tlbp(env);
2115 }
2116
2117 void helper_tlbr(CPUMIPSState *env)
2118 {
2119     env->tlb->helper_tlbr(env);
2120 }
2121
2122 void helper_tlbinv(CPUMIPSState *env)
2123 {
2124     env->tlb->helper_tlbinv(env);
2125 }
2126
2127 void helper_tlbinvf(CPUMIPSState *env)
2128 {
2129     env->tlb->helper_tlbinvf(env);
2130 }
2131
2132 /* Specials */
2133 target_ulong helper_di(CPUMIPSState *env)
2134 {
2135     target_ulong t0 = env->CP0_Status;
2136
2137     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2138     return t0;
2139 }
2140
2141 target_ulong helper_ei(CPUMIPSState *env)
2142 {
2143     target_ulong t0 = env->CP0_Status;
2144
2145     env->CP0_Status = t0 | (1 << CP0St_IE);
2146     return t0;
2147 }
2148
2149 static void debug_pre_eret(CPUMIPSState *env)
2150 {
2151     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2152         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2153                 env->active_tc.PC, env->CP0_EPC);
2154         if (env->CP0_Status & (1 << CP0St_ERL))
2155             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2156         if (env->hflags & MIPS_HFLAG_DM)
2157             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2158         qemu_log("\n");
2159     }
2160 }
2161
2162 static void debug_post_eret(CPUMIPSState *env)
2163 {
2164     MIPSCPU *cpu = mips_env_get_cpu(env);
2165
2166     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2167         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2168                 env->active_tc.PC, env->CP0_EPC);
2169         if (env->CP0_Status & (1 << CP0St_ERL))
2170             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2171         if (env->hflags & MIPS_HFLAG_DM)
2172             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2173         switch (env->hflags & MIPS_HFLAG_KSU) {
2174         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2175         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2176         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2177         default:
2178             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2179             break;
2180         }
2181     }
2182 }
2183
2184 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2185 {
2186     env->active_tc.PC = error_pc & ~(target_ulong)1;
2187     if (error_pc & 1) {
2188         env->hflags |= MIPS_HFLAG_M16;
2189     } else {
2190         env->hflags &= ~(MIPS_HFLAG_M16);
2191     }
2192 }
2193
2194 static inline void exception_return(CPUMIPSState *env)
2195 {
2196     debug_pre_eret(env);
2197     if (env->CP0_Status & (1 << CP0St_ERL)) {
2198         set_pc(env, env->CP0_ErrorEPC);
2199         env->CP0_Status &= ~(1 << CP0St_ERL);
2200     } else {
2201         set_pc(env, env->CP0_EPC);
2202         env->CP0_Status &= ~(1 << CP0St_EXL);
2203     }
2204     compute_hflags(env);
2205     debug_post_eret(env);
2206 }
2207
2208 void helper_eret(CPUMIPSState *env)
2209 {
2210     exception_return(env);
2211     env->lladdr = 1;
2212 }
2213
2214 void helper_eretnc(CPUMIPSState *env)
2215 {
2216     exception_return(env);
2217 }
2218
2219 void helper_deret(CPUMIPSState *env)
2220 {
2221     debug_pre_eret(env);
2222     set_pc(env, env->CP0_DEPC);
2223
2224     env->hflags &= ~MIPS_HFLAG_DM;
2225     compute_hflags(env);
2226     debug_post_eret(env);
2227 }
2228 #endif /* !CONFIG_USER_ONLY */
2229
2230 static inline void check_hwrena(CPUMIPSState *env, int reg)
2231 {
2232     if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2233         return;
2234     }
2235     do_raise_exception(env, EXCP_RI, GETPC());
2236 }
2237
2238 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2239 {
2240     check_hwrena(env, 0);
2241     return env->CP0_EBase & 0x3ff;
2242 }
2243
2244 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2245 {
2246     check_hwrena(env, 1);
2247     return env->SYNCI_Step;
2248 }
2249
2250 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2251 {
2252     check_hwrena(env, 2);
2253 #ifdef CONFIG_USER_ONLY
2254     return env->CP0_Count;
2255 #else
2256     return (int32_t)cpu_mips_get_count(env);
2257 #endif
2258 }
2259
2260 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2261 {
2262     check_hwrena(env, 3);
2263     return env->CCRes;
2264 }
2265
2266 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2267 {
2268     check_hwrena(env, 4);
2269     return env->CP0_Performance0;
2270 }
2271
2272 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2273 {
2274     check_hwrena(env, 5);
2275     return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2276 }
2277
2278 void helper_pmon(CPUMIPSState *env, int function)
2279 {
2280     function /= 2;
2281     switch (function) {
2282     case 2: /* TODO: char inbyte(int waitflag); */
2283         if (env->active_tc.gpr[4] == 0)
2284             env->active_tc.gpr[2] = -1;
2285         /* Fall through */
2286     case 11: /* TODO: char inbyte (void); */
2287         env->active_tc.gpr[2] = -1;
2288         break;
2289     case 3:
2290     case 12:
2291         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2292         break;
2293     case 17:
2294         break;
2295     case 158:
2296         {
2297             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2298             printf("%s", fmt);
2299         }
2300         break;
2301     }
2302 }
2303
2304 void helper_wait(CPUMIPSState *env)
2305 {
2306     CPUState *cs = CPU(mips_env_get_cpu(env));
2307
2308     cs->halted = 1;
2309     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2310     /* Last instruction in the block, PC was updated before
2311        - no need to recover PC and icount */
2312     raise_exception(env, EXCP_HLT);
2313 }
2314
2315 #if !defined(CONFIG_USER_ONLY)
2316
2317 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2318                                   int access_type, int is_user,
2319                                   uintptr_t retaddr)
2320 {
2321     MIPSCPU *cpu = MIPS_CPU(cs);
2322     CPUMIPSState *env = &cpu->env;
2323     int error_code = 0;
2324     int excp;
2325
2326     env->CP0_BadVAddr = addr;
2327
2328     if (access_type == MMU_DATA_STORE) {
2329         excp = EXCP_AdES;
2330     } else {
2331         excp = EXCP_AdEL;
2332         if (access_type == MMU_INST_FETCH) {
2333             error_code |= EXCP_INST_NOTAVAIL;
2334         }
2335     }
2336
2337     do_raise_exception_err(env, excp, error_code, retaddr);
2338 }
2339
2340 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2341               uintptr_t retaddr)
2342 {
2343     int ret;
2344
2345     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2346     if (ret) {
2347         MIPSCPU *cpu = MIPS_CPU(cs);
2348         CPUMIPSState *env = &cpu->env;
2349
2350         do_raise_exception_err(env, cs->exception_index,
2351                                env->error_code, retaddr);
2352     }
2353 }
2354
2355 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2356                                 bool is_write, bool is_exec, int unused,
2357                                 unsigned size)
2358 {
2359     MIPSCPU *cpu = MIPS_CPU(cs);
2360     CPUMIPSState *env = &cpu->env;
2361
2362     /*
2363      * Raising an exception with KVM enabled will crash because it won't be from
2364      * the main execution loop so the longjmp won't have a matching setjmp.
2365      * Until we can trigger a bus error exception through KVM lets just ignore
2366      * the access.
2367      */
2368     if (kvm_enabled()) {
2369         return;
2370     }
2371
2372     if (is_exec) {
2373         raise_exception(env, EXCP_IBE);
2374     } else {
2375         raise_exception(env, EXCP_DBE);
2376     }
2377 }
2378 #endif /* !CONFIG_USER_ONLY */
2379
2380 /* Complex FPU operations which may need stack space. */
2381
2382 #define FLOAT_TWO32 make_float32(1 << 30)
2383 #define FLOAT_TWO64 make_float64(1ULL << 62)
2384 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2385 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2386
2387 /* convert MIPS rounding mode in FCR31 to IEEE library */
2388 unsigned int ieee_rm[] = {
2389     float_round_nearest_even,
2390     float_round_to_zero,
2391     float_round_up,
2392     float_round_down
2393 };
2394
2395 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2396 {
2397     target_ulong arg1 = 0;
2398
2399     switch (reg) {
2400     case 0:
2401         arg1 = (int32_t)env->active_fpu.fcr0;
2402         break;
2403     case 1:
2404         /* UFR Support - Read Status FR */
2405         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2406             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2407                 arg1 = (int32_t)
2408                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2409             } else {
2410                 do_raise_exception(env, EXCP_RI, GETPC());
2411             }
2412         }
2413         break;
2414     case 5:
2415         /* FRE Support - read Config5.FRE bit */
2416         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2417             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2418                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2419             } else {
2420                 helper_raise_exception(env, EXCP_RI);
2421             }
2422         }
2423         break;
2424     case 25:
2425         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2426         break;
2427     case 26:
2428         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2429         break;
2430     case 28:
2431         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2432         break;
2433     default:
2434         arg1 = (int32_t)env->active_fpu.fcr31;
2435         break;
2436     }
2437
2438     return arg1;
2439 }
2440
2441 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2442 {
2443     switch (fs) {
2444     case 1:
2445         /* UFR Alias - Reset Status FR */
2446         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2447             return;
2448         }
2449         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2450             env->CP0_Status &= ~(1 << CP0St_FR);
2451             compute_hflags(env);
2452         } else {
2453             do_raise_exception(env, EXCP_RI, GETPC());
2454         }
2455         break;
2456     case 4:
2457         /* UNFR Alias - Set Status FR */
2458         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2459             return;
2460         }
2461         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2462             env->CP0_Status |= (1 << CP0St_FR);
2463             compute_hflags(env);
2464         } else {
2465             do_raise_exception(env, EXCP_RI, GETPC());
2466         }
2467         break;
2468     case 5:
2469         /* FRE Support - clear Config5.FRE bit */
2470         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2471             return;
2472         }
2473         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2474             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2475             compute_hflags(env);
2476         } else {
2477             helper_raise_exception(env, EXCP_RI);
2478         }
2479         break;
2480     case 6:
2481         /* FRE Support - set Config5.FRE bit */
2482         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2483             return;
2484         }
2485         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2486             env->CP0_Config5 |= (1 << CP0C5_FRE);
2487             compute_hflags(env);
2488         } else {
2489             helper_raise_exception(env, EXCP_RI);
2490         }
2491         break;
2492     case 25:
2493         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2494             return;
2495         }
2496         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2497                      ((arg1 & 0x1) << 23);
2498         break;
2499     case 26:
2500         if (arg1 & 0x007c0000)
2501             return;
2502         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2503         break;
2504     case 28:
2505         if (arg1 & 0x007c0000)
2506             return;
2507         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2508                      ((arg1 & 0x4) << 22);
2509         break;
2510     case 31:
2511         if (env->insn_flags & ISA_MIPS32R6) {
2512             uint32_t mask = 0xfefc0000;
2513             env->active_fpu.fcr31 = (arg1 & ~mask) |
2514                 (env->active_fpu.fcr31 & mask);
2515         } else if (!(arg1 & 0x007c0000)) {
2516             env->active_fpu.fcr31 = arg1;
2517         }
2518         break;
2519     default:
2520         return;
2521     }
2522     /* set rounding mode */
2523     restore_rounding_mode(env);
2524     /* set flush-to-zero mode */
2525     restore_flush_mode(env);
2526     set_float_exception_flags(0, &env->active_fpu.fp_status);
2527     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2528         do_raise_exception(env, EXCP_FPE, GETPC());
2529 }
2530
2531 int ieee_ex_to_mips(int xcpt)
2532 {
2533     int ret = 0;
2534     if (xcpt) {
2535         if (xcpt & float_flag_invalid) {
2536             ret |= FP_INVALID;
2537         }
2538         if (xcpt & float_flag_overflow) {
2539             ret |= FP_OVERFLOW;
2540         }
2541         if (xcpt & float_flag_underflow) {
2542             ret |= FP_UNDERFLOW;
2543         }
2544         if (xcpt & float_flag_divbyzero) {
2545             ret |= FP_DIV0;
2546         }
2547         if (xcpt & float_flag_inexact) {
2548             ret |= FP_INEXACT;
2549         }
2550     }
2551     return ret;
2552 }
2553
2554 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2555 {
2556     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2557
2558     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2559
2560     if (tmp) {
2561         set_float_exception_flags(0, &env->active_fpu.fp_status);
2562
2563         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2564             do_raise_exception(env, EXCP_FPE, pc);
2565         } else {
2566             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2567         }
2568     }
2569 }
2570
2571 /* Float support.
2572    Single precition routines have a "s" suffix, double precision a
2573    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2574    paired single lower "pl", paired single upper "pu".  */
2575
2576 /* unary operations, modifying fp status  */
2577 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2578 {
2579     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2580     update_fcr31(env, GETPC());
2581     return fdt0;
2582 }
2583
2584 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2585 {
2586     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2587     update_fcr31(env, GETPC());
2588     return fst0;
2589 }
2590
2591 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2592 {
2593     uint64_t fdt2;
2594
2595     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2596     fdt2 = float64_maybe_silence_nan(fdt2);
2597     update_fcr31(env, GETPC());
2598     return fdt2;
2599 }
2600
2601 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2602 {
2603     uint64_t fdt2;
2604
2605     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2606     update_fcr31(env, GETPC());
2607     return fdt2;
2608 }
2609
2610 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2611 {
2612     uint64_t fdt2;
2613
2614     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2615     update_fcr31(env, GETPC());
2616     return fdt2;
2617 }
2618
2619 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2620 {
2621     uint64_t dt2;
2622
2623     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2624     if (get_float_exception_flags(&env->active_fpu.fp_status)
2625         & (float_flag_invalid | float_flag_overflow)) {
2626         dt2 = FP_TO_INT64_OVERFLOW;
2627     }
2628     update_fcr31(env, GETPC());
2629     return dt2;
2630 }
2631
2632 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2633 {
2634     uint64_t dt2;
2635
2636     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2637     if (get_float_exception_flags(&env->active_fpu.fp_status)
2638         & (float_flag_invalid | float_flag_overflow)) {
2639         dt2 = FP_TO_INT64_OVERFLOW;
2640     }
2641     update_fcr31(env, GETPC());
2642     return dt2;
2643 }
2644
2645 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2646 {
2647     uint32_t fst2;
2648     uint32_t fsth2;
2649
2650     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2651     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2652     update_fcr31(env, GETPC());
2653     return ((uint64_t)fsth2 << 32) | fst2;
2654 }
2655
2656 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2657 {
2658     uint32_t wt2;
2659     uint32_t wth2;
2660     int excp, excph;
2661
2662     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2663     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2664     if (excp & (float_flag_overflow | float_flag_invalid)) {
2665         wt2 = FP_TO_INT32_OVERFLOW;
2666     }
2667
2668     set_float_exception_flags(0, &env->active_fpu.fp_status);
2669     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2670     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2671     if (excph & (float_flag_overflow | float_flag_invalid)) {
2672         wth2 = FP_TO_INT32_OVERFLOW;
2673     }
2674
2675     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2676     update_fcr31(env, GETPC());
2677
2678     return ((uint64_t)wth2 << 32) | wt2;
2679 }
2680
2681 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2682 {
2683     uint32_t fst2;
2684
2685     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2686     fst2 = float32_maybe_silence_nan(fst2);
2687     update_fcr31(env, GETPC());
2688     return fst2;
2689 }
2690
2691 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2692 {
2693     uint32_t fst2;
2694
2695     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2696     update_fcr31(env, GETPC());
2697     return fst2;
2698 }
2699
2700 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2701 {
2702     uint32_t fst2;
2703
2704     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2705     update_fcr31(env, GETPC());
2706     return fst2;
2707 }
2708
2709 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2710 {
2711     uint32_t wt2;
2712
2713     wt2 = wt0;
2714     update_fcr31(env, GETPC());
2715     return wt2;
2716 }
2717
2718 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2719 {
2720     uint32_t wt2;
2721
2722     wt2 = wth0;
2723     update_fcr31(env, GETPC());
2724     return wt2;
2725 }
2726
2727 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2728 {
2729     uint32_t wt2;
2730
2731     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2732     if (get_float_exception_flags(&env->active_fpu.fp_status)
2733         & (float_flag_invalid | float_flag_overflow)) {
2734         wt2 = FP_TO_INT32_OVERFLOW;
2735     }
2736     update_fcr31(env, GETPC());
2737     return wt2;
2738 }
2739
2740 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2741 {
2742     uint32_t wt2;
2743
2744     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2745     if (get_float_exception_flags(&env->active_fpu.fp_status)
2746         & (float_flag_invalid | float_flag_overflow)) {
2747         wt2 = FP_TO_INT32_OVERFLOW;
2748     }
2749     update_fcr31(env, GETPC());
2750     return wt2;
2751 }
2752
2753 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2754 {
2755     uint64_t dt2;
2756
2757     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2758     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2759     restore_rounding_mode(env);
2760     if (get_float_exception_flags(&env->active_fpu.fp_status)
2761         & (float_flag_invalid | float_flag_overflow)) {
2762         dt2 = FP_TO_INT64_OVERFLOW;
2763     }
2764     update_fcr31(env, GETPC());
2765     return dt2;
2766 }
2767
2768 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2769 {
2770     uint64_t dt2;
2771
2772     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2773     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2774     restore_rounding_mode(env);
2775     if (get_float_exception_flags(&env->active_fpu.fp_status)
2776         & (float_flag_invalid | float_flag_overflow)) {
2777         dt2 = FP_TO_INT64_OVERFLOW;
2778     }
2779     update_fcr31(env, GETPC());
2780     return dt2;
2781 }
2782
2783 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2784 {
2785     uint32_t wt2;
2786
2787     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2788     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2789     restore_rounding_mode(env);
2790     if (get_float_exception_flags(&env->active_fpu.fp_status)
2791         & (float_flag_invalid | float_flag_overflow)) {
2792         wt2 = FP_TO_INT32_OVERFLOW;
2793     }
2794     update_fcr31(env, GETPC());
2795     return wt2;
2796 }
2797
2798 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2799 {
2800     uint32_t wt2;
2801
2802     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2803     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2804     restore_rounding_mode(env);
2805     if (get_float_exception_flags(&env->active_fpu.fp_status)
2806         & (float_flag_invalid | float_flag_overflow)) {
2807         wt2 = FP_TO_INT32_OVERFLOW;
2808     }
2809     update_fcr31(env, GETPC());
2810     return wt2;
2811 }
2812
2813 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2814 {
2815     uint64_t dt2;
2816
2817     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2818     if (get_float_exception_flags(&env->active_fpu.fp_status)
2819         & (float_flag_invalid | float_flag_overflow)) {
2820         dt2 = FP_TO_INT64_OVERFLOW;
2821     }
2822     update_fcr31(env, GETPC());
2823     return dt2;
2824 }
2825
2826 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2827 {
2828     uint64_t dt2;
2829
2830     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2831     if (get_float_exception_flags(&env->active_fpu.fp_status)
2832         & (float_flag_invalid | float_flag_overflow)) {
2833         dt2 = FP_TO_INT64_OVERFLOW;
2834     }
2835     update_fcr31(env, GETPC());
2836     return dt2;
2837 }
2838
2839 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2840 {
2841     uint32_t wt2;
2842
2843     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2844     if (get_float_exception_flags(&env->active_fpu.fp_status)
2845         & (float_flag_invalid | float_flag_overflow)) {
2846         wt2 = FP_TO_INT32_OVERFLOW;
2847     }
2848     update_fcr31(env, GETPC());
2849     return wt2;
2850 }
2851
2852 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2853 {
2854     uint32_t wt2;
2855
2856     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2857     if (get_float_exception_flags(&env->active_fpu.fp_status)
2858         & (float_flag_invalid | float_flag_overflow)) {
2859         wt2 = FP_TO_INT32_OVERFLOW;
2860     }
2861     update_fcr31(env, GETPC());
2862     return wt2;
2863 }
2864
2865 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2866 {
2867     uint64_t dt2;
2868
2869     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2870     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2871     restore_rounding_mode(env);
2872     if (get_float_exception_flags(&env->active_fpu.fp_status)
2873         & (float_flag_invalid | float_flag_overflow)) {
2874         dt2 = FP_TO_INT64_OVERFLOW;
2875     }
2876     update_fcr31(env, GETPC());
2877     return dt2;
2878 }
2879
2880 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2881 {
2882     uint64_t dt2;
2883
2884     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2885     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2886     restore_rounding_mode(env);
2887     if (get_float_exception_flags(&env->active_fpu.fp_status)
2888         & (float_flag_invalid | float_flag_overflow)) {
2889         dt2 = FP_TO_INT64_OVERFLOW;
2890     }
2891     update_fcr31(env, GETPC());
2892     return dt2;
2893 }
2894
2895 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2896 {
2897     uint32_t wt2;
2898
2899     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2900     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2901     restore_rounding_mode(env);
2902     if (get_float_exception_flags(&env->active_fpu.fp_status)
2903         & (float_flag_invalid | float_flag_overflow)) {
2904         wt2 = FP_TO_INT32_OVERFLOW;
2905     }
2906     update_fcr31(env, GETPC());
2907     return wt2;
2908 }
2909
2910 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2911 {
2912     uint32_t wt2;
2913
2914     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2915     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2916     restore_rounding_mode(env);
2917     if (get_float_exception_flags(&env->active_fpu.fp_status)
2918         & (float_flag_invalid | float_flag_overflow)) {
2919         wt2 = FP_TO_INT32_OVERFLOW;
2920     }
2921     update_fcr31(env, GETPC());
2922     return wt2;
2923 }
2924
2925 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2926 {
2927     uint64_t dt2;
2928
2929     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2930     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2931     restore_rounding_mode(env);
2932     if (get_float_exception_flags(&env->active_fpu.fp_status)
2933         & (float_flag_invalid | float_flag_overflow)) {
2934         dt2 = FP_TO_INT64_OVERFLOW;
2935     }
2936     update_fcr31(env, GETPC());
2937     return dt2;
2938 }
2939
2940 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2941 {
2942     uint64_t dt2;
2943
2944     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2945     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2946     restore_rounding_mode(env);
2947     if (get_float_exception_flags(&env->active_fpu.fp_status)
2948         & (float_flag_invalid | float_flag_overflow)) {
2949         dt2 = FP_TO_INT64_OVERFLOW;
2950     }
2951     update_fcr31(env, GETPC());
2952     return dt2;
2953 }
2954
2955 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2956 {
2957     uint32_t wt2;
2958
2959     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2960     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2961     restore_rounding_mode(env);
2962     if (get_float_exception_flags(&env->active_fpu.fp_status)
2963         & (float_flag_invalid | float_flag_overflow)) {
2964         wt2 = FP_TO_INT32_OVERFLOW;
2965     }
2966     update_fcr31(env, GETPC());
2967     return wt2;
2968 }
2969
2970 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2971 {
2972     uint32_t wt2;
2973
2974     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2975     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2976     restore_rounding_mode(env);
2977     if (get_float_exception_flags(&env->active_fpu.fp_status)
2978         & (float_flag_invalid | float_flag_overflow)) {
2979         wt2 = FP_TO_INT32_OVERFLOW;
2980     }
2981     update_fcr31(env, GETPC());
2982     return wt2;
2983 }
2984
2985 /* unary operations, not modifying fp status  */
2986 #define FLOAT_UNOP(name)                                       \
2987 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2988 {                                                              \
2989     return float64_ ## name(fdt0);                             \
2990 }                                                              \
2991 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2992 {                                                              \
2993     return float32_ ## name(fst0);                             \
2994 }                                                              \
2995 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2996 {                                                              \
2997     uint32_t wt0;                                              \
2998     uint32_t wth0;                                             \
2999                                                                \
3000     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
3001     wth0 = float32_ ## name(fdt0 >> 32);                       \
3002     return ((uint64_t)wth0 << 32) | wt0;                       \
3003 }
3004 FLOAT_UNOP(abs)
3005 FLOAT_UNOP(chs)
3006 #undef FLOAT_UNOP
3007
3008 /* MIPS specific unary operations */
3009 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3010 {
3011     uint64_t fdt2;
3012
3013     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3014     update_fcr31(env, GETPC());
3015     return fdt2;
3016 }
3017
3018 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3019 {
3020     uint32_t fst2;
3021
3022     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3023     update_fcr31(env, GETPC());
3024     return fst2;
3025 }
3026
3027 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3028 {
3029     uint64_t fdt2;
3030
3031     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3032     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3033     update_fcr31(env, GETPC());
3034     return fdt2;
3035 }
3036
3037 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3038 {
3039     uint32_t fst2;
3040
3041     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3042     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3043     update_fcr31(env, GETPC());
3044     return fst2;
3045 }
3046
3047 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3048 {
3049     uint64_t fdt2;
3050
3051     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3052     update_fcr31(env, GETPC());
3053     return fdt2;
3054 }
3055
3056 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3057 {
3058     uint32_t fst2;
3059
3060     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3061     update_fcr31(env, GETPC());
3062     return fst2;
3063 }
3064
3065 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3066 {
3067     uint32_t fst2;
3068     uint32_t fsth2;
3069
3070     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3071     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3072     update_fcr31(env, GETPC());
3073     return ((uint64_t)fsth2 << 32) | fst2;
3074 }
3075
3076 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3077 {
3078     uint64_t fdt2;
3079
3080     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3081     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3082     update_fcr31(env, GETPC());
3083     return fdt2;
3084 }
3085
3086 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3087 {
3088     uint32_t fst2;
3089
3090     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3091     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3092     update_fcr31(env, GETPC());
3093     return fst2;
3094 }
3095
3096 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3097 {
3098     uint32_t fst2;
3099     uint32_t fsth2;
3100
3101     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3102     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3103     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3104     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3105     update_fcr31(env, GETPC());
3106     return ((uint64_t)fsth2 << 32) | fst2;
3107 }
3108
3109 #define FLOAT_RINT(name, bits)                                              \
3110 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3111                                           uint ## bits ## _t fs)            \
3112 {                                                                           \
3113     uint ## bits ## _t fdret;                                               \
3114                                                                             \
3115     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3116     update_fcr31(env, GETPC());                                             \
3117     return fdret;                                                           \
3118 }
3119
3120 FLOAT_RINT(rint_s, 32)
3121 FLOAT_RINT(rint_d, 64)
3122 #undef FLOAT_RINT
3123
3124 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3125 #define FLOAT_CLASS_QUIET_NAN          0x002
3126 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3127 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3128 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3129 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3130 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3131 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3132 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3133 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3134
3135 #define FLOAT_CLASS(name, bits)                                      \
3136 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3137 {                                                                    \
3138     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3139         return FLOAT_CLASS_SIGNALING_NAN;                            \
3140     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3141         return FLOAT_CLASS_QUIET_NAN;                                \
3142     } else if (float ## bits ## _is_neg(arg)) {                      \
3143         if (float ## bits ## _is_infinity(arg)) {                    \
3144             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3145         } else if (float ## bits ## _is_zero(arg)) {                 \
3146             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3147         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3148             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3149         } else {                                                     \
3150             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3151         }                                                            \
3152     } else {                                                         \
3153         if (float ## bits ## _is_infinity(arg)) {                    \
3154             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3155         } else if (float ## bits ## _is_zero(arg)) {                 \
3156             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3157         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3158             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3159         } else {                                                     \
3160             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3161         }                                                            \
3162     }                                                                \
3163 }
3164
3165 FLOAT_CLASS(class_s, 32)
3166 FLOAT_CLASS(class_d, 64)
3167 #undef FLOAT_CLASS
3168
3169 /* binary operations */
3170 #define FLOAT_BINOP(name)                                          \
3171 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3172                                      uint64_t fdt0, uint64_t fdt1) \
3173 {                                                                  \
3174     uint64_t dt2;                                                  \
3175                                                                    \
3176     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3177     update_fcr31(env, GETPC());                                    \
3178     return dt2;                                                    \
3179 }                                                                  \
3180                                                                    \
3181 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3182                                      uint32_t fst0, uint32_t fst1) \
3183 {                                                                  \
3184     uint32_t wt2;                                                  \
3185                                                                    \
3186     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3187     update_fcr31(env, GETPC());                                    \
3188     return wt2;                                                    \
3189 }                                                                  \
3190                                                                    \
3191 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3192                                       uint64_t fdt0,               \
3193                                       uint64_t fdt1)               \
3194 {                                                                  \
3195     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3196     uint32_t fsth0 = fdt0 >> 32;                                   \
3197     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3198     uint32_t fsth1 = fdt1 >> 32;                                   \
3199     uint32_t wt2;                                                  \
3200     uint32_t wth2;                                                 \
3201                                                                    \
3202     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3203     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3204     update_fcr31(env, GETPC());                                    \
3205     return ((uint64_t)wth2 << 32) | wt2;                           \
3206 }
3207
3208 FLOAT_BINOP(add)
3209 FLOAT_BINOP(sub)
3210 FLOAT_BINOP(mul)
3211 FLOAT_BINOP(div)
3212 #undef FLOAT_BINOP
3213
3214 /* MIPS specific binary operations */
3215 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3216 {
3217     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3218     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3219     update_fcr31(env, GETPC());
3220     return fdt2;
3221 }
3222
3223 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3224 {
3225     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3226     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3227     update_fcr31(env, GETPC());
3228     return fst2;
3229 }
3230
3231 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3232 {
3233     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3234     uint32_t fsth0 = fdt0 >> 32;
3235     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3236     uint32_t fsth2 = fdt2 >> 32;
3237
3238     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3239     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3240     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3241     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3242     update_fcr31(env, GETPC());
3243     return ((uint64_t)fsth2 << 32) | fst2;
3244 }
3245
3246 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3247 {
3248     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3249     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3250     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3251     update_fcr31(env, GETPC());
3252     return fdt2;
3253 }
3254
3255 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3256 {
3257     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3258     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3259     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3260     update_fcr31(env, GETPC());
3261     return fst2;
3262 }
3263
3264 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3265 {
3266     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3267     uint32_t fsth0 = fdt0 >> 32;
3268     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3269     uint32_t fsth2 = fdt2 >> 32;
3270
3271     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3272     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3273     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3274     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3275     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3276     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3277     update_fcr31(env, GETPC());
3278     return ((uint64_t)fsth2 << 32) | fst2;
3279 }
3280
3281 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3282 {
3283     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3284     uint32_t fsth0 = fdt0 >> 32;
3285     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3286     uint32_t fsth1 = fdt1 >> 32;
3287     uint32_t fst2;
3288     uint32_t fsth2;
3289
3290     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3291     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3292     update_fcr31(env, GETPC());
3293     return ((uint64_t)fsth2 << 32) | fst2;
3294 }
3295
3296 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3297 {
3298     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3299     uint32_t fsth0 = fdt0 >> 32;
3300     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3301     uint32_t fsth1 = fdt1 >> 32;
3302     uint32_t fst2;
3303     uint32_t fsth2;
3304
3305     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3306     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3307     update_fcr31(env, GETPC());
3308     return ((uint64_t)fsth2 << 32) | fst2;
3309 }
3310
3311 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3312 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3313                                           uint ## bits ## _t fs,        \
3314                                           uint ## bits ## _t ft)        \
3315 {                                                                       \
3316     uint ## bits ## _t fdret;                                           \
3317                                                                         \
3318     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3319                                            &env->active_fpu.fp_status); \
3320     update_fcr31(env, GETPC());                                         \
3321     return fdret;                                                       \
3322 }
3323
3324 FLOAT_MINMAX(max_s, 32, maxnum)
3325 FLOAT_MINMAX(max_d, 64, maxnum)
3326 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3327 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3328
3329 FLOAT_MINMAX(min_s, 32, minnum)
3330 FLOAT_MINMAX(min_d, 64, minnum)
3331 FLOAT_MINMAX(mina_s, 32, minnummag)
3332 FLOAT_MINMAX(mina_d, 64, minnummag)
3333 #undef FLOAT_MINMAX
3334
3335 /* ternary operations */
3336 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3337 {                                                                    \
3338     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3339     if ((flags) & float_muladd_negate_c) {                           \
3340         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3341     } else {                                                         \
3342         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3343     }                                                                \
3344     if ((flags) & float_muladd_negate_result) {                      \
3345         a = prefix##_chs(a);                                         \
3346     }                                                                \
3347 }
3348
3349 /* FMA based operations */
3350 #define FLOAT_FMA(name, type)                                        \
3351 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3352                                      uint64_t fdt0, uint64_t fdt1,   \
3353                                      uint64_t fdt2)                  \
3354 {                                                                    \
3355     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3356     update_fcr31(env, GETPC());                                      \
3357     return fdt0;                                                     \
3358 }                                                                    \
3359                                                                      \
3360 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3361                                      uint32_t fst0, uint32_t fst1,   \
3362                                      uint32_t fst2)                  \
3363 {                                                                    \
3364     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3365     update_fcr31(env, GETPC());                                      \
3366     return fst0;                                                     \
3367 }                                                                    \
3368                                                                      \
3369 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3370                                       uint64_t fdt0, uint64_t fdt1,  \
3371                                       uint64_t fdt2)                 \
3372 {                                                                    \
3373     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3374     uint32_t fsth0 = fdt0 >> 32;                                     \
3375     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3376     uint32_t fsth1 = fdt1 >> 32;                                     \
3377     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3378     uint32_t fsth2 = fdt2 >> 32;                                     \
3379                                                                      \
3380     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3381     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3382     update_fcr31(env, GETPC());                                      \
3383     return ((uint64_t)fsth0 << 32) | fst0;                           \
3384 }
3385 FLOAT_FMA(madd, 0)
3386 FLOAT_FMA(msub, float_muladd_negate_c)
3387 FLOAT_FMA(nmadd, float_muladd_negate_result)
3388 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3389 #undef FLOAT_FMA
3390
3391 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3392 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3393                                           uint ## bits ## _t fs,        \
3394                                           uint ## bits ## _t ft,        \
3395                                           uint ## bits ## _t fd)        \
3396 {                                                                       \
3397     uint ## bits ## _t fdret;                                           \
3398                                                                         \
3399     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3400                                      &env->active_fpu.fp_status);       \
3401     update_fcr31(env, GETPC());                                         \
3402     return fdret;                                                       \
3403 }
3404
3405 FLOAT_FMADDSUB(maddf_s, 32, 0)
3406 FLOAT_FMADDSUB(maddf_d, 64, 0)
3407 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3408 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3409 #undef FLOAT_FMADDSUB
3410
3411 /* compare operations */
3412 #define FOP_COND_D(op, cond)                                   \
3413 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3414                          uint64_t fdt1, int cc)                \
3415 {                                                              \
3416     int c;                                                     \
3417     c = cond;                                                  \
3418     update_fcr31(env, GETPC());                                \
3419     if (c)                                                     \
3420         SET_FP_COND(cc, env->active_fpu);                      \
3421     else                                                       \
3422         CLEAR_FP_COND(cc, env->active_fpu);                    \
3423 }                                                              \
3424 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3425                             uint64_t fdt1, int cc)             \
3426 {                                                              \
3427     int c;                                                     \
3428     fdt0 = float64_abs(fdt0);                                  \
3429     fdt1 = float64_abs(fdt1);                                  \
3430     c = cond;                                                  \
3431     update_fcr31(env, GETPC());                                \
3432     if (c)                                                     \
3433         SET_FP_COND(cc, env->active_fpu);                      \
3434     else                                                       \
3435         CLEAR_FP_COND(cc, env->active_fpu);                    \
3436 }
3437
3438 /* NOTE: the comma operator will make "cond" to eval to false,
3439  * but float64_unordered_quiet() is still called. */
3440 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3441 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3442 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3443 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3444 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3445 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3446 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3447 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3448 /* NOTE: the comma operator will make "cond" to eval to false,
3449  * but float64_unordered() is still called. */
3450 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3451 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3452 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3453 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3454 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3455 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3456 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3457 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3458
3459 #define FOP_COND_S(op, cond)                                   \
3460 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3461                          uint32_t fst1, int cc)                \
3462 {                                                              \
3463     int c;                                                     \
3464     c = cond;                                                  \
3465     update_fcr31(env, GETPC());                                \
3466     if (c)                                                     \
3467         SET_FP_COND(cc, env->active_fpu);                      \
3468     else                                                       \
3469         CLEAR_FP_COND(cc, env->active_fpu);                    \
3470 }                                                              \
3471 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3472                             uint32_t fst1, int cc)             \
3473 {                                                              \
3474     int c;                                                     \
3475     fst0 = float32_abs(fst0);                                  \
3476     fst1 = float32_abs(fst1);                                  \
3477     c = cond;                                                  \
3478     update_fcr31(env, GETPC());                                \
3479     if (c)                                                     \
3480         SET_FP_COND(cc, env->active_fpu);                      \
3481     else                                                       \
3482         CLEAR_FP_COND(cc, env->active_fpu);                    \
3483 }
3484
3485 /* NOTE: the comma operator will make "cond" to eval to false,
3486  * but float32_unordered_quiet() is still called. */
3487 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3488 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3489 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3490 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3491 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3492 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3493 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3494 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3495 /* NOTE: the comma operator will make "cond" to eval to false,
3496  * but float32_unordered() is still called. */
3497 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3498 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3499 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3500 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3501 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3502 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3503 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3504 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3505
3506 #define FOP_COND_PS(op, condl, condh)                           \
3507 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3508                           uint64_t fdt1, int cc)                \
3509 {                                                               \
3510     uint32_t fst0, fsth0, fst1, fsth1;                          \
3511     int ch, cl;                                                 \
3512     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3513     fsth0 = fdt0 >> 32;                                         \
3514     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3515     fsth1 = fdt1 >> 32;                                         \
3516     cl = condl;                                                 \
3517     ch = condh;                                                 \
3518     update_fcr31(env, GETPC());                                 \
3519     if (cl)                                                     \
3520         SET_FP_COND(cc, env->active_fpu);                       \
3521     else                                                        \
3522         CLEAR_FP_COND(cc, env->active_fpu);                     \
3523     if (ch)                                                     \
3524         SET_FP_COND(cc + 1, env->active_fpu);                   \
3525     else                                                        \
3526         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3527 }                                                               \
3528 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3529                              uint64_t fdt1, int cc)             \
3530 {                                                               \
3531     uint32_t fst0, fsth0, fst1, fsth1;                          \
3532     int ch, cl;                                                 \
3533     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3534     fsth0 = float32_abs(fdt0 >> 32);                            \
3535     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3536     fsth1 = float32_abs(fdt1 >> 32);                            \
3537     cl = condl;                                                 \
3538     ch = condh;                                                 \
3539     update_fcr31(env, GETPC());                                 \
3540     if (cl)                                                     \
3541         SET_FP_COND(cc, env->active_fpu);                       \
3542     else                                                        \
3543         CLEAR_FP_COND(cc, env->active_fpu);                     \
3544     if (ch)                                                     \
3545         SET_FP_COND(cc + 1, env->active_fpu);                   \
3546     else                                                        \
3547         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3548 }
3549
3550 /* NOTE: the comma operator will make "cond" to eval to false,
3551  * but float32_unordered_quiet() is still called. */
3552 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3553                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3554 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3555                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3556 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3557                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3558 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3559                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3560 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3561                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3562 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3563                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3564 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3565                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3566 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3567                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3568 /* NOTE: the comma operator will make "cond" to eval to false,
3569  * but float32_unordered() is still called. */
3570 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3571                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3572 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3573                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3574 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3575                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3576 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3577                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3578 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3579                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3580 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3581                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3582 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3583                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3584 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3585                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3586
3587 /* R6 compare operations */
3588 #define FOP_CONDN_D(op, cond)                                       \
3589 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3590                          uint64_t fdt1)                             \
3591 {                                                                   \
3592     uint64_t c;                                                     \
3593     c = cond;                                                       \
3594     update_fcr31(env, GETPC());                                     \
3595     if (c) {                                                        \
3596         return -1;                                                  \
3597     } else {                                                        \
3598         return 0;                                                   \
3599     }                                                               \
3600 }
3601
3602 /* NOTE: the comma operator will make "cond" to eval to false,
3603  * but float64_unordered_quiet() is still called. */
3604 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3605 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3606 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3607 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3608                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3609 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3610 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3611                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3612 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3613 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3614                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3615 /* NOTE: the comma operator will make "cond" to eval to false,
3616  * but float64_unordered() is still called. */
3617 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3618 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3619 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3620 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3621                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3622 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3623 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3624                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3625 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3626 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3627                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3628 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3629                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3630 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3631                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3632                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3633 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3634                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3635 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3636                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3637 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3638                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3639                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3640 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3641                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3642
3643 #define FOP_CONDN_S(op, cond)                                       \
3644 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3645                          uint32_t fst1)                             \
3646 {                                                                   \
3647     uint64_t c;                                                     \
3648     c = cond;                                                       \
3649     update_fcr31(env, GETPC());                                     \
3650     if (c) {                                                        \
3651         return -1;                                                  \
3652     } else {                                                        \
3653         return 0;                                                   \
3654     }                                                               \
3655 }
3656
3657 /* NOTE: the comma operator will make "cond" to eval to false,
3658  * but float32_unordered_quiet() is still called. */
3659 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3660 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3661 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3662 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3663                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3664 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3665 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3666                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3667 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3668 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3669                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3670 /* NOTE: the comma operator will make "cond" to eval to false,
3671  * but float32_unordered() is still called. */
3672 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3673 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3674 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3675 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3676                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3677 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3678 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3679                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3680 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3681 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3682                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3683 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3684                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3685 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3686                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3687                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3688 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3689                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3690 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3691                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3692 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3693                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3694                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3695 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3696                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3697
3698 /* MSA */
3699 /* Data format min and max values */
3700 #define DF_BITS(df) (1 << ((df) + 3))
3701
3702 /* Element-by-element access macros */
3703 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3704
3705 #if !defined(CONFIG_USER_ONLY)
3706 #define MEMOP_IDX(DF)                                           \
3707         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3708                                         cpu_mmu_index(env, false));
3709 #else
3710 #define MEMOP_IDX(DF)
3711 #endif
3712
3713 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3714 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3715                             target_ulong addr)                          \
3716 {                                                                       \
3717     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3718     wr_t wx;                                                            \
3719     int i;                                                              \
3720     MEMOP_IDX(DF)                                                       \
3721     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3722         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3723     }                                                                   \
3724     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3725 }
3726
3727 #if !defined(CONFIG_USER_ONLY)
3728 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3729 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3730 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3731 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3732 #else
3733 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3734 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3735 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3736 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3737 #endif
3738
3739 #define MSA_PAGESPAN(x) \
3740         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3741
3742 static inline void ensure_writable_pages(CPUMIPSState *env,
3743                                          target_ulong addr,
3744                                          int mmu_idx,
3745                                          uintptr_t retaddr)
3746 {
3747 #if !defined(CONFIG_USER_ONLY)
3748     target_ulong page_addr;
3749     if (unlikely(MSA_PAGESPAN(addr))) {
3750         /* first page */
3751         probe_write(env, addr, mmu_idx, retaddr);
3752         /* second page */
3753         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3754         probe_write(env, page_addr, mmu_idx, retaddr);
3755     }
3756 #endif
3757 }
3758
3759 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3760 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3761                             target_ulong addr)                          \
3762 {                                                                       \
3763     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3764     int mmu_idx = cpu_mmu_index(env, false);                            \
3765     int i;                                                              \
3766     MEMOP_IDX(DF)                                                       \
3767     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3768     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3769         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3770     }                                                                   \
3771 }
3772
3773 #if !defined(CONFIG_USER_ONLY)
3774 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3775 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3776 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3777 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3778 #else
3779 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3780 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3781 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3782 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3783 #endif