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qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCore
[qemu.git] / target-ppc / translate.c
blob2f1c59166eda2b1ea1adf62ce30d519c11ad88ed
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_reset_fpstatus(void)
254 {
255 gen_helper_reset_fpstatus(cpu_env);
256 }
257
258 static inline void gen_compute_fprf(TCGv_i64 arg)
259 {
260 gen_helper_compute_fprf(cpu_env, arg);
261 gen_helper_float_check_status(cpu_env);
262 }
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 void gen_update_current_nip(void *opaque)
281 {
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285 }
286
287 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
288 {
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static void gen_debug_exception(DisasContext *ctx)
314 {
315 TCGv_i32 t0;
316
317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
319 gen_update_nip(ctx, ctx->nip);
320 }
321 t0 = tcg_const_i32(EXCP_DEBUG);
322 gen_helper_raise_exception(cpu_env, t0);
323 tcg_temp_free_i32(t0);
324 }
325
326 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
327 {
328 /* Will be converted to program check if needed */
329 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
330 }
331
332 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
333 {
334 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
335 }
336
337 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
338 {
339 /* Will be converted to program check if needed */
340 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
341 }
342
343 /* Stop translation */
344 static inline void gen_stop_exception(DisasContext *ctx)
345 {
346 gen_update_nip(ctx, ctx->nip);
347 ctx->exception = POWERPC_EXCP_STOP;
348 }
349
350 #ifndef CONFIG_USER_ONLY
351 /* No need to update nip here, as execution flow will change */
352 static inline void gen_sync_exception(DisasContext *ctx)
353 {
354 ctx->exception = POWERPC_EXCP_SYNC;
355 }
356 #endif
357
358 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
359 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
360
361 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
362 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
363
364 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
369
370 typedef struct opcode_t {
371 unsigned char opc1, opc2, opc3;
372 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
373 unsigned char pad[5];
374 #else
375 unsigned char pad[1];
376 #endif
377 opc_handler_t handler;
378 const char *oname;
379 } opcode_t;
380
381 /* Helpers for priv. check */
382 #define GEN_PRIV \
383 do { \
384 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
385 } while (0)
386
387 #if defined(CONFIG_USER_ONLY)
388 #define CHK_HV GEN_PRIV
389 #define CHK_SV GEN_PRIV
390 #define CHK_HVRM GEN_PRIV
391 #else
392 #define CHK_HV \
393 do { \
394 if (unlikely(ctx->pr || !ctx->hv)) { \
395 GEN_PRIV; \
396 } \
397 } while (0)
398 #define CHK_SV \
399 do { \
400 if (unlikely(ctx->pr)) { \
401 GEN_PRIV; \
402 } \
403 } while (0)
404 #define CHK_HVRM \
405 do { \
406 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
407 GEN_PRIV; \
408 } \
409 } while (0)
410 #endif
411
412 #define CHK_NONE
413
414
415 /*****************************************************************************/
416 /*** Instruction decoding ***/
417 #define EXTRACT_HELPER(name, shift, nb) \
418 static inline uint32_t name(uint32_t opcode) \
419 { \
420 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
421 }
422
423 #define EXTRACT_SHELPER(name, shift, nb) \
424 static inline int32_t name(uint32_t opcode) \
425 { \
426 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
427 }
428
429 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
430 static inline uint32_t name(uint32_t opcode) \
431 { \
432 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
433 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
434 }
435 /* Opcode part 1 */
436 EXTRACT_HELPER(opc1, 26, 6);
437 /* Opcode part 2 */
438 EXTRACT_HELPER(opc2, 1, 5);
439 /* Opcode part 3 */
440 EXTRACT_HELPER(opc3, 6, 5);
441 /* Update Cr0 flags */
442 EXTRACT_HELPER(Rc, 0, 1);
443 /* Update Cr6 flags (Altivec) */
444 EXTRACT_HELPER(Rc21, 10, 1);
445 /* Destination */
446 EXTRACT_HELPER(rD, 21, 5);
447 /* Source */
448 EXTRACT_HELPER(rS, 21, 5);
449 /* First operand */
450 EXTRACT_HELPER(rA, 16, 5);
451 /* Second operand */
452 EXTRACT_HELPER(rB, 11, 5);
453 /* Third operand */
454 EXTRACT_HELPER(rC, 6, 5);
455 /*** Get CRn ***/
456 EXTRACT_HELPER(crfD, 23, 3);
457 EXTRACT_HELPER(crfS, 18, 3);
458 EXTRACT_HELPER(crbD, 21, 5);
459 EXTRACT_HELPER(crbA, 16, 5);
460 EXTRACT_HELPER(crbB, 11, 5);
461 /* SPR / TBL */
462 EXTRACT_HELPER(_SPR, 11, 10);
463 static inline uint32_t SPR(uint32_t opcode)
464 {
465 uint32_t sprn = _SPR(opcode);
466
467 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
468 }
469 /*** Get constants ***/
470 /* 16 bits signed immediate value */
471 EXTRACT_SHELPER(SIMM, 0, 16);
472 /* 16 bits unsigned immediate value */
473 EXTRACT_HELPER(UIMM, 0, 16);
474 /* 5 bits signed immediate value */
475 EXTRACT_HELPER(SIMM5, 16, 5);
476 /* 5 bits signed immediate value */
477 EXTRACT_HELPER(UIMM5, 16, 5);
478 /* Bit count */
479 EXTRACT_HELPER(NB, 11, 5);
480 /* Shift count */
481 EXTRACT_HELPER(SH, 11, 5);
482 /* Vector shift count */
483 EXTRACT_HELPER(VSH, 6, 4);
484 /* Mask start */
485 EXTRACT_HELPER(MB, 6, 5);
486 /* Mask end */
487 EXTRACT_HELPER(ME, 1, 5);
488 /* Trap operand */
489 EXTRACT_HELPER(TO, 21, 5);
490
491 EXTRACT_HELPER(CRM, 12, 8);
492
493 #ifndef CONFIG_USER_ONLY
494 EXTRACT_HELPER(SR, 16, 4);
495 #endif
496
497 /* mtfsf/mtfsfi */
498 EXTRACT_HELPER(FPBF, 23, 3);
499 EXTRACT_HELPER(FPIMM, 12, 4);
500 EXTRACT_HELPER(FPL, 25, 1);
501 EXTRACT_HELPER(FPFLM, 17, 8);
502 EXTRACT_HELPER(FPW, 16, 1);
503
504 /*** Jump target decoding ***/
505 /* Immediate address */
506 static inline target_ulong LI(uint32_t opcode)
507 {
508 return (opcode >> 0) & 0x03FFFFFC;
509 }
510
511 static inline uint32_t BD(uint32_t opcode)
512 {
513 return (opcode >> 0) & 0xFFFC;
514 }
515
516 EXTRACT_HELPER(BO, 21, 5);
517 EXTRACT_HELPER(BI, 16, 5);
518 /* Absolute/relative address */
519 EXTRACT_HELPER(AA, 1, 1);
520 /* Link */
521 EXTRACT_HELPER(LK, 0, 1);
522
523 /* DFP Z22-form */
524 EXTRACT_HELPER(DCM, 10, 6)
525
526 /* DFP Z23-form */
527 EXTRACT_HELPER(RMC, 9, 2)
528
529 /* Create a mask between <start> and <end> bits */
530 static inline target_ulong MASK(uint32_t start, uint32_t end)
531 {
532 target_ulong ret;
533
534 #if defined(TARGET_PPC64)
535 if (likely(start == 0)) {
536 ret = UINT64_MAX << (63 - end);
537 } else if (likely(end == 63)) {
538 ret = UINT64_MAX >> start;
539 }
540 #else
541 if (likely(start == 0)) {
542 ret = UINT32_MAX << (31 - end);
543 } else if (likely(end == 31)) {
544 ret = UINT32_MAX >> start;
545 }
546 #endif
547 else {
548 ret = (((target_ulong)(-1ULL)) >> (start)) ^
549 (((target_ulong)(-1ULL) >> (end)) >> 1);
550 if (unlikely(start > end))
551 return ~ret;
552 }
553
554 return ret;
555 }
556
557 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
558 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
559 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
560 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
561 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
562 EXTRACT_HELPER(DM, 8, 2);
563 EXTRACT_HELPER(UIM, 16, 2);
564 EXTRACT_HELPER(SHW, 8, 2);
565 EXTRACT_HELPER(SP, 19, 2);
566 /*****************************************************************************/
567 /* PowerPC instructions table */
568
569 #if defined(DO_PPC_STATISTICS)
570 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 .oname = stringify(name), \
582 }, \
583 .oname = stringify(name), \
584 }
585 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
586 { \
587 .opc1 = op1, \
588 .opc2 = op2, \
589 .opc3 = op3, \
590 .pad = { 0, }, \
591 .handler = { \
592 .inval1 = invl1, \
593 .inval2 = invl2, \
594 .type = _typ, \
595 .type2 = _typ2, \
596 .handler = &gen_##name, \
597 .oname = stringify(name), \
598 }, \
599 .oname = stringify(name), \
600 }
601 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
602 { \
603 .opc1 = op1, \
604 .opc2 = op2, \
605 .opc3 = op3, \
606 .pad = { 0, }, \
607 .handler = { \
608 .inval1 = invl, \
609 .type = _typ, \
610 .type2 = _typ2, \
611 .handler = &gen_##name, \
612 .oname = onam, \
613 }, \
614 .oname = onam, \
615 }
616 #else
617 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
618 { \
619 .opc1 = op1, \
620 .opc2 = op2, \
621 .opc3 = op3, \
622 .pad = { 0, }, \
623 .handler = { \
624 .inval1 = invl, \
625 .type = _typ, \
626 .type2 = _typ2, \
627 .handler = &gen_##name, \
628 }, \
629 .oname = stringify(name), \
630 }
631 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
632 { \
633 .opc1 = op1, \
634 .opc2 = op2, \
635 .opc3 = op3, \
636 .pad = { 0, }, \
637 .handler = { \
638 .inval1 = invl1, \
639 .inval2 = invl2, \
640 .type = _typ, \
641 .type2 = _typ2, \
642 .handler = &gen_##name, \
643 }, \
644 .oname = stringify(name), \
645 }
646 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
647 { \
648 .opc1 = op1, \
649 .opc2 = op2, \
650 .opc3 = op3, \
651 .pad = { 0, }, \
652 .handler = { \
653 .inval1 = invl, \
654 .type = _typ, \
655 .type2 = _typ2, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = onam, \
659 }
660 #endif
661
662 /* SPR load/store helpers */
663 static inline void gen_load_spr(TCGv t, int reg)
664 {
665 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
666 }
667
668 static inline void gen_store_spr(int reg, TCGv t)
669 {
670 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
671 }
672
673 /* Invalid instruction */
674 static void gen_invalid(DisasContext *ctx)
675 {
676 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
677 }
678
679 static opc_handler_t invalid_handler = {
680 .inval1 = 0xFFFFFFFF,
681 .inval2 = 0xFFFFFFFF,
682 .type = PPC_NONE,
683 .type2 = PPC_NONE,
684 .handler = gen_invalid,
685 };
686
687 /*** Integer comparison ***/
688
689 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
690 {
691 TCGv t0 = tcg_temp_new();
692 TCGv_i32 t1 = tcg_temp_new_i32();
693
694 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
695
696 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
697 tcg_gen_trunc_tl_i32(t1, t0);
698 tcg_gen_shli_i32(t1, t1, CRF_LT);
699 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
700
701 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
702 tcg_gen_trunc_tl_i32(t1, t0);
703 tcg_gen_shli_i32(t1, t1, CRF_GT);
704 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
705
706 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
707 tcg_gen_trunc_tl_i32(t1, t0);
708 tcg_gen_shli_i32(t1, t1, CRF_EQ);
709 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
710
711 tcg_temp_free(t0);
712 tcg_temp_free_i32(t1);
713 }
714
715 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
716 {
717 TCGv t0 = tcg_const_tl(arg1);
718 gen_op_cmp(arg0, t0, s, crf);
719 tcg_temp_free(t0);
720 }
721
722 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
723 {
724 TCGv t0, t1;
725 t0 = tcg_temp_new();
726 t1 = tcg_temp_new();
727 if (s) {
728 tcg_gen_ext32s_tl(t0, arg0);
729 tcg_gen_ext32s_tl(t1, arg1);
730 } else {
731 tcg_gen_ext32u_tl(t0, arg0);
732 tcg_gen_ext32u_tl(t1, arg1);
733 }
734 gen_op_cmp(t0, t1, s, crf);
735 tcg_temp_free(t1);
736 tcg_temp_free(t0);
737 }
738
739 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
740 {
741 TCGv t0 = tcg_const_tl(arg1);
742 gen_op_cmp32(arg0, t0, s, crf);
743 tcg_temp_free(t0);
744 }
745
746 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
747 {
748 if (NARROW_MODE(ctx)) {
749 gen_op_cmpi32(reg, 0, 1, 0);
750 } else {
751 gen_op_cmpi(reg, 0, 1, 0);
752 }
753 }
754
755 /* cmp */
756 static void gen_cmp(DisasContext *ctx)
757 {
758 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
759 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
760 1, crfD(ctx->opcode));
761 } else {
762 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
763 1, crfD(ctx->opcode));
764 }
765 }
766
767 /* cmpi */
768 static void gen_cmpi(DisasContext *ctx)
769 {
770 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
771 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
772 1, crfD(ctx->opcode));
773 } else {
774 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
775 1, crfD(ctx->opcode));
776 }
777 }
778
779 /* cmpl */
780 static void gen_cmpl(DisasContext *ctx)
781 {
782 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
783 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
784 0, crfD(ctx->opcode));
785 } else {
786 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 0, crfD(ctx->opcode));
788 }
789 }
790
791 /* cmpli */
792 static void gen_cmpli(DisasContext *ctx)
793 {
794 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
795 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
796 0, crfD(ctx->opcode));
797 } else {
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
799 0, crfD(ctx->opcode));
800 }
801 }
802
803 /* isel (PowerPC 2.03 specification) */
804 static void gen_isel(DisasContext *ctx)
805 {
806 uint32_t bi = rC(ctx->opcode);
807 uint32_t mask = 0x08 >> (bi & 0x03);
808 TCGv t0 = tcg_temp_new();
809 TCGv zr;
810
811 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
812 tcg_gen_andi_tl(t0, t0, mask);
813
814 zr = tcg_const_tl(0);
815 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
816 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
817 cpu_gpr[rB(ctx->opcode)]);
818 tcg_temp_free(zr);
819 tcg_temp_free(t0);
820 }
821
822 /* cmpb: PowerPC 2.05 specification */
823 static void gen_cmpb(DisasContext *ctx)
824 {
825 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
826 cpu_gpr[rB(ctx->opcode)]);
827 }
828
829 /*** Integer arithmetic ***/
830
831 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
832 TCGv arg1, TCGv arg2, int sub)
833 {
834 TCGv t0 = tcg_temp_new();
835
836 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
837 tcg_gen_xor_tl(t0, arg1, arg2);
838 if (sub) {
839 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
840 } else {
841 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
842 }
843 tcg_temp_free(t0);
844 if (NARROW_MODE(ctx)) {
845 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
846 }
847 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
848 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
849 }
850
851 /* Common add function */
852 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
853 TCGv arg2, bool add_ca, bool compute_ca,
854 bool compute_ov, bool compute_rc0)
855 {
856 TCGv t0 = ret;
857
858 if (compute_ca || compute_ov) {
859 t0 = tcg_temp_new();
860 }
861
862 if (compute_ca) {
863 if (NARROW_MODE(ctx)) {
864 /* Caution: a non-obvious corner case of the spec is that we
865 must produce the *entire* 64-bit addition, but produce the
866 carry into bit 32. */
867 TCGv t1 = tcg_temp_new();
868 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
869 tcg_gen_add_tl(t0, arg1, arg2);
870 if (add_ca) {
871 tcg_gen_add_tl(t0, t0, cpu_ca);
872 }
873 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
874 tcg_temp_free(t1);
875 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
876 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
877 } else {
878 TCGv zero = tcg_const_tl(0);
879 if (add_ca) {
880 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
881 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
882 } else {
883 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
884 }
885 tcg_temp_free(zero);
886 }
887 } else {
888 tcg_gen_add_tl(t0, arg1, arg2);
889 if (add_ca) {
890 tcg_gen_add_tl(t0, t0, cpu_ca);
891 }
892 }
893
894 if (compute_ov) {
895 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
896 }
897 if (unlikely(compute_rc0)) {
898 gen_set_Rc0(ctx, t0);
899 }
900
901 if (!TCGV_EQUAL(t0, ret)) {
902 tcg_gen_mov_tl(ret, t0);
903 tcg_temp_free(t0);
904 }
905 }
906 /* Add functions with two operands */
907 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
908 static void glue(gen_, name)(DisasContext *ctx) \
909 { \
910 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
911 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
912 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
913 }
914 /* Add functions with one operand and one immediate */
915 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
916 add_ca, compute_ca, compute_ov) \
917 static void glue(gen_, name)(DisasContext *ctx) \
918 { \
919 TCGv t0 = tcg_const_tl(const_val); \
920 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
921 cpu_gpr[rA(ctx->opcode)], t0, \
922 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
923 tcg_temp_free(t0); \
924 }
925
926 /* add add. addo addo. */
927 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
928 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
929 /* addc addc. addco addco. */
930 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
931 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
932 /* adde adde. addeo addeo. */
933 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
934 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
935 /* addme addme. addmeo addmeo. */
936 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
937 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
938 /* addze addze. addzeo addzeo.*/
939 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
940 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
941 /* addi */
942 static void gen_addi(DisasContext *ctx)
943 {
944 target_long simm = SIMM(ctx->opcode);
945
946 if (rA(ctx->opcode) == 0) {
947 /* li case */
948 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
949 } else {
950 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
951 cpu_gpr[rA(ctx->opcode)], simm);
952 }
953 }
954 /* addic addic.*/
955 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
956 {
957 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
958 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
959 c, 0, 1, 0, compute_rc0);
960 tcg_temp_free(c);
961 }
962
963 static void gen_addic(DisasContext *ctx)
964 {
965 gen_op_addic(ctx, 0);
966 }
967
968 static void gen_addic_(DisasContext *ctx)
969 {
970 gen_op_addic(ctx, 1);
971 }
972
973 /* addis */
974 static void gen_addis(DisasContext *ctx)
975 {
976 target_long simm = SIMM(ctx->opcode);
977
978 if (rA(ctx->opcode) == 0) {
979 /* lis case */
980 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
981 } else {
982 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
983 cpu_gpr[rA(ctx->opcode)], simm << 16);
984 }
985 }
986
987 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
988 TCGv arg2, int sign, int compute_ov)
989 {
990 TCGLabel *l1 = gen_new_label();
991 TCGLabel *l2 = gen_new_label();
992 TCGv_i32 t0 = tcg_temp_local_new_i32();
993 TCGv_i32 t1 = tcg_temp_local_new_i32();
994
995 tcg_gen_trunc_tl_i32(t0, arg1);
996 tcg_gen_trunc_tl_i32(t1, arg2);
997 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
998 if (sign) {
999 TCGLabel *l3 = gen_new_label();
1000 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1001 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1002 gen_set_label(l3);
1003 tcg_gen_div_i32(t0, t0, t1);
1004 } else {
1005 tcg_gen_divu_i32(t0, t0, t1);
1006 }
1007 if (compute_ov) {
1008 tcg_gen_movi_tl(cpu_ov, 0);
1009 }
1010 tcg_gen_br(l2);
1011 gen_set_label(l1);
1012 if (sign) {
1013 tcg_gen_sari_i32(t0, t0, 31);
1014 } else {
1015 tcg_gen_movi_i32(t0, 0);
1016 }
1017 if (compute_ov) {
1018 tcg_gen_movi_tl(cpu_ov, 1);
1019 tcg_gen_movi_tl(cpu_so, 1);
1020 }
1021 gen_set_label(l2);
1022 tcg_gen_extu_i32_tl(ret, t0);
1023 tcg_temp_free_i32(t0);
1024 tcg_temp_free_i32(t1);
1025 if (unlikely(Rc(ctx->opcode) != 0))
1026 gen_set_Rc0(ctx, ret);
1027 }
1028 /* Div functions */
1029 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1030 static void glue(gen_, name)(DisasContext *ctx) \
1031 { \
1032 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1033 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1034 sign, compute_ov); \
1035 }
1036 /* divwu divwu. divwuo divwuo. */
1037 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1038 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1039 /* divw divw. divwo divwo. */
1040 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1041 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1042
1043 /* div[wd]eu[o][.] */
1044 #define GEN_DIVE(name, hlpr, compute_ov) \
1045 static void gen_##name(DisasContext *ctx) \
1046 { \
1047 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1048 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1049 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1050 tcg_temp_free_i32(t0); \
1051 if (unlikely(Rc(ctx->opcode) != 0)) { \
1052 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1053 } \
1054 }
1055
1056 GEN_DIVE(divweu, divweu, 0);
1057 GEN_DIVE(divweuo, divweu, 1);
1058 GEN_DIVE(divwe, divwe, 0);
1059 GEN_DIVE(divweo, divwe, 1);
1060
1061 #if defined(TARGET_PPC64)
1062 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1063 TCGv arg2, int sign, int compute_ov)
1064 {
1065 TCGLabel *l1 = gen_new_label();
1066 TCGLabel *l2 = gen_new_label();
1067
1068 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1069 if (sign) {
1070 TCGLabel *l3 = gen_new_label();
1071 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1072 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1073 gen_set_label(l3);
1074 tcg_gen_div_i64(ret, arg1, arg2);
1075 } else {
1076 tcg_gen_divu_i64(ret, arg1, arg2);
1077 }
1078 if (compute_ov) {
1079 tcg_gen_movi_tl(cpu_ov, 0);
1080 }
1081 tcg_gen_br(l2);
1082 gen_set_label(l1);
1083 if (sign) {
1084 tcg_gen_sari_i64(ret, arg1, 63);
1085 } else {
1086 tcg_gen_movi_i64(ret, 0);
1087 }
1088 if (compute_ov) {
1089 tcg_gen_movi_tl(cpu_ov, 1);
1090 tcg_gen_movi_tl(cpu_so, 1);
1091 }
1092 gen_set_label(l2);
1093 if (unlikely(Rc(ctx->opcode) != 0))
1094 gen_set_Rc0(ctx, ret);
1095 }
1096 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1097 static void glue(gen_, name)(DisasContext *ctx) \
1098 { \
1099 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1100 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1101 sign, compute_ov); \
1102 }
1103 /* divwu divwu. divwuo divwuo. */
1104 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1105 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1106 /* divw divw. divwo divwo. */
1107 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1108 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1109
1110 GEN_DIVE(divdeu, divdeu, 0);
1111 GEN_DIVE(divdeuo, divdeu, 1);
1112 GEN_DIVE(divde, divde, 0);
1113 GEN_DIVE(divdeo, divde, 1);
1114 #endif
1115
1116 /* mulhw mulhw. */
1117 static void gen_mulhw(DisasContext *ctx)
1118 {
1119 TCGv_i32 t0 = tcg_temp_new_i32();
1120 TCGv_i32 t1 = tcg_temp_new_i32();
1121
1122 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1123 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1124 tcg_gen_muls2_i32(t0, t1, t0, t1);
1125 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1126 tcg_temp_free_i32(t0);
1127 tcg_temp_free_i32(t1);
1128 if (unlikely(Rc(ctx->opcode) != 0))
1129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1130 }
1131
1132 /* mulhwu mulhwu. */
1133 static void gen_mulhwu(DisasContext *ctx)
1134 {
1135 TCGv_i32 t0 = tcg_temp_new_i32();
1136 TCGv_i32 t1 = tcg_temp_new_i32();
1137
1138 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1139 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1140 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1141 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1146 }
1147
1148 /* mullw mullw. */
1149 static void gen_mullw(DisasContext *ctx)
1150 {
1151 #if defined(TARGET_PPC64)
1152 TCGv_i64 t0, t1;
1153 t0 = tcg_temp_new_i64();
1154 t1 = tcg_temp_new_i64();
1155 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1156 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1157 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1158 tcg_temp_free(t0);
1159 tcg_temp_free(t1);
1160 #else
1161 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1162 cpu_gpr[rB(ctx->opcode)]);
1163 #endif
1164 if (unlikely(Rc(ctx->opcode) != 0))
1165 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1166 }
1167
1168 /* mullwo mullwo. */
1169 static void gen_mullwo(DisasContext *ctx)
1170 {
1171 TCGv_i32 t0 = tcg_temp_new_i32();
1172 TCGv_i32 t1 = tcg_temp_new_i32();
1173
1174 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1175 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1176 tcg_gen_muls2_i32(t0, t1, t0, t1);
1177 #if defined(TARGET_PPC64)
1178 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1179 #else
1180 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1181 #endif
1182
1183 tcg_gen_sari_i32(t0, t0, 31);
1184 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1185 tcg_gen_extu_i32_tl(cpu_ov, t0);
1186 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1187
1188 tcg_temp_free_i32(t0);
1189 tcg_temp_free_i32(t1);
1190 if (unlikely(Rc(ctx->opcode) != 0))
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192 }
1193
1194 /* mulli */
1195 static void gen_mulli(DisasContext *ctx)
1196 {
1197 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1198 SIMM(ctx->opcode));
1199 }
1200
1201 #if defined(TARGET_PPC64)
1202 /* mulhd mulhd. */
1203 static void gen_mulhd(DisasContext *ctx)
1204 {
1205 TCGv lo = tcg_temp_new();
1206 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1207 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1208 tcg_temp_free(lo);
1209 if (unlikely(Rc(ctx->opcode) != 0)) {
1210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1211 }
1212 }
1213
1214 /* mulhdu mulhdu. */
1215 static void gen_mulhdu(DisasContext *ctx)
1216 {
1217 TCGv lo = tcg_temp_new();
1218 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1219 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1220 tcg_temp_free(lo);
1221 if (unlikely(Rc(ctx->opcode) != 0)) {
1222 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1223 }
1224 }
1225
1226 /* mulld mulld. */
1227 static void gen_mulld(DisasContext *ctx)
1228 {
1229 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1230 cpu_gpr[rB(ctx->opcode)]);
1231 if (unlikely(Rc(ctx->opcode) != 0))
1232 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1233 }
1234
1235 /* mulldo mulldo. */
1236 static void gen_mulldo(DisasContext *ctx)
1237 {
1238 TCGv_i64 t0 = tcg_temp_new_i64();
1239 TCGv_i64 t1 = tcg_temp_new_i64();
1240
1241 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1242 cpu_gpr[rB(ctx->opcode)]);
1243 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1244
1245 tcg_gen_sari_i64(t0, t0, 63);
1246 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1247 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1248
1249 tcg_temp_free_i64(t0);
1250 tcg_temp_free_i64(t1);
1251
1252 if (unlikely(Rc(ctx->opcode) != 0)) {
1253 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1254 }
1255 }
1256 #endif
1257
1258 /* Common subf function */
1259 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1260 TCGv arg2, bool add_ca, bool compute_ca,
1261 bool compute_ov, bool compute_rc0)
1262 {
1263 TCGv t0 = ret;
1264
1265 if (compute_ca || compute_ov) {
1266 t0 = tcg_temp_new();
1267 }
1268
1269 if (compute_ca) {
1270 /* dest = ~arg1 + arg2 [+ ca]. */
1271 if (NARROW_MODE(ctx)) {
1272 /* Caution: a non-obvious corner case of the spec is that we
1273 must produce the *entire* 64-bit addition, but produce the
1274 carry into bit 32. */
1275 TCGv inv1 = tcg_temp_new();
1276 TCGv t1 = tcg_temp_new();
1277 tcg_gen_not_tl(inv1, arg1);
1278 if (add_ca) {
1279 tcg_gen_add_tl(t0, arg2, cpu_ca);
1280 } else {
1281 tcg_gen_addi_tl(t0, arg2, 1);
1282 }
1283 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1284 tcg_gen_add_tl(t0, t0, inv1);
1285 tcg_temp_free(inv1);
1286 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1287 tcg_temp_free(t1);
1288 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1289 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1290 } else if (add_ca) {
1291 TCGv zero, inv1 = tcg_temp_new();
1292 tcg_gen_not_tl(inv1, arg1);
1293 zero = tcg_const_tl(0);
1294 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1295 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1296 tcg_temp_free(zero);
1297 tcg_temp_free(inv1);
1298 } else {
1299 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1300 tcg_gen_sub_tl(t0, arg2, arg1);
1301 }
1302 } else if (add_ca) {
1303 /* Since we're ignoring carry-out, we can simplify the
1304 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1305 tcg_gen_sub_tl(t0, arg2, arg1);
1306 tcg_gen_add_tl(t0, t0, cpu_ca);
1307 tcg_gen_subi_tl(t0, t0, 1);
1308 } else {
1309 tcg_gen_sub_tl(t0, arg2, arg1);
1310 }
1311
1312 if (compute_ov) {
1313 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1314 }
1315 if (unlikely(compute_rc0)) {
1316 gen_set_Rc0(ctx, t0);
1317 }
1318
1319 if (!TCGV_EQUAL(t0, ret)) {
1320 tcg_gen_mov_tl(ret, t0);
1321 tcg_temp_free(t0);
1322 }
1323 }
1324 /* Sub functions with Two operands functions */
1325 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1326 static void glue(gen_, name)(DisasContext *ctx) \
1327 { \
1328 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1329 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1330 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1331 }
1332 /* Sub functions with one operand and one immediate */
1333 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1334 add_ca, compute_ca, compute_ov) \
1335 static void glue(gen_, name)(DisasContext *ctx) \
1336 { \
1337 TCGv t0 = tcg_const_tl(const_val); \
1338 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1339 cpu_gpr[rA(ctx->opcode)], t0, \
1340 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1341 tcg_temp_free(t0); \
1342 }
1343 /* subf subf. subfo subfo. */
1344 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1345 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1346 /* subfc subfc. subfco subfco. */
1347 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1348 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1349 /* subfe subfe. subfeo subfo. */
1350 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1351 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1352 /* subfme subfme. subfmeo subfmeo. */
1353 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1354 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1355 /* subfze subfze. subfzeo subfzeo.*/
1356 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1357 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1358
1359 /* subfic */
1360 static void gen_subfic(DisasContext *ctx)
1361 {
1362 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1363 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1364 c, 0, 1, 0, 0);
1365 tcg_temp_free(c);
1366 }
1367
1368 /* neg neg. nego nego. */
1369 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1370 {
1371 TCGv zero = tcg_const_tl(0);
1372 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1373 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1374 tcg_temp_free(zero);
1375 }
1376
1377 static void gen_neg(DisasContext *ctx)
1378 {
1379 gen_op_arith_neg(ctx, 0);
1380 }
1381
1382 static void gen_nego(DisasContext *ctx)
1383 {
1384 gen_op_arith_neg(ctx, 1);
1385 }
1386
1387 /*** Integer logical ***/
1388 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1389 static void glue(gen_, name)(DisasContext *ctx) \
1390 { \
1391 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1392 cpu_gpr[rB(ctx->opcode)]); \
1393 if (unlikely(Rc(ctx->opcode) != 0)) \
1394 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1395 }
1396
1397 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1398 static void glue(gen_, name)(DisasContext *ctx) \
1399 { \
1400 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1401 if (unlikely(Rc(ctx->opcode) != 0)) \
1402 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1403 }
1404
1405 /* and & and. */
1406 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1407 /* andc & andc. */
1408 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1409
1410 /* andi. */
1411 static void gen_andi_(DisasContext *ctx)
1412 {
1413 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1414 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1415 }
1416
1417 /* andis. */
1418 static void gen_andis_(DisasContext *ctx)
1419 {
1420 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1421 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1422 }
1423
1424 /* cntlzw */
1425 static void gen_cntlzw(DisasContext *ctx)
1426 {
1427 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1428 if (unlikely(Rc(ctx->opcode) != 0))
1429 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1430 }
1431 /* eqv & eqv. */
1432 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1433 /* extsb & extsb. */
1434 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1435 /* extsh & extsh. */
1436 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1437 /* nand & nand. */
1438 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1439 /* nor & nor. */
1440 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1441
1442 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1443 static void gen_pause(DisasContext *ctx)
1444 {
1445 TCGv_i32 t0 = tcg_const_i32(0);
1446 tcg_gen_st_i32(t0, cpu_env,
1447 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1448 tcg_temp_free_i32(t0);
1449
1450 /* Stop translation, this gives other CPUs a chance to run */
1451 gen_exception_err(ctx, EXCP_HLT, 1);
1452 }
1453 #endif /* defined(TARGET_PPC64) */
1454
1455 /* or & or. */
1456 static void gen_or(DisasContext *ctx)
1457 {
1458 int rs, ra, rb;
1459
1460 rs = rS(ctx->opcode);
1461 ra = rA(ctx->opcode);
1462 rb = rB(ctx->opcode);
1463 /* Optimisation for mr. ri case */
1464 if (rs != ra || rs != rb) {
1465 if (rs != rb)
1466 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1467 else
1468 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1469 if (unlikely(Rc(ctx->opcode) != 0))
1470 gen_set_Rc0(ctx, cpu_gpr[ra]);
1471 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1472 gen_set_Rc0(ctx, cpu_gpr[rs]);
1473 #if defined(TARGET_PPC64)
1474 } else {
1475 int prio = 0;
1476
1477 switch (rs) {
1478 case 1:
1479 /* Set process priority to low */
1480 prio = 2;
1481 break;
1482 case 6:
1483 /* Set process priority to medium-low */
1484 prio = 3;
1485 break;
1486 case 2:
1487 /* Set process priority to normal */
1488 prio = 4;
1489 break;
1490 #if !defined(CONFIG_USER_ONLY)
1491 case 31:
1492 if (!ctx->pr) {
1493 /* Set process priority to very low */
1494 prio = 1;
1495 }
1496 break;
1497 case 5:
1498 if (!ctx->pr) {
1499 /* Set process priority to medium-hight */
1500 prio = 5;
1501 }
1502 break;
1503 case 3:
1504 if (!ctx->pr) {
1505 /* Set process priority to high */
1506 prio = 6;
1507 }
1508 break;
1509 case 7:
1510 if (ctx->hv && !ctx->pr) {
1511 /* Set process priority to very high */
1512 prio = 7;
1513 }
1514 break;
1515 #endif
1516 default:
1517 /* nop */
1518 break;
1519 }
1520 if (prio) {
1521 TCGv t0 = tcg_temp_new();
1522 gen_load_spr(t0, SPR_PPR);
1523 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1524 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1525 gen_store_spr(SPR_PPR, t0);
1526 tcg_temp_free(t0);
1527 /* Pause us out of TCG otherwise spin loops with smt_low
1528 * eat too much CPU and the kernel hangs
1529 */
1530 #if !defined(CONFIG_USER_ONLY)
1531 gen_pause(ctx);
1532 #endif
1533 }
1534 #endif
1535 }
1536 }
1537 /* orc & orc. */
1538 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1539
1540 /* xor & xor. */
1541 static void gen_xor(DisasContext *ctx)
1542 {
1543 /* Optimisation for "set to zero" case */
1544 if (rS(ctx->opcode) != rB(ctx->opcode))
1545 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1546 else
1547 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1548 if (unlikely(Rc(ctx->opcode) != 0))
1549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1550 }
1551
1552 /* ori */
1553 static void gen_ori(DisasContext *ctx)
1554 {
1555 target_ulong uimm = UIMM(ctx->opcode);
1556
1557 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1558 return;
1559 }
1560 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1561 }
1562
1563 /* oris */
1564 static void gen_oris(DisasContext *ctx)
1565 {
1566 target_ulong uimm = UIMM(ctx->opcode);
1567
1568 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1569 /* NOP */
1570 return;
1571 }
1572 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1573 }
1574
1575 /* xori */
1576 static void gen_xori(DisasContext *ctx)
1577 {
1578 target_ulong uimm = UIMM(ctx->opcode);
1579
1580 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1581 /* NOP */
1582 return;
1583 }
1584 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1585 }
1586
1587 /* xoris */
1588 static void gen_xoris(DisasContext *ctx)
1589 {
1590 target_ulong uimm = UIMM(ctx->opcode);
1591
1592 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1593 /* NOP */
1594 return;
1595 }
1596 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1597 }
1598
1599 /* popcntb : PowerPC 2.03 specification */
1600 static void gen_popcntb(DisasContext *ctx)
1601 {
1602 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1603 }
1604
1605 static void gen_popcntw(DisasContext *ctx)
1606 {
1607 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1608 }
1609
1610 #if defined(TARGET_PPC64)
1611 /* popcntd: PowerPC 2.06 specification */
1612 static void gen_popcntd(DisasContext *ctx)
1613 {
1614 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1615 }
1616 #endif
1617
1618 /* prtyw: PowerPC 2.05 specification */
1619 static void gen_prtyw(DisasContext *ctx)
1620 {
1621 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1622 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1623 TCGv t0 = tcg_temp_new();
1624 tcg_gen_shri_tl(t0, rs, 16);
1625 tcg_gen_xor_tl(ra, rs, t0);
1626 tcg_gen_shri_tl(t0, ra, 8);
1627 tcg_gen_xor_tl(ra, ra, t0);
1628 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1629 tcg_temp_free(t0);
1630 }
1631
1632 #if defined(TARGET_PPC64)
1633 /* prtyd: PowerPC 2.05 specification */
1634 static void gen_prtyd(DisasContext *ctx)
1635 {
1636 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1637 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1638 TCGv t0 = tcg_temp_new();
1639 tcg_gen_shri_tl(t0, rs, 32);
1640 tcg_gen_xor_tl(ra, rs, t0);
1641 tcg_gen_shri_tl(t0, ra, 16);
1642 tcg_gen_xor_tl(ra, ra, t0);
1643 tcg_gen_shri_tl(t0, ra, 8);
1644 tcg_gen_xor_tl(ra, ra, t0);
1645 tcg_gen_andi_tl(ra, ra, 1);
1646 tcg_temp_free(t0);
1647 }
1648 #endif
1649
1650 #if defined(TARGET_PPC64)
1651 /* bpermd */
1652 static void gen_bpermd(DisasContext *ctx)
1653 {
1654 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1655 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1656 }
1657 #endif
1658
1659 #if defined(TARGET_PPC64)
1660 /* extsw & extsw. */
1661 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1662
1663 /* cntlzd */
1664 static void gen_cntlzd(DisasContext *ctx)
1665 {
1666 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1667 if (unlikely(Rc(ctx->opcode) != 0))
1668 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1669 }
1670 #endif
1671
1672 /*** Integer rotate ***/
1673
1674 /* rlwimi & rlwimi. */
1675 static void gen_rlwimi(DisasContext *ctx)
1676 {
1677 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1678 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1679 uint32_t sh = SH(ctx->opcode);
1680 uint32_t mb = MB(ctx->opcode);
1681 uint32_t me = ME(ctx->opcode);
1682
1683 if (sh == (31-me) && mb <= me) {
1684 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1685 } else {
1686 target_ulong mask;
1687 TCGv t1;
1688
1689 #if defined(TARGET_PPC64)
1690 mb += 32;
1691 me += 32;
1692 #endif
1693 mask = MASK(mb, me);
1694
1695 t1 = tcg_temp_new();
1696 if (mask <= 0xffffffffu) {
1697 TCGv_i32 t0 = tcg_temp_new_i32();
1698 tcg_gen_trunc_tl_i32(t0, t_rs);
1699 tcg_gen_rotli_i32(t0, t0, sh);
1700 tcg_gen_extu_i32_tl(t1, t0);
1701 tcg_temp_free_i32(t0);
1702 } else {
1703 #if defined(TARGET_PPC64)
1704 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1705 tcg_gen_rotli_i64(t1, t1, sh);
1706 #else
1707 g_assert_not_reached();
1708 #endif
1709 }
1710
1711 tcg_gen_andi_tl(t1, t1, mask);
1712 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1713 tcg_gen_or_tl(t_ra, t_ra, t1);
1714 tcg_temp_free(t1);
1715 }
1716 if (unlikely(Rc(ctx->opcode) != 0)) {
1717 gen_set_Rc0(ctx, t_ra);
1718 }
1719 }
1720
1721 /* rlwinm & rlwinm. */
1722 static void gen_rlwinm(DisasContext *ctx)
1723 {
1724 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1725 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1726 uint32_t sh = SH(ctx->opcode);
1727 uint32_t mb = MB(ctx->opcode);
1728 uint32_t me = ME(ctx->opcode);
1729
1730 if (mb == 0 && me == (31 - sh)) {
1731 tcg_gen_shli_tl(t_ra, t_rs, sh);
1732 tcg_gen_ext32u_tl(t_ra, t_ra);
1733 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1734 tcg_gen_ext32u_tl(t_ra, t_rs);
1735 tcg_gen_shri_tl(t_ra, t_ra, mb);
1736 } else {
1737 target_ulong mask;
1738 #if defined(TARGET_PPC64)
1739 mb += 32;
1740 me += 32;
1741 #endif
1742 mask = MASK(mb, me);
1743
1744 if (mask <= 0xffffffffu) {
1745 TCGv_i32 t0 = tcg_temp_new_i32();
1746 tcg_gen_trunc_tl_i32(t0, t_rs);
1747 tcg_gen_rotli_i32(t0, t0, sh);
1748 tcg_gen_andi_i32(t0, t0, mask);
1749 tcg_gen_extu_i32_tl(t_ra, t0);
1750 tcg_temp_free_i32(t0);
1751 } else {
1752 #if defined(TARGET_PPC64)
1753 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1754 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1755 tcg_gen_andi_i64(t_ra, t_ra, mask);
1756 #else
1757 g_assert_not_reached();
1758 #endif
1759 }
1760 }
1761 if (unlikely(Rc(ctx->opcode) != 0)) {
1762 gen_set_Rc0(ctx, t_ra);
1763 }
1764 }
1765
1766 /* rlwnm & rlwnm. */
1767 static void gen_rlwnm(DisasContext *ctx)
1768 {
1769 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1770 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1771 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1772 uint32_t mb = MB(ctx->opcode);
1773 uint32_t me = ME(ctx->opcode);
1774 target_ulong mask;
1775
1776 #if defined(TARGET_PPC64)
1777 mb += 32;
1778 me += 32;
1779 #endif
1780 mask = MASK(mb, me);
1781
1782 if (mask <= 0xffffffffu) {
1783 TCGv_i32 t0 = tcg_temp_new_i32();
1784 TCGv_i32 t1 = tcg_temp_new_i32();
1785 tcg_gen_trunc_tl_i32(t0, t_rb);
1786 tcg_gen_trunc_tl_i32(t1, t_rs);
1787 tcg_gen_andi_i32(t0, t0, 0x1f);
1788 tcg_gen_rotl_i32(t1, t1, t0);
1789 tcg_gen_extu_i32_tl(t_ra, t1);
1790 tcg_temp_free_i32(t0);
1791 tcg_temp_free_i32(t1);
1792 } else {
1793 #if defined(TARGET_PPC64)
1794 TCGv_i64 t0 = tcg_temp_new_i64();
1795 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1796 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1797 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1798 tcg_temp_free_i64(t0);
1799 #else
1800 g_assert_not_reached();
1801 #endif
1802 }
1803
1804 tcg_gen_andi_tl(t_ra, t_ra, mask);
1805
1806 if (unlikely(Rc(ctx->opcode) != 0)) {
1807 gen_set_Rc0(ctx, t_ra);
1808 }
1809 }
1810
1811 #if defined(TARGET_PPC64)
1812 #define GEN_PPC64_R2(name, opc1, opc2) \
1813 static void glue(gen_, name##0)(DisasContext *ctx) \
1814 { \
1815 gen_##name(ctx, 0); \
1816 } \
1817 \
1818 static void glue(gen_, name##1)(DisasContext *ctx) \
1819 { \
1820 gen_##name(ctx, 1); \
1821 }
1822 #define GEN_PPC64_R4(name, opc1, opc2) \
1823 static void glue(gen_, name##0)(DisasContext *ctx) \
1824 { \
1825 gen_##name(ctx, 0, 0); \
1826 } \
1827 \
1828 static void glue(gen_, name##1)(DisasContext *ctx) \
1829 { \
1830 gen_##name(ctx, 0, 1); \
1831 } \
1832 \
1833 static void glue(gen_, name##2)(DisasContext *ctx) \
1834 { \
1835 gen_##name(ctx, 1, 0); \
1836 } \
1837 \
1838 static void glue(gen_, name##3)(DisasContext *ctx) \
1839 { \
1840 gen_##name(ctx, 1, 1); \
1841 }
1842
1843 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1844 {
1845 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1846 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1847
1848 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1849 tcg_gen_shli_tl(t_ra, t_rs, sh);
1850 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1851 tcg_gen_shri_tl(t_ra, t_rs, mb);
1852 } else {
1853 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1854 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1855 }
1856 if (unlikely(Rc(ctx->opcode) != 0)) {
1857 gen_set_Rc0(ctx, t_ra);
1858 }
1859 }
1860
1861 /* rldicl - rldicl. */
1862 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1863 {
1864 uint32_t sh, mb;
1865
1866 sh = SH(ctx->opcode) | (shn << 5);
1867 mb = MB(ctx->opcode) | (mbn << 5);
1868 gen_rldinm(ctx, mb, 63, sh);
1869 }
1870 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1871
1872 /* rldicr - rldicr. */
1873 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1874 {
1875 uint32_t sh, me;
1876
1877 sh = SH(ctx->opcode) | (shn << 5);
1878 me = MB(ctx->opcode) | (men << 5);
1879 gen_rldinm(ctx, 0, me, sh);
1880 }
1881 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1882
1883 /* rldic - rldic. */
1884 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1885 {
1886 uint32_t sh, mb;
1887
1888 sh = SH(ctx->opcode) | (shn << 5);
1889 mb = MB(ctx->opcode) | (mbn << 5);
1890 gen_rldinm(ctx, mb, 63 - sh, sh);
1891 }
1892 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1893
1894 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1895 {
1896 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1897 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1898 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1899 TCGv t0;
1900
1901 t0 = tcg_temp_new();
1902 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1903 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1904 tcg_temp_free(t0);
1905
1906 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1907 if (unlikely(Rc(ctx->opcode) != 0)) {
1908 gen_set_Rc0(ctx, t_ra);
1909 }
1910 }
1911
1912 /* rldcl - rldcl. */
1913 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1914 {
1915 uint32_t mb;
1916
1917 mb = MB(ctx->opcode) | (mbn << 5);
1918 gen_rldnm(ctx, mb, 63);
1919 }
1920 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1921
1922 /* rldcr - rldcr. */
1923 static inline void gen_rldcr(DisasContext *ctx, int men)
1924 {
1925 uint32_t me;
1926
1927 me = MB(ctx->opcode) | (men << 5);
1928 gen_rldnm(ctx, 0, me);
1929 }
1930 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1931
1932 /* rldimi - rldimi. */
1933 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1934 {
1935 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1936 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1937 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1938 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1939 uint32_t me = 63 - sh;
1940
1941 if (mb <= me) {
1942 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1943 } else {
1944 target_ulong mask = MASK(mb, me);
1945 TCGv t1 = tcg_temp_new();
1946
1947 tcg_gen_rotli_tl(t1, t_rs, sh);
1948 tcg_gen_andi_tl(t1, t1, mask);
1949 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1950 tcg_gen_or_tl(t_ra, t_ra, t1);
1951 tcg_temp_free(t1);
1952 }
1953 if (unlikely(Rc(ctx->opcode) != 0)) {
1954 gen_set_Rc0(ctx, t_ra);
1955 }
1956 }
1957 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1958 #endif
1959
1960 /*** Integer shift ***/
1961
1962 /* slw & slw. */
1963 static void gen_slw(DisasContext *ctx)
1964 {
1965 TCGv t0, t1;
1966
1967 t0 = tcg_temp_new();
1968 /* AND rS with a mask that is 0 when rB >= 0x20 */
1969 #if defined(TARGET_PPC64)
1970 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1971 tcg_gen_sari_tl(t0, t0, 0x3f);
1972 #else
1973 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1974 tcg_gen_sari_tl(t0, t0, 0x1f);
1975 #endif
1976 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1977 t1 = tcg_temp_new();
1978 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1979 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1980 tcg_temp_free(t1);
1981 tcg_temp_free(t0);
1982 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1983 if (unlikely(Rc(ctx->opcode) != 0))
1984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1985 }
1986
1987 /* sraw & sraw. */
1988 static void gen_sraw(DisasContext *ctx)
1989 {
1990 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1991 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1992 if (unlikely(Rc(ctx->opcode) != 0))
1993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1994 }
1995
1996 /* srawi & srawi. */
1997 static void gen_srawi(DisasContext *ctx)
1998 {
1999 int sh = SH(ctx->opcode);
2000 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2001 TCGv src = cpu_gpr[rS(ctx->opcode)];
2002 if (sh == 0) {
2003 tcg_gen_ext32s_tl(dst, src);
2004 tcg_gen_movi_tl(cpu_ca, 0);
2005 } else {
2006 TCGv t0;
2007 tcg_gen_ext32s_tl(dst, src);
2008 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2009 t0 = tcg_temp_new();
2010 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2011 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2012 tcg_temp_free(t0);
2013 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2014 tcg_gen_sari_tl(dst, dst, sh);
2015 }
2016 if (unlikely(Rc(ctx->opcode) != 0)) {
2017 gen_set_Rc0(ctx, dst);
2018 }
2019 }
2020
2021 /* srw & srw. */
2022 static void gen_srw(DisasContext *ctx)
2023 {
2024 TCGv t0, t1;
2025
2026 t0 = tcg_temp_new();
2027 /* AND rS with a mask that is 0 when rB >= 0x20 */
2028 #if defined(TARGET_PPC64)
2029 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2030 tcg_gen_sari_tl(t0, t0, 0x3f);
2031 #else
2032 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2033 tcg_gen_sari_tl(t0, t0, 0x1f);
2034 #endif
2035 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2036 tcg_gen_ext32u_tl(t0, t0);
2037 t1 = tcg_temp_new();
2038 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2039 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2040 tcg_temp_free(t1);
2041 tcg_temp_free(t0);
2042 if (unlikely(Rc(ctx->opcode) != 0))
2043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2044 }
2045
2046 #if defined(TARGET_PPC64)
2047 /* sld & sld. */
2048 static void gen_sld(DisasContext *ctx)
2049 {
2050 TCGv t0, t1;
2051
2052 t0 = tcg_temp_new();
2053 /* AND rS with a mask that is 0 when rB >= 0x40 */
2054 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2055 tcg_gen_sari_tl(t0, t0, 0x3f);
2056 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2057 t1 = tcg_temp_new();
2058 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2059 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2060 tcg_temp_free(t1);
2061 tcg_temp_free(t0);
2062 if (unlikely(Rc(ctx->opcode) != 0))
2063 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2064 }
2065
2066 /* srad & srad. */
2067 static void gen_srad(DisasContext *ctx)
2068 {
2069 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2070 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2071 if (unlikely(Rc(ctx->opcode) != 0))
2072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2073 }
2074 /* sradi & sradi. */
2075 static inline void gen_sradi(DisasContext *ctx, int n)
2076 {
2077 int sh = SH(ctx->opcode) + (n << 5);
2078 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2079 TCGv src = cpu_gpr[rS(ctx->opcode)];
2080 if (sh == 0) {
2081 tcg_gen_mov_tl(dst, src);
2082 tcg_gen_movi_tl(cpu_ca, 0);
2083 } else {
2084 TCGv t0;
2085 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2086 t0 = tcg_temp_new();
2087 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2088 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2089 tcg_temp_free(t0);
2090 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2091 tcg_gen_sari_tl(dst, src, sh);
2092 }
2093 if (unlikely(Rc(ctx->opcode) != 0)) {
2094 gen_set_Rc0(ctx, dst);
2095 }
2096 }
2097
2098 static void gen_sradi0(DisasContext *ctx)
2099 {
2100 gen_sradi(ctx, 0);
2101 }
2102
2103 static void gen_sradi1(DisasContext *ctx)
2104 {
2105 gen_sradi(ctx, 1);
2106 }
2107
2108 /* srd & srd. */
2109 static void gen_srd(DisasContext *ctx)
2110 {
2111 TCGv t0, t1;
2112
2113 t0 = tcg_temp_new();
2114 /* AND rS with a mask that is 0 when rB >= 0x40 */
2115 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2116 tcg_gen_sari_tl(t0, t0, 0x3f);
2117 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2118 t1 = tcg_temp_new();
2119 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2120 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2121 tcg_temp_free(t1);
2122 tcg_temp_free(t0);
2123 if (unlikely(Rc(ctx->opcode) != 0))
2124 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2125 }
2126 #endif
2127
2128 #if defined(TARGET_PPC64)
2129 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2130 {
2131 TCGv_i32 tmp = tcg_temp_new_i32();
2132 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2133 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2134 tcg_temp_free_i32(tmp);
2135 }
2136 #else
2137 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2138 {
2139 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2140 }
2141 #endif
2142
2143 /*** Floating-Point arithmetic ***/
2144 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2145 static void gen_f##name(DisasContext *ctx) \
2146 { \
2147 if (unlikely(!ctx->fpu_enabled)) { \
2148 gen_exception(ctx, POWERPC_EXCP_FPU); \
2149 return; \
2150 } \
2151 /* NIP cannot be restored if the memory exception comes from an helper */ \
2152 gen_update_nip(ctx, ctx->nip - 4); \
2153 gen_reset_fpstatus(); \
2154 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2155 cpu_fpr[rA(ctx->opcode)], \
2156 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2157 if (isfloat) { \
2158 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2159 cpu_fpr[rD(ctx->opcode)]); \
2160 } \
2161 if (set_fprf) { \
2162 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2163 } \
2164 if (unlikely(Rc(ctx->opcode) != 0)) { \
2165 gen_set_cr1_from_fpscr(ctx); \
2166 } \
2167 }
2168
2169 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2170 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2171 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2172
2173 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2174 static void gen_f##name(DisasContext *ctx) \
2175 { \
2176 if (unlikely(!ctx->fpu_enabled)) { \
2177 gen_exception(ctx, POWERPC_EXCP_FPU); \
2178 return; \
2179 } \
2180 /* NIP cannot be restored if the memory exception comes from an helper */ \
2181 gen_update_nip(ctx, ctx->nip - 4); \
2182 gen_reset_fpstatus(); \
2183 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2184 cpu_fpr[rA(ctx->opcode)], \
2185 cpu_fpr[rB(ctx->opcode)]); \
2186 if (isfloat) { \
2187 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2188 cpu_fpr[rD(ctx->opcode)]); \
2189 } \
2190 if (set_fprf) { \
2191 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2192 } \
2193 if (unlikely(Rc(ctx->opcode) != 0)) { \
2194 gen_set_cr1_from_fpscr(ctx); \
2195 } \
2196 }
2197 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2198 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2199 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2200
2201 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2202 static void gen_f##name(DisasContext *ctx) \
2203 { \
2204 if (unlikely(!ctx->fpu_enabled)) { \
2205 gen_exception(ctx, POWERPC_EXCP_FPU); \
2206 return; \
2207 } \
2208 /* NIP cannot be restored if the memory exception comes from an helper */ \
2209 gen_update_nip(ctx, ctx->nip - 4); \
2210 gen_reset_fpstatus(); \
2211 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2212 cpu_fpr[rA(ctx->opcode)], \
2213 cpu_fpr[rC(ctx->opcode)]); \
2214 if (isfloat) { \
2215 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2216 cpu_fpr[rD(ctx->opcode)]); \
2217 } \
2218 if (set_fprf) { \
2219 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2220 } \
2221 if (unlikely(Rc(ctx->opcode) != 0)) { \
2222 gen_set_cr1_from_fpscr(ctx); \
2223 } \
2224 }
2225 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2226 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2227 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2228
2229 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2230 static void gen_f##name(DisasContext *ctx) \
2231 { \
2232 if (unlikely(!ctx->fpu_enabled)) { \
2233 gen_exception(ctx, POWERPC_EXCP_FPU); \
2234 return; \
2235 } \
2236 /* NIP cannot be restored if the memory exception comes from an helper */ \
2237 gen_update_nip(ctx, ctx->nip - 4); \
2238 gen_reset_fpstatus(); \
2239 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2240 cpu_fpr[rB(ctx->opcode)]); \
2241 if (set_fprf) { \
2242 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2243 } \
2244 if (unlikely(Rc(ctx->opcode) != 0)) { \
2245 gen_set_cr1_from_fpscr(ctx); \
2246 } \
2247 }
2248
2249 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2250 static void gen_f##name(DisasContext *ctx) \
2251 { \
2252 if (unlikely(!ctx->fpu_enabled)) { \
2253 gen_exception(ctx, POWERPC_EXCP_FPU); \
2254 return; \
2255 } \
2256 /* NIP cannot be restored if the memory exception comes from an helper */ \
2257 gen_update_nip(ctx, ctx->nip - 4); \
2258 gen_reset_fpstatus(); \
2259 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2260 cpu_fpr[rB(ctx->opcode)]); \
2261 if (set_fprf) { \
2262 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2263 } \
2264 if (unlikely(Rc(ctx->opcode) != 0)) { \
2265 gen_set_cr1_from_fpscr(ctx); \
2266 } \
2267 }
2268
2269 /* fadd - fadds */
2270 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2271 /* fdiv - fdivs */
2272 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2273 /* fmul - fmuls */
2274 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2275
2276 /* fre */
2277 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2278
2279 /* fres */
2280 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2281
2282 /* frsqrte */
2283 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2284
2285 /* frsqrtes */
2286 static void gen_frsqrtes(DisasContext *ctx)
2287 {
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 /* NIP cannot be restored if the memory exception comes from an helper */
2293 gen_update_nip(ctx, ctx->nip - 4);
2294 gen_reset_fpstatus();
2295 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2296 cpu_fpr[rB(ctx->opcode)]);
2297 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2298 cpu_fpr[rD(ctx->opcode)]);
2299 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2300 if (unlikely(Rc(ctx->opcode) != 0)) {
2301 gen_set_cr1_from_fpscr(ctx);
2302 }
2303 }
2304
2305 /* fsel */
2306 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2307 /* fsub - fsubs */
2308 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2309 /* Optional: */
2310
2311 /* fsqrt */
2312 static void gen_fsqrt(DisasContext *ctx)
2313 {
2314 if (unlikely(!ctx->fpu_enabled)) {
2315 gen_exception(ctx, POWERPC_EXCP_FPU);
2316 return;
2317 }
2318 /* NIP cannot be restored if the memory exception comes from an helper */
2319 gen_update_nip(ctx, ctx->nip - 4);
2320 gen_reset_fpstatus();
2321 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2322 cpu_fpr[rB(ctx->opcode)]);
2323 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2324 if (unlikely(Rc(ctx->opcode) != 0)) {
2325 gen_set_cr1_from_fpscr(ctx);
2326 }
2327 }
2328
2329 static void gen_fsqrts(DisasContext *ctx)
2330 {
2331 if (unlikely(!ctx->fpu_enabled)) {
2332 gen_exception(ctx, POWERPC_EXCP_FPU);
2333 return;
2334 }
2335 /* NIP cannot be restored if the memory exception comes from an helper */
2336 gen_update_nip(ctx, ctx->nip - 4);
2337 gen_reset_fpstatus();
2338 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2339 cpu_fpr[rB(ctx->opcode)]);
2340 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2341 cpu_fpr[rD(ctx->opcode)]);
2342 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2343 if (unlikely(Rc(ctx->opcode) != 0)) {
2344 gen_set_cr1_from_fpscr(ctx);
2345 }
2346 }
2347
2348 /*** Floating-Point multiply-and-add ***/
2349 /* fmadd - fmadds */
2350 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2351 /* fmsub - fmsubs */
2352 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2353 /* fnmadd - fnmadds */
2354 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2355 /* fnmsub - fnmsubs */
2356 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2357
2358 /*** Floating-Point round & convert ***/
2359 /* fctiw */
2360 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2361 /* fctiwu */
2362 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2363 /* fctiwz */
2364 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2365 /* fctiwuz */
2366 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2367 /* frsp */
2368 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2369 /* fcfid */
2370 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2371 /* fcfids */
2372 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2373 /* fcfidu */
2374 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2375 /* fcfidus */
2376 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2377 /* fctid */
2378 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2379 /* fctidu */
2380 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2381 /* fctidz */
2382 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2383 /* fctidu */
2384 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2385
2386 /* frin */
2387 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2388 /* friz */
2389 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2390 /* frip */
2391 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2392 /* frim */
2393 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2394
2395 static void gen_ftdiv(DisasContext *ctx)
2396 {
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2402 cpu_fpr[rB(ctx->opcode)]);
2403 }
2404
2405 static void gen_ftsqrt(DisasContext *ctx)
2406 {
2407 if (unlikely(!ctx->fpu_enabled)) {
2408 gen_exception(ctx, POWERPC_EXCP_FPU);
2409 return;
2410 }
2411 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2412 }
2413
2414
2415
2416 /*** Floating-Point compare ***/
2417
2418 /* fcmpo */
2419 static void gen_fcmpo(DisasContext *ctx)
2420 {
2421 TCGv_i32 crf;
2422 if (unlikely(!ctx->fpu_enabled)) {
2423 gen_exception(ctx, POWERPC_EXCP_FPU);
2424 return;
2425 }
2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx, ctx->nip - 4);
2428 gen_reset_fpstatus();
2429 crf = tcg_const_i32(crfD(ctx->opcode));
2430 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2431 cpu_fpr[rB(ctx->opcode)], crf);
2432 tcg_temp_free_i32(crf);
2433 gen_helper_float_check_status(cpu_env);
2434 }
2435
2436 /* fcmpu */
2437 static void gen_fcmpu(DisasContext *ctx)
2438 {
2439 TCGv_i32 crf;
2440 if (unlikely(!ctx->fpu_enabled)) {
2441 gen_exception(ctx, POWERPC_EXCP_FPU);
2442 return;
2443 }
2444 /* NIP cannot be restored if the memory exception comes from an helper */
2445 gen_update_nip(ctx, ctx->nip - 4);
2446 gen_reset_fpstatus();
2447 crf = tcg_const_i32(crfD(ctx->opcode));
2448 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2449 cpu_fpr[rB(ctx->opcode)], crf);
2450 tcg_temp_free_i32(crf);
2451 gen_helper_float_check_status(cpu_env);
2452 }
2453
2454 /*** Floating-point move ***/
2455 /* fabs */
2456 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2457 static void gen_fabs(DisasContext *ctx)
2458 {
2459 if (unlikely(!ctx->fpu_enabled)) {
2460 gen_exception(ctx, POWERPC_EXCP_FPU);
2461 return;
2462 }
2463 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2464 ~(1ULL << 63));
2465 if (unlikely(Rc(ctx->opcode))) {
2466 gen_set_cr1_from_fpscr(ctx);
2467 }
2468 }
2469
2470 /* fmr - fmr. */
2471 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2472 static void gen_fmr(DisasContext *ctx)
2473 {
2474 if (unlikely(!ctx->fpu_enabled)) {
2475 gen_exception(ctx, POWERPC_EXCP_FPU);
2476 return;
2477 }
2478 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2479 if (unlikely(Rc(ctx->opcode))) {
2480 gen_set_cr1_from_fpscr(ctx);
2481 }
2482 }
2483
2484 /* fnabs */
2485 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2486 static void gen_fnabs(DisasContext *ctx)
2487 {
2488 if (unlikely(!ctx->fpu_enabled)) {
2489 gen_exception(ctx, POWERPC_EXCP_FPU);
2490 return;
2491 }
2492 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2493 1ULL << 63);
2494 if (unlikely(Rc(ctx->opcode))) {
2495 gen_set_cr1_from_fpscr(ctx);
2496 }
2497 }
2498
2499 /* fneg */
2500 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2501 static void gen_fneg(DisasContext *ctx)
2502 {
2503 if (unlikely(!ctx->fpu_enabled)) {
2504 gen_exception(ctx, POWERPC_EXCP_FPU);
2505 return;
2506 }
2507 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2508 1ULL << 63);
2509 if (unlikely(Rc(ctx->opcode))) {
2510 gen_set_cr1_from_fpscr(ctx);
2511 }
2512 }
2513
2514 /* fcpsgn: PowerPC 2.05 specification */
2515 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2516 static void gen_fcpsgn(DisasContext *ctx)
2517 {
2518 if (unlikely(!ctx->fpu_enabled)) {
2519 gen_exception(ctx, POWERPC_EXCP_FPU);
2520 return;
2521 }
2522 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2523 cpu_fpr[rB(ctx->opcode)], 0, 63);
2524 if (unlikely(Rc(ctx->opcode))) {
2525 gen_set_cr1_from_fpscr(ctx);
2526 }
2527 }
2528
2529 static void gen_fmrgew(DisasContext *ctx)
2530 {
2531 TCGv_i64 b0;
2532 if (unlikely(!ctx->fpu_enabled)) {
2533 gen_exception(ctx, POWERPC_EXCP_FPU);
2534 return;
2535 }
2536 b0 = tcg_temp_new_i64();
2537 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2538 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2539 b0, 0, 32);
2540 tcg_temp_free_i64(b0);
2541 }
2542
2543 static void gen_fmrgow(DisasContext *ctx)
2544 {
2545 if (unlikely(!ctx->fpu_enabled)) {
2546 gen_exception(ctx, POWERPC_EXCP_FPU);
2547 return;
2548 }
2549 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2550 cpu_fpr[rB(ctx->opcode)],
2551 cpu_fpr[rA(ctx->opcode)],
2552 32, 32);
2553 }
2554
2555 /*** Floating-Point status & ctrl register ***/
2556
2557 /* mcrfs */
2558 static void gen_mcrfs(DisasContext *ctx)
2559 {
2560 TCGv tmp = tcg_temp_new();
2561 TCGv_i32 tmask;
2562 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2563 int bfa;
2564 int nibble;
2565 int shift;
2566
2567 if (unlikely(!ctx->fpu_enabled)) {
2568 gen_exception(ctx, POWERPC_EXCP_FPU);
2569 return;
2570 }
2571 bfa = crfS(ctx->opcode);
2572 nibble = 7 - bfa;
2573 shift = 4 * nibble;
2574 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2575 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2576 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2577 tcg_temp_free(tmp);
2578 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2579 /* Only the exception bits (including FX) should be cleared if read */
2580 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2581 /* FEX and VX need to be updated, so don't set fpscr directly */
2582 tmask = tcg_const_i32(1 << nibble);
2583 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2584 tcg_temp_free_i32(tmask);
2585 tcg_temp_free_i64(tnew_fpscr);
2586 }
2587
2588 /* mffs */
2589 static void gen_mffs(DisasContext *ctx)
2590 {
2591 if (unlikely(!ctx->fpu_enabled)) {
2592 gen_exception(ctx, POWERPC_EXCP_FPU);
2593 return;
2594 }
2595 gen_reset_fpstatus();
2596 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2597 if (unlikely(Rc(ctx->opcode))) {
2598 gen_set_cr1_from_fpscr(ctx);
2599 }
2600 }
2601
2602 /* mtfsb0 */
2603 static void gen_mtfsb0(DisasContext *ctx)
2604 {
2605 uint8_t crb;
2606
2607 if (unlikely(!ctx->fpu_enabled)) {
2608 gen_exception(ctx, POWERPC_EXCP_FPU);
2609 return;
2610 }
2611 crb = 31 - crbD(ctx->opcode);
2612 gen_reset_fpstatus();
2613 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2614 TCGv_i32 t0;
2615 /* NIP cannot be restored if the memory exception comes from an helper */
2616 gen_update_nip(ctx, ctx->nip - 4);
2617 t0 = tcg_const_i32(crb);
2618 gen_helper_fpscr_clrbit(cpu_env, t0);
2619 tcg_temp_free_i32(t0);
2620 }
2621 if (unlikely(Rc(ctx->opcode) != 0)) {
2622 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2623 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2624 }
2625 }
2626
2627 /* mtfsb1 */
2628 static void gen_mtfsb1(DisasContext *ctx)
2629 {
2630 uint8_t crb;
2631
2632 if (unlikely(!ctx->fpu_enabled)) {
2633 gen_exception(ctx, POWERPC_EXCP_FPU);
2634 return;
2635 }
2636 crb = 31 - crbD(ctx->opcode);
2637 gen_reset_fpstatus();
2638 /* XXX: we pretend we can only do IEEE floating-point computations */
2639 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2640 TCGv_i32 t0;
2641 /* NIP cannot be restored if the memory exception comes from an helper */
2642 gen_update_nip(ctx, ctx->nip - 4);
2643 t0 = tcg_const_i32(crb);
2644 gen_helper_fpscr_setbit(cpu_env, t0);
2645 tcg_temp_free_i32(t0);
2646 }
2647 if (unlikely(Rc(ctx->opcode) != 0)) {
2648 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2649 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2650 }
2651 /* We can raise a differed exception */
2652 gen_helper_float_check_status(cpu_env);
2653 }
2654
2655 /* mtfsf */
2656 static void gen_mtfsf(DisasContext *ctx)
2657 {
2658 TCGv_i32 t0;
2659 int flm, l, w;
2660
2661 if (unlikely(!ctx->fpu_enabled)) {
2662 gen_exception(ctx, POWERPC_EXCP_FPU);
2663 return;
2664 }
2665 flm = FPFLM(ctx->opcode);
2666 l = FPL(ctx->opcode);
2667 w = FPW(ctx->opcode);
2668 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2669 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2670 return;
2671 }
2672 /* NIP cannot be restored if the memory exception comes from an helper */
2673 gen_update_nip(ctx, ctx->nip - 4);
2674 gen_reset_fpstatus();
2675 if (l) {
2676 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2677 } else {
2678 t0 = tcg_const_i32(flm << (w * 8));
2679 }
2680 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2681 tcg_temp_free_i32(t0);
2682 if (unlikely(Rc(ctx->opcode) != 0)) {
2683 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2684 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2685 }
2686 /* We can raise a differed exception */
2687 gen_helper_float_check_status(cpu_env);
2688 }
2689
2690 /* mtfsfi */
2691 static void gen_mtfsfi(DisasContext *ctx)
2692 {
2693 int bf, sh, w;
2694 TCGv_i64 t0;
2695 TCGv_i32 t1;
2696
2697 if (unlikely(!ctx->fpu_enabled)) {
2698 gen_exception(ctx, POWERPC_EXCP_FPU);
2699 return;
2700 }
2701 w = FPW(ctx->opcode);
2702 bf = FPBF(ctx->opcode);
2703 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2705 return;
2706 }
2707 sh = (8 * w) + 7 - bf;
2708 /* NIP cannot be restored if the memory exception comes from an helper */
2709 gen_update_nip(ctx, ctx->nip - 4);
2710 gen_reset_fpstatus();
2711 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2712 t1 = tcg_const_i32(1 << sh);
2713 gen_helper_store_fpscr(cpu_env, t0, t1);
2714 tcg_temp_free_i64(t0);
2715 tcg_temp_free_i32(t1);
2716 if (unlikely(Rc(ctx->opcode) != 0)) {
2717 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2718 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2719 }
2720 /* We can raise a differed exception */
2721 gen_helper_float_check_status(cpu_env);
2722 }
2723
2724 /*** Addressing modes ***/
2725 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2726 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2727 target_long maskl)
2728 {
2729 target_long simm = SIMM(ctx->opcode);
2730
2731 simm &= ~maskl;
2732 if (rA(ctx->opcode) == 0) {
2733 if (NARROW_MODE(ctx)) {
2734 simm = (uint32_t)simm;
2735 }
2736 tcg_gen_movi_tl(EA, simm);
2737 } else if (likely(simm != 0)) {
2738 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2739 if (NARROW_MODE(ctx)) {
2740 tcg_gen_ext32u_tl(EA, EA);
2741 }
2742 } else {
2743 if (NARROW_MODE(ctx)) {
2744 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2745 } else {
2746 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2747 }
2748 }
2749 }
2750
2751 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2752 {
2753 if (rA(ctx->opcode) == 0) {
2754 if (NARROW_MODE(ctx)) {
2755 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2756 } else {
2757 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2758 }
2759 } else {
2760 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2761 if (NARROW_MODE(ctx)) {
2762 tcg_gen_ext32u_tl(EA, EA);
2763 }
2764 }
2765 }
2766
2767 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2768 {
2769 if (rA(ctx->opcode) == 0) {
2770 tcg_gen_movi_tl(EA, 0);
2771 } else if (NARROW_MODE(ctx)) {
2772 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2773 } else {
2774 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2775 }
2776 }
2777
2778 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2779 target_long val)
2780 {
2781 tcg_gen_addi_tl(ret, arg1, val);
2782 if (NARROW_MODE(ctx)) {
2783 tcg_gen_ext32u_tl(ret, ret);
2784 }
2785 }
2786
2787 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2788 {
2789 TCGLabel *l1 = gen_new_label();
2790 TCGv t0 = tcg_temp_new();
2791 TCGv_i32 t1, t2;
2792 /* NIP cannot be restored if the memory exception comes from an helper */
2793 gen_update_nip(ctx, ctx->nip - 4);
2794 tcg_gen_andi_tl(t0, EA, mask);
2795 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2796 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2797 t2 = tcg_const_i32(0);
2798 gen_helper_raise_exception_err(cpu_env, t1, t2);
2799 tcg_temp_free_i32(t1);
2800 tcg_temp_free_i32(t2);
2801 gen_set_label(l1);
2802 tcg_temp_free(t0);
2803 }
2804
2805 /*** Integer load ***/
2806 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2807 {
2808 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2809 }
2810
2811 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2812 {
2813 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2814 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2815 }
2816
2817 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2818 {
2819 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2820 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2821 }
2822
2823 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2824 {
2825 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2826 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2827 }
2828
2829 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2830 {
2831 TCGv tmp = tcg_temp_new();
2832 gen_qemu_ld32u(ctx, tmp, addr);
2833 tcg_gen_extu_tl_i64(val, tmp);
2834 tcg_temp_free(tmp);
2835 }
2836
2837 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2838 {
2839 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2840 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2841 }
2842
2843 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2844 {
2845 TCGv tmp = tcg_temp_new();
2846 gen_qemu_ld32s(ctx, tmp, addr);
2847 tcg_gen_ext_tl_i64(val, tmp);
2848 tcg_temp_free(tmp);
2849 }
2850
2851 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2852 {
2853 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2854 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2855 }
2856
2857 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2858 {
2859 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2860 }
2861
2862 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2863 {
2864 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2865 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2866 }
2867
2868 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2869 {
2870 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2871 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2872 }
2873
2874 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2875 {
2876 TCGv tmp = tcg_temp_new();
2877 tcg_gen_trunc_i64_tl(tmp, val);
2878 gen_qemu_st32(ctx, tmp, addr);
2879 tcg_temp_free(tmp);
2880 }
2881
2882 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2883 {
2884 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2885 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2886 }
2887
2888 #define GEN_LD(name, ldop, opc, type) \
2889 static void glue(gen_, name)(DisasContext *ctx) \
2890 { \
2891 TCGv EA; \
2892 gen_set_access_type(ctx, ACCESS_INT); \
2893 EA = tcg_temp_new(); \
2894 gen_addr_imm_index(ctx, EA, 0); \
2895 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2896 tcg_temp_free(EA); \
2897 }
2898
2899 #define GEN_LDU(name, ldop, opc, type) \
2900 static void glue(gen_, name##u)(DisasContext *ctx) \
2901 { \
2902 TCGv EA; \
2903 if (unlikely(rA(ctx->opcode) == 0 || \
2904 rA(ctx->opcode) == rD(ctx->opcode))) { \
2905 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2906 return; \
2907 } \
2908 gen_set_access_type(ctx, ACCESS_INT); \
2909 EA = tcg_temp_new(); \
2910 if (type == PPC_64B) \
2911 gen_addr_imm_index(ctx, EA, 0x03); \
2912 else \
2913 gen_addr_imm_index(ctx, EA, 0); \
2914 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2915 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2916 tcg_temp_free(EA); \
2917 }
2918
2919 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2920 static void glue(gen_, name##ux)(DisasContext *ctx) \
2921 { \
2922 TCGv EA; \
2923 if (unlikely(rA(ctx->opcode) == 0 || \
2924 rA(ctx->opcode) == rD(ctx->opcode))) { \
2925 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2926 return; \
2927 } \
2928 gen_set_access_type(ctx, ACCESS_INT); \
2929 EA = tcg_temp_new(); \
2930 gen_addr_reg_index(ctx, EA); \
2931 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2932 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2933 tcg_temp_free(EA); \
2934 }
2935
2936 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2937 static void glue(gen_, name##x)(DisasContext *ctx) \
2938 { \
2939 TCGv EA; \
2940 chk; \
2941 gen_set_access_type(ctx, ACCESS_INT); \
2942 EA = tcg_temp_new(); \
2943 gen_addr_reg_index(ctx, EA); \
2944 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2945 tcg_temp_free(EA); \
2946 }
2947
2948 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2949 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2950
2951 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2952 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2953
2954 #define GEN_LDS(name, ldop, op, type) \
2955 GEN_LD(name, ldop, op | 0x20, type); \
2956 GEN_LDU(name, ldop, op | 0x21, type); \
2957 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2958 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2959
2960 /* lbz lbzu lbzux lbzx */
2961 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2962 /* lha lhau lhaux lhax */
2963 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2964 /* lhz lhzu lhzux lhzx */
2965 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2966 /* lwz lwzu lwzux lwzx */
2967 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2968 #if defined(TARGET_PPC64)
2969 /* lwaux */
2970 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2971 /* lwax */
2972 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2973 /* ldux */
2974 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2975 /* ldx */
2976 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2977
2978 /* CI load/store variants */
2979 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2980 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2981 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2982 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2983
2984 static void gen_ld(DisasContext *ctx)
2985 {
2986 TCGv EA;
2987 if (Rc(ctx->opcode)) {
2988 if (unlikely(rA(ctx->opcode) == 0 ||
2989 rA(ctx->opcode) == rD(ctx->opcode))) {
2990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2991 return;
2992 }
2993 }
2994 gen_set_access_type(ctx, ACCESS_INT);
2995 EA = tcg_temp_new();
2996 gen_addr_imm_index(ctx, EA, 0x03);
2997 if (ctx->opcode & 0x02) {
2998 /* lwa (lwau is undefined) */
2999 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3000 } else {
3001 /* ld - ldu */
3002 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3003 }
3004 if (Rc(ctx->opcode))
3005 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3006 tcg_temp_free(EA);
3007 }
3008
3009 /* lq */
3010 static void gen_lq(DisasContext *ctx)
3011 {
3012 int ra, rd;
3013 TCGv EA;
3014
3015 /* lq is a legal user mode instruction starting in ISA 2.07 */
3016 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3017 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3018
3019 if (!legal_in_user_mode && ctx->pr) {
3020 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3021 return;
3022 }
3023
3024 if (!le_is_supported && ctx->le_mode) {
3025 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3026 return;
3027 }
3028
3029 ra = rA(ctx->opcode);
3030 rd = rD(ctx->opcode);
3031 if (unlikely((rd & 1) || rd == ra)) {
3032 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3033 return;
3034 }
3035
3036 gen_set_access_type(ctx, ACCESS_INT);
3037 EA = tcg_temp_new();
3038 gen_addr_imm_index(ctx, EA, 0x0F);
3039
3040 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3041 64-bit byteswap already. */
3042 if (unlikely(ctx->le_mode)) {
3043 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3044 gen_addr_add(ctx, EA, EA, 8);
3045 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3046 } else {
3047 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
3048 gen_addr_add(ctx, EA, EA, 8);
3049 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
3050 }
3051 tcg_temp_free(EA);
3052 }
3053 #endif
3054
3055 /*** Integer store ***/
3056 #define GEN_ST(name, stop, opc, type) \
3057 static void glue(gen_, name)(DisasContext *ctx) \
3058 { \
3059 TCGv EA; \
3060 gen_set_access_type(ctx, ACCESS_INT); \
3061 EA = tcg_temp_new(); \
3062 gen_addr_imm_index(ctx, EA, 0); \
3063 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3064 tcg_temp_free(EA); \
3065 }
3066
3067 #define GEN_STU(name, stop, opc, type) \
3068 static void glue(gen_, stop##u)(DisasContext *ctx) \
3069 { \
3070 TCGv EA; \
3071 if (unlikely(rA(ctx->opcode) == 0)) { \
3072 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3073 return; \
3074 } \
3075 gen_set_access_type(ctx, ACCESS_INT); \
3076 EA = tcg_temp_new(); \
3077 if (type == PPC_64B) \
3078 gen_addr_imm_index(ctx, EA, 0x03); \
3079 else \
3080 gen_addr_imm_index(ctx, EA, 0); \
3081 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3082 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3083 tcg_temp_free(EA); \
3084 }
3085
3086 #define GEN_STUX(name, stop, opc2, opc3, type) \
3087 static void glue(gen_, name##ux)(DisasContext *ctx) \
3088 { \
3089 TCGv EA; \
3090 if (unlikely(rA(ctx->opcode) == 0)) { \
3091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3092 return; \
3093 } \
3094 gen_set_access_type(ctx, ACCESS_INT); \
3095 EA = tcg_temp_new(); \
3096 gen_addr_reg_index(ctx, EA); \
3097 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3098 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3099 tcg_temp_free(EA); \
3100 }
3101
3102 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3103 static void glue(gen_, name##x)(DisasContext *ctx) \
3104 { \
3105 TCGv EA; \
3106 chk; \
3107 gen_set_access_type(ctx, ACCESS_INT); \
3108 EA = tcg_temp_new(); \
3109 gen_addr_reg_index(ctx, EA); \
3110 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3111 tcg_temp_free(EA); \
3112 }
3113 #define GEN_STX(name, stop, opc2, opc3, type) \
3114 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3115
3116 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3117 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3118
3119 #define GEN_STS(name, stop, op, type) \
3120 GEN_ST(name, stop, op | 0x20, type); \
3121 GEN_STU(name, stop, op | 0x21, type); \
3122 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3123 GEN_STX(name, stop, 0x17, op | 0x00, type)
3124
3125 /* stb stbu stbux stbx */
3126 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3127 /* sth sthu sthux sthx */
3128 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3129 /* stw stwu stwux stwx */
3130 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3131 #if defined(TARGET_PPC64)
3132 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3133 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3134 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
3135 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3136 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3137 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3138
3139 static void gen_std(DisasContext *ctx)
3140 {
3141 int rs;
3142 TCGv EA;
3143
3144 rs = rS(ctx->opcode);
3145 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3146 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3147 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3148
3149 if (!(ctx->insns_flags & PPC_64BX)) {
3150 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3151 }
3152
3153 if (!legal_in_user_mode && ctx->pr) {
3154 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3155 return;
3156 }
3157
3158 if (!le_is_supported && ctx->le_mode) {
3159 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3160 return;
3161 }
3162
3163 if (unlikely(rs & 1)) {
3164 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3165 return;
3166 }
3167 gen_set_access_type(ctx, ACCESS_INT);
3168 EA = tcg_temp_new();
3169 gen_addr_imm_index(ctx, EA, 0x03);
3170
3171 /* We only need to swap high and low halves. gen_qemu_st64 does
3172 necessary 64-bit byteswap already. */
3173 if (unlikely(ctx->le_mode)) {
3174 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3175 gen_addr_add(ctx, EA, EA, 8);
3176 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3177 } else {
3178 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3179 gen_addr_add(ctx, EA, EA, 8);
3180 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3181 }
3182 tcg_temp_free(EA);
3183 } else {
3184 /* std / stdu*/
3185 if (Rc(ctx->opcode)) {
3186 if (unlikely(rA(ctx->opcode) == 0)) {
3187 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3188 return;
3189 }
3190 }
3191 gen_set_access_type(ctx, ACCESS_INT);
3192 EA = tcg_temp_new();
3193 gen_addr_imm_index(ctx, EA, 0x03);
3194 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3195 if (Rc(ctx->opcode))
3196 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3197 tcg_temp_free(EA);
3198 }
3199 }
3200 #endif
3201 /*** Integer load and store with byte reverse ***/
3202
3203 /* lhbrx */
3204 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3205 {
3206 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3207 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3208 }
3209 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3210
3211 /* lwbrx */
3212 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3213 {
3214 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3215 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3216 }
3217 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3218
3219 #if defined(TARGET_PPC64)
3220 /* ldbrx */
3221 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3222 {
3223 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3224 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3225 }
3226 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3227 #endif /* TARGET_PPC64 */
3228
3229 /* sthbrx */
3230 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3231 {
3232 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3233 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3234 }
3235 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3236
3237 /* stwbrx */
3238 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3239 {
3240 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3241 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3242 }
3243 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3244
3245 #if defined(TARGET_PPC64)
3246 /* stdbrx */
3247 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3248 {
3249 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3250 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3251 }
3252 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3253 #endif /* TARGET_PPC64 */
3254
3255 /*** Integer load and store multiple ***/
3256
3257 /* lmw */
3258 static void gen_lmw(DisasContext *ctx)
3259 {
3260 TCGv t0;
3261 TCGv_i32 t1;
3262 gen_set_access_type(ctx, ACCESS_INT);
3263 /* NIP cannot be restored if the memory exception comes from an helper */
3264 gen_update_nip(ctx, ctx->nip - 4);
3265 t0 = tcg_temp_new();
3266 t1 = tcg_const_i32(rD(ctx->opcode));
3267 gen_addr_imm_index(ctx, t0, 0);
3268 gen_helper_lmw(cpu_env, t0, t1);
3269 tcg_temp_free(t0);
3270 tcg_temp_free_i32(t1);
3271 }
3272
3273 /* stmw */
3274 static void gen_stmw(DisasContext *ctx)
3275 {
3276 TCGv t0;
3277 TCGv_i32 t1;
3278 gen_set_access_type(ctx, ACCESS_INT);
3279 /* NIP cannot be restored if the memory exception comes from an helper */
3280 gen_update_nip(ctx, ctx->nip - 4);
3281 t0 = tcg_temp_new();
3282 t1 = tcg_const_i32(rS(ctx->opcode));
3283 gen_addr_imm_index(ctx, t0, 0);
3284 gen_helper_stmw(cpu_env, t0, t1);
3285 tcg_temp_free(t0);
3286 tcg_temp_free_i32(t1);
3287 }
3288
3289 /*** Integer load and store strings ***/
3290
3291 /* lswi */
3292 /* PowerPC32 specification says we must generate an exception if
3293 * rA is in the range of registers to be loaded.
3294 * In an other hand, IBM says this is valid, but rA won't be loaded.
3295 * For now, I'll follow the spec...
3296 */
3297 static void gen_lswi(DisasContext *ctx)
3298 {
3299 TCGv t0;
3300 TCGv_i32 t1, t2;
3301 int nb = NB(ctx->opcode);
3302 int start = rD(ctx->opcode);
3303 int ra = rA(ctx->opcode);
3304 int nr;
3305
3306 if (nb == 0)
3307 nb = 32;
3308 nr = (nb + 3) / 4;
3309 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3310 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3311 return;
3312 }
3313 gen_set_access_type(ctx, ACCESS_INT);
3314 /* NIP cannot be restored if the memory exception comes from an helper */
3315 gen_update_nip(ctx, ctx->nip - 4);
3316 t0 = tcg_temp_new();
3317 gen_addr_register(ctx, t0);
3318 t1 = tcg_const_i32(nb);
3319 t2 = tcg_const_i32(start);
3320 gen_helper_lsw(cpu_env, t0, t1, t2);
3321 tcg_temp_free(t0);
3322 tcg_temp_free_i32(t1);
3323 tcg_temp_free_i32(t2);
3324 }
3325
3326 /* lswx */
3327 static void gen_lswx(DisasContext *ctx)
3328 {
3329 TCGv t0;
3330 TCGv_i32 t1, t2, t3;
3331 gen_set_access_type(ctx, ACCESS_INT);
3332 /* NIP cannot be restored if the memory exception comes from an helper */
3333 gen_update_nip(ctx, ctx->nip - 4);
3334 t0 = tcg_temp_new();
3335 gen_addr_reg_index(ctx, t0);
3336 t1 = tcg_const_i32(rD(ctx->opcode));
3337 t2 = tcg_const_i32(rA(ctx->opcode));
3338 t3 = tcg_const_i32(rB(ctx->opcode));
3339 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3340 tcg_temp_free(t0);
3341 tcg_temp_free_i32(t1);
3342 tcg_temp_free_i32(t2);
3343 tcg_temp_free_i32(t3);
3344 }
3345
3346 /* stswi */
3347 static void gen_stswi(DisasContext *ctx)
3348 {
3349 TCGv t0;
3350 TCGv_i32 t1, t2;
3351 int nb = NB(ctx->opcode);
3352 gen_set_access_type(ctx, ACCESS_INT);
3353 /* NIP cannot be restored if the memory exception comes from an helper */
3354 gen_update_nip(ctx, ctx->nip - 4);
3355 t0 = tcg_temp_new();
3356 gen_addr_register(ctx, t0);
3357 if (nb == 0)
3358 nb = 32;
3359 t1 = tcg_const_i32(nb);
3360 t2 = tcg_const_i32(rS(ctx->opcode));
3361 gen_helper_stsw(cpu_env, t0, t1, t2);
3362 tcg_temp_free(t0);
3363 tcg_temp_free_i32(t1);
3364 tcg_temp_free_i32(t2);
3365 }
3366
3367 /* stswx */
3368 static void gen_stswx(DisasContext *ctx)
3369 {
3370 TCGv t0;
3371 TCGv_i32 t1, t2;
3372 gen_set_access_type(ctx, ACCESS_INT);
3373 /* NIP cannot be restored if the memory exception comes from an helper */
3374 gen_update_nip(ctx, ctx->nip - 4);
3375 t0 = tcg_temp_new();
3376 gen_addr_reg_index(ctx, t0);
3377 t1 = tcg_temp_new_i32();
3378 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3379 tcg_gen_andi_i32(t1, t1, 0x7F);
3380 t2 = tcg_const_i32(rS(ctx->opcode));
3381 gen_helper_stsw(cpu_env, t0, t1, t2);
3382 tcg_temp_free(t0);
3383 tcg_temp_free_i32(t1);
3384 tcg_temp_free_i32(t2);
3385 }
3386
3387 /*** Memory synchronisation ***/
3388 /* eieio */
3389 static void gen_eieio(DisasContext *ctx)
3390 {
3391 }
3392
3393 #if !defined(CONFIG_USER_ONLY)
3394 static inline void gen_check_tlb_flush(DisasContext *ctx)
3395 {
3396 TCGv_i32 t;
3397 TCGLabel *l;
3398
3399 if (!ctx->lazy_tlb_flush) {
3400 return;
3401 }
3402 l = gen_new_label();
3403 t = tcg_temp_new_i32();
3404 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3405 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3406 gen_helper_check_tlb_flush(cpu_env);
3407 gen_set_label(l);
3408 tcg_temp_free_i32(t);
3409 }
3410 #else
3411 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3412 #endif
3413
3414 /* isync */
3415 static void gen_isync(DisasContext *ctx)
3416 {
3417 /*
3418 * We need to check for a pending TLB flush. This can only happen in
3419 * kernel mode however so check MSR_PR
3420 */
3421 if (!ctx->pr) {
3422 gen_check_tlb_flush(ctx);
3423 }
3424 gen_stop_exception(ctx);
3425 }
3426
3427 #define LARX(name, len, loadop) \
3428 static void gen_##name(DisasContext *ctx) \
3429 { \
3430 TCGv t0; \
3431 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3432 gen_set_access_type(ctx, ACCESS_RES); \
3433 t0 = tcg_temp_local_new(); \
3434 gen_addr_reg_index(ctx, t0); \
3435 if ((len) > 1) { \
3436 gen_check_align(ctx, t0, (len)-1); \
3437 } \
3438 gen_qemu_##loadop(ctx, gpr, t0); \
3439 tcg_gen_mov_tl(cpu_reserve, t0); \
3440 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3441 tcg_temp_free(t0); \
3442 }
3443
3444 /* lwarx */
3445 LARX(lbarx, 1, ld8u);
3446 LARX(lharx, 2, ld16u);
3447 LARX(lwarx, 4, ld32u);
3448
3449
3450 #if defined(CONFIG_USER_ONLY)
3451 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3452 int reg, int size)
3453 {
3454 TCGv t0 = tcg_temp_new();
3455 uint32_t save_exception = ctx->exception;
3456
3457 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3458 tcg_gen_movi_tl(t0, (size << 5) | reg);
3459 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3460 tcg_temp_free(t0);
3461 gen_update_nip(ctx, ctx->nip-4);
3462 ctx->exception = POWERPC_EXCP_BRANCH;
3463 gen_exception(ctx, POWERPC_EXCP_STCX);
3464 ctx->exception = save_exception;
3465 }
3466 #else
3467 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3468 int reg, int size)
3469 {
3470 TCGLabel *l1;
3471
3472 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3473 l1 = gen_new_label();
3474 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3475 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3476 #if defined(TARGET_PPC64)
3477 if (size == 8) {
3478 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3479 } else
3480 #endif
3481 if (size == 4) {
3482 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3483 } else if (size == 2) {
3484 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3485 #if defined(TARGET_PPC64)
3486 } else if (size == 16) {
3487 TCGv gpr1, gpr2 , EA8;
3488 if (unlikely(ctx->le_mode)) {
3489 gpr1 = cpu_gpr[reg+1];
3490 gpr2 = cpu_gpr[reg];
3491 } else {
3492 gpr1 = cpu_gpr[reg];
3493 gpr2 = cpu_gpr[reg+1];
3494 }
3495 gen_qemu_st64(ctx, gpr1, EA);
3496 EA8 = tcg_temp_local_new();
3497 gen_addr_add(ctx, EA8, EA, 8);
3498 gen_qemu_st64(ctx, gpr2, EA8);
3499 tcg_temp_free(EA8);
3500 #endif
3501 } else {
3502 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3503 }
3504 gen_set_label(l1);
3505 tcg_gen_movi_tl(cpu_reserve, -1);
3506 }
3507 #endif
3508
3509 #define STCX(name, len) \
3510 static void gen_##name(DisasContext *ctx) \
3511 { \
3512 TCGv t0; \
3513 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3514 gen_inval_exception(ctx, \
3515 POWERPC_EXCP_INVAL_INVAL); \
3516 return; \
3517 } \
3518 gen_set_access_type(ctx, ACCESS_RES); \
3519 t0 = tcg_temp_local_new(); \
3520 gen_addr_reg_index(ctx, t0); \
3521 if (len > 1) { \
3522 gen_check_align(ctx, t0, (len)-1); \
3523 } \
3524 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3525 tcg_temp_free(t0); \
3526 }
3527
3528 STCX(stbcx_, 1);
3529 STCX(sthcx_, 2);
3530 STCX(stwcx_, 4);
3531
3532 #if defined(TARGET_PPC64)
3533 /* ldarx */
3534 LARX(ldarx, 8, ld64);
3535
3536 /* lqarx */
3537 static void gen_lqarx(DisasContext *ctx)
3538 {
3539 TCGv EA;
3540 int rd = rD(ctx->opcode);
3541 TCGv gpr1, gpr2;
3542
3543 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3544 (rd == rB(ctx->opcode)))) {
3545 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3546 return;
3547 }
3548
3549 gen_set_access_type(ctx, ACCESS_RES);
3550 EA = tcg_temp_local_new();
3551 gen_addr_reg_index(ctx, EA);
3552 gen_check_align(ctx, EA, 15);
3553 if (unlikely(ctx->le_mode)) {
3554 gpr1 = cpu_gpr[rd+1];
3555 gpr2 = cpu_gpr[rd];
3556 } else {
3557 gpr1 = cpu_gpr[rd];
3558 gpr2 = cpu_gpr[rd+1];
3559 }
3560 gen_qemu_ld64(ctx, gpr1, EA);
3561 tcg_gen_mov_tl(cpu_reserve, EA);
3562
3563 gen_addr_add(ctx, EA, EA, 8);
3564 gen_qemu_ld64(ctx, gpr2, EA);
3565
3566 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3567 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3568
3569 tcg_temp_free(EA);
3570 }
3571
3572 /* stdcx. */
3573 STCX(stdcx_, 8);
3574 STCX(stqcx_, 16);
3575 #endif /* defined(TARGET_PPC64) */
3576
3577 /* sync */
3578 static void gen_sync(DisasContext *ctx)
3579 {
3580 uint32_t l = (ctx->opcode >> 21) & 3;
3581
3582 /*
3583 * We may need to check for a pending TLB flush.
3584 *
3585 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3586 *
3587 * Additionally, this can only happen in kernel mode however so
3588 * check MSR_PR as well.
3589 */
3590 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3591 gen_check_tlb_flush(ctx);
3592 }
3593 }
3594
3595 /* wait */
3596 static void gen_wait(DisasContext *ctx)
3597 {
3598 TCGv_i32 t0 = tcg_const_i32(1);
3599 tcg_gen_st_i32(t0, cpu_env,
3600 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3601 tcg_temp_free_i32(t0);
3602 /* Stop translation, as the CPU is supposed to sleep from now */
3603 gen_exception_err(ctx, EXCP_HLT, 1);
3604 }
3605
3606 #if defined(TARGET_PPC64)
3607 static void gen_doze(DisasContext *ctx)
3608 {
3609 #if defined(CONFIG_USER_ONLY)
3610 GEN_PRIV;
3611 #else
3612 TCGv_i32 t;
3613
3614 CHK_HV;
3615 t = tcg_const_i32(PPC_PM_DOZE);
3616 gen_helper_pminsn(cpu_env, t);
3617 tcg_temp_free_i32(t);
3618 gen_stop_exception(ctx);
3619 #endif /* defined(CONFIG_USER_ONLY) */
3620 }
3621
3622 static void gen_nap(DisasContext *ctx)
3623 {
3624 #if defined(CONFIG_USER_ONLY)
3625 GEN_PRIV;
3626 #else
3627 TCGv_i32 t;
3628
3629 CHK_HV;
3630 t = tcg_const_i32(PPC_PM_NAP);
3631 gen_helper_pminsn(cpu_env, t);
3632 tcg_temp_free_i32(t);
3633 gen_stop_exception(ctx);
3634 #endif /* defined(CONFIG_USER_ONLY) */
3635 }
3636
3637 static void gen_sleep(DisasContext *ctx)
3638 {
3639 #if defined(CONFIG_USER_ONLY)
3640 GEN_PRIV;
3641 #else
3642 TCGv_i32 t;
3643
3644 CHK_HV;
3645 t = tcg_const_i32(PPC_PM_SLEEP);
3646 gen_helper_pminsn(cpu_env, t);
3647 tcg_temp_free_i32(t);
3648 gen_stop_exception(ctx);
3649 #endif /* defined(CONFIG_USER_ONLY) */
3650 }
3651
3652 static void gen_rvwinkle(DisasContext *ctx)
3653 {
3654 #if defined(CONFIG_USER_ONLY)
3655 GEN_PRIV;
3656 #else
3657 TCGv_i32 t;
3658
3659 CHK_HV;
3660 t = tcg_const_i32(PPC_PM_RVWINKLE);
3661 gen_helper_pminsn(cpu_env, t);
3662 tcg_temp_free_i32(t);
3663 gen_stop_exception(ctx);
3664 #endif /* defined(CONFIG_USER_ONLY) */
3665 }
3666 #endif /* #if defined(TARGET_PPC64) */
3667
3668 /*** Floating-point load ***/
3669 #define GEN_LDF(name, ldop, opc, type) \
3670 static void glue(gen_, name)(DisasContext *ctx) \
3671 { \
3672 TCGv EA; \
3673 if (unlikely(!ctx->fpu_enabled)) { \
3674 gen_exception(ctx, POWERPC_EXCP_FPU); \
3675 return; \
3676 } \
3677 gen_set_access_type(ctx, ACCESS_FLOAT); \
3678 EA = tcg_temp_new(); \
3679 gen_addr_imm_index(ctx, EA, 0); \
3680 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3681 tcg_temp_free(EA); \
3682 }
3683
3684 #define GEN_LDUF(name, ldop, opc, type) \
3685 static void glue(gen_, name##u)(DisasContext *ctx) \
3686 { \
3687 TCGv EA; \
3688 if (unlikely(!ctx->fpu_enabled)) { \
3689 gen_exception(ctx, POWERPC_EXCP_FPU); \
3690 return; \
3691 } \
3692 if (unlikely(rA(ctx->opcode) == 0)) { \
3693 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3694 return; \
3695 } \
3696 gen_set_access_type(ctx, ACCESS_FLOAT); \
3697 EA = tcg_temp_new(); \
3698 gen_addr_imm_index(ctx, EA, 0); \
3699 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3700 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3701 tcg_temp_free(EA); \
3702 }
3703
3704 #define GEN_LDUXF(name, ldop, opc, type) \
3705 static void glue(gen_, name##ux)(DisasContext *ctx) \
3706 { \
3707 TCGv EA; \
3708 if (unlikely(!ctx->fpu_enabled)) { \
3709 gen_exception(ctx, POWERPC_EXCP_FPU); \
3710 return; \
3711 } \
3712 if (unlikely(rA(ctx->opcode) == 0)) { \
3713 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3714 return; \
3715 } \
3716 gen_set_access_type(ctx, ACCESS_FLOAT); \
3717 EA = tcg_temp_new(); \
3718 gen_addr_reg_index(ctx, EA); \
3719 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3720 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3721 tcg_temp_free(EA); \
3722 }
3723
3724 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3725 static void glue(gen_, name##x)(DisasContext *ctx) \
3726 { \
3727 TCGv EA; \
3728 if (unlikely(!ctx->fpu_enabled)) { \
3729 gen_exception(ctx, POWERPC_EXCP_FPU); \
3730 return; \
3731 } \
3732 gen_set_access_type(ctx, ACCESS_FLOAT); \
3733 EA = tcg_temp_new(); \
3734 gen_addr_reg_index(ctx, EA); \
3735 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3736 tcg_temp_free(EA); \
3737 }
3738
3739 #define GEN_LDFS(name, ldop, op, type) \
3740 GEN_LDF(name, ldop, op | 0x20, type); \
3741 GEN_LDUF(name, ldop, op | 0x21, type); \
3742 GEN_LDUXF(name, ldop, op | 0x01, type); \
3743 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3744
3745 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3746 {
3747 TCGv t0 = tcg_temp_new();
3748 TCGv_i32 t1 = tcg_temp_new_i32();
3749 gen_qemu_ld32u(ctx, t0, arg2);
3750 tcg_gen_trunc_tl_i32(t1, t0);
3751 tcg_temp_free(t0);
3752 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3753 tcg_temp_free_i32(t1);
3754 }
3755
3756 /* lfd lfdu lfdux lfdx */
3757 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3758 /* lfs lfsu lfsux lfsx */
3759 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3760
3761 /* lfdp */
3762 static void gen_lfdp(DisasContext *ctx)
3763 {
3764 TCGv EA;
3765 if (unlikely(!ctx->fpu_enabled)) {
3766 gen_exception(ctx, POWERPC_EXCP_FPU);
3767 return;
3768 }
3769 gen_set_access_type(ctx, ACCESS_FLOAT);
3770 EA = tcg_temp_new();
3771 gen_addr_imm_index(ctx, EA, 0);
3772 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3773 64-bit byteswap already. */
3774 if (unlikely(ctx->le_mode)) {
3775 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3776 tcg_gen_addi_tl(EA, EA, 8);
3777 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3778 } else {
3779 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3780 tcg_gen_addi_tl(EA, EA, 8);
3781 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3782 }
3783 tcg_temp_free(EA);
3784 }
3785
3786 /* lfdpx */
3787 static void gen_lfdpx(DisasContext *ctx)
3788 {
3789 TCGv EA;
3790 if (unlikely(!ctx->fpu_enabled)) {
3791 gen_exception(ctx, POWERPC_EXCP_FPU);
3792 return;
3793 }
3794 gen_set_access_type(ctx, ACCESS_FLOAT);
3795 EA = tcg_temp_new();
3796 gen_addr_reg_index(ctx, EA);
3797 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3798 64-bit byteswap already. */
3799 if (unlikely(ctx->le_mode)) {
3800 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3801 tcg_gen_addi_tl(EA, EA, 8);
3802 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3803 } else {
3804 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3805 tcg_gen_addi_tl(EA, EA, 8);
3806 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3807 }
3808 tcg_temp_free(EA);
3809 }
3810
3811 /* lfiwax */
3812 static void gen_lfiwax(DisasContext *ctx)
3813 {
3814 TCGv EA;
3815 TCGv t0;
3816 if (unlikely(!ctx->fpu_enabled)) {
3817 gen_exception(ctx, POWERPC_EXCP_FPU);
3818 return;
3819 }
3820 gen_set_access_type(ctx, ACCESS_FLOAT);
3821 EA = tcg_temp_new();
3822 t0 = tcg_temp_new();
3823 gen_addr_reg_index(ctx, EA);
3824 gen_qemu_ld32s(ctx, t0, EA);
3825 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3826 tcg_temp_free(EA);
3827 tcg_temp_free(t0);
3828 }
3829
3830 /* lfiwzx */
3831 static void gen_lfiwzx(DisasContext *ctx)
3832 {
3833 TCGv EA;
3834 if (unlikely(!ctx->fpu_enabled)) {
3835 gen_exception(ctx, POWERPC_EXCP_FPU);
3836 return;
3837 }
3838 gen_set_access_type(ctx, ACCESS_FLOAT);
3839 EA = tcg_temp_new();
3840 gen_addr_reg_index(ctx, EA);
3841 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3842 tcg_temp_free(EA);
3843 }
3844 /*** Floating-point store ***/
3845 #define GEN_STF(name, stop, opc, type) \
3846 static void glue(gen_, name)(DisasContext *ctx) \
3847 { \
3848 TCGv EA; \
3849 if (unlikely(!ctx->fpu_enabled)) { \
3850 gen_exception(ctx, POWERPC_EXCP_FPU); \
3851 return; \
3852 } \
3853 gen_set_access_type(ctx, ACCESS_FLOAT); \
3854 EA = tcg_temp_new(); \
3855 gen_addr_imm_index(ctx, EA, 0); \
3856 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3857 tcg_temp_free(EA); \
3858 }
3859
3860 #define GEN_STUF(name, stop, opc, type) \
3861 static void glue(gen_, name##u)(DisasContext *ctx) \
3862 { \
3863 TCGv EA; \
3864 if (unlikely(!ctx->fpu_enabled)) { \
3865 gen_exception(ctx, POWERPC_EXCP_FPU); \
3866 return; \
3867 } \
3868 if (unlikely(rA(ctx->opcode) == 0)) { \
3869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3870 return; \
3871 } \
3872 gen_set_access_type(ctx, ACCESS_FLOAT); \
3873 EA = tcg_temp_new(); \
3874 gen_addr_imm_index(ctx, EA, 0); \
3875 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3877 tcg_temp_free(EA); \
3878 }
3879
3880 #define GEN_STUXF(name, stop, opc, type) \
3881 static void glue(gen_, name##ux)(DisasContext *ctx) \
3882 { \
3883 TCGv EA; \
3884 if (unlikely(!ctx->fpu_enabled)) { \
3885 gen_exception(ctx, POWERPC_EXCP_FPU); \
3886 return; \
3887 } \
3888 if (unlikely(rA(ctx->opcode) == 0)) { \
3889 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3890 return; \
3891 } \
3892 gen_set_access_type(ctx, ACCESS_FLOAT); \
3893 EA = tcg_temp_new(); \
3894 gen_addr_reg_index(ctx, EA); \
3895 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3896 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3897 tcg_temp_free(EA); \
3898 }
3899
3900 #define GEN_STXF(name, stop, opc2, opc3, type) \
3901 static void glue(gen_, name##x)(DisasContext *ctx) \
3902 { \
3903 TCGv EA; \
3904 if (unlikely(!ctx->fpu_enabled)) { \
3905 gen_exception(ctx, POWERPC_EXCP_FPU); \
3906 return; \
3907 } \
3908 gen_set_access_type(ctx, ACCESS_FLOAT); \
3909 EA = tcg_temp_new(); \
3910 gen_addr_reg_index(ctx, EA); \
3911 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3912 tcg_temp_free(EA); \
3913 }
3914
3915 #define GEN_STFS(name, stop, op, type) \
3916 GEN_STF(name, stop, op | 0x20, type); \
3917 GEN_STUF(name, stop, op | 0x21, type); \
3918 GEN_STUXF(name, stop, op | 0x01, type); \
3919 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3920
3921 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3922 {
3923 TCGv_i32 t0 = tcg_temp_new_i32();
3924 TCGv t1 = tcg_temp_new();
3925 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3926 tcg_gen_extu_i32_tl(t1, t0);
3927 tcg_temp_free_i32(t0);
3928 gen_qemu_st32(ctx, t1, arg2);
3929 tcg_temp_free(t1);
3930 }
3931
3932 /* stfd stfdu stfdux stfdx */
3933 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3934 /* stfs stfsu stfsux stfsx */
3935 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3936
3937 /* stfdp */
3938 static void gen_stfdp(DisasContext *ctx)
3939 {
3940 TCGv EA;
3941 if (unlikely(!ctx->fpu_enabled)) {
3942 gen_exception(ctx, POWERPC_EXCP_FPU);
3943 return;
3944 }
3945 gen_set_access_type(ctx, ACCESS_FLOAT);
3946 EA = tcg_temp_new();
3947 gen_addr_imm_index(ctx, EA, 0);
3948 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3949 64-bit byteswap already. */
3950 if (unlikely(ctx->le_mode)) {
3951 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3952 tcg_gen_addi_tl(EA, EA, 8);
3953 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3954 } else {
3955 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3956 tcg_gen_addi_tl(EA, EA, 8);
3957 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3958 }
3959 tcg_temp_free(EA);
3960 }
3961
3962 /* stfdpx */
3963 static void gen_stfdpx(DisasContext *ctx)
3964 {
3965 TCGv EA;
3966 if (unlikely(!ctx->fpu_enabled)) {
3967 gen_exception(ctx, POWERPC_EXCP_FPU);
3968 return;
3969 }
3970 gen_set_access_type(ctx, ACCESS_FLOAT);
3971 EA = tcg_temp_new();
3972 gen_addr_reg_index(ctx, EA);
3973 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3974 64-bit byteswap already. */
3975 if (unlikely(ctx->le_mode)) {
3976 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3977 tcg_gen_addi_tl(EA, EA, 8);
3978 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3979 } else {
3980 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3981 tcg_gen_addi_tl(EA, EA, 8);
3982 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3983 }
3984 tcg_temp_free(EA);
3985 }
3986
3987 /* Optional: */
3988 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3989 {
3990 TCGv t0 = tcg_temp_new();
3991 tcg_gen_trunc_i64_tl(t0, arg1),
3992 gen_qemu_st32(ctx, t0, arg2);
3993 tcg_temp_free(t0);
3994 }
3995 /* stfiwx */
3996 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3997
3998 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3999 {
4000 #if defined(TARGET_PPC64)
4001 if (ctx->has_cfar)
4002 tcg_gen_movi_tl(cpu_cfar, nip);
4003 #endif
4004 }
4005
4006 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4007 {
4008 if (unlikely(ctx->singlestep_enabled)) {
4009 return false;
4010 }
4011
4012 #ifndef CONFIG_USER_ONLY
4013 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4014 #else
4015 return true;
4016 #endif
4017 }
4018
4019 /*** Branch ***/
4020 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4021 {
4022 if (NARROW_MODE(ctx)) {
4023 dest = (uint32_t) dest;
4024 }
4025 if (use_goto_tb(ctx, dest)) {
4026 tcg_gen_goto_tb(n);
4027 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4028 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
4029 } else {
4030 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4031 if (unlikely(ctx->singlestep_enabled)) {
4032 if ((ctx->singlestep_enabled &
4033 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
4034 (ctx->exception == POWERPC_EXCP_BRANCH ||
4035 ctx->exception == POWERPC_EXCP_TRACE)) {
4036 target_ulong tmp = ctx->nip;
4037 ctx->nip = dest;
4038 gen_exception(ctx, POWERPC_EXCP_TRACE);
4039 ctx->nip = tmp;
4040 }
4041 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
4042 gen_debug_exception(ctx);
4043 }
4044 }
4045 tcg_gen_exit_tb(0);
4046 }
4047 }
4048
4049 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4050 {
4051 if (NARROW_MODE(ctx)) {
4052 nip = (uint32_t)nip;
4053 }
4054 tcg_gen_movi_tl(cpu_lr, nip);
4055 }
4056
4057 /* b ba bl bla */
4058 static void gen_b(DisasContext *ctx)
4059 {
4060 target_ulong li, target;
4061
4062 ctx->exception = POWERPC_EXCP_BRANCH;
4063 /* sign extend LI */
4064 li = LI(ctx->opcode);
4065 li = (li ^ 0x02000000) - 0x02000000;
4066 if (likely(AA(ctx->opcode) == 0)) {
4067 target = ctx->nip + li - 4;
4068 } else {
4069 target = li;
4070 }
4071 if (LK(ctx->opcode)) {
4072 gen_setlr(ctx, ctx->nip);
4073 }
4074 gen_update_cfar(ctx, ctx->nip);
4075 gen_goto_tb(ctx, 0, target);
4076 }
4077
4078 #define BCOND_IM 0
4079 #define BCOND_LR 1
4080 #define BCOND_CTR 2
4081 #define BCOND_TAR 3
4082
4083 static inline void gen_bcond(DisasContext *ctx, int type)
4084 {
4085 uint32_t bo = BO(ctx->opcode);
4086 TCGLabel *l1;
4087 TCGv target;
4088
4089 ctx->exception = POWERPC_EXCP_BRANCH;
4090 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4091 target = tcg_temp_local_new();
4092 if (type == BCOND_CTR)
4093 tcg_gen_mov_tl(target, cpu_ctr);
4094 else if (type == BCOND_TAR)
4095 gen_load_spr(target, SPR_TAR);
4096 else
4097 tcg_gen_mov_tl(target, cpu_lr);
4098 } else {
4099 TCGV_UNUSED(target);
4100 }
4101 if (LK(ctx->opcode))
4102 gen_setlr(ctx, ctx->nip);
4103 l1 = gen_new_label();
4104 if ((bo & 0x4) == 0) {
4105 /* Decrement and test CTR */
4106 TCGv temp = tcg_temp_new();
4107 if (unlikely(type == BCOND_CTR)) {
4108 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4109 return;
4110 }
4111 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4112 if (NARROW_MODE(ctx)) {
4113 tcg_gen_ext32u_tl(temp, cpu_ctr);
4114 } else {
4115 tcg_gen_mov_tl(temp, cpu_ctr);
4116 }
4117 if (bo & 0x2) {
4118 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4119 } else {
4120 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4121 }
4122 tcg_temp_free(temp);
4123 }
4124 if ((bo & 0x10) == 0) {
4125 /* Test CR */
4126 uint32_t bi = BI(ctx->opcode);
4127 uint32_t mask = 0x08 >> (bi & 0x03);
4128 TCGv_i32 temp = tcg_temp_new_i32();
4129
4130 if (bo & 0x8) {
4131 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4132 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4133 } else {
4134 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4135 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4136 }
4137 tcg_temp_free_i32(temp);
4138 }
4139 gen_update_cfar(ctx, ctx->nip);
4140 if (type == BCOND_IM) {
4141 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4142 if (likely(AA(ctx->opcode) == 0)) {
4143 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
4144 } else {
4145 gen_goto_tb(ctx, 0, li);
4146 }
4147 gen_set_label(l1);
4148 gen_goto_tb(ctx, 1, ctx->nip);
4149 } else {
4150 if (NARROW_MODE(ctx)) {
4151 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4152 } else {
4153 tcg_gen_andi_tl(cpu_nip, target, ~3);
4154 }
4155 tcg_gen_exit_tb(0);
4156 gen_set_label(l1);
4157 gen_update_nip(ctx, ctx->nip);
4158 tcg_gen_exit_tb(0);
4159 }
4160 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4161 tcg_temp_free(target);
4162 }
4163 }
4164
4165 static void gen_bc(DisasContext *ctx)
4166 {
4167 gen_bcond(ctx, BCOND_IM);
4168 }
4169
4170 static void gen_bcctr(DisasContext *ctx)
4171 {
4172 gen_bcond(ctx, BCOND_CTR);
4173 }
4174
4175 static void gen_bclr(DisasContext *ctx)
4176 {
4177 gen_bcond(ctx, BCOND_LR);
4178 }
4179
4180 static void gen_bctar(DisasContext *ctx)
4181 {
4182 gen_bcond(ctx, BCOND_TAR);
4183 }
4184
4185 /*** Condition register logical ***/
4186 #define GEN_CRLOGIC(name, tcg_op, opc) \
4187 static void glue(gen_, name)(DisasContext *ctx) \
4188 { \
4189 uint8_t bitmask; \
4190 int sh; \
4191 TCGv_i32 t0, t1; \
4192 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4193 t0 = tcg_temp_new_i32(); \
4194 if (sh > 0) \
4195 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4196 else if (sh < 0) \
4197 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4198 else \
4199 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4200 t1 = tcg_temp_new_i32(); \
4201 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4202 if (sh > 0) \
4203 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4204 else if (sh < 0) \
4205 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4206 else \
4207 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4208 tcg_op(t0, t0, t1); \
4209 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4210 tcg_gen_andi_i32(t0, t0, bitmask); \
4211 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4212 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4213 tcg_temp_free_i32(t0); \
4214 tcg_temp_free_i32(t1); \
4215 }
4216
4217 /* crand */
4218 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4219 /* crandc */
4220 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4221 /* creqv */
4222 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4223 /* crnand */
4224 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4225 /* crnor */
4226 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4227 /* cror */
4228 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4229 /* crorc */
4230 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4231 /* crxor */
4232 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4233
4234 /* mcrf */
4235 static void gen_mcrf(DisasContext *ctx)
4236 {
4237 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4238 }
4239
4240 /*** System linkage ***/
4241
4242 /* rfi (supervisor only) */
4243 static void gen_rfi(DisasContext *ctx)
4244 {
4245 #if defined(CONFIG_USER_ONLY)
4246 GEN_PRIV;
4247 #else
4248 /* FIXME: This instruction doesn't exist anymore on 64-bit server
4249 * processors compliant with arch 2.x, we should remove it there,
4250 * but we need to fix OpenBIOS not to use it on 970 first
4251 */
4252 /* Restore CPU state */
4253 CHK_SV;
4254 gen_update_cfar(ctx, ctx->nip);
4255 gen_helper_rfi(cpu_env);
4256 gen_sync_exception(ctx);
4257 #endif
4258 }
4259
4260 #if defined(TARGET_PPC64)
4261 static void gen_rfid(DisasContext *ctx)
4262 {
4263 #if defined(CONFIG_USER_ONLY)
4264 GEN_PRIV;
4265 #else
4266 /* Restore CPU state */
4267 CHK_SV;
4268 gen_update_cfar(ctx, ctx->nip);
4269 gen_helper_rfid(cpu_env);
4270 gen_sync_exception(ctx);
4271 #endif
4272 }
4273
4274 static void gen_hrfid(DisasContext *ctx)
4275 {
4276 #if defined(CONFIG_USER_ONLY)
4277 GEN_PRIV;
4278 #else
4279 /* Restore CPU state */
4280 CHK_HV;
4281 gen_helper_hrfid(cpu_env);
4282 gen_sync_exception(ctx);
4283 #endif
4284 }
4285 #endif
4286
4287 /* sc */
4288 #if defined(CONFIG_USER_ONLY)
4289 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4290 #else
4291 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4292 #endif
4293 static void gen_sc(DisasContext *ctx)
4294 {
4295 uint32_t lev;
4296
4297 lev = (ctx->opcode >> 5) & 0x7F;
4298 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4299 }
4300
4301 /*** Trap ***/
4302
4303 /* tw */
4304 static void gen_tw(DisasContext *ctx)
4305 {
4306 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4307 /* Update the nip since this might generate a trap exception */
4308 gen_update_nip(ctx, ctx->nip);
4309 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4310 t0);
4311 tcg_temp_free_i32(t0);
4312 }
4313
4314 /* twi */
4315 static void gen_twi(DisasContext *ctx)
4316 {
4317 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4318 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4319 /* Update the nip since this might generate a trap exception */
4320 gen_update_nip(ctx, ctx->nip);
4321 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4322 tcg_temp_free(t0);
4323 tcg_temp_free_i32(t1);
4324 }
4325
4326 #if defined(TARGET_PPC64)
4327 /* td */
4328 static void gen_td(DisasContext *ctx)
4329 {
4330 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4331 /* Update the nip since this might generate a trap exception */
4332 gen_update_nip(ctx, ctx->nip);
4333 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4334 t0);
4335 tcg_temp_free_i32(t0);
4336 }
4337
4338 /* tdi */
4339 static void gen_tdi(DisasContext *ctx)
4340 {
4341 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4342 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4343 /* Update the nip since this might generate a trap exception */
4344 gen_update_nip(ctx, ctx->nip);
4345 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4346 tcg_temp_free(t0);
4347 tcg_temp_free_i32(t1);
4348 }
4349 #endif
4350
4351 /*** Processor control ***/
4352
4353 static void gen_read_xer(TCGv dst)
4354 {
4355 TCGv t0 = tcg_temp_new();
4356 TCGv t1 = tcg_temp_new();
4357 TCGv t2 = tcg_temp_new();
4358 tcg_gen_mov_tl(dst, cpu_xer);
4359 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4360 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4361 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4362 tcg_gen_or_tl(t0, t0, t1);
4363 tcg_gen_or_tl(dst, dst, t2);
4364 tcg_gen_or_tl(dst, dst, t0);
4365 tcg_temp_free(t0);
4366 tcg_temp_free(t1);
4367 tcg_temp_free(t2);
4368 }
4369
4370 static void gen_write_xer(TCGv src)
4371 {
4372 tcg_gen_andi_tl(cpu_xer, src,
4373 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4374 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4375 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4376 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4377 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4378 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4379 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4380 }
4381
4382 /* mcrxr */
4383 static void gen_mcrxr(DisasContext *ctx)
4384 {
4385 TCGv_i32 t0 = tcg_temp_new_i32();
4386 TCGv_i32 t1 = tcg_temp_new_i32();
4387 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4388
4389 tcg_gen_trunc_tl_i32(t0, cpu_so);
4390 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4391 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4392 tcg_gen_shli_i32(t0, t0, 3);
4393 tcg_gen_shli_i32(t1, t1, 2);
4394 tcg_gen_shli_i32(dst, dst, 1);
4395 tcg_gen_or_i32(dst, dst, t0);
4396 tcg_gen_or_i32(dst, dst, t1);
4397 tcg_temp_free_i32(t0);
4398 tcg_temp_free_i32(t1);
4399
4400 tcg_gen_movi_tl(cpu_so, 0);
4401 tcg_gen_movi_tl(cpu_ov, 0);
4402 tcg_gen_movi_tl(cpu_ca, 0);
4403 }
4404
4405 /* mfcr mfocrf */
4406 static void gen_mfcr(DisasContext *ctx)
4407 {
4408 uint32_t crm, crn;
4409
4410 if (likely(ctx->opcode & 0x00100000)) {
4411 crm = CRM(ctx->opcode);
4412 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4413 crn = ctz32 (crm);
4414 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4415 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4416 cpu_gpr[rD(ctx->opcode)], crn * 4);
4417 }
4418 } else {
4419 TCGv_i32 t0 = tcg_temp_new_i32();
4420 tcg_gen_mov_i32(t0, cpu_crf[0]);
4421 tcg_gen_shli_i32(t0, t0, 4);
4422 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4423 tcg_gen_shli_i32(t0, t0, 4);
4424 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4425 tcg_gen_shli_i32(t0, t0, 4);
4426 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4427 tcg_gen_shli_i32(t0, t0, 4);
4428 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4429 tcg_gen_shli_i32(t0, t0, 4);
4430 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4431 tcg_gen_shli_i32(t0, t0, 4);
4432 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4433 tcg_gen_shli_i32(t0, t0, 4);
4434 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4435 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4436 tcg_temp_free_i32(t0);
4437 }
4438 }
4439
4440 /* mfmsr */
4441 static void gen_mfmsr(DisasContext *ctx)
4442 {
4443 CHK_SV;
4444 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4445 }
4446
4447 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4448 {
4449 #if 0
4450 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4451 printf("ERROR: try to access SPR %d !\n", sprn);
4452 #endif
4453 }
4454 #define SPR_NOACCESS (&spr_noaccess)
4455
4456 /* mfspr */
4457 static inline void gen_op_mfspr(DisasContext *ctx)
4458 {
4459 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4460 uint32_t sprn = SPR(ctx->opcode);
4461
4462 #if defined(CONFIG_USER_ONLY)
4463 read_cb = ctx->spr_cb[sprn].uea_read;
4464 #else
4465 if (ctx->pr) {
4466 read_cb = ctx->spr_cb[sprn].uea_read;
4467 } else if (ctx->hv) {
4468 read_cb = ctx->spr_cb[sprn].hea_read;
4469 } else {
4470 read_cb = ctx->spr_cb[sprn].oea_read;
4471 }
4472 #endif
4473 if (likely(read_cb != NULL)) {
4474 if (likely(read_cb != SPR_NOACCESS)) {
4475 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4476 } else {
4477 /* Privilege exception */
4478 /* This is a hack to avoid warnings when running Linux:
4479 * this OS breaks the PowerPC virtualisation model,
4480 * allowing userland application to read the PVR
4481 */
4482 if (sprn != SPR_PVR) {
4483 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4484 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4485 if (qemu_log_separate()) {
4486 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4487 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4488 }
4489 }
4490 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4491 }
4492 } else {
4493 /* ISA 2.07 defines these as no-ops */
4494 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4495 (sprn >= 808 && sprn <= 811)) {
4496 /* This is a nop */
4497 return;
4498 }
4499 /* Not defined */
4500 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4501 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4502 if (qemu_log_separate()) {
4503 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4504 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4505 }
4506
4507 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4508 * it can generate a priv, a hv emu or a no-op
4509 */
4510 if (sprn & 0x10) {
4511 if (ctx->pr) {
4512 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4513 }
4514 } else {
4515 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4516 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4517 }
4518 }
4519 }
4520 }
4521
4522 static void gen_mfspr(DisasContext *ctx)
4523 {
4524 gen_op_mfspr(ctx);
4525 }
4526
4527 /* mftb */
4528 static void gen_mftb(DisasContext *ctx)
4529 {
4530 gen_op_mfspr(ctx);
4531 }
4532
4533 /* mtcrf mtocrf*/
4534 static void gen_mtcrf(DisasContext *ctx)
4535 {
4536 uint32_t crm, crn;
4537
4538 crm = CRM(ctx->opcode);
4539 if (likely((ctx->opcode & 0x00100000))) {
4540 if (crm && ((crm & (crm - 1)) == 0)) {
4541 TCGv_i32 temp = tcg_temp_new_i32();
4542 crn = ctz32 (crm);
4543 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4544 tcg_gen_shri_i32(temp, temp, crn * 4);
4545 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4546 tcg_temp_free_i32(temp);
4547 }
4548 } else {
4549 TCGv_i32 temp = tcg_temp_new_i32();
4550 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4551 for (crn = 0 ; crn < 8 ; crn++) {
4552 if (crm & (1 << crn)) {
4553 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4554 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4555 }
4556 }
4557 tcg_temp_free_i32(temp);
4558 }
4559 }
4560
4561 /* mtmsr */
4562 #if defined(TARGET_PPC64)
4563 static void gen_mtmsrd(DisasContext *ctx)
4564 {
4565 CHK_SV;
4566
4567 #if !defined(CONFIG_USER_ONLY)
4568 if (ctx->opcode & 0x00010000) {
4569 /* Special form that does not need any synchronisation */
4570 TCGv t0 = tcg_temp_new();
4571 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4572 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4573 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4574 tcg_temp_free(t0);
4575 } else {
4576 /* XXX: we need to update nip before the store
4577 * if we enter power saving mode, we will exit the loop
4578 * directly from ppc_store_msr
4579 */
4580 gen_update_nip(ctx, ctx->nip);
4581 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4582 /* Must stop the translation as machine state (may have) changed */
4583 /* Note that mtmsr is not always defined as context-synchronizing */
4584 gen_stop_exception(ctx);
4585 }
4586 #endif /* !defined(CONFIG_USER_ONLY) */
4587 }
4588 #endif /* defined(TARGET_PPC64) */
4589
4590 static void gen_mtmsr(DisasContext *ctx)
4591 {
4592 CHK_SV;
4593
4594 #if !defined(CONFIG_USER_ONLY)
4595 if (ctx->opcode & 0x00010000) {
4596 /* Special form that does not need any synchronisation */
4597 TCGv t0 = tcg_temp_new();
4598 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4599 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4600 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4601 tcg_temp_free(t0);
4602 } else {
4603 TCGv msr = tcg_temp_new();
4604
4605 /* XXX: we need to update nip before the store
4606 * if we enter power saving mode, we will exit the loop
4607 * directly from ppc_store_msr
4608 */
4609 gen_update_nip(ctx, ctx->nip);
4610 #if defined(TARGET_PPC64)
4611 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4612 #else
4613 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4614 #endif
4615 gen_helper_store_msr(cpu_env, msr);
4616 tcg_temp_free(msr);
4617 /* Must stop the translation as machine state (may have) changed */
4618 /* Note that mtmsr is not always defined as context-synchronizing */
4619 gen_stop_exception(ctx);
4620 }
4621 #endif
4622 }
4623
4624 /* mtspr */
4625 static void gen_mtspr(DisasContext *ctx)
4626 {
4627 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4628 uint32_t sprn = SPR(ctx->opcode);
4629
4630 #if defined(CONFIG_USER_ONLY)
4631 write_cb = ctx->spr_cb[sprn].uea_write;
4632 #else
4633 if (ctx->pr) {
4634 write_cb = ctx->spr_cb[sprn].uea_write;
4635 } else if (ctx->hv) {
4636 write_cb = ctx->spr_cb[sprn].hea_write;
4637 } else {
4638 write_cb = ctx->spr_cb[sprn].oea_write;
4639 }
4640 #endif
4641 if (likely(write_cb != NULL)) {
4642 if (likely(write_cb != SPR_NOACCESS)) {
4643 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4644 } else {
4645 /* Privilege exception */
4646 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4647 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4648 if (qemu_log_separate()) {
4649 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4650 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4651 }
4652 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4653 }
4654 } else {
4655 /* ISA 2.07 defines these as no-ops */
4656 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4657 (sprn >= 808 && sprn <= 811)) {
4658 /* This is a nop */
4659 return;
4660 }
4661
4662 /* Not defined */
4663 if (qemu_log_separate()) {
4664 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4665 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4666 }
4667 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4668 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4669
4670
4671 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4672 * it can generate a priv, a hv emu or a no-op
4673 */
4674 if (sprn & 0x10) {
4675 if (ctx->pr) {
4676 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4677 }
4678 } else {
4679 if (ctx->pr || sprn == 0) {
4680 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4681 }
4682 }
4683 }
4684 }
4685
4686 /*** Cache management ***/
4687
4688 /* dcbf */
4689 static void gen_dcbf(DisasContext *ctx)
4690 {
4691 /* XXX: specification says this is treated as a load by the MMU */
4692 TCGv t0;
4693 gen_set_access_type(ctx, ACCESS_CACHE);
4694 t0 = tcg_temp_new();
4695 gen_addr_reg_index(ctx, t0);
4696 gen_qemu_ld8u(ctx, t0, t0);
4697 tcg_temp_free(t0);
4698 }
4699
4700 /* dcbi (Supervisor only) */
4701 static void gen_dcbi(DisasContext *ctx)
4702 {
4703 #if defined(CONFIG_USER_ONLY)
4704 GEN_PRIV;
4705 #else
4706 TCGv EA, val;
4707
4708 CHK_SV;
4709 EA = tcg_temp_new();
4710 gen_set_access_type(ctx, ACCESS_CACHE);
4711 gen_addr_reg_index(ctx, EA);
4712 val = tcg_temp_new();
4713 /* XXX: specification says this should be treated as a store by the MMU */
4714 gen_qemu_ld8u(ctx, val, EA);
4715 gen_qemu_st8(ctx, val, EA);
4716 tcg_temp_free(val);
4717 tcg_temp_free(EA);
4718 #endif /* defined(CONFIG_USER_ONLY) */
4719 }
4720
4721 /* dcdst */
4722 static void gen_dcbst(DisasContext *ctx)
4723 {
4724 /* XXX: specification say this is treated as a load by the MMU */
4725 TCGv t0;
4726 gen_set_access_type(ctx, ACCESS_CACHE);
4727 t0 = tcg_temp_new();
4728 gen_addr_reg_index(ctx, t0);
4729 gen_qemu_ld8u(ctx, t0, t0);
4730 tcg_temp_free(t0);
4731 }
4732
4733 /* dcbt */
4734 static void gen_dcbt(DisasContext *ctx)
4735 {
4736 /* interpreted as no-op */
4737 /* XXX: specification say this is treated as a load by the MMU
4738 * but does not generate any exception
4739 */
4740 }
4741
4742 /* dcbtst */
4743 static void gen_dcbtst(DisasContext *ctx)
4744 {
4745 /* interpreted as no-op */
4746 /* XXX: specification say this is treated as a load by the MMU
4747 * but does not generate any exception
4748 */
4749 }
4750
4751 /* dcbtls */
4752 static void gen_dcbtls(DisasContext *ctx)
4753 {
4754 /* Always fails locking the cache */
4755 TCGv t0 = tcg_temp_new();
4756 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4757 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4758 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4759 tcg_temp_free(t0);
4760 }
4761
4762 /* dcbz */
4763 static void gen_dcbz(DisasContext *ctx)
4764 {
4765 TCGv tcgv_addr;
4766 TCGv_i32 tcgv_is_dcbzl;
4767 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4768
4769 gen_set_access_type(ctx, ACCESS_CACHE);
4770 /* NIP cannot be restored if the memory exception comes from an helper */
4771 gen_update_nip(ctx, ctx->nip - 4);
4772 tcgv_addr = tcg_temp_new();
4773 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4774
4775 gen_addr_reg_index(ctx, tcgv_addr);
4776 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4777
4778 tcg_temp_free(tcgv_addr);
4779 tcg_temp_free_i32(tcgv_is_dcbzl);
4780 }
4781
4782 /* dst / dstt */
4783 static void gen_dst(DisasContext *ctx)
4784 {
4785 if (rA(ctx->opcode) == 0) {
4786 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4787 } else {
4788 /* interpreted as no-op */
4789 }
4790 }
4791
4792 /* dstst /dststt */
4793 static void gen_dstst(DisasContext *ctx)
4794 {
4795 if (rA(ctx->opcode) == 0) {
4796 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4797 } else {
4798 /* interpreted as no-op */
4799 }
4800
4801 }
4802
4803 /* dss / dssall */
4804 static void gen_dss(DisasContext *ctx)
4805 {
4806 /* interpreted as no-op */
4807 }
4808
4809 /* icbi */
4810 static void gen_icbi(DisasContext *ctx)
4811 {
4812 TCGv t0;
4813 gen_set_access_type(ctx, ACCESS_CACHE);
4814 /* NIP cannot be restored if the memory exception comes from an helper */
4815 gen_update_nip(ctx, ctx->nip - 4);
4816 t0 = tcg_temp_new();
4817 gen_addr_reg_index(ctx, t0);
4818 gen_helper_icbi(cpu_env, t0);
4819 tcg_temp_free(t0);
4820 }
4821
4822 /* Optional: */
4823 /* dcba */
4824 static void gen_dcba(DisasContext *ctx)
4825 {
4826 /* interpreted as no-op */
4827 /* XXX: specification say this is treated as a store by the MMU
4828 * but does not generate any exception
4829 */
4830 }
4831
4832 /*** Segment register manipulation ***/
4833 /* Supervisor only: */
4834
4835 /* mfsr */
4836 static void gen_mfsr(DisasContext *ctx)
4837 {
4838 #if defined(CONFIG_USER_ONLY)
4839 GEN_PRIV;
4840 #else
4841 TCGv t0;
4842
4843 CHK_SV;
4844 t0 = tcg_const_tl(SR(ctx->opcode));
4845 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4846 tcg_temp_free(t0);
4847 #endif /* defined(CONFIG_USER_ONLY) */
4848 }
4849
4850 /* mfsrin */
4851 static void gen_mfsrin(DisasContext *ctx)
4852 {
4853 #if defined(CONFIG_USER_ONLY)
4854 GEN_PRIV;
4855 #else
4856 TCGv t0;
4857
4858 CHK_SV;
4859 t0 = tcg_temp_new();
4860 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4861 tcg_gen_andi_tl(t0, t0, 0xF);
4862 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4863 tcg_temp_free(t0);
4864 #endif /* defined(CONFIG_USER_ONLY) */
4865 }
4866
4867 /* mtsr */
4868 static void gen_mtsr(DisasContext *ctx)
4869 {
4870 #if defined(CONFIG_USER_ONLY)
4871 GEN_PRIV;
4872 #else
4873 TCGv t0;
4874
4875 CHK_SV;
4876 t0 = tcg_const_tl(SR(ctx->opcode));
4877 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4878 tcg_temp_free(t0);
4879 #endif /* defined(CONFIG_USER_ONLY) */
4880 }
4881
4882 /* mtsrin */
4883 static void gen_mtsrin(DisasContext *ctx)
4884 {
4885 #if defined(CONFIG_USER_ONLY)
4886 GEN_PRIV;
4887 #else
4888 TCGv t0;
4889 CHK_SV;
4890
4891 t0 = tcg_temp_new();
4892 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4893 tcg_gen_andi_tl(t0, t0, 0xF);
4894 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4895 tcg_temp_free(t0);
4896 #endif /* defined(CONFIG_USER_ONLY) */
4897 }
4898
4899 #if defined(TARGET_PPC64)
4900 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4901
4902 /* mfsr */
4903 static void gen_mfsr_64b(DisasContext *ctx)
4904 {
4905 #if defined(CONFIG_USER_ONLY)
4906 GEN_PRIV;
4907 #else
4908 TCGv t0;
4909
4910 CHK_SV;
4911 t0 = tcg_const_tl(SR(ctx->opcode));
4912 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4913 tcg_temp_free(t0);
4914 #endif /* defined(CONFIG_USER_ONLY) */
4915 }
4916
4917 /* mfsrin */
4918 static void gen_mfsrin_64b(DisasContext *ctx)
4919 {
4920 #if defined(CONFIG_USER_ONLY)
4921 GEN_PRIV;
4922 #else
4923 TCGv t0;
4924
4925 CHK_SV;
4926 t0 = tcg_temp_new();
4927 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4928 tcg_gen_andi_tl(t0, t0, 0xF);
4929 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4930 tcg_temp_free(t0);
4931 #endif /* defined(CONFIG_USER_ONLY) */
4932 }
4933
4934 /* mtsr */
4935 static void gen_mtsr_64b(DisasContext *ctx)
4936 {
4937 #if defined(CONFIG_USER_ONLY)
4938 GEN_PRIV;
4939 #else
4940 TCGv t0;
4941
4942 CHK_SV;
4943 t0 = tcg_const_tl(SR(ctx->opcode));
4944 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4945 tcg_temp_free(t0);
4946 #endif /* defined(CONFIG_USER_ONLY) */
4947 }
4948
4949 /* mtsrin */
4950 static void gen_mtsrin_64b(DisasContext *ctx)
4951 {
4952 #if defined(CONFIG_USER_ONLY)
4953 GEN_PRIV;
4954 #else
4955 TCGv t0;
4956
4957 CHK_SV;
4958 t0 = tcg_temp_new();
4959 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4960 tcg_gen_andi_tl(t0, t0, 0xF);
4961 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4962 tcg_temp_free(t0);
4963 #endif /* defined(CONFIG_USER_ONLY) */
4964 }
4965
4966 /* slbmte */
4967 static void gen_slbmte(DisasContext *ctx)
4968 {
4969 #if defined(CONFIG_USER_ONLY)
4970 GEN_PRIV;
4971 #else
4972 CHK_SV;
4973
4974 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4975 cpu_gpr[rS(ctx->opcode)]);
4976 #endif /* defined(CONFIG_USER_ONLY) */
4977 }
4978
4979 static void gen_slbmfee(DisasContext *ctx)
4980 {
4981 #if defined(CONFIG_USER_ONLY)
4982 GEN_PRIV;
4983 #else
4984 CHK_SV;
4985
4986 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4987 cpu_gpr[rB(ctx->opcode)]);
4988 #endif /* defined(CONFIG_USER_ONLY) */
4989 }
4990
4991 static void gen_slbmfev(DisasContext *ctx)
4992 {
4993 #if defined(CONFIG_USER_ONLY)
4994 GEN_PRIV;
4995 #else
4996 CHK_SV;
4997
4998 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4999 cpu_gpr[rB(ctx->opcode)]);
5000 #endif /* defined(CONFIG_USER_ONLY) */
5001 }
5002
5003 static void gen_slbfee_(DisasContext *ctx)
5004 {
5005 #if defined(CONFIG_USER_ONLY)
5006 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5007 #else
5008 TCGLabel *l1, *l2;
5009
5010 if (unlikely(ctx->pr)) {
5011 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5012 return;
5013 }
5014 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5015 cpu_gpr[rB(ctx->opcode)]);
5016 l1 = gen_new_label();
5017 l2 = gen_new_label();
5018 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5019 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5020 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
5021 tcg_gen_br(l2);
5022 gen_set_label(l1);
5023 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5024 gen_set_label(l2);
5025 #endif
5026 }
5027 #endif /* defined(TARGET_PPC64) */
5028
5029 /*** Lookaside buffer management ***/
5030 /* Optional & supervisor only: */
5031
5032 /* tlbia */
5033 static void gen_tlbia(DisasContext *ctx)
5034 {
5035 #if defined(CONFIG_USER_ONLY)
5036 GEN_PRIV;
5037 #else
5038 CHK_HV;
5039
5040 gen_helper_tlbia(cpu_env);
5041 #endif /* defined(CONFIG_USER_ONLY) */
5042 }
5043
5044 /* tlbiel */
5045 static void gen_tlbiel(DisasContext *ctx)
5046 {
5047 #if defined(CONFIG_USER_ONLY)
5048 GEN_PRIV;
5049 #else
5050 CHK_SV;
5051
5052 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5053 #endif /* defined(CONFIG_USER_ONLY) */
5054 }
5055
5056 /* tlbie */
5057 static void gen_tlbie(DisasContext *ctx)
5058 {
5059 #if defined(CONFIG_USER_ONLY)
5060 GEN_PRIV;
5061 #else
5062 CHK_HV;
5063
5064 if (NARROW_MODE(ctx)) {
5065 TCGv t0 = tcg_temp_new();
5066 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
5067 gen_helper_tlbie(cpu_env, t0);
5068 tcg_temp_free(t0);
5069 } else {
5070 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5071 }
5072 #endif /* defined(CONFIG_USER_ONLY) */
5073 }
5074
5075 /* tlbsync */
5076 static void gen_tlbsync(DisasContext *ctx)
5077 {
5078 #if defined(CONFIG_USER_ONLY)
5079 GEN_PRIV;
5080 #else
5081 CHK_HV;
5082
5083 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
5084 * embedded however needs to deal with tlbsync. We don't try to be
5085 * fancy and swallow the overhead of checking for both.
5086 */
5087 gen_check_tlb_flush(ctx);
5088 #endif /* defined(CONFIG_USER_ONLY) */
5089 }
5090
5091 #if defined(TARGET_PPC64)
5092 /* slbia */
5093 static void gen_slbia(DisasContext *ctx)
5094 {
5095 #if defined(CONFIG_USER_ONLY)
5096 GEN_PRIV;
5097 #else
5098 CHK_SV;
5099
5100 gen_helper_slbia(cpu_env);
5101 #endif /* defined(CONFIG_USER_ONLY) */
5102 }
5103
5104 /* slbie */
5105 static void gen_slbie(DisasContext *ctx)
5106 {
5107 #if defined(CONFIG_USER_ONLY)
5108 GEN_PRIV;
5109 #else
5110 CHK_SV;
5111
5112 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5113 #endif /* defined(CONFIG_USER_ONLY) */
5114 }
5115 #endif /* defined(TARGET_PPC64) */
5116
5117 /*** External control ***/
5118 /* Optional: */
5119
5120 /* eciwx */
5121 static void gen_eciwx(DisasContext *ctx)
5122 {
5123 TCGv t0;
5124 /* Should check EAR[E] ! */
5125 gen_set_access_type(ctx, ACCESS_EXT);
5126 t0 = tcg_temp_new();
5127 gen_addr_reg_index(ctx, t0);
5128 gen_check_align(ctx, t0, 0x03);
5129 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5130 tcg_temp_free(t0);
5131 }
5132
5133 /* ecowx */
5134 static void gen_ecowx(DisasContext *ctx)
5135 {
5136 TCGv t0;
5137 /* Should check EAR[E] ! */
5138 gen_set_access_type(ctx, ACCESS_EXT);
5139 t0 = tcg_temp_new();
5140 gen_addr_reg_index(ctx, t0);
5141 gen_check_align(ctx, t0, 0x03);
5142 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5143 tcg_temp_free(t0);
5144 }
5145
5146 /* PowerPC 601 specific instructions */
5147
5148 /* abs - abs. */
5149 static void gen_abs(DisasContext *ctx)
5150 {
5151 TCGLabel *l1 = gen_new_label();
5152 TCGLabel *l2 = gen_new_label();
5153 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5154 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5155 tcg_gen_br(l2);
5156 gen_set_label(l1);
5157 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5158 gen_set_label(l2);
5159 if (unlikely(Rc(ctx->opcode) != 0))
5160 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5161 }
5162
5163 /* abso - abso. */
5164 static void gen_abso(DisasContext *ctx)
5165 {
5166 TCGLabel *l1 = gen_new_label();
5167 TCGLabel *l2 = gen_new_label();
5168 TCGLabel *l3 = gen_new_label();
5169 /* Start with XER OV disabled, the most likely case */
5170 tcg_gen_movi_tl(cpu_ov, 0);
5171 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5172 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5173 tcg_gen_movi_tl(cpu_ov, 1);
5174 tcg_gen_movi_tl(cpu_so, 1);
5175 tcg_gen_br(l2);
5176 gen_set_label(l1);
5177 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5178 tcg_gen_br(l3);
5179 gen_set_label(l2);
5180 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5181 gen_set_label(l3);
5182 if (unlikely(Rc(ctx->opcode) != 0))
5183 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5184 }
5185
5186 /* clcs */
5187 static void gen_clcs(DisasContext *ctx)
5188 {
5189 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5190 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5191 tcg_temp_free_i32(t0);
5192 /* Rc=1 sets CR0 to an undefined state */
5193 }
5194
5195 /* div - div. */
5196 static void gen_div(DisasContext *ctx)
5197 {
5198 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5199 cpu_gpr[rB(ctx->opcode)]);
5200 if (unlikely(Rc(ctx->opcode) != 0))
5201 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5202 }
5203
5204 /* divo - divo. */
5205 static void gen_divo(DisasContext *ctx)
5206 {
5207 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5208 cpu_gpr[rB(ctx->opcode)]);
5209 if (unlikely(Rc(ctx->opcode) != 0))
5210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5211 }
5212
5213 /* divs - divs. */
5214 static void gen_divs(DisasContext *ctx)
5215 {
5216 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5217 cpu_gpr[rB(ctx->opcode)]);
5218 if (unlikely(Rc(ctx->opcode) != 0))
5219 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5220 }
5221
5222 /* divso - divso. */
5223 static void gen_divso(DisasContext *ctx)
5224 {
5225 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5226 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5227 if (unlikely(Rc(ctx->opcode) != 0))
5228 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5229 }
5230
5231 /* doz - doz. */
5232 static void gen_doz(DisasContext *ctx)
5233 {
5234 TCGLabel *l1 = gen_new_label();
5235 TCGLabel *l2 = gen_new_label();
5236 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5237 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5238 tcg_gen_br(l2);
5239 gen_set_label(l1);
5240 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5241 gen_set_label(l2);
5242 if (unlikely(Rc(ctx->opcode) != 0))
5243 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5244 }
5245
5246 /* dozo - dozo. */
5247 static void gen_dozo(DisasContext *ctx)
5248 {
5249 TCGLabel *l1 = gen_new_label();
5250 TCGLabel *l2 = gen_new_label();
5251 TCGv t0 = tcg_temp_new();
5252 TCGv t1 = tcg_temp_new();
5253 TCGv t2 = tcg_temp_new();
5254 /* Start with XER OV disabled, the most likely case */
5255 tcg_gen_movi_tl(cpu_ov, 0);
5256 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5257 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5258 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5259 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5260 tcg_gen_andc_tl(t1, t1, t2);
5261 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5262 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5263 tcg_gen_movi_tl(cpu_ov, 1);
5264 tcg_gen_movi_tl(cpu_so, 1);
5265 tcg_gen_br(l2);
5266 gen_set_label(l1);
5267 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5268 gen_set_label(l2);
5269 tcg_temp_free(t0);
5270 tcg_temp_free(t1);
5271 tcg_temp_free(t2);
5272 if (unlikely(Rc(ctx->opcode) != 0))
5273 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5274 }
5275
5276 /* dozi */
5277 static void gen_dozi(DisasContext *ctx)
5278 {
5279 target_long simm = SIMM(ctx->opcode);
5280 TCGLabel *l1 = gen_new_label();
5281 TCGLabel *l2 = gen_new_label();
5282 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5283 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5284 tcg_gen_br(l2);
5285 gen_set_label(l1);
5286 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5287 gen_set_label(l2);
5288 if (unlikely(Rc(ctx->opcode) != 0))
5289 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5290 }
5291
5292 /* lscbx - lscbx. */
5293 static void gen_lscbx(DisasContext *ctx)
5294 {
5295 TCGv t0 = tcg_temp_new();
5296 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5297 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5298 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5299
5300 gen_addr_reg_index(ctx, t0);
5301 /* NIP cannot be restored if the memory exception comes from an helper */
5302 gen_update_nip(ctx, ctx->nip - 4);
5303 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5304 tcg_temp_free_i32(t1);
5305 tcg_temp_free_i32(t2);
5306 tcg_temp_free_i32(t3);
5307 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5308 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5309 if (unlikely(Rc(ctx->opcode) != 0))
5310 gen_set_Rc0(ctx, t0);
5311 tcg_temp_free(t0);
5312 }
5313
5314 /* maskg - maskg. */
5315 static void gen_maskg(DisasContext *ctx)
5316 {
5317 TCGLabel *l1 = gen_new_label();
5318 TCGv t0 = tcg_temp_new();
5319 TCGv t1 = tcg_temp_new();
5320 TCGv t2 = tcg_temp_new();
5321 TCGv t3 = tcg_temp_new();
5322 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5323 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5324 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5325 tcg_gen_addi_tl(t2, t0, 1);
5326 tcg_gen_shr_tl(t2, t3, t2);
5327 tcg_gen_shr_tl(t3, t3, t1);
5328 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5329 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5330 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5331 gen_set_label(l1);
5332 tcg_temp_free(t0);
5333 tcg_temp_free(t1);
5334 tcg_temp_free(t2);
5335 tcg_temp_free(t3);
5336 if (unlikely(Rc(ctx->opcode) != 0))
5337 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5338 }
5339
5340 /* maskir - maskir. */
5341 static void gen_maskir(DisasContext *ctx)
5342 {
5343 TCGv t0 = tcg_temp_new();
5344 TCGv t1 = tcg_temp_new();
5345 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5346 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5347 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5348 tcg_temp_free(t0);
5349 tcg_temp_free(t1);
5350 if (unlikely(Rc(ctx->opcode) != 0))
5351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5352 }
5353
5354 /* mul - mul. */
5355 static void gen_mul(DisasContext *ctx)
5356 {
5357 TCGv_i64 t0 = tcg_temp_new_i64();
5358 TCGv_i64 t1 = tcg_temp_new_i64();
5359 TCGv t2 = tcg_temp_new();
5360 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5361 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5362 tcg_gen_mul_i64(t0, t0, t1);
5363 tcg_gen_trunc_i64_tl(t2, t0);
5364 gen_store_spr(SPR_MQ, t2);
5365 tcg_gen_shri_i64(t1, t0, 32);
5366 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5367 tcg_temp_free_i64(t0);
5368 tcg_temp_free_i64(t1);
5369 tcg_temp_free(t2);
5370 if (unlikely(Rc(ctx->opcode) != 0))
5371 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5372 }
5373
5374 /* mulo - mulo. */
5375 static void gen_mulo(DisasContext *ctx)
5376 {
5377 TCGLabel *l1 = gen_new_label();
5378 TCGv_i64 t0 = tcg_temp_new_i64();
5379 TCGv_i64 t1 = tcg_temp_new_i64();
5380 TCGv t2 = tcg_temp_new();
5381 /* Start with XER OV disabled, the most likely case */
5382 tcg_gen_movi_tl(cpu_ov, 0);
5383 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5384 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5385 tcg_gen_mul_i64(t0, t0, t1);
5386 tcg_gen_trunc_i64_tl(t2, t0);
5387 gen_store_spr(SPR_MQ, t2);
5388 tcg_gen_shri_i64(t1, t0, 32);
5389 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5390 tcg_gen_ext32s_i64(t1, t0);
5391 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5392 tcg_gen_movi_tl(cpu_ov, 1);
5393 tcg_gen_movi_tl(cpu_so, 1);
5394 gen_set_label(l1);
5395 tcg_temp_free_i64(t0);
5396 tcg_temp_free_i64(t1);
5397 tcg_temp_free(t2);
5398 if (unlikely(Rc(ctx->opcode) != 0))
5399 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5400 }
5401
5402 /* nabs - nabs. */
5403 static void gen_nabs(DisasContext *ctx)
5404 {
5405 TCGLabel *l1 = gen_new_label();
5406 TCGLabel *l2 = gen_new_label();
5407 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5408 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5409 tcg_gen_br(l2);
5410 gen_set_label(l1);
5411 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5412 gen_set_label(l2);
5413 if (unlikely(Rc(ctx->opcode) != 0))
5414 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5415 }
5416
5417 /* nabso - nabso. */
5418 static void gen_nabso(DisasContext *ctx)
5419 {
5420 TCGLabel *l1 = gen_new_label();
5421 TCGLabel *l2 = gen_new_label();
5422 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5423 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5424 tcg_gen_br(l2);
5425 gen_set_label(l1);
5426 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5427 gen_set_label(l2);
5428 /* nabs never overflows */
5429 tcg_gen_movi_tl(cpu_ov, 0);
5430 if (unlikely(Rc(ctx->opcode) != 0))
5431 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5432 }
5433
5434 /* rlmi - rlmi. */
5435 static void gen_rlmi(DisasContext *ctx)
5436 {
5437 uint32_t mb = MB(ctx->opcode);
5438 uint32_t me = ME(ctx->opcode);
5439 TCGv t0 = tcg_temp_new();
5440 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5441 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5442 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5443 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5444 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5445 tcg_temp_free(t0);
5446 if (unlikely(Rc(ctx->opcode) != 0))
5447 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5448 }
5449
5450 /* rrib - rrib. */
5451 static void gen_rrib(DisasContext *ctx)
5452 {
5453 TCGv t0 = tcg_temp_new();
5454 TCGv t1 = tcg_temp_new();
5455 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5456 tcg_gen_movi_tl(t1, 0x80000000);
5457 tcg_gen_shr_tl(t1, t1, t0);
5458 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5459 tcg_gen_and_tl(t0, t0, t1);
5460 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5461 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5462 tcg_temp_free(t0);
5463 tcg_temp_free(t1);
5464 if (unlikely(Rc(ctx->opcode) != 0))
5465 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5466 }
5467
5468 /* sle - sle. */
5469 static void gen_sle(DisasContext *ctx)
5470 {
5471 TCGv t0 = tcg_temp_new();
5472 TCGv t1 = tcg_temp_new();
5473 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5474 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5475 tcg_gen_subfi_tl(t1, 32, t1);
5476 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5477 tcg_gen_or_tl(t1, t0, t1);
5478 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5479 gen_store_spr(SPR_MQ, t1);
5480 tcg_temp_free(t0);
5481 tcg_temp_free(t1);
5482 if (unlikely(Rc(ctx->opcode) != 0))
5483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5484 }
5485
5486 /* sleq - sleq. */
5487 static void gen_sleq(DisasContext *ctx)
5488 {
5489 TCGv t0 = tcg_temp_new();
5490 TCGv t1 = tcg_temp_new();
5491 TCGv t2 = tcg_temp_new();
5492 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5493 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5494 tcg_gen_shl_tl(t2, t2, t0);
5495 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5496 gen_load_spr(t1, SPR_MQ);
5497 gen_store_spr(SPR_MQ, t0);
5498 tcg_gen_and_tl(t0, t0, t2);
5499 tcg_gen_andc_tl(t1, t1, t2);
5500 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5501 tcg_temp_free(t0);
5502 tcg_temp_free(t1);
5503 tcg_temp_free(t2);
5504 if (unlikely(Rc(ctx->opcode) != 0))
5505 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5506 }
5507
5508 /* sliq - sliq. */
5509 static void gen_sliq(DisasContext *ctx)
5510 {
5511 int sh = SH(ctx->opcode);
5512 TCGv t0 = tcg_temp_new();
5513 TCGv t1 = tcg_temp_new();
5514 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5515 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5516 tcg_gen_or_tl(t1, t0, t1);
5517 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5518 gen_store_spr(SPR_MQ, t1);
5519 tcg_temp_free(t0);
5520 tcg_temp_free(t1);
5521 if (unlikely(Rc(ctx->opcode) != 0))
5522 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5523 }
5524
5525 /* slliq - slliq. */
5526 static void gen_slliq(DisasContext *ctx)
5527 {
5528 int sh = SH(ctx->opcode);
5529 TCGv t0 = tcg_temp_new();
5530 TCGv t1 = tcg_temp_new();
5531 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5532 gen_load_spr(t1, SPR_MQ);
5533 gen_store_spr(SPR_MQ, t0);
5534 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5535 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5536 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5537 tcg_temp_free(t0);
5538 tcg_temp_free(t1);
5539 if (unlikely(Rc(ctx->opcode) != 0))
5540 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5541 }
5542
5543 /* sllq - sllq. */
5544 static void gen_sllq(DisasContext *ctx)
5545 {
5546 TCGLabel *l1 = gen_new_label();
5547 TCGLabel *l2 = gen_new_label();
5548 TCGv t0 = tcg_temp_local_new();
5549 TCGv t1 = tcg_temp_local_new();
5550 TCGv t2 = tcg_temp_local_new();
5551 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5552 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5553 tcg_gen_shl_tl(t1, t1, t2);
5554 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5555 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5556 gen_load_spr(t0, SPR_MQ);
5557 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5558 tcg_gen_br(l2);
5559 gen_set_label(l1);
5560 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5561 gen_load_spr(t2, SPR_MQ);
5562 tcg_gen_andc_tl(t1, t2, t1);
5563 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5564 gen_set_label(l2);
5565 tcg_temp_free(t0);
5566 tcg_temp_free(t1);
5567 tcg_temp_free(t2);
5568 if (unlikely(Rc(ctx->opcode) != 0))
5569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5570 }
5571
5572 /* slq - slq. */
5573 static void gen_slq(DisasContext *ctx)
5574 {
5575 TCGLabel *l1 = gen_new_label();
5576 TCGv t0 = tcg_temp_new();
5577 TCGv t1 = tcg_temp_new();
5578 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5579 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5580 tcg_gen_subfi_tl(t1, 32, t1);
5581 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5582 tcg_gen_or_tl(t1, t0, t1);
5583 gen_store_spr(SPR_MQ, t1);
5584 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5585 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5586 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5587 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5588 gen_set_label(l1);
5589 tcg_temp_free(t0);
5590 tcg_temp_free(t1);
5591 if (unlikely(Rc(ctx->opcode) != 0))
5592 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5593 }
5594
5595 /* sraiq - sraiq. */
5596 static void gen_sraiq(DisasContext *ctx)
5597 {
5598 int sh = SH(ctx->opcode);
5599 TCGLabel *l1 = gen_new_label();
5600 TCGv t0 = tcg_temp_new();
5601 TCGv t1 = tcg_temp_new();
5602 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5603 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5604 tcg_gen_or_tl(t0, t0, t1);
5605 gen_store_spr(SPR_MQ, t0);
5606 tcg_gen_movi_tl(cpu_ca, 0);
5607 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5608 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5609 tcg_gen_movi_tl(cpu_ca, 1);
5610 gen_set_label(l1);
5611 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5612 tcg_temp_free(t0);
5613 tcg_temp_free(t1);
5614 if (unlikely(Rc(ctx->opcode) != 0))
5615 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5616 }
5617
5618 /* sraq - sraq. */
5619 static void gen_sraq(DisasContext *ctx)
5620 {
5621 TCGLabel *l1 = gen_new_label();
5622 TCGLabel *l2 = gen_new_label();
5623 TCGv t0 = tcg_temp_new();
5624 TCGv t1 = tcg_temp_local_new();
5625 TCGv t2 = tcg_temp_local_new();
5626 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5627 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5628 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5629 tcg_gen_subfi_tl(t2, 32, t2);
5630 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5631 tcg_gen_or_tl(t0, t0, t2);
5632 gen_store_spr(SPR_MQ, t0);
5633 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5634 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5635 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5636 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5637 gen_set_label(l1);
5638 tcg_temp_free(t0);
5639 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5640 tcg_gen_movi_tl(cpu_ca, 0);
5641 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5642 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5643 tcg_gen_movi_tl(cpu_ca, 1);
5644 gen_set_label(l2);
5645 tcg_temp_free(t1);
5646 tcg_temp_free(t2);
5647 if (unlikely(Rc(ctx->opcode) != 0))
5648 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5649 }
5650
5651 /* sre - sre. */
5652 static void gen_sre(DisasContext *ctx)
5653 {
5654 TCGv t0 = tcg_temp_new();
5655 TCGv t1 = tcg_temp_new();
5656 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5657 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5658 tcg_gen_subfi_tl(t1, 32, t1);
5659 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5660 tcg_gen_or_tl(t1, t0, t1);
5661 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5662 gen_store_spr(SPR_MQ, t1);
5663 tcg_temp_free(t0);
5664 tcg_temp_free(t1);
5665 if (unlikely(Rc(ctx->opcode) != 0))
5666 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5667 }
5668
5669 /* srea - srea. */
5670 static void gen_srea(DisasContext *ctx)
5671 {
5672 TCGv t0 = tcg_temp_new();
5673 TCGv t1 = tcg_temp_new();
5674 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5675 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5676 gen_store_spr(SPR_MQ, t0);
5677 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5678 tcg_temp_free(t0);
5679 tcg_temp_free(t1);
5680 if (unlikely(Rc(ctx->opcode) != 0))
5681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5682 }
5683
5684 /* sreq */
5685 static void gen_sreq(DisasContext *ctx)
5686 {
5687 TCGv t0 = tcg_temp_new();
5688 TCGv t1 = tcg_temp_new();
5689 TCGv t2 = tcg_temp_new();
5690 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5691 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5692 tcg_gen_shr_tl(t1, t1, t0);
5693 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5694 gen_load_spr(t2, SPR_MQ);
5695 gen_store_spr(SPR_MQ, t0);
5696 tcg_gen_and_tl(t0, t0, t1);
5697 tcg_gen_andc_tl(t2, t2, t1);
5698 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5699 tcg_temp_free(t0);
5700 tcg_temp_free(t1);
5701 tcg_temp_free(t2);
5702 if (unlikely(Rc(ctx->opcode) != 0))
5703 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5704 }
5705
5706 /* sriq */
5707 static void gen_sriq(DisasContext *ctx)
5708 {
5709 int sh = SH(ctx->opcode);
5710 TCGv t0 = tcg_temp_new();
5711 TCGv t1 = tcg_temp_new();
5712 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5713 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5714 tcg_gen_or_tl(t1, t0, t1);
5715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5716 gen_store_spr(SPR_MQ, t1);
5717 tcg_temp_free(t0);
5718 tcg_temp_free(t1);
5719 if (unlikely(Rc(ctx->opcode) != 0))
5720 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5721 }
5722
5723 /* srliq */
5724 static void gen_srliq(DisasContext *ctx)
5725 {
5726 int sh = SH(ctx->opcode);
5727 TCGv t0 = tcg_temp_new();
5728 TCGv t1 = tcg_temp_new();
5729 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5730 gen_load_spr(t1, SPR_MQ);
5731 gen_store_spr(SPR_MQ, t0);
5732 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5733 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5734 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5735 tcg_temp_free(t0);
5736 tcg_temp_free(t1);
5737 if (unlikely(Rc(ctx->opcode) != 0))
5738 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5739 }
5740
5741 /* srlq */
5742 static void gen_srlq(DisasContext *ctx)
5743 {
5744 TCGLabel *l1 = gen_new_label();
5745 TCGLabel *l2 = gen_new_label();
5746 TCGv t0 = tcg_temp_local_new();
5747 TCGv t1 = tcg_temp_local_new();
5748 TCGv t2 = tcg_temp_local_new();
5749 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5750 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5751 tcg_gen_shr_tl(t2, t1, t2);
5752 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5753 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5754 gen_load_spr(t0, SPR_MQ);
5755 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5756 tcg_gen_br(l2);
5757 gen_set_label(l1);
5758 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5759 tcg_gen_and_tl(t0, t0, t2);
5760 gen_load_spr(t1, SPR_MQ);
5761 tcg_gen_andc_tl(t1, t1, t2);
5762 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5763 gen_set_label(l2);
5764 tcg_temp_free(t0);
5765 tcg_temp_free(t1);
5766 tcg_temp_free(t2);
5767 if (unlikely(Rc(ctx->opcode) != 0))
5768 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5769 }
5770
5771 /* srq */
5772 static void gen_srq(DisasContext *ctx)
5773 {
5774 TCGLabel *l1 = gen_new_label();
5775 TCGv t0 = tcg_temp_new();
5776 TCGv t1 = tcg_temp_new();
5777 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5778 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5779 tcg_gen_subfi_tl(t1, 32, t1);
5780 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5781 tcg_gen_or_tl(t1, t0, t1);
5782 gen_store_spr(SPR_MQ, t1);
5783 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5784 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5785 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5786 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5787 gen_set_label(l1);
5788 tcg_temp_free(t0);
5789 tcg_temp_free(t1);
5790 if (unlikely(Rc(ctx->opcode) != 0))
5791 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5792 }
5793
5794 /* PowerPC 602 specific instructions */
5795
5796 /* dsa */
5797 static void gen_dsa(DisasContext *ctx)
5798 {
5799 /* XXX: TODO */
5800 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5801 }
5802
5803 /* esa */
5804 static void gen_esa(DisasContext *ctx)
5805 {
5806 /* XXX: TODO */
5807 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5808 }
5809
5810 /* mfrom */
5811 static void gen_mfrom(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814 GEN_PRIV;
5815 #else
5816 CHK_SV;
5817 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5818 #endif /* defined(CONFIG_USER_ONLY) */
5819 }
5820
5821 /* 602 - 603 - G2 TLB management */
5822
5823 /* tlbld */
5824 static void gen_tlbld_6xx(DisasContext *ctx)
5825 {
5826 #if defined(CONFIG_USER_ONLY)
5827 GEN_PRIV;
5828 #else
5829 CHK_SV;
5830 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5831 #endif /* defined(CONFIG_USER_ONLY) */
5832 }
5833
5834 /* tlbli */
5835 static void gen_tlbli_6xx(DisasContext *ctx)
5836 {
5837 #if defined(CONFIG_USER_ONLY)
5838 GEN_PRIV;
5839 #else
5840 CHK_SV;
5841 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5842 #endif /* defined(CONFIG_USER_ONLY) */
5843 }
5844
5845 /* 74xx TLB management */
5846
5847 /* tlbld */
5848 static void gen_tlbld_74xx(DisasContext *ctx)
5849 {
5850 #if defined(CONFIG_USER_ONLY)
5851 GEN_PRIV;
5852 #else
5853 CHK_SV;
5854 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5855 #endif /* defined(CONFIG_USER_ONLY) */
5856 }
5857
5858 /* tlbli */
5859 static void gen_tlbli_74xx(DisasContext *ctx)
5860 {
5861 #if defined(CONFIG_USER_ONLY)
5862 GEN_PRIV;
5863 #else
5864 CHK_SV;
5865 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5866 #endif /* defined(CONFIG_USER_ONLY) */
5867 }
5868
5869 /* POWER instructions not in PowerPC 601 */
5870
5871 /* clf */
5872 static void gen_clf(DisasContext *ctx)
5873 {
5874 /* Cache line flush: implemented as no-op */
5875 }
5876
5877 /* cli */
5878 static void gen_cli(DisasContext *ctx)
5879 {
5880 #if defined(CONFIG_USER_ONLY)
5881 GEN_PRIV;
5882 #else
5883 /* Cache line invalidate: privileged and treated as no-op */
5884 CHK_SV;
5885 #endif /* defined(CONFIG_USER_ONLY) */
5886 }
5887
5888 /* dclst */
5889 static void gen_dclst(DisasContext *ctx)
5890 {
5891 /* Data cache line store: treated as no-op */
5892 }
5893
5894 static void gen_mfsri(DisasContext *ctx)
5895 {
5896 #if defined(CONFIG_USER_ONLY)
5897 GEN_PRIV;
5898 #else
5899 int ra = rA(ctx->opcode);
5900 int rd = rD(ctx->opcode);
5901 TCGv t0;
5902
5903 CHK_SV;
5904 t0 = tcg_temp_new();
5905 gen_addr_reg_index(ctx, t0);
5906 tcg_gen_shri_tl(t0, t0, 28);
5907 tcg_gen_andi_tl(t0, t0, 0xF);
5908 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5909 tcg_temp_free(t0);
5910 if (ra != 0 && ra != rd)
5911 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5912 #endif /* defined(CONFIG_USER_ONLY) */
5913 }
5914
5915 static void gen_rac(DisasContext *ctx)
5916 {
5917 #if defined(CONFIG_USER_ONLY)
5918 GEN_PRIV;
5919 #else
5920 TCGv t0;
5921
5922 CHK_SV;
5923 t0 = tcg_temp_new();
5924 gen_addr_reg_index(ctx, t0);
5925 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5926 tcg_temp_free(t0);
5927 #endif /* defined(CONFIG_USER_ONLY) */
5928 }
5929
5930 static void gen_rfsvc(DisasContext *ctx)
5931 {
5932 #if defined(CONFIG_USER_ONLY)
5933 GEN_PRIV;
5934 #else
5935 CHK_SV;
5936
5937 gen_helper_rfsvc(cpu_env);
5938 gen_sync_exception(ctx);
5939 #endif /* defined(CONFIG_USER_ONLY) */
5940 }
5941
5942 /* svc is not implemented for now */
5943
5944 /* POWER2 specific instructions */
5945 /* Quad manipulation (load/store two floats at a time) */
5946
5947 /* lfq */
5948 static void gen_lfq(DisasContext *ctx)
5949 {
5950 int rd = rD(ctx->opcode);
5951 TCGv t0;
5952 gen_set_access_type(ctx, ACCESS_FLOAT);
5953 t0 = tcg_temp_new();
5954 gen_addr_imm_index(ctx, t0, 0);
5955 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5956 gen_addr_add(ctx, t0, t0, 8);
5957 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5958 tcg_temp_free(t0);
5959 }
5960
5961 /* lfqu */
5962 static void gen_lfqu(DisasContext *ctx)
5963 {
5964 int ra = rA(ctx->opcode);
5965 int rd = rD(ctx->opcode);
5966 TCGv t0, t1;
5967 gen_set_access_type(ctx, ACCESS_FLOAT);
5968 t0 = tcg_temp_new();
5969 t1 = tcg_temp_new();
5970 gen_addr_imm_index(ctx, t0, 0);
5971 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5972 gen_addr_add(ctx, t1, t0, 8);
5973 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5974 if (ra != 0)
5975 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5976 tcg_temp_free(t0);
5977 tcg_temp_free(t1);
5978 }
5979
5980 /* lfqux */
5981 static void gen_lfqux(DisasContext *ctx)
5982 {
5983 int ra = rA(ctx->opcode);
5984 int rd = rD(ctx->opcode);
5985 gen_set_access_type(ctx, ACCESS_FLOAT);
5986 TCGv t0, t1;
5987 t0 = tcg_temp_new();
5988 gen_addr_reg_index(ctx, t0);
5989 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5990 t1 = tcg_temp_new();
5991 gen_addr_add(ctx, t1, t0, 8);
5992 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5993 tcg_temp_free(t1);
5994 if (ra != 0)
5995 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5996 tcg_temp_free(t0);
5997 }
5998
5999 /* lfqx */
6000 static void gen_lfqx(DisasContext *ctx)
6001 {
6002 int rd = rD(ctx->opcode);
6003 TCGv t0;
6004 gen_set_access_type(ctx, ACCESS_FLOAT);
6005 t0 = tcg_temp_new();
6006 gen_addr_reg_index(ctx, t0);
6007 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
6008 gen_addr_add(ctx, t0, t0, 8);
6009 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6010 tcg_temp_free(t0);
6011 }
6012
6013 /* stfq */
6014 static void gen_stfq(DisasContext *ctx)
6015 {
6016 int rd = rD(ctx->opcode);
6017 TCGv t0;
6018 gen_set_access_type(ctx, ACCESS_FLOAT);
6019 t0 = tcg_temp_new();
6020 gen_addr_imm_index(ctx, t0, 0);
6021 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6022 gen_addr_add(ctx, t0, t0, 8);
6023 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6024 tcg_temp_free(t0);
6025 }
6026
6027 /* stfqu */
6028 static void gen_stfqu(DisasContext *ctx)
6029 {
6030 int ra = rA(ctx->opcode);
6031 int rd = rD(ctx->opcode);
6032 TCGv t0, t1;
6033 gen_set_access_type(ctx, ACCESS_FLOAT);
6034 t0 = tcg_temp_new();
6035 gen_addr_imm_index(ctx, t0, 0);
6036 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6037 t1 = tcg_temp_new();
6038 gen_addr_add(ctx, t1, t0, 8);
6039 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6040 tcg_temp_free(t1);
6041 if (ra != 0)
6042 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6043 tcg_temp_free(t0);
6044 }
6045
6046 /* stfqux */
6047 static void gen_stfqux(DisasContext *ctx)
6048 {
6049 int ra = rA(ctx->opcode);
6050 int rd = rD(ctx->opcode);
6051 TCGv t0, t1;
6052 gen_set_access_type(ctx, ACCESS_FLOAT);
6053 t0 = tcg_temp_new();
6054 gen_addr_reg_index(ctx, t0);
6055 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6056 t1 = tcg_temp_new();
6057 gen_addr_add(ctx, t1, t0, 8);
6058 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
6059 tcg_temp_free(t1);
6060 if (ra != 0)
6061 tcg_gen_mov_tl(cpu_gpr[ra], t0);
6062 tcg_temp_free(t0);
6063 }
6064
6065 /* stfqx */
6066 static void gen_stfqx(DisasContext *ctx)
6067 {
6068 int rd = rD(ctx->opcode);
6069 TCGv t0;
6070 gen_set_access_type(ctx, ACCESS_FLOAT);
6071 t0 = tcg_temp_new();
6072 gen_addr_reg_index(ctx, t0);
6073 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
6074 gen_addr_add(ctx, t0, t0, 8);
6075 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
6076 tcg_temp_free(t0);
6077 }
6078
6079 /* BookE specific instructions */
6080
6081 /* XXX: not implemented on 440 ? */
6082 static void gen_mfapidi(DisasContext *ctx)
6083 {
6084 /* XXX: TODO */
6085 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6086 }
6087
6088 /* XXX: not implemented on 440 ? */
6089 static void gen_tlbiva(DisasContext *ctx)
6090 {
6091 #if defined(CONFIG_USER_ONLY)
6092 GEN_PRIV;
6093 #else
6094 TCGv t0;
6095
6096 CHK_SV;
6097 t0 = tcg_temp_new();
6098 gen_addr_reg_index(ctx, t0);
6099 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6100 tcg_temp_free(t0);
6101 #endif /* defined(CONFIG_USER_ONLY) */
6102 }
6103
6104 /* All 405 MAC instructions are translated here */
6105 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6106 int ra, int rb, int rt, int Rc)
6107 {
6108 TCGv t0, t1;
6109
6110 t0 = tcg_temp_local_new();
6111 t1 = tcg_temp_local_new();
6112
6113 switch (opc3 & 0x0D) {
6114 case 0x05:
6115 /* macchw - macchw. - macchwo - macchwo. */
6116 /* macchws - macchws. - macchwso - macchwso. */
6117 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6118 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6119 /* mulchw - mulchw. */
6120 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6121 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6122 tcg_gen_ext16s_tl(t1, t1);
6123 break;
6124 case 0x04:
6125 /* macchwu - macchwu. - macchwuo - macchwuo. */
6126 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6127 /* mulchwu - mulchwu. */
6128 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6129 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6130 tcg_gen_ext16u_tl(t1, t1);
6131 break;
6132 case 0x01:
6133 /* machhw - machhw. - machhwo - machhwo. */
6134 /* machhws - machhws. - machhwso - machhwso. */
6135 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6136 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6137 /* mulhhw - mulhhw. */
6138 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6139 tcg_gen_ext16s_tl(t0, t0);
6140 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6141 tcg_gen_ext16s_tl(t1, t1);
6142 break;
6143 case 0x00:
6144 /* machhwu - machhwu. - machhwuo - machhwuo. */
6145 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6146 /* mulhhwu - mulhhwu. */
6147 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6148 tcg_gen_ext16u_tl(t0, t0);
6149 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6150 tcg_gen_ext16u_tl(t1, t1);
6151 break;
6152 case 0x0D:
6153 /* maclhw - maclhw. - maclhwo - maclhwo. */
6154 /* maclhws - maclhws. - maclhwso - maclhwso. */
6155 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6156 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6157 /* mullhw - mullhw. */
6158 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6159 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6160 break;
6161 case 0x0C:
6162 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6163 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6164 /* mullhwu - mullhwu. */
6165 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6166 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6167 break;
6168 }
6169 if (opc2 & 0x04) {
6170 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6171 tcg_gen_mul_tl(t1, t0, t1);
6172 if (opc2 & 0x02) {
6173 /* nmultiply-and-accumulate (0x0E) */
6174 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6175 } else {
6176 /* multiply-and-accumulate (0x0C) */
6177 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6178 }
6179
6180 if (opc3 & 0x12) {
6181 /* Check overflow and/or saturate */
6182 TCGLabel *l1 = gen_new_label();
6183
6184 if (opc3 & 0x10) {
6185 /* Start with XER OV disabled, the most likely case */
6186 tcg_gen_movi_tl(cpu_ov, 0);
6187 }
6188 if (opc3 & 0x01) {
6189 /* Signed */
6190 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6191 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6192 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6193 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6194 if (opc3 & 0x02) {
6195 /* Saturate */
6196 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6197 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6198 }
6199 } else {
6200 /* Unsigned */
6201 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6202 if (opc3 & 0x02) {
6203 /* Saturate */
6204 tcg_gen_movi_tl(t0, UINT32_MAX);
6205 }
6206 }
6207 if (opc3 & 0x10) {
6208 /* Check overflow */
6209 tcg_gen_movi_tl(cpu_ov, 1);
6210 tcg_gen_movi_tl(cpu_so, 1);
6211 }
6212 gen_set_label(l1);
6213 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6214 }
6215 } else {
6216 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6217 }
6218 tcg_temp_free(t0);
6219 tcg_temp_free(t1);
6220 if (unlikely(Rc) != 0) {
6221 /* Update Rc0 */
6222 gen_set_Rc0(ctx, cpu_gpr[rt]);
6223 }
6224 }
6225
6226 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6227 static void glue(gen_, name)(DisasContext *ctx) \
6228 { \
6229 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6230 rD(ctx->opcode), Rc(ctx->opcode)); \
6231 }
6232
6233 /* macchw - macchw. */
6234 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6235 /* macchwo - macchwo. */
6236 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6237 /* macchws - macchws. */
6238 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6239 /* macchwso - macchwso. */
6240 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6241 /* macchwsu - macchwsu. */
6242 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6243 /* macchwsuo - macchwsuo. */
6244 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6245 /* macchwu - macchwu. */
6246 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6247 /* macchwuo - macchwuo. */
6248 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6249 /* machhw - machhw. */
6250 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6251 /* machhwo - machhwo. */
6252 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6253 /* machhws - machhws. */
6254 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6255 /* machhwso - machhwso. */
6256 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6257 /* machhwsu - machhwsu. */
6258 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6259 /* machhwsuo - machhwsuo. */
6260 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6261 /* machhwu - machhwu. */
6262 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6263 /* machhwuo - machhwuo. */
6264 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6265 /* maclhw - maclhw. */
6266 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6267 /* maclhwo - maclhwo. */
6268 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6269 /* maclhws - maclhws. */
6270 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6271 /* maclhwso - maclhwso. */
6272 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6273 /* maclhwu - maclhwu. */
6274 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6275 /* maclhwuo - maclhwuo. */
6276 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6277 /* maclhwsu - maclhwsu. */
6278 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6279 /* maclhwsuo - maclhwsuo. */
6280 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6281 /* nmacchw - nmacchw. */
6282 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6283 /* nmacchwo - nmacchwo. */
6284 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6285 /* nmacchws - nmacchws. */
6286 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6287 /* nmacchwso - nmacchwso. */
6288 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6289 /* nmachhw - nmachhw. */
6290 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6291 /* nmachhwo - nmachhwo. */
6292 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6293 /* nmachhws - nmachhws. */
6294 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6295 /* nmachhwso - nmachhwso. */
6296 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6297 /* nmaclhw - nmaclhw. */
6298 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6299 /* nmaclhwo - nmaclhwo. */
6300 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6301 /* nmaclhws - nmaclhws. */
6302 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6303 /* nmaclhwso - nmaclhwso. */
6304 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6305
6306 /* mulchw - mulchw. */
6307 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6308 /* mulchwu - mulchwu. */
6309 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6310 /* mulhhw - mulhhw. */
6311 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6312 /* mulhhwu - mulhhwu. */
6313 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6314 /* mullhw - mullhw. */
6315 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6316 /* mullhwu - mullhwu. */
6317 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6318
6319 /* mfdcr */
6320 static void gen_mfdcr(DisasContext *ctx)
6321 {
6322 #if defined(CONFIG_USER_ONLY)
6323 GEN_PRIV;
6324 #else
6325 TCGv dcrn;
6326
6327 CHK_SV;
6328 /* NIP cannot be restored if the memory exception comes from an helper */
6329 gen_update_nip(ctx, ctx->nip - 4);
6330 dcrn = tcg_const_tl(SPR(ctx->opcode));
6331 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6332 tcg_temp_free(dcrn);
6333 #endif /* defined(CONFIG_USER_ONLY) */
6334 }
6335
6336 /* mtdcr */
6337 static void gen_mtdcr(DisasContext *ctx)
6338 {
6339 #if defined(CONFIG_USER_ONLY)
6340 GEN_PRIV;
6341 #else
6342 TCGv dcrn;
6343
6344 CHK_SV;
6345 /* NIP cannot be restored if the memory exception comes from an helper */
6346 gen_update_nip(ctx, ctx->nip - 4);
6347 dcrn = tcg_const_tl(SPR(ctx->opcode));
6348 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6349 tcg_temp_free(dcrn);
6350 #endif /* defined(CONFIG_USER_ONLY) */
6351 }
6352
6353 /* mfdcrx */
6354 /* XXX: not implemented on 440 ? */
6355 static void gen_mfdcrx(DisasContext *ctx)
6356 {
6357 #if defined(CONFIG_USER_ONLY)
6358 GEN_PRIV;
6359 #else
6360 CHK_SV;
6361 /* NIP cannot be restored if the memory exception comes from an helper */
6362 gen_update_nip(ctx, ctx->nip - 4);
6363 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6364 cpu_gpr[rA(ctx->opcode)]);
6365 /* Note: Rc update flag set leads to undefined state of Rc0 */
6366 #endif /* defined(CONFIG_USER_ONLY) */
6367 }
6368
6369 /* mtdcrx */
6370 /* XXX: not implemented on 440 ? */
6371 static void gen_mtdcrx(DisasContext *ctx)
6372 {
6373 #if defined(CONFIG_USER_ONLY)
6374 GEN_PRIV;
6375 #else
6376 CHK_SV;
6377 /* NIP cannot be restored if the memory exception comes from an helper */
6378 gen_update_nip(ctx, ctx->nip - 4);
6379 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6380 cpu_gpr[rS(ctx->opcode)]);
6381 /* Note: Rc update flag set leads to undefined state of Rc0 */
6382 #endif /* defined(CONFIG_USER_ONLY) */
6383 }
6384
6385 /* mfdcrux (PPC 460) : user-mode access to DCR */
6386 static void gen_mfdcrux(DisasContext *ctx)
6387 {
6388 /* NIP cannot be restored if the memory exception comes from an helper */
6389 gen_update_nip(ctx, ctx->nip - 4);
6390 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6391 cpu_gpr[rA(ctx->opcode)]);
6392 /* Note: Rc update flag set leads to undefined state of Rc0 */
6393 }
6394
6395 /* mtdcrux (PPC 460) : user-mode access to DCR */
6396 static void gen_mtdcrux(DisasContext *ctx)
6397 {
6398 /* NIP cannot be restored if the memory exception comes from an helper */
6399 gen_update_nip(ctx, ctx->nip - 4);
6400 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6401 cpu_gpr[rS(ctx->opcode)]);
6402 /* Note: Rc update flag set leads to undefined state of Rc0 */
6403 }
6404
6405 /* dccci */
6406 static void gen_dccci(DisasContext *ctx)
6407 {
6408 CHK_SV;
6409 /* interpreted as no-op */
6410 }
6411
6412 /* dcread */
6413 static void gen_dcread(DisasContext *ctx)
6414 {
6415 #if defined(CONFIG_USER_ONLY)
6416 GEN_PRIV;
6417 #else
6418 TCGv EA, val;
6419
6420 CHK_SV;
6421 gen_set_access_type(ctx, ACCESS_CACHE);
6422 EA = tcg_temp_new();
6423 gen_addr_reg_index(ctx, EA);
6424 val = tcg_temp_new();
6425 gen_qemu_ld32u(ctx, val, EA);
6426 tcg_temp_free(val);
6427 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6428 tcg_temp_free(EA);
6429 #endif /* defined(CONFIG_USER_ONLY) */
6430 }
6431
6432 /* icbt */
6433 static void gen_icbt_40x(DisasContext *ctx)
6434 {
6435 /* interpreted as no-op */
6436 /* XXX: specification say this is treated as a load by the MMU
6437 * but does not generate any exception
6438 */
6439 }
6440
6441 /* iccci */
6442 static void gen_iccci(DisasContext *ctx)
6443 {
6444 CHK_SV;
6445 /* interpreted as no-op */
6446 }
6447
6448 /* icread */
6449 static void gen_icread(DisasContext *ctx)
6450 {
6451 CHK_SV;
6452 /* interpreted as no-op */
6453 }
6454
6455 /* rfci (supervisor only) */
6456 static void gen_rfci_40x(DisasContext *ctx)
6457 {
6458 #if defined(CONFIG_USER_ONLY)
6459 GEN_PRIV;
6460 #else
6461 CHK_SV;
6462 /* Restore CPU state */
6463 gen_helper_40x_rfci(cpu_env);
6464 gen_sync_exception(ctx);
6465 #endif /* defined(CONFIG_USER_ONLY) */
6466 }
6467
6468 static void gen_rfci(DisasContext *ctx)
6469 {
6470 #if defined(CONFIG_USER_ONLY)
6471 GEN_PRIV;
6472 #else
6473 CHK_SV;
6474 /* Restore CPU state */
6475 gen_helper_rfci(cpu_env);
6476 gen_sync_exception(ctx);
6477 #endif /* defined(CONFIG_USER_ONLY) */
6478 }
6479
6480 /* BookE specific */
6481
6482 /* XXX: not implemented on 440 ? */
6483 static void gen_rfdi(DisasContext *ctx)
6484 {
6485 #if defined(CONFIG_USER_ONLY)
6486 GEN_PRIV;
6487 #else
6488 CHK_SV;
6489 /* Restore CPU state */
6490 gen_helper_rfdi(cpu_env);
6491 gen_sync_exception(ctx);
6492 #endif /* defined(CONFIG_USER_ONLY) */
6493 }
6494
6495 /* XXX: not implemented on 440 ? */
6496 static void gen_rfmci(DisasContext *ctx)
6497 {
6498 #if defined(CONFIG_USER_ONLY)
6499 GEN_PRIV;
6500 #else
6501 CHK_SV;
6502 /* Restore CPU state */
6503 gen_helper_rfmci(cpu_env);
6504 gen_sync_exception(ctx);
6505 #endif /* defined(CONFIG_USER_ONLY) */
6506 }
6507
6508 /* TLB management - PowerPC 405 implementation */
6509
6510 /* tlbre */
6511 static void gen_tlbre_40x(DisasContext *ctx)
6512 {
6513 #if defined(CONFIG_USER_ONLY)
6514 GEN_PRIV;
6515 #else
6516 CHK_SV;
6517 switch (rB(ctx->opcode)) {
6518 case 0:
6519 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6520 cpu_gpr[rA(ctx->opcode)]);
6521 break;
6522 case 1:
6523 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6524 cpu_gpr[rA(ctx->opcode)]);
6525 break;
6526 default:
6527 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6528 break;
6529 }
6530 #endif /* defined(CONFIG_USER_ONLY) */
6531 }
6532
6533 /* tlbsx - tlbsx. */
6534 static void gen_tlbsx_40x(DisasContext *ctx)
6535 {
6536 #if defined(CONFIG_USER_ONLY)
6537 GEN_PRIV;
6538 #else
6539 TCGv t0;
6540
6541 CHK_SV;
6542 t0 = tcg_temp_new();
6543 gen_addr_reg_index(ctx, t0);
6544 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6545 tcg_temp_free(t0);
6546 if (Rc(ctx->opcode)) {
6547 TCGLabel *l1 = gen_new_label();
6548 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6549 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6550 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6551 gen_set_label(l1);
6552 }
6553 #endif /* defined(CONFIG_USER_ONLY) */
6554 }
6555
6556 /* tlbwe */
6557 static void gen_tlbwe_40x(DisasContext *ctx)
6558 {
6559 #if defined(CONFIG_USER_ONLY)
6560 GEN_PRIV;
6561 #else
6562 CHK_SV;
6563
6564 switch (rB(ctx->opcode)) {
6565 case 0:
6566 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6567 cpu_gpr[rS(ctx->opcode)]);
6568 break;
6569 case 1:
6570 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6571 cpu_gpr[rS(ctx->opcode)]);
6572 break;
6573 default:
6574 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6575 break;
6576 }
6577 #endif /* defined(CONFIG_USER_ONLY) */
6578 }
6579
6580 /* TLB management - PowerPC 440 implementation */
6581
6582 /* tlbre */
6583 static void gen_tlbre_440(DisasContext *ctx)
6584 {
6585 #if defined(CONFIG_USER_ONLY)
6586 GEN_PRIV;
6587 #else
6588 CHK_SV;
6589
6590 switch (rB(ctx->opcode)) {
6591 case 0:
6592 case 1:
6593 case 2:
6594 {
6595 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6596 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6597 t0, cpu_gpr[rA(ctx->opcode)]);
6598 tcg_temp_free_i32(t0);
6599 }
6600 break;
6601 default:
6602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6603 break;
6604 }
6605 #endif /* defined(CONFIG_USER_ONLY) */
6606 }
6607
6608 /* tlbsx - tlbsx. */
6609 static void gen_tlbsx_440(DisasContext *ctx)
6610 {
6611 #if defined(CONFIG_USER_ONLY)
6612 GEN_PRIV;
6613 #else
6614 TCGv t0;
6615
6616 CHK_SV;
6617 t0 = tcg_temp_new();
6618 gen_addr_reg_index(ctx, t0);
6619 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6620 tcg_temp_free(t0);
6621 if (Rc(ctx->opcode)) {
6622 TCGLabel *l1 = gen_new_label();
6623 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6624 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6625 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6626 gen_set_label(l1);
6627 }
6628 #endif /* defined(CONFIG_USER_ONLY) */
6629 }
6630
6631 /* tlbwe */
6632 static void gen_tlbwe_440(DisasContext *ctx)
6633 {
6634 #if defined(CONFIG_USER_ONLY)
6635 GEN_PRIV;
6636 #else
6637 CHK_SV;
6638 switch (rB(ctx->opcode)) {
6639 case 0:
6640 case 1:
6641 case 2:
6642 {
6643 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6644 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6645 cpu_gpr[rS(ctx->opcode)]);
6646 tcg_temp_free_i32(t0);
6647 }
6648 break;
6649 default:
6650 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6651 break;
6652 }
6653 #endif /* defined(CONFIG_USER_ONLY) */
6654 }
6655
6656 /* TLB management - PowerPC BookE 2.06 implementation */
6657
6658 /* tlbre */
6659 static void gen_tlbre_booke206(DisasContext *ctx)
6660 {
6661 #if defined(CONFIG_USER_ONLY)
6662 GEN_PRIV;
6663 #else
6664 CHK_SV;
6665 gen_helper_booke206_tlbre(cpu_env);
6666 #endif /* defined(CONFIG_USER_ONLY) */
6667 }
6668
6669 /* tlbsx - tlbsx. */
6670 static void gen_tlbsx_booke206(DisasContext *ctx)
6671 {
6672 #if defined(CONFIG_USER_ONLY)
6673 GEN_PRIV;
6674 #else
6675 TCGv t0;
6676
6677 CHK_SV;
6678 if (rA(ctx->opcode)) {
6679 t0 = tcg_temp_new();
6680 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6681 } else {
6682 t0 = tcg_const_tl(0);
6683 }
6684
6685 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6686 gen_helper_booke206_tlbsx(cpu_env, t0);
6687 tcg_temp_free(t0);
6688 #endif /* defined(CONFIG_USER_ONLY) */
6689 }
6690
6691 /* tlbwe */
6692 static void gen_tlbwe_booke206(DisasContext *ctx)
6693 {
6694 #if defined(CONFIG_USER_ONLY)
6695 GEN_PRIV;
6696 #else
6697 CHK_SV;
6698 gen_update_nip(ctx, ctx->nip - 4);
6699 gen_helper_booke206_tlbwe(cpu_env);
6700 #endif /* defined(CONFIG_USER_ONLY) */
6701 }
6702
6703 static void gen_tlbivax_booke206(DisasContext *ctx)
6704 {
6705 #if defined(CONFIG_USER_ONLY)
6706 GEN_PRIV;
6707 #else
6708 TCGv t0;
6709
6710 CHK_SV;
6711 t0 = tcg_temp_new();
6712 gen_addr_reg_index(ctx, t0);
6713 gen_helper_booke206_tlbivax(cpu_env, t0);
6714 tcg_temp_free(t0);
6715 #endif /* defined(CONFIG_USER_ONLY) */
6716 }
6717
6718 static void gen_tlbilx_booke206(DisasContext *ctx)
6719 {
6720 #if defined(CONFIG_USER_ONLY)
6721 GEN_PRIV;
6722 #else
6723 TCGv t0;
6724
6725 CHK_SV;
6726 t0 = tcg_temp_new();
6727 gen_addr_reg_index(ctx, t0);
6728
6729 switch((ctx->opcode >> 21) & 0x3) {
6730 case 0:
6731 gen_helper_booke206_tlbilx0(cpu_env, t0);
6732 break;
6733 case 1:
6734 gen_helper_booke206_tlbilx1(cpu_env, t0);
6735 break;
6736 case 3:
6737 gen_helper_booke206_tlbilx3(cpu_env, t0);
6738 break;
6739 default:
6740 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6741 break;
6742 }
6743
6744 tcg_temp_free(t0);
6745 #endif /* defined(CONFIG_USER_ONLY) */
6746 }
6747
6748
6749 /* wrtee */
6750 static void gen_wrtee(DisasContext *ctx)
6751 {
6752 #if defined(CONFIG_USER_ONLY)
6753 GEN_PRIV;
6754 #else
6755 TCGv t0;
6756
6757 CHK_SV;
6758 t0 = tcg_temp_new();
6759 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6760 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6761 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6762 tcg_temp_free(t0);
6763 /* Stop translation to have a chance to raise an exception
6764 * if we just set msr_ee to 1
6765 */
6766 gen_stop_exception(ctx);
6767 #endif /* defined(CONFIG_USER_ONLY) */
6768 }
6769
6770 /* wrteei */
6771 static void gen_wrteei(DisasContext *ctx)
6772 {
6773 #if defined(CONFIG_USER_ONLY)
6774 GEN_PRIV;
6775 #else
6776 CHK_SV;
6777 if (ctx->opcode & 0x00008000) {
6778 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6779 /* Stop translation to have a chance to raise an exception */
6780 gen_stop_exception(ctx);
6781 } else {
6782 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6783 }
6784 #endif /* defined(CONFIG_USER_ONLY) */
6785 }
6786
6787 /* PowerPC 440 specific instructions */
6788
6789 /* dlmzb */
6790 static void gen_dlmzb(DisasContext *ctx)
6791 {
6792 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6793 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6794 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6795 tcg_temp_free_i32(t0);
6796 }
6797
6798 /* mbar replaces eieio on 440 */
6799 static void gen_mbar(DisasContext *ctx)
6800 {
6801 /* interpreted as no-op */
6802 }
6803
6804 /* msync replaces sync on 440 */
6805 static void gen_msync_4xx(DisasContext *ctx)
6806 {
6807 /* interpreted as no-op */
6808 }
6809
6810 /* icbt */
6811 static void gen_icbt_440(DisasContext *ctx)
6812 {
6813 /* interpreted as no-op */
6814 /* XXX: specification say this is treated as a load by the MMU
6815 * but does not generate any exception
6816 */
6817 }
6818
6819 /* Embedded.Processor Control */
6820
6821 static void gen_msgclr(DisasContext *ctx)
6822 {
6823 #if defined(CONFIG_USER_ONLY)
6824 GEN_PRIV;
6825 #else
6826 CHK_SV;
6827 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6828 #endif /* defined(CONFIG_USER_ONLY) */
6829 }
6830
6831 static void gen_msgsnd(DisasContext *ctx)
6832 {
6833 #if defined(CONFIG_USER_ONLY)
6834 GEN_PRIV;
6835 #else
6836 CHK_SV;
6837 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6838 #endif /* defined(CONFIG_USER_ONLY) */
6839 }
6840
6841 /*** Altivec vector extension ***/
6842 /* Altivec registers moves */
6843
6844 static inline TCGv_ptr gen_avr_ptr(int reg)
6845 {
6846 TCGv_ptr r = tcg_temp_new_ptr();
6847 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6848 return r;
6849 }
6850
6851 #define GEN_VR_LDX(name, opc2, opc3) \
6852 static void glue(gen_, name)(DisasContext *ctx) \
6853 { \
6854 TCGv EA; \
6855 if (unlikely(!ctx->altivec_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_VPU); \
6857 return; \
6858 } \
6859 gen_set_access_type(ctx, ACCESS_INT); \
6860 EA = tcg_temp_new(); \
6861 gen_addr_reg_index(ctx, EA); \
6862 tcg_gen_andi_tl(EA, EA, ~0xf); \
6863 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6864 64-bit byteswap already. */ \
6865 if (ctx->le_mode) { \
6866 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6867 tcg_gen_addi_tl(EA, EA, 8); \
6868 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6869 } else { \
6870 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6871 tcg_gen_addi_tl(EA, EA, 8); \
6872 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6873 } \
6874 tcg_temp_free(EA); \
6875 }
6876
6877 #define GEN_VR_STX(name, opc2, opc3) \
6878 static void gen_st##name(DisasContext *ctx) \
6879 { \
6880 TCGv EA; \
6881 if (unlikely(!ctx->altivec_enabled)) { \
6882 gen_exception(ctx, POWERPC_EXCP_VPU); \
6883 return; \
6884 } \
6885 gen_set_access_type(ctx, ACCESS_INT); \
6886 EA = tcg_temp_new(); \
6887 gen_addr_reg_index(ctx, EA); \
6888 tcg_gen_andi_tl(EA, EA, ~0xf); \
6889 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6890 64-bit byteswap already. */ \
6891 if (ctx->le_mode) { \
6892 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6893 tcg_gen_addi_tl(EA, EA, 8); \
6894 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6895 } else { \
6896 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6897 tcg_gen_addi_tl(EA, EA, 8); \
6898 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6899 } \
6900 tcg_temp_free(EA); \
6901 }
6902
6903 #define GEN_VR_LVE(name, opc2, opc3, size) \
6904 static void gen_lve##name(DisasContext *ctx) \
6905 { \
6906 TCGv EA; \
6907 TCGv_ptr rs; \
6908 if (unlikely(!ctx->altivec_enabled)) { \
6909 gen_exception(ctx, POWERPC_EXCP_VPU); \
6910 return; \
6911 } \
6912 gen_set_access_type(ctx, ACCESS_INT); \
6913 EA = tcg_temp_new(); \
6914 gen_addr_reg_index(ctx, EA); \
6915 if (size > 1) { \
6916 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6917 } \
6918 rs = gen_avr_ptr(rS(ctx->opcode)); \
6919 gen_helper_lve##name(cpu_env, rs, EA); \
6920 tcg_temp_free(EA); \
6921 tcg_temp_free_ptr(rs); \
6922 }
6923
6924 #define GEN_VR_STVE(name, opc2, opc3, size) \
6925 static void gen_stve##name(DisasContext *ctx) \
6926 { \
6927 TCGv EA; \
6928 TCGv_ptr rs; \
6929 if (unlikely(!ctx->altivec_enabled)) { \
6930 gen_exception(ctx, POWERPC_EXCP_VPU); \
6931 return; \
6932 } \
6933 gen_set_access_type(ctx, ACCESS_INT); \
6934 EA = tcg_temp_new(); \
6935 gen_addr_reg_index(ctx, EA); \
6936 if (size > 1) { \
6937 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6938 } \
6939 rs = gen_avr_ptr(rS(ctx->opcode)); \
6940 gen_helper_stve##name(cpu_env, rs, EA); \
6941 tcg_temp_free(EA); \
6942 tcg_temp_free_ptr(rs); \
6943 }
6944
6945 GEN_VR_LDX(lvx, 0x07, 0x03);
6946 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6947 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6948
6949 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6950 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6951 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6952
6953 GEN_VR_STX(svx, 0x07, 0x07);
6954 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6955 GEN_VR_STX(svxl, 0x07, 0x0F);
6956
6957 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6958 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6959 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6960
6961 static void gen_lvsl(DisasContext *ctx)
6962 {
6963 TCGv_ptr rd;
6964 TCGv EA;
6965 if (unlikely(!ctx->altivec_enabled)) {
6966 gen_exception(ctx, POWERPC_EXCP_VPU);
6967 return;
6968 }
6969 EA = tcg_temp_new();
6970 gen_addr_reg_index(ctx, EA);
6971 rd = gen_avr_ptr(rD(ctx->opcode));
6972 gen_helper_lvsl(rd, EA);
6973 tcg_temp_free(EA);
6974 tcg_temp_free_ptr(rd);
6975 }
6976
6977 static void gen_lvsr(DisasContext *ctx)
6978 {
6979 TCGv_ptr rd;
6980 TCGv EA;
6981 if (unlikely(!ctx->altivec_enabled)) {
6982 gen_exception(ctx, POWERPC_EXCP_VPU);
6983 return;
6984 }
6985 EA = tcg_temp_new();
6986 gen_addr_reg_index(ctx, EA);
6987 rd = gen_avr_ptr(rD(ctx->opcode));
6988 gen_helper_lvsr(rd, EA);
6989 tcg_temp_free(EA);
6990 tcg_temp_free_ptr(rd);
6991 }
6992
6993 static void gen_mfvscr(DisasContext *ctx)
6994 {
6995 TCGv_i32 t;
6996 if (unlikely(!ctx->altivec_enabled)) {
6997 gen_exception(ctx, POWERPC_EXCP_VPU);
6998 return;
6999 }
7000 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
7001 t = tcg_temp_new_i32();
7002 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
7003 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
7004 tcg_temp_free_i32(t);
7005 }
7006
7007 static void gen_mtvscr(DisasContext *ctx)
7008 {
7009 TCGv_ptr p;
7010 if (unlikely(!ctx->altivec_enabled)) {
7011 gen_exception(ctx, POWERPC_EXCP_VPU);
7012 return;
7013 }
7014 p = gen_avr_ptr(rB(ctx->opcode));
7015 gen_helper_mtvscr(cpu_env, p);
7016 tcg_temp_free_ptr(p);
7017 }
7018
7019 /* Logical operations */
7020 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7021 static void glue(gen_, name)(DisasContext *ctx) \
7022 { \
7023 if (unlikely(!ctx->altivec_enabled)) { \
7024 gen_exception(ctx, POWERPC_EXCP_VPU); \
7025 return; \
7026 } \
7027 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7028 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7029 }
7030
7031 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7032 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7033 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7034 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7035 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
7036 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7037 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7038 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7039
7040 #define GEN_VXFORM(name, opc2, opc3) \
7041 static void glue(gen_, name)(DisasContext *ctx) \
7042 { \
7043 TCGv_ptr ra, rb, rd; \
7044 if (unlikely(!ctx->altivec_enabled)) { \
7045 gen_exception(ctx, POWERPC_EXCP_VPU); \
7046 return; \
7047 } \
7048 ra = gen_avr_ptr(rA(ctx->opcode)); \
7049 rb = gen_avr_ptr(rB(ctx->opcode)); \
7050 rd = gen_avr_ptr(rD(ctx->opcode)); \
7051 gen_helper_##name (rd, ra, rb); \
7052 tcg_temp_free_ptr(ra); \
7053 tcg_temp_free_ptr(rb); \
7054 tcg_temp_free_ptr(rd); \
7055 }
7056
7057 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7058 static void glue(gen_, name)(DisasContext *ctx) \
7059 { \
7060 TCGv_ptr ra, rb, rd; \
7061 if (unlikely(!ctx->altivec_enabled)) { \
7062 gen_exception(ctx, POWERPC_EXCP_VPU); \
7063 return; \
7064 } \
7065 ra = gen_avr_ptr(rA(ctx->opcode)); \
7066 rb = gen_avr_ptr(rB(ctx->opcode)); \
7067 rd = gen_avr_ptr(rD(ctx->opcode)); \
7068 gen_helper_##name(cpu_env, rd, ra, rb); \
7069 tcg_temp_free_ptr(ra); \
7070 tcg_temp_free_ptr(rb); \
7071 tcg_temp_free_ptr(rd); \
7072 }
7073
7074 #define GEN_VXFORM3(name, opc2, opc3) \
7075 static void glue(gen_, name)(DisasContext *ctx) \
7076 { \
7077 TCGv_ptr ra, rb, rc, rd; \
7078 if (unlikely(!ctx->altivec_enabled)) { \
7079 gen_exception(ctx, POWERPC_EXCP_VPU); \
7080 return; \
7081 } \
7082 ra = gen_avr_ptr(rA(ctx->opcode)); \
7083 rb = gen_avr_ptr(rB(ctx->opcode)); \
7084 rc = gen_avr_ptr(rC(ctx->opcode)); \
7085 rd = gen_avr_ptr(rD(ctx->opcode)); \
7086 gen_helper_##name(rd, ra, rb, rc); \
7087 tcg_temp_free_ptr(ra); \
7088 tcg_temp_free_ptr(rb); \
7089 tcg_temp_free_ptr(rc); \
7090 tcg_temp_free_ptr(rd); \
7091 }
7092
7093 /*
7094 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7095 * an opcode bit. In general, these pairs come from different
7096 * versions of the ISA, so we must also support a pair of flags for
7097 * each instruction.
7098 */
7099 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7100 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7101 { \
7102 if ((Rc(ctx->opcode) == 0) && \
7103 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7104 gen_##name0(ctx); \
7105 } else if ((Rc(ctx->opcode) == 1) && \
7106 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7107 gen_##name1(ctx); \
7108 } else { \
7109 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7110 } \
7111 }
7112
7113 GEN_VXFORM(vaddubm, 0, 0);
7114 GEN_VXFORM(vadduhm, 0, 1);
7115 GEN_VXFORM(vadduwm, 0, 2);
7116 GEN_VXFORM(vaddudm, 0, 3);
7117 GEN_VXFORM(vsububm, 0, 16);
7118 GEN_VXFORM(vsubuhm, 0, 17);
7119 GEN_VXFORM(vsubuwm, 0, 18);
7120 GEN_VXFORM(vsubudm, 0, 19);
7121 GEN_VXFORM(vmaxub, 1, 0);
7122 GEN_VXFORM(vmaxuh, 1, 1);
7123 GEN_VXFORM(vmaxuw, 1, 2);
7124 GEN_VXFORM(vmaxud, 1, 3);
7125 GEN_VXFORM(vmaxsb, 1, 4);
7126 GEN_VXFORM(vmaxsh, 1, 5);
7127 GEN_VXFORM(vmaxsw, 1, 6);
7128 GEN_VXFORM(vmaxsd, 1, 7);
7129 GEN_VXFORM(vminub, 1, 8);
7130 GEN_VXFORM(vminuh, 1, 9);
7131 GEN_VXFORM(vminuw, 1, 10);
7132 GEN_VXFORM(vminud, 1, 11);
7133 GEN_VXFORM(vminsb, 1, 12);
7134 GEN_VXFORM(vminsh, 1, 13);
7135 GEN_VXFORM(vminsw, 1, 14);
7136 GEN_VXFORM(vminsd, 1, 15);
7137 GEN_VXFORM(vavgub, 1, 16);
7138 GEN_VXFORM(vavguh, 1, 17);
7139 GEN_VXFORM(vavguw, 1, 18);
7140 GEN_VXFORM(vavgsb, 1, 20);
7141 GEN_VXFORM(vavgsh, 1, 21);
7142 GEN_VXFORM(vavgsw, 1, 22);
7143 GEN_VXFORM(vmrghb, 6, 0);
7144 GEN_VXFORM(vmrghh, 6, 1);
7145 GEN_VXFORM(vmrghw, 6, 2);
7146 GEN_VXFORM(vmrglb, 6, 4);
7147 GEN_VXFORM(vmrglh, 6, 5);
7148 GEN_VXFORM(vmrglw, 6, 6);
7149
7150 static void gen_vmrgew(DisasContext *ctx)
7151 {
7152 TCGv_i64 tmp;
7153 int VT, VA, VB;
7154 if (unlikely(!ctx->altivec_enabled)) {
7155 gen_exception(ctx, POWERPC_EXCP_VPU);
7156 return;
7157 }
7158 VT = rD(ctx->opcode);
7159 VA = rA(ctx->opcode);
7160 VB = rB(ctx->opcode);
7161 tmp = tcg_temp_new_i64();
7162 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7163 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7164 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7165 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7166 tcg_temp_free_i64(tmp);
7167 }
7168
7169 static void gen_vmrgow(DisasContext *ctx)
7170 {
7171 int VT, VA, VB;
7172 if (unlikely(!ctx->altivec_enabled)) {
7173 gen_exception(ctx, POWERPC_EXCP_VPU);
7174 return;
7175 }
7176 VT = rD(ctx->opcode);
7177 VA = rA(ctx->opcode);
7178 VB = rB(ctx->opcode);
7179
7180 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7181 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7182 }
7183
7184 GEN_VXFORM(vmuloub, 4, 0);
7185 GEN_VXFORM(vmulouh, 4, 1);
7186 GEN_VXFORM(vmulouw, 4, 2);
7187 GEN_VXFORM(vmuluwm, 4, 2);
7188 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7189 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7190 GEN_VXFORM(vmulosb, 4, 4);
7191 GEN_VXFORM(vmulosh, 4, 5);
7192 GEN_VXFORM(vmulosw, 4, 6);
7193 GEN_VXFORM(vmuleub, 4, 8);
7194 GEN_VXFORM(vmuleuh, 4, 9);
7195 GEN_VXFORM(vmuleuw, 4, 10);
7196 GEN_VXFORM(vmulesb, 4, 12);
7197 GEN_VXFORM(vmulesh, 4, 13);
7198 GEN_VXFORM(vmulesw, 4, 14);
7199 GEN_VXFORM(vslb, 2, 4);
7200 GEN_VXFORM(vslh, 2, 5);
7201 GEN_VXFORM(vslw, 2, 6);
7202 GEN_VXFORM(vsld, 2, 23);
7203 GEN_VXFORM(vsrb, 2, 8);
7204 GEN_VXFORM(vsrh, 2, 9);
7205 GEN_VXFORM(vsrw, 2, 10);
7206 GEN_VXFORM(vsrd, 2, 27);
7207 GEN_VXFORM(vsrab, 2, 12);
7208 GEN_VXFORM(vsrah, 2, 13);
7209 GEN_VXFORM(vsraw, 2, 14);
7210 GEN_VXFORM(vsrad, 2, 15);
7211 GEN_VXFORM(vslo, 6, 16);
7212 GEN_VXFORM(vsro, 6, 17);
7213 GEN_VXFORM(vaddcuw, 0, 6);
7214 GEN_VXFORM(vsubcuw, 0, 22);
7215 GEN_VXFORM_ENV(vaddubs, 0, 8);
7216 GEN_VXFORM_ENV(vadduhs, 0, 9);
7217 GEN_VXFORM_ENV(vadduws, 0, 10);
7218 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7219 GEN_VXFORM_ENV(vaddshs, 0, 13);
7220 GEN_VXFORM_ENV(vaddsws, 0, 14);
7221 GEN_VXFORM_ENV(vsububs, 0, 24);
7222 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7223 GEN_VXFORM_ENV(vsubuws, 0, 26);
7224 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7225 GEN_VXFORM_ENV(vsubshs, 0, 29);
7226 GEN_VXFORM_ENV(vsubsws, 0, 30);
7227 GEN_VXFORM(vadduqm, 0, 4);
7228 GEN_VXFORM(vaddcuq, 0, 5);
7229 GEN_VXFORM3(vaddeuqm, 30, 0);
7230 GEN_VXFORM3(vaddecuq, 30, 0);
7231 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7232 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7233 GEN_VXFORM(vsubuqm, 0, 20);
7234 GEN_VXFORM(vsubcuq, 0, 21);
7235 GEN_VXFORM3(vsubeuqm, 31, 0);
7236 GEN_VXFORM3(vsubecuq, 31, 0);
7237 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7238 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7239 GEN_VXFORM(vrlb, 2, 0);
7240 GEN_VXFORM(vrlh, 2, 1);
7241 GEN_VXFORM(vrlw, 2, 2);
7242 GEN_VXFORM(vrld, 2, 3);
7243 GEN_VXFORM(vsl, 2, 7);
7244 GEN_VXFORM(vsr, 2, 11);
7245 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7246 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7247 GEN_VXFORM_ENV(vpkudum, 7, 17);
7248 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7249 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7250 GEN_VXFORM_ENV(vpkudus, 7, 19);
7251 GEN_VXFORM_ENV(vpkshus, 7, 4);
7252 GEN_VXFORM_ENV(vpkswus, 7, 5);
7253 GEN_VXFORM_ENV(vpksdus, 7, 21);
7254 GEN_VXFORM_ENV(vpkshss, 7, 6);
7255 GEN_VXFORM_ENV(vpkswss, 7, 7);
7256 GEN_VXFORM_ENV(vpksdss, 7, 23);
7257 GEN_VXFORM(vpkpx, 7, 12);
7258 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7259 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7260 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7261 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7262 GEN_VXFORM_ENV(vsumsws, 4, 30);
7263 GEN_VXFORM_ENV(vaddfp, 5, 0);
7264 GEN_VXFORM_ENV(vsubfp, 5, 1);
7265 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7266 GEN_VXFORM_ENV(vminfp, 5, 17);
7267
7268 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7269 static void glue(gen_, name)(DisasContext *ctx) \
7270 { \
7271 TCGv_ptr ra, rb, rd; \
7272 if (unlikely(!ctx->altivec_enabled)) { \
7273 gen_exception(ctx, POWERPC_EXCP_VPU); \
7274 return; \
7275 } \
7276 ra = gen_avr_ptr(rA(ctx->opcode)); \
7277 rb = gen_avr_ptr(rB(ctx->opcode)); \
7278 rd = gen_avr_ptr(rD(ctx->opcode)); \
7279 gen_helper_##opname(cpu_env, rd, ra, rb); \
7280 tcg_temp_free_ptr(ra); \
7281 tcg_temp_free_ptr(rb); \
7282 tcg_temp_free_ptr(rd); \
7283 }
7284
7285 #define GEN_VXRFORM(name, opc2, opc3) \
7286 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7287 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7288
7289 /*
7290 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7291 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7292 * come from different versions of the ISA, so we must also support a
7293 * pair of flags for each instruction.
7294 */
7295 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7296 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7297 { \
7298 if ((Rc(ctx->opcode) == 0) && \
7299 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7300 if (Rc21(ctx->opcode) == 0) { \
7301 gen_##name0(ctx); \
7302 } else { \
7303 gen_##name0##_(ctx); \
7304 } \
7305 } else if ((Rc(ctx->opcode) == 1) && \
7306 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7307 if (Rc21(ctx->opcode) == 0) { \
7308 gen_##name1(ctx); \
7309 } else { \
7310 gen_##name1##_(ctx); \
7311 } \
7312 } else { \
7313 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7314 } \
7315 }
7316
7317 GEN_VXRFORM(vcmpequb, 3, 0)
7318 GEN_VXRFORM(vcmpequh, 3, 1)
7319 GEN_VXRFORM(vcmpequw, 3, 2)
7320 GEN_VXRFORM(vcmpequd, 3, 3)
7321 GEN_VXRFORM(vcmpgtsb, 3, 12)
7322 GEN_VXRFORM(vcmpgtsh, 3, 13)
7323 GEN_VXRFORM(vcmpgtsw, 3, 14)
7324 GEN_VXRFORM(vcmpgtsd, 3, 15)
7325 GEN_VXRFORM(vcmpgtub, 3, 8)
7326 GEN_VXRFORM(vcmpgtuh, 3, 9)
7327 GEN_VXRFORM(vcmpgtuw, 3, 10)
7328 GEN_VXRFORM(vcmpgtud, 3, 11)
7329 GEN_VXRFORM(vcmpeqfp, 3, 3)
7330 GEN_VXRFORM(vcmpgefp, 3, 7)
7331 GEN_VXRFORM(vcmpgtfp, 3, 11)
7332 GEN_VXRFORM(vcmpbfp, 3, 15)
7333
7334 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7335 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7336 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7337 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7338 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7339 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7340
7341 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7342 static void glue(gen_, name)(DisasContext *ctx) \
7343 { \
7344 TCGv_ptr rd; \
7345 TCGv_i32 simm; \
7346 if (unlikely(!ctx->altivec_enabled)) { \
7347 gen_exception(ctx, POWERPC_EXCP_VPU); \
7348 return; \
7349 } \
7350 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7351 rd = gen_avr_ptr(rD(ctx->opcode)); \
7352 gen_helper_##name (rd, simm); \
7353 tcg_temp_free_i32(simm); \
7354 tcg_temp_free_ptr(rd); \
7355 }
7356
7357 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7358 GEN_VXFORM_SIMM(vspltish, 6, 13);
7359 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7360
7361 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7362 static void glue(gen_, name)(DisasContext *ctx) \
7363 { \
7364 TCGv_ptr rb, rd; \
7365 if (unlikely(!ctx->altivec_enabled)) { \
7366 gen_exception(ctx, POWERPC_EXCP_VPU); \
7367 return; \
7368 } \
7369 rb = gen_avr_ptr(rB(ctx->opcode)); \
7370 rd = gen_avr_ptr(rD(ctx->opcode)); \
7371 gen_helper_##name (rd, rb); \
7372 tcg_temp_free_ptr(rb); \
7373 tcg_temp_free_ptr(rd); \
7374 }
7375
7376 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7377 static void glue(gen_, name)(DisasContext *ctx) \
7378 { \
7379 TCGv_ptr rb, rd; \
7380 \
7381 if (unlikely(!ctx->altivec_enabled)) { \
7382 gen_exception(ctx, POWERPC_EXCP_VPU); \
7383 return; \
7384 } \
7385 rb = gen_avr_ptr(rB(ctx->opcode)); \
7386 rd = gen_avr_ptr(rD(ctx->opcode)); \
7387 gen_helper_##name(cpu_env, rd, rb); \
7388 tcg_temp_free_ptr(rb); \
7389 tcg_temp_free_ptr(rd); \
7390 }
7391
7392 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7393 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7394 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7395 GEN_VXFORM_NOA(vupklsb, 7, 10);
7396 GEN_VXFORM_NOA(vupklsh, 7, 11);
7397 GEN_VXFORM_NOA(vupklsw, 7, 27);
7398 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7399 GEN_VXFORM_NOA(vupklpx, 7, 15);
7400 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7401 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7402 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7403 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7404 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7405 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7406 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7407 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7408
7409 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7410 static void glue(gen_, name)(DisasContext *ctx) \
7411 { \
7412 TCGv_ptr rd; \
7413 TCGv_i32 simm; \
7414 if (unlikely(!ctx->altivec_enabled)) { \
7415 gen_exception(ctx, POWERPC_EXCP_VPU); \
7416 return; \
7417 } \
7418 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7419 rd = gen_avr_ptr(rD(ctx->opcode)); \
7420 gen_helper_##name (rd, simm); \
7421 tcg_temp_free_i32(simm); \
7422 tcg_temp_free_ptr(rd); \
7423 }
7424
7425 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7426 static void glue(gen_, name)(DisasContext *ctx) \
7427 { \
7428 TCGv_ptr rb, rd; \
7429 TCGv_i32 uimm; \
7430 if (unlikely(!ctx->altivec_enabled)) { \
7431 gen_exception(ctx, POWERPC_EXCP_VPU); \
7432 return; \
7433 } \
7434 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7435 rb = gen_avr_ptr(rB(ctx->opcode)); \
7436 rd = gen_avr_ptr(rD(ctx->opcode)); \
7437 gen_helper_##name (rd, rb, uimm); \
7438 tcg_temp_free_i32(uimm); \
7439 tcg_temp_free_ptr(rb); \
7440 tcg_temp_free_ptr(rd); \
7441 }
7442
7443 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7444 static void glue(gen_, name)(DisasContext *ctx) \
7445 { \
7446 TCGv_ptr rb, rd; \
7447 TCGv_i32 uimm; \
7448 \
7449 if (unlikely(!ctx->altivec_enabled)) { \
7450 gen_exception(ctx, POWERPC_EXCP_VPU); \
7451 return; \
7452 } \
7453 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7454 rb = gen_avr_ptr(rB(ctx->opcode)); \
7455 rd = gen_avr_ptr(rD(ctx->opcode)); \
7456 gen_helper_##name(cpu_env, rd, rb, uimm); \
7457 tcg_temp_free_i32(uimm); \
7458 tcg_temp_free_ptr(rb); \
7459 tcg_temp_free_ptr(rd); \
7460 }
7461
7462 GEN_VXFORM_UIMM(vspltb, 6, 8);
7463 GEN_VXFORM_UIMM(vsplth, 6, 9);
7464 GEN_VXFORM_UIMM(vspltw, 6, 10);
7465 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7466 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7467 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7468 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7469
7470 static void gen_vsldoi(DisasContext *ctx)
7471 {
7472 TCGv_ptr ra, rb, rd;
7473 TCGv_i32 sh;
7474 if (unlikely(!ctx->altivec_enabled)) {
7475 gen_exception(ctx, POWERPC_EXCP_VPU);
7476 return;
7477 }
7478 ra = gen_avr_ptr(rA(ctx->opcode));
7479 rb = gen_avr_ptr(rB(ctx->opcode));
7480 rd = gen_avr_ptr(rD(ctx->opcode));
7481 sh = tcg_const_i32(VSH(ctx->opcode));
7482 gen_helper_vsldoi (rd, ra, rb, sh);
7483 tcg_temp_free_ptr(ra);
7484 tcg_temp_free_ptr(rb);
7485 tcg_temp_free_ptr(rd);
7486 tcg_temp_free_i32(sh);
7487 }
7488
7489 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7490 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7491 { \
7492 TCGv_ptr ra, rb, rc, rd; \
7493 if (unlikely(!ctx->altivec_enabled)) { \
7494 gen_exception(ctx, POWERPC_EXCP_VPU); \
7495 return; \
7496 } \
7497 ra = gen_avr_ptr(rA(ctx->opcode)); \
7498 rb = gen_avr_ptr(rB(ctx->opcode)); \
7499 rc = gen_avr_ptr(rC(ctx->opcode)); \
7500 rd = gen_avr_ptr(rD(ctx->opcode)); \
7501 if (Rc(ctx->opcode)) { \
7502 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7503 } else { \
7504 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7505 } \
7506 tcg_temp_free_ptr(ra); \
7507 tcg_temp_free_ptr(rb); \
7508 tcg_temp_free_ptr(rc); \
7509 tcg_temp_free_ptr(rd); \
7510 }
7511
7512 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7513
7514 static void gen_vmladduhm(DisasContext *ctx)
7515 {
7516 TCGv_ptr ra, rb, rc, rd;
7517 if (unlikely(!ctx->altivec_enabled)) {
7518 gen_exception(ctx, POWERPC_EXCP_VPU);
7519 return;
7520 }
7521 ra = gen_avr_ptr(rA(ctx->opcode));
7522 rb = gen_avr_ptr(rB(ctx->opcode));
7523 rc = gen_avr_ptr(rC(ctx->opcode));
7524 rd = gen_avr_ptr(rD(ctx->opcode));
7525 gen_helper_vmladduhm(rd, ra, rb, rc);
7526 tcg_temp_free_ptr(ra);
7527 tcg_temp_free_ptr(rb);
7528 tcg_temp_free_ptr(rc);
7529 tcg_temp_free_ptr(rd);
7530 }
7531
7532 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7533 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7534 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7535 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7536 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7537
7538 GEN_VXFORM_NOA(vclzb, 1, 28)
7539 GEN_VXFORM_NOA(vclzh, 1, 29)
7540 GEN_VXFORM_NOA(vclzw, 1, 30)
7541 GEN_VXFORM_NOA(vclzd, 1, 31)
7542 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7543 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7544 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7545 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7546 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7547 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7548 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7549 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7550 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7551 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7552 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7553 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7554 GEN_VXFORM(vbpermq, 6, 21);
7555 GEN_VXFORM_NOA(vgbbd, 6, 20);
7556 GEN_VXFORM(vpmsumb, 4, 16)
7557 GEN_VXFORM(vpmsumh, 4, 17)
7558 GEN_VXFORM(vpmsumw, 4, 18)
7559 GEN_VXFORM(vpmsumd, 4, 19)
7560
7561 #define GEN_BCD(op) \
7562 static void gen_##op(DisasContext *ctx) \
7563 { \
7564 TCGv_ptr ra, rb, rd; \
7565 TCGv_i32 ps; \
7566 \
7567 if (unlikely(!ctx->altivec_enabled)) { \
7568 gen_exception(ctx, POWERPC_EXCP_VPU); \
7569 return; \
7570 } \
7571 \
7572 ra = gen_avr_ptr(rA(ctx->opcode)); \
7573 rb = gen_avr_ptr(rB(ctx->opcode)); \
7574 rd = gen_avr_ptr(rD(ctx->opcode)); \
7575 \
7576 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7577 \
7578 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7579 \
7580 tcg_temp_free_ptr(ra); \
7581 tcg_temp_free_ptr(rb); \
7582 tcg_temp_free_ptr(rd); \
7583 tcg_temp_free_i32(ps); \
7584 }
7585
7586 GEN_BCD(bcdadd)
7587 GEN_BCD(bcdsub)
7588
7589 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7590 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7591 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7592 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7593 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7594 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7595 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7596 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7597
7598 static void gen_vsbox(DisasContext *ctx)
7599 {
7600 TCGv_ptr ra, rd;
7601 if (unlikely(!ctx->altivec_enabled)) {
7602 gen_exception(ctx, POWERPC_EXCP_VPU);
7603 return;
7604 }
7605 ra = gen_avr_ptr(rA(ctx->opcode));
7606 rd = gen_avr_ptr(rD(ctx->opcode));
7607 gen_helper_vsbox(rd, ra);
7608 tcg_temp_free_ptr(ra);
7609 tcg_temp_free_ptr(rd);
7610 }
7611
7612 GEN_VXFORM(vcipher, 4, 20)
7613 GEN_VXFORM(vcipherlast, 4, 20)
7614 GEN_VXFORM(vncipher, 4, 21)
7615 GEN_VXFORM(vncipherlast, 4, 21)
7616
7617 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7618 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7619 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7620 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7621
7622 #define VSHASIGMA(op) \
7623 static void gen_##op(DisasContext *ctx) \
7624 { \
7625 TCGv_ptr ra, rd; \
7626 TCGv_i32 st_six; \
7627 if (unlikely(!ctx->altivec_enabled)) { \
7628 gen_exception(ctx, POWERPC_EXCP_VPU); \
7629 return; \
7630 } \
7631 ra = gen_avr_ptr(rA(ctx->opcode)); \
7632 rd = gen_avr_ptr(rD(ctx->opcode)); \
7633 st_six = tcg_const_i32(rB(ctx->opcode)); \
7634 gen_helper_##op(rd, ra, st_six); \
7635 tcg_temp_free_ptr(ra); \
7636 tcg_temp_free_ptr(rd); \
7637 tcg_temp_free_i32(st_six); \
7638 }
7639
7640 VSHASIGMA(vshasigmaw)
7641 VSHASIGMA(vshasigmad)
7642
7643 GEN_VXFORM3(vpermxor, 22, 0xFF)
7644 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7645 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7646
7647 /*** VSX extension ***/
7648
7649 static inline TCGv_i64 cpu_vsrh(int n)
7650 {
7651 if (n < 32) {
7652 return cpu_fpr[n];
7653 } else {
7654 return cpu_avrh[n-32];
7655 }
7656 }
7657
7658 static inline TCGv_i64 cpu_vsrl(int n)
7659 {
7660 if (n < 32) {
7661 return cpu_vsr[n];
7662 } else {
7663 return cpu_avrl[n-32];
7664 }
7665 }
7666
7667 #define VSX_LOAD_SCALAR(name, operation) \
7668 static void gen_##name(DisasContext *ctx) \
7669 { \
7670 TCGv EA; \
7671 if (unlikely(!ctx->vsx_enabled)) { \
7672 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7673 return; \
7674 } \
7675 gen_set_access_type(ctx, ACCESS_INT); \
7676 EA = tcg_temp_new(); \
7677 gen_addr_reg_index(ctx, EA); \
7678 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7679 /* NOTE: cpu_vsrl is undefined */ \
7680 tcg_temp_free(EA); \
7681 }
7682
7683 VSX_LOAD_SCALAR(lxsdx, ld64)
7684 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7685 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7686 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7687
7688 static void gen_lxvd2x(DisasContext *ctx)
7689 {
7690 TCGv EA;
7691 if (unlikely(!ctx->vsx_enabled)) {
7692 gen_exception(ctx, POWERPC_EXCP_VSXU);
7693 return;
7694 }
7695 gen_set_access_type(ctx, ACCESS_INT);
7696 EA = tcg_temp_new();
7697 gen_addr_reg_index(ctx, EA);
7698 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7699 tcg_gen_addi_tl(EA, EA, 8);
7700 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7701 tcg_temp_free(EA);
7702 }
7703
7704 static void gen_lxvdsx(DisasContext *ctx)
7705 {
7706 TCGv EA;
7707 if (unlikely(!ctx->vsx_enabled)) {
7708 gen_exception(ctx, POWERPC_EXCP_VSXU);
7709 return;
7710 }
7711 gen_set_access_type(ctx, ACCESS_INT);
7712 EA = tcg_temp_new();
7713 gen_addr_reg_index(ctx, EA);
7714 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7715 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7716 tcg_temp_free(EA);
7717 }
7718
7719 static void gen_lxvw4x(DisasContext *ctx)
7720 {
7721 TCGv EA;
7722 TCGv_i64 tmp;
7723 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7724 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7725 if (unlikely(!ctx->vsx_enabled)) {
7726 gen_exception(ctx, POWERPC_EXCP_VSXU);
7727 return;
7728 }
7729 gen_set_access_type(ctx, ACCESS_INT);
7730 EA = tcg_temp_new();
7731 tmp = tcg_temp_new_i64();
7732
7733 gen_addr_reg_index(ctx, EA);
7734 gen_qemu_ld32u_i64(ctx, tmp, EA);
7735 tcg_gen_addi_tl(EA, EA, 4);
7736 gen_qemu_ld32u_i64(ctx, xth, EA);
7737 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7738
7739 tcg_gen_addi_tl(EA, EA, 4);
7740 gen_qemu_ld32u_i64(ctx, tmp, EA);
7741 tcg_gen_addi_tl(EA, EA, 4);
7742 gen_qemu_ld32u_i64(ctx, xtl, EA);
7743 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7744
7745 tcg_temp_free(EA);
7746 tcg_temp_free_i64(tmp);
7747 }
7748
7749 #define VSX_STORE_SCALAR(name, operation) \
7750 static void gen_##name(DisasContext *ctx) \
7751 { \
7752 TCGv EA; \
7753 if (unlikely(!ctx->vsx_enabled)) { \
7754 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7755 return; \
7756 } \
7757 gen_set_access_type(ctx, ACCESS_INT); \
7758 EA = tcg_temp_new(); \
7759 gen_addr_reg_index(ctx, EA); \
7760 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7761 tcg_temp_free(EA); \
7762 }
7763
7764 VSX_STORE_SCALAR(stxsdx, st64)
7765 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7766 VSX_STORE_SCALAR(stxsspx, st32fs)
7767
7768 static void gen_stxvd2x(DisasContext *ctx)
7769 {
7770 TCGv EA;
7771 if (unlikely(!ctx->vsx_enabled)) {
7772 gen_exception(ctx, POWERPC_EXCP_VSXU);
7773 return;
7774 }
7775 gen_set_access_type(ctx, ACCESS_INT);
7776 EA = tcg_temp_new();
7777 gen_addr_reg_index(ctx, EA);
7778 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7779 tcg_gen_addi_tl(EA, EA, 8);
7780 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7781 tcg_temp_free(EA);
7782 }
7783
7784 static void gen_stxvw4x(DisasContext *ctx)
7785 {
7786 TCGv_i64 tmp;
7787 TCGv EA;
7788 if (unlikely(!ctx->vsx_enabled)) {
7789 gen_exception(ctx, POWERPC_EXCP_VSXU);
7790 return;
7791 }
7792 gen_set_access_type(ctx, ACCESS_INT);
7793 EA = tcg_temp_new();
7794 gen_addr_reg_index(ctx, EA);
7795 tmp = tcg_temp_new_i64();
7796
7797 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7798 gen_qemu_st32_i64(ctx, tmp, EA);
7799 tcg_gen_addi_tl(EA, EA, 4);
7800 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7801
7802 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7803 tcg_gen_addi_tl(EA, EA, 4);
7804 gen_qemu_st32_i64(ctx, tmp, EA);
7805 tcg_gen_addi_tl(EA, EA, 4);
7806 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7807
7808 tcg_temp_free(EA);
7809 tcg_temp_free_i64(tmp);
7810 }
7811
7812 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7813 static void gen_##name(DisasContext *ctx) \
7814 { \
7815 if (xS(ctx->opcode) < 32) { \
7816 if (unlikely(!ctx->fpu_enabled)) { \
7817 gen_exception(ctx, POWERPC_EXCP_FPU); \
7818 return; \
7819 } \
7820 } else { \
7821 if (unlikely(!ctx->altivec_enabled)) { \
7822 gen_exception(ctx, POWERPC_EXCP_VPU); \
7823 return; \
7824 } \
7825 } \
7826 TCGv_i64 tmp = tcg_temp_new_i64(); \
7827 tcg_gen_##tcgop1(tmp, source); \
7828 tcg_gen_##tcgop2(target, tmp); \
7829 tcg_temp_free_i64(tmp); \
7830 }
7831
7832
7833 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7834 cpu_vsrh(xS(ctx->opcode)))
7835 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7836 cpu_gpr[rA(ctx->opcode)])
7837 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7838 cpu_gpr[rA(ctx->opcode)])
7839
7840 #if defined(TARGET_PPC64)
7841 #define MV_VSRD(name, target, source) \
7842 static void gen_##name(DisasContext *ctx) \
7843 { \
7844 if (xS(ctx->opcode) < 32) { \
7845 if (unlikely(!ctx->fpu_enabled)) { \
7846 gen_exception(ctx, POWERPC_EXCP_FPU); \
7847 return; \
7848 } \
7849 } else { \
7850 if (unlikely(!ctx->altivec_enabled)) { \
7851 gen_exception(ctx, POWERPC_EXCP_VPU); \
7852 return; \
7853 } \
7854 } \
7855 tcg_gen_mov_i64(target, source); \
7856 }
7857
7858 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7859 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7860
7861 #endif
7862
7863 static void gen_xxpermdi(DisasContext *ctx)
7864 {
7865 if (unlikely(!ctx->vsx_enabled)) {
7866 gen_exception(ctx, POWERPC_EXCP_VSXU);
7867 return;
7868 }
7869
7870 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7871 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7872 TCGv_i64 xh, xl;
7873
7874 xh = tcg_temp_new_i64();
7875 xl = tcg_temp_new_i64();
7876
7877 if ((DM(ctx->opcode) & 2) == 0) {
7878 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7879 } else {
7880 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7881 }
7882 if ((DM(ctx->opcode) & 1) == 0) {
7883 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7884 } else {
7885 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7886 }
7887
7888 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7889 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7890
7891 tcg_temp_free_i64(xh);
7892 tcg_temp_free_i64(xl);
7893 } else {
7894 if ((DM(ctx->opcode) & 2) == 0) {
7895 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7896 } else {
7897 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7898 }
7899 if ((DM(ctx->opcode) & 1) == 0) {
7900 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7901 } else {
7902 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7903 }
7904 }
7905 }
7906
7907 #define OP_ABS 1
7908 #define OP_NABS 2
7909 #define OP_NEG 3
7910 #define OP_CPSGN 4
7911 #define SGN_MASK_DP 0x8000000000000000ull
7912 #define SGN_MASK_SP 0x8000000080000000ull
7913
7914 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7915 static void glue(gen_, name)(DisasContext * ctx) \
7916 { \
7917 TCGv_i64 xb, sgm; \
7918 if (unlikely(!ctx->vsx_enabled)) { \
7919 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7920 return; \
7921 } \
7922 xb = tcg_temp_new_i64(); \
7923 sgm = tcg_temp_new_i64(); \
7924 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7925 tcg_gen_movi_i64(sgm, sgn_mask); \
7926 switch (op) { \
7927 case OP_ABS: { \
7928 tcg_gen_andc_i64(xb, xb, sgm); \
7929 break; \
7930 } \
7931 case OP_NABS: { \
7932 tcg_gen_or_i64(xb, xb, sgm); \
7933 break; \
7934 } \
7935 case OP_NEG: { \
7936 tcg_gen_xor_i64(xb, xb, sgm); \
7937 break; \
7938 } \
7939 case OP_CPSGN: { \
7940 TCGv_i64 xa = tcg_temp_new_i64(); \
7941 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7942 tcg_gen_and_i64(xa, xa, sgm); \
7943 tcg_gen_andc_i64(xb, xb, sgm); \
7944 tcg_gen_or_i64(xb, xb, xa); \
7945 tcg_temp_free_i64(xa); \
7946 break; \
7947 } \
7948 } \
7949 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7950 tcg_temp_free_i64(xb); \
7951 tcg_temp_free_i64(sgm); \
7952 }
7953
7954 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7955 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7956 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7957 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7958
7959 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7960 static void glue(gen_, name)(DisasContext * ctx) \
7961 { \
7962 TCGv_i64 xbh, xbl, sgm; \
7963 if (unlikely(!ctx->vsx_enabled)) { \
7964 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7965 return; \
7966 } \
7967 xbh = tcg_temp_new_i64(); \
7968 xbl = tcg_temp_new_i64(); \
7969 sgm = tcg_temp_new_i64(); \
7970 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7971 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7972 tcg_gen_movi_i64(sgm, sgn_mask); \
7973 switch (op) { \
7974 case OP_ABS: { \
7975 tcg_gen_andc_i64(xbh, xbh, sgm); \
7976 tcg_gen_andc_i64(xbl, xbl, sgm); \
7977 break; \
7978 } \
7979 case OP_NABS: { \
7980 tcg_gen_or_i64(xbh, xbh, sgm); \
7981 tcg_gen_or_i64(xbl, xbl, sgm); \
7982 break; \
7983 } \
7984 case OP_NEG: { \
7985 tcg_gen_xor_i64(xbh, xbh, sgm); \
7986 tcg_gen_xor_i64(xbl, xbl, sgm); \
7987 break; \
7988 } \
7989 case OP_CPSGN: { \
7990 TCGv_i64 xah = tcg_temp_new_i64(); \
7991 TCGv_i64 xal = tcg_temp_new_i64(); \
7992 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7993 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7994 tcg_gen_and_i64(xah, xah, sgm); \
7995 tcg_gen_and_i64(xal, xal, sgm); \
7996 tcg_gen_andc_i64(xbh, xbh, sgm); \
7997 tcg_gen_andc_i64(xbl, xbl, sgm); \
7998 tcg_gen_or_i64(xbh, xbh, xah); \
7999 tcg_gen_or_i64(xbl, xbl, xal); \
8000 tcg_temp_free_i64(xah); \
8001 tcg_temp_free_i64(xal); \
8002 break; \
8003 } \
8004 } \
8005 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
8006 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
8007 tcg_temp_free_i64(xbh); \
8008 tcg_temp_free_i64(xbl); \
8009 tcg_temp_free_i64(sgm); \
8010 }
8011
8012 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
8013 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
8014 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
8015 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
8016 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
8017 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8018 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8019 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8020
8021 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8022 static void gen_##name(DisasContext * ctx) \
8023 { \
8024 TCGv_i32 opc; \
8025 if (unlikely(!ctx->vsx_enabled)) { \
8026 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8027 return; \
8028 } \
8029 /* NIP cannot be restored if the memory exception comes from an helper */ \
8030 gen_update_nip(ctx, ctx->nip - 4); \
8031 opc = tcg_const_i32(ctx->opcode); \
8032 gen_helper_##name(cpu_env, opc); \
8033 tcg_temp_free_i32(opc); \
8034 }
8035
8036 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8037 static void gen_##name(DisasContext * ctx) \
8038 { \
8039 if (unlikely(!ctx->vsx_enabled)) { \
8040 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8041 return; \
8042 } \
8043 /* NIP cannot be restored if the exception comes */ \
8044 /* from a helper. */ \
8045 gen_update_nip(ctx, ctx->nip - 4); \
8046 \
8047 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8048 cpu_vsrh(xB(ctx->opcode))); \
8049 }
8050
8051 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8074 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8076 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8088
8089 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8090 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8091 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8092 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8093 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8094 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8095 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8096 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8097 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8098 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8099 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8100 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8101 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8102 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8103 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8104 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8105 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8106
8107 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8108 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8109 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8110 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8111 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8112 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8113 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8114 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8115 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8116 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8117 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8118 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8119 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8120 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8121 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8122 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8123 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8124 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8125 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8126 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8127 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8128 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8129 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8130 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8131 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8132 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8133 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8134 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8135 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8136 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8137 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8138 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8139 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8140 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8141 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8142 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8143
8144 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8145 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8146 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8147 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8148 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8149 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8150 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8151 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8152 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8153 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8154 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8155 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8156 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8157 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8158 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8159 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8160 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8161 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8162 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8163 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8164 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8165 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8166 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8167 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8168 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8169 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8170 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8171 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8172 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8173 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8174 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8175 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8176 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8177 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8178 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8179 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8180
8181 #define VSX_LOGICAL(name, tcg_op) \
8182 static void glue(gen_, name)(DisasContext * ctx) \
8183 { \
8184 if (unlikely(!ctx->vsx_enabled)) { \
8185 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8186 return; \
8187 } \
8188 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8189 cpu_vsrh(xB(ctx->opcode))); \
8190 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8191 cpu_vsrl(xB(ctx->opcode))); \
8192 }
8193
8194 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8195 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8196 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8197 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8198 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8199 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8200 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8201 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8202
8203 #define VSX_XXMRG(name, high) \
8204 static void glue(gen_, name)(DisasContext * ctx) \
8205 { \
8206 TCGv_i64 a0, a1, b0, b1; \
8207 if (unlikely(!ctx->vsx_enabled)) { \
8208 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8209 return; \
8210 } \
8211 a0 = tcg_temp_new_i64(); \
8212 a1 = tcg_temp_new_i64(); \
8213 b0 = tcg_temp_new_i64(); \
8214 b1 = tcg_temp_new_i64(); \
8215 if (high) { \
8216 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8217 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8218 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8219 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8220 } else { \
8221 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8222 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8223 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8224 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8225 } \
8226 tcg_gen_shri_i64(a0, a0, 32); \
8227 tcg_gen_shri_i64(b0, b0, 32); \
8228 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8229 b0, a0, 32, 32); \
8230 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8231 b1, a1, 32, 32); \
8232 tcg_temp_free_i64(a0); \
8233 tcg_temp_free_i64(a1); \
8234 tcg_temp_free_i64(b0); \
8235 tcg_temp_free_i64(b1); \
8236 }
8237
8238 VSX_XXMRG(xxmrghw, 1)
8239 VSX_XXMRG(xxmrglw, 0)
8240
8241 static void gen_xxsel(DisasContext * ctx)
8242 {
8243 TCGv_i64 a, b, c;
8244 if (unlikely(!ctx->vsx_enabled)) {
8245 gen_exception(ctx, POWERPC_EXCP_VSXU);
8246 return;
8247 }
8248 a = tcg_temp_new_i64();
8249 b = tcg_temp_new_i64();
8250 c = tcg_temp_new_i64();
8251
8252 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8253 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8254 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8255
8256 tcg_gen_and_i64(b, b, c);
8257 tcg_gen_andc_i64(a, a, c);
8258 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8259
8260 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8261 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8262 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8263
8264 tcg_gen_and_i64(b, b, c);
8265 tcg_gen_andc_i64(a, a, c);
8266 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8267
8268 tcg_temp_free_i64(a);
8269 tcg_temp_free_i64(b);
8270 tcg_temp_free_i64(c);
8271 }
8272
8273 static void gen_xxspltw(DisasContext *ctx)
8274 {
8275 TCGv_i64 b, b2;
8276 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8277 cpu_vsrl(xB(ctx->opcode)) :
8278 cpu_vsrh(xB(ctx->opcode));
8279
8280 if (unlikely(!ctx->vsx_enabled)) {
8281 gen_exception(ctx, POWERPC_EXCP_VSXU);
8282 return;
8283 }
8284
8285 b = tcg_temp_new_i64();
8286 b2 = tcg_temp_new_i64();
8287
8288 if (UIM(ctx->opcode) & 1) {
8289 tcg_gen_ext32u_i64(b, vsr);
8290 } else {
8291 tcg_gen_shri_i64(b, vsr, 32);
8292 }
8293
8294 tcg_gen_shli_i64(b2, b, 32);
8295 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8296 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8297
8298 tcg_temp_free_i64(b);
8299 tcg_temp_free_i64(b2);
8300 }
8301
8302 static void gen_xxsldwi(DisasContext *ctx)
8303 {
8304 TCGv_i64 xth, xtl;
8305 if (unlikely(!ctx->vsx_enabled)) {
8306 gen_exception(ctx, POWERPC_EXCP_VSXU);
8307 return;
8308 }
8309 xth = tcg_temp_new_i64();
8310 xtl = tcg_temp_new_i64();
8311
8312 switch (SHW(ctx->opcode)) {
8313 case 0: {
8314 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8315 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8316 break;
8317 }
8318 case 1: {
8319 TCGv_i64 t0 = tcg_temp_new_i64();
8320 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8321 tcg_gen_shli_i64(xth, xth, 32);
8322 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8323 tcg_gen_shri_i64(t0, t0, 32);
8324 tcg_gen_or_i64(xth, xth, t0);
8325 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8326 tcg_gen_shli_i64(xtl, xtl, 32);
8327 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8328 tcg_gen_shri_i64(t0, t0, 32);
8329 tcg_gen_or_i64(xtl, xtl, t0);
8330 tcg_temp_free_i64(t0);
8331 break;
8332 }
8333 case 2: {
8334 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8335 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8336 break;
8337 }
8338 case 3: {
8339 TCGv_i64 t0 = tcg_temp_new_i64();
8340 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8341 tcg_gen_shli_i64(xth, xth, 32);
8342 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8343 tcg_gen_shri_i64(t0, t0, 32);
8344 tcg_gen_or_i64(xth, xth, t0);
8345 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8346 tcg_gen_shli_i64(xtl, xtl, 32);
8347 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8348 tcg_gen_shri_i64(t0, t0, 32);
8349 tcg_gen_or_i64(xtl, xtl, t0);
8350 tcg_temp_free_i64(t0);
8351 break;
8352 }
8353 }
8354
8355 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8356 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8357
8358 tcg_temp_free_i64(xth);
8359 tcg_temp_free_i64(xtl);
8360 }
8361
8362 /*** Decimal Floating Point ***/
8363
8364 static inline TCGv_ptr gen_fprp_ptr(int reg)
8365 {
8366 TCGv_ptr r = tcg_temp_new_ptr();
8367 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8368 return r;
8369 }
8370
8371 #define GEN_DFP_T_A_B_Rc(name) \
8372 static void gen_##name(DisasContext *ctx) \
8373 { \
8374 TCGv_ptr rd, ra, rb; \
8375 if (unlikely(!ctx->fpu_enabled)) { \
8376 gen_exception(ctx, POWERPC_EXCP_FPU); \
8377 return; \
8378 } \
8379 gen_update_nip(ctx, ctx->nip - 4); \
8380 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8381 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8382 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8383 gen_helper_##name(cpu_env, rd, ra, rb); \
8384 if (unlikely(Rc(ctx->opcode) != 0)) { \
8385 gen_set_cr1_from_fpscr(ctx); \
8386 } \
8387 tcg_temp_free_ptr(rd); \
8388 tcg_temp_free_ptr(ra); \
8389 tcg_temp_free_ptr(rb); \
8390 }
8391
8392 #define GEN_DFP_BF_A_B(name) \
8393 static void gen_##name(DisasContext *ctx) \
8394 { \
8395 TCGv_ptr ra, rb; \
8396 if (unlikely(!ctx->fpu_enabled)) { \
8397 gen_exception(ctx, POWERPC_EXCP_FPU); \
8398 return; \
8399 } \
8400 gen_update_nip(ctx, ctx->nip - 4); \
8401 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8402 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8403 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8404 cpu_env, ra, rb); \
8405 tcg_temp_free_ptr(ra); \
8406 tcg_temp_free_ptr(rb); \
8407 }
8408
8409 #define GEN_DFP_BF_A_DCM(name) \
8410 static void gen_##name(DisasContext *ctx) \
8411 { \
8412 TCGv_ptr ra; \
8413 TCGv_i32 dcm; \
8414 if (unlikely(!ctx->fpu_enabled)) { \
8415 gen_exception(ctx, POWERPC_EXCP_FPU); \
8416 return; \
8417 } \
8418 gen_update_nip(ctx, ctx->nip - 4); \
8419 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8420 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8421 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8422 cpu_env, ra, dcm); \
8423 tcg_temp_free_ptr(ra); \
8424 tcg_temp_free_i32(dcm); \
8425 }
8426
8427 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8428 static void gen_##name(DisasContext *ctx) \
8429 { \
8430 TCGv_ptr rt, rb; \
8431 TCGv_i32 u32_1, u32_2; \
8432 if (unlikely(!ctx->fpu_enabled)) { \
8433 gen_exception(ctx, POWERPC_EXCP_FPU); \
8434 return; \
8435 } \
8436 gen_update_nip(ctx, ctx->nip - 4); \
8437 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8438 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8439 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8440 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8441 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8442 if (unlikely(Rc(ctx->opcode) != 0)) { \
8443 gen_set_cr1_from_fpscr(ctx); \
8444 } \
8445 tcg_temp_free_ptr(rt); \
8446 tcg_temp_free_ptr(rb); \
8447 tcg_temp_free_i32(u32_1); \
8448 tcg_temp_free_i32(u32_2); \
8449 }
8450
8451 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8452 static void gen_##name(DisasContext *ctx) \
8453 { \
8454 TCGv_ptr rt, ra, rb; \
8455 TCGv_i32 i32; \
8456 if (unlikely(!ctx->fpu_enabled)) { \
8457 gen_exception(ctx, POWERPC_EXCP_FPU); \
8458 return; \
8459 } \
8460 gen_update_nip(ctx, ctx->nip - 4); \
8461 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8462 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8463 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8464 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8465 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8466 if (unlikely(Rc(ctx->opcode) != 0)) { \
8467 gen_set_cr1_from_fpscr(ctx); \
8468 } \
8469 tcg_temp_free_ptr(rt); \
8470 tcg_temp_free_ptr(rb); \
8471 tcg_temp_free_ptr(ra); \
8472 tcg_temp_free_i32(i32); \
8473 }
8474
8475 #define GEN_DFP_T_B_Rc(name) \
8476 static void gen_##name(DisasContext *ctx) \
8477 { \
8478 TCGv_ptr rt, rb; \
8479 if (unlikely(!ctx->fpu_enabled)) { \
8480 gen_exception(ctx, POWERPC_EXCP_FPU); \
8481 return; \
8482 } \
8483 gen_update_nip(ctx, ctx->nip - 4); \
8484 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8485 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8486 gen_helper_##name(cpu_env, rt, rb); \
8487 if (unlikely(Rc(ctx->opcode) != 0)) { \
8488 gen_set_cr1_from_fpscr(ctx); \
8489 } \
8490 tcg_temp_free_ptr(rt); \
8491 tcg_temp_free_ptr(rb); \
8492 }
8493
8494 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8495 static void gen_##name(DisasContext *ctx) \
8496 { \
8497 TCGv_ptr rt, rs; \
8498 TCGv_i32 i32; \
8499 if (unlikely(!ctx->fpu_enabled)) { \
8500 gen_exception(ctx, POWERPC_EXCP_FPU); \
8501 return; \
8502 } \
8503 gen_update_nip(ctx, ctx->nip - 4); \
8504 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8505 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8506 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8507 gen_helper_##name(cpu_env, rt, rs, i32); \
8508 if (unlikely(Rc(ctx->opcode) != 0)) { \
8509 gen_set_cr1_from_fpscr(ctx); \
8510 } \
8511 tcg_temp_free_ptr(rt); \
8512 tcg_temp_free_ptr(rs); \
8513 tcg_temp_free_i32(i32); \
8514 }
8515
8516 GEN_DFP_T_A_B_Rc(dadd)
8517 GEN_DFP_T_A_B_Rc(daddq)
8518 GEN_DFP_T_A_B_Rc(dsub)
8519 GEN_DFP_T_A_B_Rc(dsubq)
8520 GEN_DFP_T_A_B_Rc(dmul)
8521 GEN_DFP_T_A_B_Rc(dmulq)
8522 GEN_DFP_T_A_B_Rc(ddiv)
8523 GEN_DFP_T_A_B_Rc(ddivq)
8524 GEN_DFP_BF_A_B(dcmpu)
8525 GEN_DFP_BF_A_B(dcmpuq)
8526 GEN_DFP_BF_A_B(dcmpo)
8527 GEN_DFP_BF_A_B(dcmpoq)
8528 GEN_DFP_BF_A_DCM(dtstdc)
8529 GEN_DFP_BF_A_DCM(dtstdcq)
8530 GEN_DFP_BF_A_DCM(dtstdg)
8531 GEN_DFP_BF_A_DCM(dtstdgq)
8532 GEN_DFP_BF_A_B(dtstex)
8533 GEN_DFP_BF_A_B(dtstexq)
8534 GEN_DFP_BF_A_B(dtstsf)
8535 GEN_DFP_BF_A_B(dtstsfq)
8536 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8537 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8538 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8539 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8540 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8541 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8542 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8543 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8544 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8545 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8546 GEN_DFP_T_B_Rc(dctdp)
8547 GEN_DFP_T_B_Rc(dctqpq)
8548 GEN_DFP_T_B_Rc(drsp)
8549 GEN_DFP_T_B_Rc(drdpq)
8550 GEN_DFP_T_B_Rc(dcffix)
8551 GEN_DFP_T_B_Rc(dcffixq)
8552 GEN_DFP_T_B_Rc(dctfix)
8553 GEN_DFP_T_B_Rc(dctfixq)
8554 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8555 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8556 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8557 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8558 GEN_DFP_T_B_Rc(dxex)
8559 GEN_DFP_T_B_Rc(dxexq)
8560 GEN_DFP_T_A_B_Rc(diex)
8561 GEN_DFP_T_A_B_Rc(diexq)
8562 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8563 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8564 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8565 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8566
8567 /*** SPE extension ***/
8568 /* Register moves */
8569
8570 static inline void gen_evmra(DisasContext *ctx)
8571 {
8572
8573 if (unlikely(!ctx->spe_enabled)) {
8574 gen_exception(ctx, POWERPC_EXCP_SPEU);
8575 return;
8576 }
8577
8578 TCGv_i64 tmp = tcg_temp_new_i64();
8579
8580 /* tmp := rA_lo + rA_hi << 32 */
8581 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8582
8583 /* spe_acc := tmp */
8584 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8585 tcg_temp_free_i64(tmp);
8586
8587 /* rD := rA */
8588 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8589 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8590 }
8591
8592 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8593 {
8594 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8595 }
8596
8597 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8598 {
8599 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8600 }
8601
8602 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8603 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8604 { \
8605 if (Rc(ctx->opcode)) \
8606 gen_##name1(ctx); \
8607 else \
8608 gen_##name0(ctx); \
8609 }
8610
8611 /* Handler for undefined SPE opcodes */
8612 static inline void gen_speundef(DisasContext *ctx)
8613 {
8614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8615 }
8616
8617 /* SPE logic */
8618 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8619 static inline void gen_##name(DisasContext *ctx) \
8620 { \
8621 if (unlikely(!ctx->spe_enabled)) { \
8622 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8623 return; \
8624 } \
8625 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8626 cpu_gpr[rB(ctx->opcode)]); \
8627 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8628 cpu_gprh[rB(ctx->opcode)]); \
8629 }
8630
8631 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8632 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8633 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8634 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8635 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8636 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8637 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8638 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8639
8640 /* SPE logic immediate */
8641 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8642 static inline void gen_##name(DisasContext *ctx) \
8643 { \
8644 TCGv_i32 t0; \
8645 if (unlikely(!ctx->spe_enabled)) { \
8646 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8647 return; \
8648 } \
8649 t0 = tcg_temp_new_i32(); \
8650 \
8651 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8652 tcg_opi(t0, t0, rB(ctx->opcode)); \
8653 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8654 \
8655 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8656 tcg_opi(t0, t0, rB(ctx->opcode)); \
8657 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8658 \
8659 tcg_temp_free_i32(t0); \
8660 }
8661 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8662 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8663 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8664 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8665
8666 /* SPE arithmetic */
8667 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8668 static inline void gen_##name(DisasContext *ctx) \
8669 { \
8670 TCGv_i32 t0; \
8671 if (unlikely(!ctx->spe_enabled)) { \
8672 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8673 return; \
8674 } \
8675 t0 = tcg_temp_new_i32(); \
8676 \
8677 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8678 tcg_op(t0, t0); \
8679 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8680 \
8681 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8682 tcg_op(t0, t0); \
8683 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8684 \
8685 tcg_temp_free_i32(t0); \
8686 }
8687
8688 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8689 {
8690 TCGLabel *l1 = gen_new_label();
8691 TCGLabel *l2 = gen_new_label();
8692
8693 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8694 tcg_gen_neg_i32(ret, arg1);
8695 tcg_gen_br(l2);
8696 gen_set_label(l1);
8697 tcg_gen_mov_i32(ret, arg1);
8698 gen_set_label(l2);
8699 }
8700 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8701 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8702 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8703 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8704 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8705 {
8706 tcg_gen_addi_i32(ret, arg1, 0x8000);
8707 tcg_gen_ext16u_i32(ret, ret);
8708 }
8709 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8710 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8711 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8712
8713 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8714 static inline void gen_##name(DisasContext *ctx) \
8715 { \
8716 TCGv_i32 t0, t1; \
8717 if (unlikely(!ctx->spe_enabled)) { \
8718 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8719 return; \
8720 } \
8721 t0 = tcg_temp_new_i32(); \
8722 t1 = tcg_temp_new_i32(); \
8723 \
8724 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8725 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8726 tcg_op(t0, t0, t1); \
8727 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8728 \
8729 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8730 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8731 tcg_op(t0, t0, t1); \
8732 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8733 \
8734 tcg_temp_free_i32(t0); \
8735 tcg_temp_free_i32(t1); \
8736 }
8737
8738 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8739 {
8740 TCGLabel *l1 = gen_new_label();
8741 TCGLabel *l2 = gen_new_label();
8742 TCGv_i32 t0 = tcg_temp_local_new_i32();
8743
8744 /* No error here: 6 bits are used */
8745 tcg_gen_andi_i32(t0, arg2, 0x3F);
8746 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8747 tcg_gen_shr_i32(ret, arg1, t0);
8748 tcg_gen_br(l2);
8749 gen_set_label(l1);
8750 tcg_gen_movi_i32(ret, 0);
8751 gen_set_label(l2);
8752 tcg_temp_free_i32(t0);
8753 }
8754 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8755 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8756 {
8757 TCGLabel *l1 = gen_new_label();
8758 TCGLabel *l2 = gen_new_label();
8759 TCGv_i32 t0 = tcg_temp_local_new_i32();
8760
8761 /* No error here: 6 bits are used */
8762 tcg_gen_andi_i32(t0, arg2, 0x3F);
8763 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8764 tcg_gen_sar_i32(ret, arg1, t0);
8765 tcg_gen_br(l2);
8766 gen_set_label(l1);
8767 tcg_gen_movi_i32(ret, 0);
8768 gen_set_label(l2);
8769 tcg_temp_free_i32(t0);
8770 }
8771 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8772 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8773 {
8774 TCGLabel *l1 = gen_new_label();
8775 TCGLabel *l2 = gen_new_label();
8776 TCGv_i32 t0 = tcg_temp_local_new_i32();
8777
8778 /* No error here: 6 bits are used */
8779 tcg_gen_andi_i32(t0, arg2, 0x3F);
8780 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8781 tcg_gen_shl_i32(ret, arg1, t0);
8782 tcg_gen_br(l2);
8783 gen_set_label(l1);
8784 tcg_gen_movi_i32(ret, 0);
8785 gen_set_label(l2);
8786 tcg_temp_free_i32(t0);
8787 }
8788 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8789 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8790 {
8791 TCGv_i32 t0 = tcg_temp_new_i32();
8792 tcg_gen_andi_i32(t0, arg2, 0x1F);
8793 tcg_gen_rotl_i32(ret, arg1, t0);
8794 tcg_temp_free_i32(t0);
8795 }
8796 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8797 static inline void gen_evmergehi(DisasContext *ctx)
8798 {
8799 if (unlikely(!ctx->spe_enabled)) {
8800 gen_exception(ctx, POWERPC_EXCP_SPEU);
8801 return;
8802 }
8803 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8804 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8805 }
8806 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8807 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8808 {
8809 tcg_gen_sub_i32(ret, arg2, arg1);
8810 }
8811 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8812
8813 /* SPE arithmetic immediate */
8814 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8815 static inline void gen_##name(DisasContext *ctx) \
8816 { \
8817 TCGv_i32 t0; \
8818 if (unlikely(!ctx->spe_enabled)) { \
8819 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8820 return; \
8821 } \
8822 t0 = tcg_temp_new_i32(); \
8823 \
8824 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8825 tcg_op(t0, t0, rA(ctx->opcode)); \
8826 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8827 \
8828 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8829 tcg_op(t0, t0, rA(ctx->opcode)); \
8830 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8831 \
8832 tcg_temp_free_i32(t0); \
8833 }
8834 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8835 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8836
8837 /* SPE comparison */
8838 #define GEN_SPEOP_COMP(name, tcg_cond) \
8839 static inline void gen_##name(DisasContext *ctx) \
8840 { \
8841 if (unlikely(!ctx->spe_enabled)) { \
8842 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8843 return; \
8844 } \
8845 TCGLabel *l1 = gen_new_label(); \
8846 TCGLabel *l2 = gen_new_label(); \
8847 TCGLabel *l3 = gen_new_label(); \
8848 TCGLabel *l4 = gen_new_label(); \
8849 \
8850 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8851 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8852 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8853 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8854 \
8855 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8856 cpu_gpr[rB(ctx->opcode)], l1); \
8857 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8858 tcg_gen_br(l2); \
8859 gen_set_label(l1); \
8860 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8861 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8862 gen_set_label(l2); \
8863 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8864 cpu_gprh[rB(ctx->opcode)], l3); \
8865 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8866 ~(CRF_CH | CRF_CH_AND_CL)); \
8867 tcg_gen_br(l4); \
8868 gen_set_label(l3); \
8869 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8870 CRF_CH | CRF_CH_OR_CL); \
8871 gen_set_label(l4); \
8872 }
8873 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8874 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8875 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8876 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8877 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8878
8879 /* SPE misc */
8880 static inline void gen_brinc(DisasContext *ctx)
8881 {
8882 /* Note: brinc is usable even if SPE is disabled */
8883 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8884 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8885 }
8886 static inline void gen_evmergelo(DisasContext *ctx)
8887 {
8888 if (unlikely(!ctx->spe_enabled)) {
8889 gen_exception(ctx, POWERPC_EXCP_SPEU);
8890 return;
8891 }
8892 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8893 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8894 }
8895 static inline void gen_evmergehilo(DisasContext *ctx)
8896 {
8897 if (unlikely(!ctx->spe_enabled)) {
8898 gen_exception(ctx, POWERPC_EXCP_SPEU);
8899 return;
8900 }
8901 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8902 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8903 }
8904 static inline void gen_evmergelohi(DisasContext *ctx)
8905 {
8906 if (unlikely(!ctx->spe_enabled)) {
8907 gen_exception(ctx, POWERPC_EXCP_SPEU);
8908 return;
8909 }
8910 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8911 TCGv tmp = tcg_temp_new();
8912 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8913 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8914 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8915 tcg_temp_free(tmp);
8916 } else {
8917 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8918 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8919 }
8920 }
8921 static inline void gen_evsplati(DisasContext *ctx)
8922 {
8923 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8924
8925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8926 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8927 }
8928 static inline void gen_evsplatfi(DisasContext *ctx)
8929 {
8930 uint64_t imm = rA(ctx->opcode) << 27;
8931
8932 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8933 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8934 }
8935
8936 static inline void gen_evsel(DisasContext *ctx)
8937 {
8938 TCGLabel *l1 = gen_new_label();
8939 TCGLabel *l2 = gen_new_label();
8940 TCGLabel *l3 = gen_new_label();
8941 TCGLabel *l4 = gen_new_label();
8942 TCGv_i32 t0 = tcg_temp_local_new_i32();
8943
8944 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8945 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8946 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8947 tcg_gen_br(l2);
8948 gen_set_label(l1);
8949 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8950 gen_set_label(l2);
8951 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8952 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8953 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8954 tcg_gen_br(l4);
8955 gen_set_label(l3);
8956 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8957 gen_set_label(l4);
8958 tcg_temp_free_i32(t0);
8959 }
8960
8961 static void gen_evsel0(DisasContext *ctx)
8962 {
8963 gen_evsel(ctx);
8964 }
8965
8966 static void gen_evsel1(DisasContext *ctx)
8967 {
8968 gen_evsel(ctx);
8969 }
8970
8971 static void gen_evsel2(DisasContext *ctx)
8972 {
8973 gen_evsel(ctx);
8974 }
8975
8976 static void gen_evsel3(DisasContext *ctx)
8977 {
8978 gen_evsel(ctx);
8979 }
8980
8981 /* Multiply */
8982
8983 static inline void gen_evmwumi(DisasContext *ctx)
8984 {
8985 TCGv_i64 t0, t1;
8986
8987 if (unlikely(!ctx->spe_enabled)) {
8988 gen_exception(ctx, POWERPC_EXCP_SPEU);
8989 return;
8990 }
8991
8992 t0 = tcg_temp_new_i64();
8993 t1 = tcg_temp_new_i64();
8994
8995 /* t0 := rA; t1 := rB */
8996 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8997 tcg_gen_ext32u_i64(t0, t0);
8998 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8999 tcg_gen_ext32u_i64(t1, t1);
9000
9001 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9002
9003 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9004
9005 tcg_temp_free_i64(t0);
9006 tcg_temp_free_i64(t1);
9007 }
9008
9009 static inline void gen_evmwumia(DisasContext *ctx)
9010 {
9011 TCGv_i64 tmp;
9012
9013 if (unlikely(!ctx->spe_enabled)) {
9014 gen_exception(ctx, POWERPC_EXCP_SPEU);
9015 return;
9016 }
9017
9018 gen_evmwumi(ctx); /* rD := rA * rB */
9019
9020 tmp = tcg_temp_new_i64();
9021
9022 /* acc := rD */
9023 gen_load_gpr64(tmp, rD(ctx->opcode));
9024 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9025 tcg_temp_free_i64(tmp);
9026 }
9027
9028 static inline void gen_evmwumiaa(DisasContext *ctx)
9029 {
9030 TCGv_i64 acc;
9031 TCGv_i64 tmp;
9032
9033 if (unlikely(!ctx->spe_enabled)) {
9034 gen_exception(ctx, POWERPC_EXCP_SPEU);
9035 return;
9036 }
9037
9038 gen_evmwumi(ctx); /* rD := rA * rB */
9039
9040 acc = tcg_temp_new_i64();
9041 tmp = tcg_temp_new_i64();
9042
9043 /* tmp := rD */
9044 gen_load_gpr64(tmp, rD(ctx->opcode));
9045
9046 /* Load acc */
9047 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9048
9049 /* acc := tmp + acc */
9050 tcg_gen_add_i64(acc, acc, tmp);
9051
9052 /* Store acc */
9053 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9054
9055 /* rD := acc */
9056 gen_store_gpr64(rD(ctx->opcode), acc);
9057
9058 tcg_temp_free_i64(acc);
9059 tcg_temp_free_i64(tmp);
9060 }
9061
9062 static inline void gen_evmwsmi(DisasContext *ctx)
9063 {
9064 TCGv_i64 t0, t1;
9065
9066 if (unlikely(!ctx->spe_enabled)) {
9067 gen_exception(ctx, POWERPC_EXCP_SPEU);
9068 return;
9069 }
9070
9071 t0 = tcg_temp_new_i64();
9072 t1 = tcg_temp_new_i64();
9073
9074 /* t0 := rA; t1 := rB */
9075 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9076 tcg_gen_ext32s_i64(t0, t0);
9077 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9078 tcg_gen_ext32s_i64(t1, t1);
9079
9080 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9081
9082 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9083
9084 tcg_temp_free_i64(t0);
9085 tcg_temp_free_i64(t1);
9086 }
9087
9088 static inline void gen_evmwsmia(DisasContext *ctx)
9089 {
9090 TCGv_i64 tmp;
9091
9092 gen_evmwsmi(ctx); /* rD := rA * rB */
9093
9094 tmp = tcg_temp_new_i64();
9095
9096 /* acc := rD */
9097 gen_load_gpr64(tmp, rD(ctx->opcode));
9098 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9099
9100 tcg_temp_free_i64(tmp);
9101 }
9102
9103 static inline void gen_evmwsmiaa(DisasContext *ctx)
9104 {
9105 TCGv_i64 acc = tcg_temp_new_i64();
9106 TCGv_i64 tmp = tcg_temp_new_i64();
9107
9108 gen_evmwsmi(ctx); /* rD := rA * rB */
9109
9110 acc = tcg_temp_new_i64();
9111 tmp = tcg_temp_new_i64();
9112
9113 /* tmp := rD */
9114 gen_load_gpr64(tmp, rD(ctx->opcode));
9115
9116 /* Load acc */
9117 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9118
9119 /* acc := tmp + acc */
9120 tcg_gen_add_i64(acc, acc, tmp);
9121
9122 /* Store acc */
9123 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9124
9125 /* rD := acc */
9126 gen_store_gpr64(rD(ctx->opcode), acc);
9127
9128 tcg_temp_free_i64(acc);
9129 tcg_temp_free_i64(tmp);
9130 }
9131
9132 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9133 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9134 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9135 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9136 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9137 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9138 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9139 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9140 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9141 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9142 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9143 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9144 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9145 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9146 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9147 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9148 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9149 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9150 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9151 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9152 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9153 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9154 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9155 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9156 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9157 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9158 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9159 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9160 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9161
9162 /* SPE load and stores */
9163 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9164 {
9165 target_ulong uimm = rB(ctx->opcode);
9166
9167 if (rA(ctx->opcode) == 0) {
9168 tcg_gen_movi_tl(EA, uimm << sh);
9169 } else {
9170 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9171 if (NARROW_MODE(ctx)) {
9172 tcg_gen_ext32u_tl(EA, EA);
9173 }
9174 }
9175 }
9176
9177 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9178 {
9179 TCGv_i64 t0 = tcg_temp_new_i64();
9180 gen_qemu_ld64(ctx, t0, addr);
9181 gen_store_gpr64(rD(ctx->opcode), t0);
9182 tcg_temp_free_i64(t0);
9183 }
9184
9185 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9186 {
9187 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9188 gen_addr_add(ctx, addr, addr, 4);
9189 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9190 }
9191
9192 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9193 {
9194 TCGv t0 = tcg_temp_new();
9195 gen_qemu_ld16u(ctx, t0, addr);
9196 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9197 gen_addr_add(ctx, addr, addr, 2);
9198 gen_qemu_ld16u(ctx, t0, addr);
9199 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9200 gen_addr_add(ctx, addr, addr, 2);
9201 gen_qemu_ld16u(ctx, t0, addr);
9202 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9203 gen_addr_add(ctx, addr, addr, 2);
9204 gen_qemu_ld16u(ctx, t0, addr);
9205 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9206 tcg_temp_free(t0);
9207 }
9208
9209 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9210 {
9211 TCGv t0 = tcg_temp_new();
9212 gen_qemu_ld16u(ctx, t0, addr);
9213 tcg_gen_shli_tl(t0, t0, 16);
9214 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9215 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9216 tcg_temp_free(t0);
9217 }
9218
9219 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9220 {
9221 TCGv t0 = tcg_temp_new();
9222 gen_qemu_ld16u(ctx, t0, addr);
9223 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9224 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9225 tcg_temp_free(t0);
9226 }
9227
9228 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9229 {
9230 TCGv t0 = tcg_temp_new();
9231 gen_qemu_ld16s(ctx, t0, addr);
9232 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9233 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9234 tcg_temp_free(t0);
9235 }
9236
9237 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9238 {
9239 TCGv t0 = tcg_temp_new();
9240 gen_qemu_ld16u(ctx, t0, addr);
9241 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9242 gen_addr_add(ctx, addr, addr, 2);
9243 gen_qemu_ld16u(ctx, t0, addr);
9244 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9245 tcg_temp_free(t0);
9246 }
9247
9248 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9249 {
9250 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9251 gen_addr_add(ctx, addr, addr, 2);
9252 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9253 }
9254
9255 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9256 {
9257 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9258 gen_addr_add(ctx, addr, addr, 2);
9259 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9260 }
9261
9262 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9263 {
9264 TCGv t0 = tcg_temp_new();
9265 gen_qemu_ld32u(ctx, t0, addr);
9266 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9267 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9268 tcg_temp_free(t0);
9269 }
9270
9271 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9272 {
9273 TCGv t0 = tcg_temp_new();
9274 gen_qemu_ld16u(ctx, t0, addr);
9275 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9276 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9277 gen_addr_add(ctx, addr, addr, 2);
9278 gen_qemu_ld16u(ctx, t0, addr);
9279 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9280 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9281 tcg_temp_free(t0);
9282 }
9283
9284 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9285 {
9286 TCGv_i64 t0 = tcg_temp_new_i64();
9287 gen_load_gpr64(t0, rS(ctx->opcode));
9288 gen_qemu_st64(ctx, t0, addr);
9289 tcg_temp_free_i64(t0);
9290 }
9291
9292 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9293 {
9294 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9295 gen_addr_add(ctx, addr, addr, 4);
9296 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9297 }
9298
9299 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9300 {
9301 TCGv t0 = tcg_temp_new();
9302 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9303 gen_qemu_st16(ctx, t0, addr);
9304 gen_addr_add(ctx, addr, addr, 2);
9305 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9306 gen_addr_add(ctx, addr, addr, 2);
9307 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9308 gen_qemu_st16(ctx, t0, addr);
9309 tcg_temp_free(t0);
9310 gen_addr_add(ctx, addr, addr, 2);
9311 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9312 }
9313
9314 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9315 {
9316 TCGv t0 = tcg_temp_new();
9317 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9318 gen_qemu_st16(ctx, t0, addr);
9319 gen_addr_add(ctx, addr, addr, 2);
9320 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9321 gen_qemu_st16(ctx, t0, addr);
9322 tcg_temp_free(t0);
9323 }
9324
9325 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9326 {
9327 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9328 gen_addr_add(ctx, addr, addr, 2);
9329 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9330 }
9331
9332 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9333 {
9334 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9335 }
9336
9337 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9338 {
9339 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9340 }
9341
9342 #define GEN_SPEOP_LDST(name, opc2, sh) \
9343 static void glue(gen_, name)(DisasContext *ctx) \
9344 { \
9345 TCGv t0; \
9346 if (unlikely(!ctx->spe_enabled)) { \
9347 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9348 return; \
9349 } \
9350 gen_set_access_type(ctx, ACCESS_INT); \
9351 t0 = tcg_temp_new(); \
9352 if (Rc(ctx->opcode)) { \
9353 gen_addr_spe_imm_index(ctx, t0, sh); \
9354 } else { \
9355 gen_addr_reg_index(ctx, t0); \
9356 } \
9357 gen_op_##name(ctx, t0); \
9358 tcg_temp_free(t0); \
9359 }
9360
9361 GEN_SPEOP_LDST(evldd, 0x00, 3);
9362 GEN_SPEOP_LDST(evldw, 0x01, 3);
9363 GEN_SPEOP_LDST(evldh, 0x02, 3);
9364 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9365 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9366 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9367 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9368 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9369 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9370 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9371 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9372
9373 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9374 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9375 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9376 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9377 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9378 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9379 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9380
9381 /* Multiply and add - TODO */
9382 #if 0
9383 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9384 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9385 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9386 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9387 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9388 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9389 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9390 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9391 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9392 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9393 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9394 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9395
9396 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9397 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9398 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9399 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9400 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9402 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9403 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9404 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9405 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9406 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9408
9409 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9410 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9411 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9412 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9413 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9414
9415 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9416 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9417 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9418 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9419 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9420 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9421 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9422 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9423 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9424 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9425 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9426 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9427
9428 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9429 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9430 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9431 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9432
9433 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9434 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9435 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9436 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9437 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9438 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9439 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9440 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9441 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9442 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9443 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9444 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9445
9446 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9447 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9448 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9449 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9450 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9451 #endif
9452
9453 /*** SPE floating-point extension ***/
9454 #define GEN_SPEFPUOP_CONV_32_32(name) \
9455 static inline void gen_##name(DisasContext *ctx) \
9456 { \
9457 TCGv_i32 t0 = tcg_temp_new_i32(); \
9458 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9459 gen_helper_##name(t0, cpu_env, t0); \
9460 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9461 tcg_temp_free_i32(t0); \
9462 }
9463 #define GEN_SPEFPUOP_CONV_32_64(name) \
9464 static inline void gen_##name(DisasContext *ctx) \
9465 { \
9466 TCGv_i64 t0 = tcg_temp_new_i64(); \
9467 TCGv_i32 t1 = tcg_temp_new_i32(); \
9468 gen_load_gpr64(t0, rB(ctx->opcode)); \
9469 gen_helper_##name(t1, cpu_env, t0); \
9470 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9471 tcg_temp_free_i64(t0); \
9472 tcg_temp_free_i32(t1); \
9473 }
9474 #define GEN_SPEFPUOP_CONV_64_32(name) \
9475 static inline void gen_##name(DisasContext *ctx) \
9476 { \
9477 TCGv_i64 t0 = tcg_temp_new_i64(); \
9478 TCGv_i32 t1 = tcg_temp_new_i32(); \
9479 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9480 gen_helper_##name(t0, cpu_env, t1); \
9481 gen_store_gpr64(rD(ctx->opcode), t0); \
9482 tcg_temp_free_i64(t0); \
9483 tcg_temp_free_i32(t1); \
9484 }
9485 #define GEN_SPEFPUOP_CONV_64_64(name) \
9486 static inline void gen_##name(DisasContext *ctx) \
9487 { \
9488 TCGv_i64 t0 = tcg_temp_new_i64(); \
9489 gen_load_gpr64(t0, rB(ctx->opcode)); \
9490 gen_helper_##name(t0, cpu_env, t0); \
9491 gen_store_gpr64(rD(ctx->opcode), t0); \
9492 tcg_temp_free_i64(t0); \
9493 }
9494 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9495 static inline void gen_##name(DisasContext *ctx) \
9496 { \
9497 TCGv_i32 t0, t1; \
9498 if (unlikely(!ctx->spe_enabled)) { \
9499 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9500 return; \
9501 } \
9502 t0 = tcg_temp_new_i32(); \
9503 t1 = tcg_temp_new_i32(); \
9504 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9505 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9506 gen_helper_##name(t0, cpu_env, t0, t1); \
9507 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9508 \
9509 tcg_temp_free_i32(t0); \
9510 tcg_temp_free_i32(t1); \
9511 }
9512 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9513 static inline void gen_##name(DisasContext *ctx) \
9514 { \
9515 TCGv_i64 t0, t1; \
9516 if (unlikely(!ctx->spe_enabled)) { \
9517 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9518 return; \
9519 } \
9520 t0 = tcg_temp_new_i64(); \
9521 t1 = tcg_temp_new_i64(); \
9522 gen_load_gpr64(t0, rA(ctx->opcode)); \
9523 gen_load_gpr64(t1, rB(ctx->opcode)); \
9524 gen_helper_##name(t0, cpu_env, t0, t1); \
9525 gen_store_gpr64(rD(ctx->opcode), t0); \
9526 tcg_temp_free_i64(t0); \
9527 tcg_temp_free_i64(t1); \
9528 }
9529 #define GEN_SPEFPUOP_COMP_32(name) \
9530 static inline void gen_##name(DisasContext *ctx) \
9531 { \
9532 TCGv_i32 t0, t1; \
9533 if (unlikely(!ctx->spe_enabled)) { \
9534 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9535 return; \
9536 } \
9537 t0 = tcg_temp_new_i32(); \
9538 t1 = tcg_temp_new_i32(); \
9539 \
9540 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9541 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9542 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9543 \
9544 tcg_temp_free_i32(t0); \
9545 tcg_temp_free_i32(t1); \
9546 }
9547 #define GEN_SPEFPUOP_COMP_64(name) \
9548 static inline void gen_##name(DisasContext *ctx) \
9549 { \
9550 TCGv_i64 t0, t1; \
9551 if (unlikely(!ctx->spe_enabled)) { \
9552 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9553 return; \
9554 } \
9555 t0 = tcg_temp_new_i64(); \
9556 t1 = tcg_temp_new_i64(); \
9557 gen_load_gpr64(t0, rA(ctx->opcode)); \
9558 gen_load_gpr64(t1, rB(ctx->opcode)); \
9559 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9560 tcg_temp_free_i64(t0); \
9561 tcg_temp_free_i64(t1); \
9562 }
9563
9564 /* Single precision floating-point vectors operations */
9565 /* Arithmetic */
9566 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9567 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9568 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9569 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9570 static inline void gen_evfsabs(DisasContext *ctx)
9571 {
9572 if (unlikely(!ctx->spe_enabled)) {
9573 gen_exception(ctx, POWERPC_EXCP_SPEU);
9574 return;
9575 }
9576 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9577 ~0x80000000);
9578 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9579 ~0x80000000);
9580 }
9581 static inline void gen_evfsnabs(DisasContext *ctx)
9582 {
9583 if (unlikely(!ctx->spe_enabled)) {
9584 gen_exception(ctx, POWERPC_EXCP_SPEU);
9585 return;
9586 }
9587 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9588 0x80000000);
9589 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9590 0x80000000);
9591 }
9592 static inline void gen_evfsneg(DisasContext *ctx)
9593 {
9594 if (unlikely(!ctx->spe_enabled)) {
9595 gen_exception(ctx, POWERPC_EXCP_SPEU);
9596 return;
9597 }
9598 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9599 0x80000000);
9600 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9601 0x80000000);
9602 }
9603
9604 /* Conversion */
9605 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9606 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9607 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9608 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9609 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9610 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9611 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9612 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9613 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9614 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9615
9616 /* Comparison */
9617 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9618 GEN_SPEFPUOP_COMP_64(evfscmplt);
9619 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9620 GEN_SPEFPUOP_COMP_64(evfststgt);
9621 GEN_SPEFPUOP_COMP_64(evfststlt);
9622 GEN_SPEFPUOP_COMP_64(evfststeq);
9623
9624 /* Opcodes definitions */
9625 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9626 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9627 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9628 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9629 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9630 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9631 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9632 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9633 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9634 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9635 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9636 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9637 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9638 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9639
9640 /* Single precision floating-point operations */
9641 /* Arithmetic */
9642 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9643 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9644 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9645 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9646 static inline void gen_efsabs(DisasContext *ctx)
9647 {
9648 if (unlikely(!ctx->spe_enabled)) {
9649 gen_exception(ctx, POWERPC_EXCP_SPEU);
9650 return;
9651 }
9652 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9653 }
9654 static inline void gen_efsnabs(DisasContext *ctx)
9655 {
9656 if (unlikely(!ctx->spe_enabled)) {
9657 gen_exception(ctx, POWERPC_EXCP_SPEU);
9658 return;
9659 }
9660 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9661 }
9662 static inline void gen_efsneg(DisasContext *ctx)
9663 {
9664 if (unlikely(!ctx->spe_enabled)) {
9665 gen_exception(ctx, POWERPC_EXCP_SPEU);
9666 return;
9667 }
9668 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9669 }
9670
9671 /* Conversion */
9672 GEN_SPEFPUOP_CONV_32_32(efscfui);
9673 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9674 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9675 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9676 GEN_SPEFPUOP_CONV_32_32(efsctui);
9677 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9678 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9679 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9680 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9681 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9682 GEN_SPEFPUOP_CONV_32_64(efscfd);
9683
9684 /* Comparison */
9685 GEN_SPEFPUOP_COMP_32(efscmpgt);
9686 GEN_SPEFPUOP_COMP_32(efscmplt);
9687 GEN_SPEFPUOP_COMP_32(efscmpeq);
9688 GEN_SPEFPUOP_COMP_32(efststgt);
9689 GEN_SPEFPUOP_COMP_32(efststlt);
9690 GEN_SPEFPUOP_COMP_32(efststeq);
9691
9692 /* Opcodes definitions */
9693 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9694 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9695 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9696 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9697 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9698 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9699 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9700 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9701 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9702 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9703 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9704 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9705 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9706 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9707
9708 /* Double precision floating-point operations */
9709 /* Arithmetic */
9710 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9711 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9712 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9713 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9714 static inline void gen_efdabs(DisasContext *ctx)
9715 {
9716 if (unlikely(!ctx->spe_enabled)) {
9717 gen_exception(ctx, POWERPC_EXCP_SPEU);
9718 return;
9719 }
9720 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9721 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9722 ~0x80000000);
9723 }
9724 static inline void gen_efdnabs(DisasContext *ctx)
9725 {
9726 if (unlikely(!ctx->spe_enabled)) {
9727 gen_exception(ctx, POWERPC_EXCP_SPEU);
9728 return;
9729 }
9730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9731 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9732 0x80000000);
9733 }
9734 static inline void gen_efdneg(DisasContext *ctx)
9735 {
9736 if (unlikely(!ctx->spe_enabled)) {
9737 gen_exception(ctx, POWERPC_EXCP_SPEU);
9738 return;
9739 }
9740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9741 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9742 0x80000000);
9743 }
9744
9745 /* Conversion */
9746 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9747 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9748 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9749 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9750 GEN_SPEFPUOP_CONV_32_64(efdctui);
9751 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9752 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9753 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9754 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9755 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9756 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9757 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9758 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9759 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9760 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9761
9762 /* Comparison */
9763 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9764 GEN_SPEFPUOP_COMP_64(efdcmplt);
9765 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9766 GEN_SPEFPUOP_COMP_64(efdtstgt);
9767 GEN_SPEFPUOP_COMP_64(efdtstlt);
9768 GEN_SPEFPUOP_COMP_64(efdtsteq);
9769
9770 /* Opcodes definitions */
9771 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9772 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9773 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9774 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9775 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9776 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9777 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9778 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9779 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9780 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9781 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9782 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9783 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9784 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9785 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9786 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9787
9788 static void gen_tbegin(DisasContext *ctx)
9789 {
9790 if (unlikely(!ctx->tm_enabled)) {
9791 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9792 return;
9793 }
9794 gen_helper_tbegin(cpu_env);
9795 }
9796
9797 #define GEN_TM_NOOP(name) \
9798 static inline void gen_##name(DisasContext *ctx) \
9799 { \
9800 if (unlikely(!ctx->tm_enabled)) { \
9801 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9802 return; \
9803 } \
9804 /* Because tbegin always fails in QEMU, these user \
9805 * space instructions all have a simple implementation: \
9806 * \
9807 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9808 * = 0b0 || 0b00 || 0b0 \
9809 */ \
9810 tcg_gen_movi_i32(cpu_crf[0], 0); \
9811 }
9812
9813 GEN_TM_NOOP(tend);
9814 GEN_TM_NOOP(tabort);
9815 GEN_TM_NOOP(tabortwc);
9816 GEN_TM_NOOP(tabortwci);
9817 GEN_TM_NOOP(tabortdc);
9818 GEN_TM_NOOP(tabortdci);
9819 GEN_TM_NOOP(tsr);
9820
9821 static void gen_tcheck(DisasContext *ctx)
9822 {
9823 if (unlikely(!ctx->tm_enabled)) {
9824 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9825 return;
9826 }
9827 /* Because tbegin always fails, the tcheck implementation
9828 * is simple:
9829 *
9830 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9831 * = 0b1 || 0b00 || 0b0
9832 */
9833 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9834 }
9835
9836 #if defined(CONFIG_USER_ONLY)
9837 #define GEN_TM_PRIV_NOOP(name) \
9838 static inline void gen_##name(DisasContext *ctx) \
9839 { \
9840 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9841 }
9842
9843 #else
9844
9845 #define GEN_TM_PRIV_NOOP(name) \
9846 static inline void gen_##name(DisasContext *ctx) \
9847 { \
9848 CHK_SV; \
9849 if (unlikely(!ctx->tm_enabled)) { \
9850 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9851 return; \
9852 } \
9853 /* Because tbegin always fails, the implementation is \
9854 * simple: \
9855 * \
9856 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9857 * = 0b0 || 0b00 | 0b0 \
9858 */ \
9859 tcg_gen_movi_i32(cpu_crf[0], 0); \
9860 }
9861
9862 #endif
9863
9864 GEN_TM_PRIV_NOOP(treclaim);
9865 GEN_TM_PRIV_NOOP(trechkpt);
9866
9867 static opcode_t opcodes[] = {
9868 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9869 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9870 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9871 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9872 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9873 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9874 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9875 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9877 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9878 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9879 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9880 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9881 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9882 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9883 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9884 #if defined(TARGET_PPC64)
9885 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9886 #endif
9887 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9888 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9889 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9890 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9891 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9892 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9893 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9894 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9895 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9896 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9897 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9898 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9899 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9900 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9901 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9902 #if defined(TARGET_PPC64)
9903 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9904 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9905 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9906 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9907 #endif
9908 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9909 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9910 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9911 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9912 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9913 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9914 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9915 #if defined(TARGET_PPC64)
9916 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9917 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9918 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9919 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9920 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9921 #endif
9922 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9923 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9924 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9925 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9926 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9927 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9928 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9929 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9930 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9931 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9932 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9933 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9934 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9935 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9936 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9937 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9938 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9939 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9940 #if defined(TARGET_PPC64)
9941 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9942 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9943 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9944 #endif
9945 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9946 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9947 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9948 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9949 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9950 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9951 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9952 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9953 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9954 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9955 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9956 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9957 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9958 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9959 #if defined(TARGET_PPC64)
9960 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9961 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9962 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9963 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9964 #endif
9965 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9966 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9967 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9968 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9969 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9970 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9971 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9972 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9973 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9974 #if defined(TARGET_PPC64)
9975 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9976 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
9977 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
9978 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
9979 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
9980 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9981 #endif
9982 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9983 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9984 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9985 #if defined(TARGET_PPC64)
9986 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9987 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9988 #endif
9989 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9990 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9991 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9992 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9993 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9994 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9995 #if defined(TARGET_PPC64)
9996 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9997 #endif
9998 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
9999 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
10000 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
10001 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
10002 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
10003 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
10004 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
10005 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
10006 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
10007 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
10008 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
10009 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
10010 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
10011 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
10012 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
10013 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
10014 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
10015 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
10016 #if defined(TARGET_PPC64)
10017 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
10018 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10019 PPC_SEGMENT_64B),
10020 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10021 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10022 PPC_SEGMENT_64B),
10023 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10024 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10025 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10026 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
10027 #endif
10028 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10029 /* XXX Those instructions will need to be handled differently for
10030 * different ISA versions */
10031 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10032 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
10033 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10034 #if defined(TARGET_PPC64)
10035 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
10036 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10037 #endif
10038 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10039 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10040 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10041 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10042 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10043 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10044 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10045 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10046 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10047 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10048 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10049 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10050 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10051 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10052 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10053 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10054 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10055 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10056 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10057 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10058 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10059 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10060 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10061 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10062 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10063 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10064 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10065 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10066 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10067 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10068 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10069 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10070 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10071 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10072 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10073 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10074 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10075 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10076 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10077 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10078 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10079 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10080 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10081 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10082 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10083 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10084 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10085 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10086 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10087 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10088 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10089 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10090 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10091 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10092 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10093 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10094 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10095 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10096 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10097 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10098 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10099 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10100 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10101 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10102 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10103 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10104 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10105 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10106 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10107 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10108 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10109 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10110 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10111 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10112 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10113 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10114 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10115 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10116 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10117 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10118 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10119 PPC_NONE, PPC2_BOOKE206),
10120 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10121 PPC_NONE, PPC2_BOOKE206),
10122 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10123 PPC_NONE, PPC2_BOOKE206),
10124 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10125 PPC_NONE, PPC2_BOOKE206),
10126 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10127 PPC_NONE, PPC2_BOOKE206),
10128 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10129 PPC_NONE, PPC2_PRCNTL),
10130 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10131 PPC_NONE, PPC2_PRCNTL),
10132 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10133 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10134 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10135 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10136 PPC_BOOKE, PPC2_BOOKE206),
10137 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10138 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10139 PPC_BOOKE, PPC2_BOOKE206),
10140 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10141 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10142 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10143 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10144 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10145 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10146 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10147 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10148 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10149
10150 #undef GEN_INT_ARITH_ADD
10151 #undef GEN_INT_ARITH_ADD_CONST
10152 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10153 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10154 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10155 add_ca, compute_ca, compute_ov) \
10156 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10157 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10158 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10159 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10160 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10161 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10162 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10163 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10164 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10165 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10166 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10167
10168 #undef GEN_INT_ARITH_DIVW
10169 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10170 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10171 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10172 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10173 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10174 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10175 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10176 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10177 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10178 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10179
10180 #if defined(TARGET_PPC64)
10181 #undef GEN_INT_ARITH_DIVD
10182 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10183 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10184 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10185 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10186 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10187 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10188
10189 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10190 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10191 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10192 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10193
10194 #undef GEN_INT_ARITH_MUL_HELPER
10195 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10196 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10197 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10198 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10199 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10200 #endif
10201
10202 #undef GEN_INT_ARITH_SUBF
10203 #undef GEN_INT_ARITH_SUBF_CONST
10204 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10205 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10206 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10207 add_ca, compute_ca, compute_ov) \
10208 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10209 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10210 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10211 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10212 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10213 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10214 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10215 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10216 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10217 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10218 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10219
10220 #undef GEN_LOGICAL1
10221 #undef GEN_LOGICAL2
10222 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10223 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10224 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10225 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10226 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10227 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10228 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10229 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10230 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10231 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10232 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10233 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10234 #if defined(TARGET_PPC64)
10235 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10236 #endif
10237
10238 #if defined(TARGET_PPC64)
10239 #undef GEN_PPC64_R2
10240 #undef GEN_PPC64_R4
10241 #define GEN_PPC64_R2(name, opc1, opc2) \
10242 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10243 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10244 PPC_64B)
10245 #define GEN_PPC64_R4(name, opc1, opc2) \
10246 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10247 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10248 PPC_64B), \
10249 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10250 PPC_64B), \
10251 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10252 PPC_64B)
10253 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10254 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10255 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10256 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10257 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10258 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10259 #endif
10260
10261 #undef _GEN_FLOAT_ACB
10262 #undef GEN_FLOAT_ACB
10263 #undef _GEN_FLOAT_AB
10264 #undef GEN_FLOAT_AB
10265 #undef _GEN_FLOAT_AC
10266 #undef GEN_FLOAT_AC
10267 #undef GEN_FLOAT_B
10268 #undef GEN_FLOAT_BS
10269 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10270 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10271 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10272 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10273 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10274 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10275 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10276 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10277 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10278 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10279 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10280 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10281 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10282 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10283 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10284 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10285 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10286 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10287 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10288
10289 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10290 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10291 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10292 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10293 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10294 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10295 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10296 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10297 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10298 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10299 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10300 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10301 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10302 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10303 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10304 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10305 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10306 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10307 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10308 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10309 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10310 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10311 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10312 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10313 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10314 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10315 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10316 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10317 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10318 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10319 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10320
10321 #undef GEN_LD
10322 #undef GEN_LDU
10323 #undef GEN_LDUX
10324 #undef GEN_LDX_E
10325 #undef GEN_LDS
10326 #define GEN_LD(name, ldop, opc, type) \
10327 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10328 #define GEN_LDU(name, ldop, opc, type) \
10329 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10330 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10331 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10332 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
10333 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10334 #define GEN_LDS(name, ldop, op, type) \
10335 GEN_LD(name, ldop, op | 0x20, type) \
10336 GEN_LDU(name, ldop, op | 0x21, type) \
10337 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10338 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10339
10340 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10341 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10342 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10343 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10344 #if defined(TARGET_PPC64)
10345 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10346 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10347 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10348 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10349 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
10350
10351 /* HV/P7 and later only */
10352 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
10353 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
10354 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
10355 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
10356 #endif
10357 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10358 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10359
10360 #undef GEN_ST
10361 #undef GEN_STU
10362 #undef GEN_STUX
10363 #undef GEN_STX_E
10364 #undef GEN_STS
10365 #define GEN_ST(name, stop, opc, type) \
10366 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10367 #define GEN_STU(name, stop, opc, type) \
10368 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10369 #define GEN_STUX(name, stop, opc2, opc3, type) \
10370 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10371 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
10372 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10373 #define GEN_STS(name, stop, op, type) \
10374 GEN_ST(name, stop, op | 0x20, type) \
10375 GEN_STU(name, stop, op | 0x21, type) \
10376 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10377 GEN_STX(name, stop, 0x17, op | 0x00, type)
10378
10379 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10380 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10381 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10382 #if defined(TARGET_PPC64)
10383 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10384 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10385 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
10386 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
10387 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
10388 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
10389 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
10390 #endif
10391 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10392 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10393
10394 #undef GEN_LDF
10395 #undef GEN_LDUF
10396 #undef GEN_LDUXF
10397 #undef GEN_LDXF
10398 #undef GEN_LDFS
10399 #define GEN_LDF(name, ldop, opc, type) \
10400 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10401 #define GEN_LDUF(name, ldop, opc, type) \
10402 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10403 #define GEN_LDUXF(name, ldop, opc, type) \
10404 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10405 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10406 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10407 #define GEN_LDFS(name, ldop, op, type) \
10408 GEN_LDF(name, ldop, op | 0x20, type) \
10409 GEN_LDUF(name, ldop, op | 0x21, type) \
10410 GEN_LDUXF(name, ldop, op | 0x01, type) \
10411 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10412
10413 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10414 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10415 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10416 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10417 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10418 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10419
10420 #undef GEN_STF
10421 #undef GEN_STUF
10422 #undef GEN_STUXF
10423 #undef GEN_STXF
10424 #undef GEN_STFS
10425 #define GEN_STF(name, stop, opc, type) \
10426 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10427 #define GEN_STUF(name, stop, opc, type) \
10428 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10429 #define GEN_STUXF(name, stop, opc, type) \
10430 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10431 #define GEN_STXF(name, stop, opc2, opc3, type) \
10432 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10433 #define GEN_STFS(name, stop, op, type) \
10434 GEN_STF(name, stop, op | 0x20, type) \
10435 GEN_STUF(name, stop, op | 0x21, type) \
10436 GEN_STUXF(name, stop, op | 0x01, type) \
10437 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10438
10439 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10440 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10441 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10442 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10443 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10444
10445 #undef GEN_CRLOGIC
10446 #define GEN_CRLOGIC(name, tcg_op, opc) \
10447 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10448 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10449 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10450 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10451 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10452 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10453 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10454 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10455 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10456
10457 #undef GEN_MAC_HANDLER
10458 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10459 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10460 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10461 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10462 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10463 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10464 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10465 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10466 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10467 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10468 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10469 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10470 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10471 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10472 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10473 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10474 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10475 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10476 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10477 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10478 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10479 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10480 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10481 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10482 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10483 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10484 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10485 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10486 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10487 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10488 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10489 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10490 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10491 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10492 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10493 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10494 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10495 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10496 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10497 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10498 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10499 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10500 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10501 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10502
10503 #undef GEN_VR_LDX
10504 #undef GEN_VR_STX
10505 #undef GEN_VR_LVE
10506 #undef GEN_VR_STVE
10507 #define GEN_VR_LDX(name, opc2, opc3) \
10508 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10509 #define GEN_VR_STX(name, opc2, opc3) \
10510 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10511 #define GEN_VR_LVE(name, opc2, opc3) \
10512 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10513 #define GEN_VR_STVE(name, opc2, opc3) \
10514 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10515 GEN_VR_LDX(lvx, 0x07, 0x03),
10516 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10517 GEN_VR_LVE(bx, 0x07, 0x00),
10518 GEN_VR_LVE(hx, 0x07, 0x01),
10519 GEN_VR_LVE(wx, 0x07, 0x02),
10520 GEN_VR_STX(svx, 0x07, 0x07),
10521 GEN_VR_STX(svxl, 0x07, 0x0F),
10522 GEN_VR_STVE(bx, 0x07, 0x04),
10523 GEN_VR_STVE(hx, 0x07, 0x05),
10524 GEN_VR_STVE(wx, 0x07, 0x06),
10525
10526 #undef GEN_VX_LOGICAL
10527 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10528 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10529
10530 #undef GEN_VX_LOGICAL_207
10531 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10532 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10533
10534 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10535 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10536 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10537 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10538 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10539 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10540 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10541 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10542
10543 #undef GEN_VXFORM
10544 #define GEN_VXFORM(name, opc2, opc3) \
10545 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10546
10547 #undef GEN_VXFORM_207
10548 #define GEN_VXFORM_207(name, opc2, opc3) \
10549 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10550
10551 #undef GEN_VXFORM_DUAL
10552 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10553 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10554
10555 #undef GEN_VXRFORM_DUAL
10556 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10557 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10558 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10559
10560 GEN_VXFORM(vaddubm, 0, 0),
10561 GEN_VXFORM(vadduhm, 0, 1),
10562 GEN_VXFORM(vadduwm, 0, 2),
10563 GEN_VXFORM_207(vaddudm, 0, 3),
10564 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10565 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10566 GEN_VXFORM(vsubuwm, 0, 18),
10567 GEN_VXFORM_207(vsubudm, 0, 19),
10568 GEN_VXFORM(vmaxub, 1, 0),
10569 GEN_VXFORM(vmaxuh, 1, 1),
10570 GEN_VXFORM(vmaxuw, 1, 2),
10571 GEN_VXFORM_207(vmaxud, 1, 3),
10572 GEN_VXFORM(vmaxsb, 1, 4),
10573 GEN_VXFORM(vmaxsh, 1, 5),
10574 GEN_VXFORM(vmaxsw, 1, 6),
10575 GEN_VXFORM_207(vmaxsd, 1, 7),
10576 GEN_VXFORM(vminub, 1, 8),
10577 GEN_VXFORM(vminuh, 1, 9),
10578 GEN_VXFORM(vminuw, 1, 10),
10579 GEN_VXFORM_207(vminud, 1, 11),
10580 GEN_VXFORM(vminsb, 1, 12),
10581 GEN_VXFORM(vminsh, 1, 13),
10582 GEN_VXFORM(vminsw, 1, 14),
10583 GEN_VXFORM_207(vminsd, 1, 15),
10584 GEN_VXFORM(vavgub, 1, 16),
10585 GEN_VXFORM(vavguh, 1, 17),
10586 GEN_VXFORM(vavguw, 1, 18),
10587 GEN_VXFORM(vavgsb, 1, 20),
10588 GEN_VXFORM(vavgsh, 1, 21),
10589 GEN_VXFORM(vavgsw, 1, 22),
10590 GEN_VXFORM(vmrghb, 6, 0),
10591 GEN_VXFORM(vmrghh, 6, 1),
10592 GEN_VXFORM(vmrghw, 6, 2),
10593 GEN_VXFORM(vmrglb, 6, 4),
10594 GEN_VXFORM(vmrglh, 6, 5),
10595 GEN_VXFORM(vmrglw, 6, 6),
10596 GEN_VXFORM_207(vmrgew, 6, 30),
10597 GEN_VXFORM_207(vmrgow, 6, 26),
10598 GEN_VXFORM(vmuloub, 4, 0),
10599 GEN_VXFORM(vmulouh, 4, 1),
10600 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10601 GEN_VXFORM(vmulosb, 4, 4),
10602 GEN_VXFORM(vmulosh, 4, 5),
10603 GEN_VXFORM_207(vmulosw, 4, 6),
10604 GEN_VXFORM(vmuleub, 4, 8),
10605 GEN_VXFORM(vmuleuh, 4, 9),
10606 GEN_VXFORM_207(vmuleuw, 4, 10),
10607 GEN_VXFORM(vmulesb, 4, 12),
10608 GEN_VXFORM(vmulesh, 4, 13),
10609 GEN_VXFORM_207(vmulesw, 4, 14),
10610 GEN_VXFORM(vslb, 2, 4),
10611 GEN_VXFORM(vslh, 2, 5),
10612 GEN_VXFORM(vslw, 2, 6),
10613 GEN_VXFORM_207(vsld, 2, 23),
10614 GEN_VXFORM(vsrb, 2, 8),
10615 GEN_VXFORM(vsrh, 2, 9),
10616 GEN_VXFORM(vsrw, 2, 10),
10617 GEN_VXFORM_207(vsrd, 2, 27),
10618 GEN_VXFORM(vsrab, 2, 12),
10619 GEN_VXFORM(vsrah, 2, 13),
10620 GEN_VXFORM(vsraw, 2, 14),
10621 GEN_VXFORM_207(vsrad, 2, 15),
10622 GEN_VXFORM(vslo, 6, 16),
10623 GEN_VXFORM(vsro, 6, 17),
10624 GEN_VXFORM(vaddcuw, 0, 6),
10625 GEN_VXFORM(vsubcuw, 0, 22),
10626 GEN_VXFORM(vaddubs, 0, 8),
10627 GEN_VXFORM(vadduhs, 0, 9),
10628 GEN_VXFORM(vadduws, 0, 10),
10629 GEN_VXFORM(vaddsbs, 0, 12),
10630 GEN_VXFORM(vaddshs, 0, 13),
10631 GEN_VXFORM(vaddsws, 0, 14),
10632 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10633 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10634 GEN_VXFORM(vsubuws, 0, 26),
10635 GEN_VXFORM(vsubsbs, 0, 28),
10636 GEN_VXFORM(vsubshs, 0, 29),
10637 GEN_VXFORM(vsubsws, 0, 30),
10638 GEN_VXFORM_207(vadduqm, 0, 4),
10639 GEN_VXFORM_207(vaddcuq, 0, 5),
10640 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10641 GEN_VXFORM_207(vsubuqm, 0, 20),
10642 GEN_VXFORM_207(vsubcuq, 0, 21),
10643 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10644 GEN_VXFORM(vrlb, 2, 0),
10645 GEN_VXFORM(vrlh, 2, 1),
10646 GEN_VXFORM(vrlw, 2, 2),
10647 GEN_VXFORM_207(vrld, 2, 3),
10648 GEN_VXFORM(vsl, 2, 7),
10649 GEN_VXFORM(vsr, 2, 11),
10650 GEN_VXFORM(vpkuhum, 7, 0),
10651 GEN_VXFORM(vpkuwum, 7, 1),
10652 GEN_VXFORM_207(vpkudum, 7, 17),
10653 GEN_VXFORM(vpkuhus, 7, 2),
10654 GEN_VXFORM(vpkuwus, 7, 3),
10655 GEN_VXFORM_207(vpkudus, 7, 19),
10656 GEN_VXFORM(vpkshus, 7, 4),
10657 GEN_VXFORM(vpkswus, 7, 5),
10658 GEN_VXFORM_207(vpksdus, 7, 21),
10659 GEN_VXFORM(vpkshss, 7, 6),
10660 GEN_VXFORM(vpkswss, 7, 7),
10661 GEN_VXFORM_207(vpksdss, 7, 23),
10662 GEN_VXFORM(vpkpx, 7, 12),
10663 GEN_VXFORM(vsum4ubs, 4, 24),
10664 GEN_VXFORM(vsum4sbs, 4, 28),
10665 GEN_VXFORM(vsum4shs, 4, 25),
10666 GEN_VXFORM(vsum2sws, 4, 26),
10667 GEN_VXFORM(vsumsws, 4, 30),
10668 GEN_VXFORM(vaddfp, 5, 0),
10669 GEN_VXFORM(vsubfp, 5, 1),
10670 GEN_VXFORM(vmaxfp, 5, 16),
10671 GEN_VXFORM(vminfp, 5, 17),
10672
10673 #undef GEN_VXRFORM1
10674 #undef GEN_VXRFORM
10675 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10676 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10677 #define GEN_VXRFORM(name, opc2, opc3) \
10678 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10679 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10680 GEN_VXRFORM(vcmpequb, 3, 0)
10681 GEN_VXRFORM(vcmpequh, 3, 1)
10682 GEN_VXRFORM(vcmpequw, 3, 2)
10683 GEN_VXRFORM(vcmpgtsb, 3, 12)
10684 GEN_VXRFORM(vcmpgtsh, 3, 13)
10685 GEN_VXRFORM(vcmpgtsw, 3, 14)
10686 GEN_VXRFORM(vcmpgtub, 3, 8)
10687 GEN_VXRFORM(vcmpgtuh, 3, 9)
10688 GEN_VXRFORM(vcmpgtuw, 3, 10)
10689 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10690 GEN_VXRFORM(vcmpgefp, 3, 7)
10691 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10692 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10693
10694 #undef GEN_VXFORM_SIMM
10695 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10696 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10697 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10698 GEN_VXFORM_SIMM(vspltish, 6, 13),
10699 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10700
10701 #undef GEN_VXFORM_NOA
10702 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10703 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10704 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10705 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10706 GEN_VXFORM_207(vupkhsw, 7, 25),
10707 GEN_VXFORM_NOA(vupklsb, 7, 10),
10708 GEN_VXFORM_NOA(vupklsh, 7, 11),
10709 GEN_VXFORM_207(vupklsw, 7, 27),
10710 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10711 GEN_VXFORM_NOA(vupklpx, 7, 15),
10712 GEN_VXFORM_NOA(vrefp, 5, 4),
10713 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10714 GEN_VXFORM_NOA(vexptefp, 5, 6),
10715 GEN_VXFORM_NOA(vlogefp, 5, 7),
10716 GEN_VXFORM_NOA(vrfim, 5, 11),
10717 GEN_VXFORM_NOA(vrfin, 5, 8),
10718 GEN_VXFORM_NOA(vrfip, 5, 10),
10719 GEN_VXFORM_NOA(vrfiz, 5, 9),
10720
10721 #undef GEN_VXFORM_UIMM
10722 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10723 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10724 GEN_VXFORM_UIMM(vspltb, 6, 8),
10725 GEN_VXFORM_UIMM(vsplth, 6, 9),
10726 GEN_VXFORM_UIMM(vspltw, 6, 10),
10727 GEN_VXFORM_UIMM(vcfux, 5, 12),
10728 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10729 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10730 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10731
10732 #undef GEN_VAFORM_PAIRED
10733 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10734 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10735 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10736 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10737 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10738 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10739 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10740 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10741
10742 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10743 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10744 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10745 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10746
10747 GEN_VXFORM_207(vbpermq, 6, 21),
10748 GEN_VXFORM_207(vgbbd, 6, 20),
10749 GEN_VXFORM_207(vpmsumb, 4, 16),
10750 GEN_VXFORM_207(vpmsumh, 4, 17),
10751 GEN_VXFORM_207(vpmsumw, 4, 18),
10752 GEN_VXFORM_207(vpmsumd, 4, 19),
10753
10754 GEN_VXFORM_207(vsbox, 4, 23),
10755
10756 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10757 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10758
10759 GEN_VXFORM_207(vshasigmaw, 1, 26),
10760 GEN_VXFORM_207(vshasigmad, 1, 27),
10761
10762 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10763
10764 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10765 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10766 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10767 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10768 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10769 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10770 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10771
10772 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10773 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10774 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10775 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10776 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10777
10778 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10779 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10780 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10781 #if defined(TARGET_PPC64)
10782 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10783 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10784 #endif
10785
10786 #undef GEN_XX2FORM
10787 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10788 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10789 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10790
10791 #undef GEN_XX3FORM
10792 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10793 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10794 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10795 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10796 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10797
10798 #undef GEN_XX2IFORM
10799 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10800 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10801 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10802 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10803 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10804
10805 #undef GEN_XX3_RC_FORM
10806 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10807 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10808 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10809 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10810 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10811 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10812 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10813 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10814 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10815
10816 #undef GEN_XX3FORM_DM
10817 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10818 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10819 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10820 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10821 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10822 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10823 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10824 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10825 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10826 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10827 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10828 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10829 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10830 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10831 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10832 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10833 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10834
10835 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10836 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10837 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10838 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10839
10840 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10841 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10842 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10843 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10844 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10845 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10846 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10847 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10848
10849 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10850 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10851 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10852 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10853 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10854 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10855 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10856 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10857 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10858 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10859 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10860 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10861 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10862 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10863 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10864 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10865 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10866 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10867 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10868 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10869 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10870 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10871 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10872 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10873 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10874 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10875 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10876 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10877 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10878 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10879 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10880 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10881 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10882 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10883 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10884 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10885
10886 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10887 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10888 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10889 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10890 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10891 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10892 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10893 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10894 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10895 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10896 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10897 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10898 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10899 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10900 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10901 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10902 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10903 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10904
10905 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10906 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10907 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10908 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10909 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10910 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10911 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10912 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10913 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10914 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10915 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10916 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10917 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10918 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10919 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10920 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10921 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10922 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10923 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10924 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10925 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10926 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10927 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10928 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10929 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10930 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10931 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10932 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10933 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10934 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10935 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10936 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10937 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10938 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10939 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10940 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10941
10942 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10943 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10944 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10945 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10946 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10947 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10948 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10949 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10950 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10951 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10952 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10953 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10954 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10955 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10956 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10957 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10958 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10959 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10960 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10961 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10962 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10963 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10964 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10965 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10966 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10967 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10968 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10969 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10970 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10971 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10972 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10973 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10974 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10975 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10976 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10977 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10978
10979 #undef VSX_LOGICAL
10980 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10981 GEN_XX3FORM(name, opc2, opc3, fl2)
10982
10983 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10984 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10985 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10986 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10987 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10988 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10989 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10990 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10991 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10992 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10993 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10994 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10995
10996 #define GEN_XXSEL_ROW(opc3) \
10997 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10998 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10999 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11000 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11001 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11002 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11003 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11004 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11005
11006 GEN_XXSEL_ROW(0x00)
11007 GEN_XXSEL_ROW(0x01)
11008 GEN_XXSEL_ROW(0x02)
11009 GEN_XXSEL_ROW(0x03)
11010 GEN_XXSEL_ROW(0x04)
11011 GEN_XXSEL_ROW(0x05)
11012 GEN_XXSEL_ROW(0x06)
11013 GEN_XXSEL_ROW(0x07)
11014 GEN_XXSEL_ROW(0x08)
11015 GEN_XXSEL_ROW(0x09)
11016 GEN_XXSEL_ROW(0x0A)
11017 GEN_XXSEL_ROW(0x0B)
11018 GEN_XXSEL_ROW(0x0C)
11019 GEN_XXSEL_ROW(0x0D)
11020 GEN_XXSEL_ROW(0x0E)
11021 GEN_XXSEL_ROW(0x0F)
11022 GEN_XXSEL_ROW(0x10)
11023 GEN_XXSEL_ROW(0x11)
11024 GEN_XXSEL_ROW(0x12)
11025 GEN_XXSEL_ROW(0x13)
11026 GEN_XXSEL_ROW(0x14)
11027 GEN_XXSEL_ROW(0x15)
11028 GEN_XXSEL_ROW(0x16)
11029 GEN_XXSEL_ROW(0x17)
11030 GEN_XXSEL_ROW(0x18)
11031 GEN_XXSEL_ROW(0x19)
11032 GEN_XXSEL_ROW(0x1A)
11033 GEN_XXSEL_ROW(0x1B)
11034 GEN_XXSEL_ROW(0x1C)
11035 GEN_XXSEL_ROW(0x1D)
11036 GEN_XXSEL_ROW(0x1E)
11037 GEN_XXSEL_ROW(0x1F)
11038
11039 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11040
11041 #undef GEN_DFP_T_A_B_Rc
11042 #undef GEN_DFP_BF_A_B
11043 #undef GEN_DFP_BF_A_DCM
11044 #undef GEN_DFP_T_B_U32_U32_Rc
11045 #undef GEN_DFP_T_A_B_I32_Rc
11046 #undef GEN_DFP_T_B_Rc
11047 #undef GEN_DFP_T_FPR_I32_Rc
11048
11049 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11050 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11051
11052 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11053 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11054 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11055
11056 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11057 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11058 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11059 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11060 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11061
11062 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11063 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11064
11065 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11066 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11067 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11068
11069 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11070 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11071 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11072 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11073 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11074
11075 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11076 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11077
11078 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11079 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11080
11081 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11082 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11083
11084 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11085 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11086
11087 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11088 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11089
11090 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11091 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11092
11093 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11094 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11095
11096 #define GEN_DFP_BF_A_B(name, op1, op2) \
11097 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11098
11099 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11100 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11101
11102 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11103 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11104
11105 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11106 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11107
11108 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11109 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11110
11111 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11112 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11113
11114 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11115 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11116
11117 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11118 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11119
11120 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11121 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11122
11123 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11124 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11125
11126 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11127 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11128
11129 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11130 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11131
11132 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11133 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11134
11135 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11136 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11137
11138 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11139 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11140
11141 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11142 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11143
11144 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11145 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11146
11147 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11148 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11149
11150 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11151 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11152 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11153 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11154 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11155 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11156 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11157 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11158 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11159 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11160 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11161 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11162 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11163 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11164 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11165 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11166 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11167 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11168 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11169 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11170 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11171 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11172 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11173 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11174 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11175 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11176 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11177 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11178 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11179 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11180 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11181 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11182 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11183 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11184 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11185 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11186 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11187 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11188 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11189 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11190 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11191 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11192 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11193 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11194 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11195 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11196 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11197 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11198 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11199 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11200
11201 #undef GEN_SPE
11202 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11203 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11204 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11205 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11206 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11207 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11208 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11209 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11210 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11211 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11212 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11213 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11214 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11215 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11216 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11217 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11218 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11219 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11220 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11221 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11222 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11223 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11224 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11225 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11226 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11227 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11228 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11229 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11230 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11231 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11232 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11233
11234 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11235 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11236 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11237 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11238 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11239 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11240 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11241 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11242 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11243 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11244 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11245 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11246 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11247 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11248
11249 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11250 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11251 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11252 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11253 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11254 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11255 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11256 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11257 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11258 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11259 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11260 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11261 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11262 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11263
11264 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11265 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11266 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11267 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11268 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11269 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11270 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11271 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11272 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11273 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11274 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11275 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11276 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11277 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11278 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11279 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11280
11281 #undef GEN_SPEOP_LDST
11282 #define GEN_SPEOP_LDST(name, opc2, sh) \
11283 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11284 GEN_SPEOP_LDST(evldd, 0x00, 3),
11285 GEN_SPEOP_LDST(evldw, 0x01, 3),
11286 GEN_SPEOP_LDST(evldh, 0x02, 3),
11287 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11288 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11289 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11290 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11291 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11292 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11293 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11294 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11295
11296 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11297 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11298 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11299 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11300 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11301 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11302 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11303
11304 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11305 PPC_NONE, PPC2_TM),
11306 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11307 PPC_NONE, PPC2_TM),
11308 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11309 PPC_NONE, PPC2_TM),
11310 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11311 PPC_NONE, PPC2_TM),
11312 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11313 PPC_NONE, PPC2_TM),
11314 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11315 PPC_NONE, PPC2_TM),
11316 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11317 PPC_NONE, PPC2_TM),
11318 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11319 PPC_NONE, PPC2_TM),
11320 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11321 PPC_NONE, PPC2_TM),
11322 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11323 PPC_NONE, PPC2_TM),
11324 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11325 PPC_NONE, PPC2_TM),
11326 };
11327
11328 #include "helper_regs.h"
11329 #include "translate_init.c"
11330
11331 /*****************************************************************************/
11332 /* Misc PowerPC helpers */
11333 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11334 int flags)
11335 {
11336 #define RGPL 4
11337 #define RFPL 4
11338
11339 PowerPCCPU *cpu = POWERPC_CPU(cs);
11340 CPUPPCState *env = &cpu->env;
11341 int i;
11342
11343 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11344 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11345 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11346 cs->cpu_index);
11347 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11348 TARGET_FMT_lx " iidx %d didx %d\n",
11349 env->msr, env->spr[SPR_HID0],
11350 env->hflags, env->immu_idx, env->dmmu_idx);
11351 #if !defined(NO_TIMER_DUMP)
11352 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11353 #if !defined(CONFIG_USER_ONLY)
11354 " DECR %08" PRIu32
11355 #endif
11356 "\n",
11357 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11358 #if !defined(CONFIG_USER_ONLY)
11359 , cpu_ppc_load_decr(env)
11360 #endif
11361 );
11362 #endif
11363 for (i = 0; i < 32; i++) {
11364 if ((i & (RGPL - 1)) == 0)
11365 cpu_fprintf(f, "GPR%02d", i);
11366 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11367 if ((i & (RGPL - 1)) == (RGPL - 1))
11368 cpu_fprintf(f, "\n");
11369 }
11370 cpu_fprintf(f, "CR ");
11371 for (i = 0; i < 8; i++)
11372 cpu_fprintf(f, "%01x", env->crf[i]);
11373 cpu_fprintf(f, " [");
11374 for (i = 0; i < 8; i++) {
11375 char a = '-';
11376 if (env->crf[i] & 0x08)
11377 a = 'L';
11378 else if (env->crf[i] & 0x04)
11379 a = 'G';
11380 else if (env->crf[i] & 0x02)
11381 a = 'E';
11382 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11383 }
11384 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11385 env->reserve_addr);
11386 for (i = 0; i < 32; i++) {
11387 if ((i & (RFPL - 1)) == 0)
11388 cpu_fprintf(f, "FPR%02d", i);
11389 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11390 if ((i & (RFPL - 1)) == (RFPL - 1))
11391 cpu_fprintf(f, "\n");
11392 }
11393 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11394 #if !defined(CONFIG_USER_ONLY)
11395 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11396 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11397 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11398 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11399
11400 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11401 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11402 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11403 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11404
11405 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11406 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11407 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11408 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11409
11410 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11411 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11412 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11413 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11414 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11415
11416 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11417 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11418 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11419 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11420
11421 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11422 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11423 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11424 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11425
11426 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11427 " EPR " TARGET_FMT_lx "\n",
11428 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11429 env->spr[SPR_BOOKE_EPR]);
11430
11431 /* FSL-specific */
11432 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11433 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11434 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11435 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11436
11437 /*
11438 * IVORs are left out as they are large and do not change often --
11439 * they can be read with "p $ivor0", "p $ivor1", etc.
11440 */
11441 }
11442
11443 #if defined(TARGET_PPC64)
11444 if (env->flags & POWERPC_FLAG_CFAR) {
11445 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11446 }
11447 #endif
11448
11449 switch (env->mmu_model) {
11450 case POWERPC_MMU_32B:
11451 case POWERPC_MMU_601:
11452 case POWERPC_MMU_SOFT_6xx:
11453 case POWERPC_MMU_SOFT_74xx:
11454 #if defined(TARGET_PPC64)
11455 case POWERPC_MMU_64B:
11456 case POWERPC_MMU_2_03:
11457 case POWERPC_MMU_2_06:
11458 case POWERPC_MMU_2_06a:
11459 case POWERPC_MMU_2_07:
11460 case POWERPC_MMU_2_07a:
11461 #endif
11462 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11463 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11464 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11465 break;
11466 case POWERPC_MMU_BOOKE206:
11467 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11468 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11469 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11470 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11471
11472 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11473 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11474 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11475 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11476
11477 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11478 " TLB1CFG " TARGET_FMT_lx "\n",
11479 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11480 env->spr[SPR_BOOKE_TLB1CFG]);
11481 break;
11482 default:
11483 break;
11484 }
11485 #endif
11486
11487 #undef RGPL
11488 #undef RFPL
11489 }
11490
11491 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11492 fprintf_function cpu_fprintf, int flags)
11493 {
11494 #if defined(DO_PPC_STATISTICS)
11495 PowerPCCPU *cpu = POWERPC_CPU(cs);
11496 opc_handler_t **t1, **t2, **t3, *handler;
11497 int op1, op2, op3;
11498
11499 t1 = cpu->env.opcodes;
11500 for (op1 = 0; op1 < 64; op1++) {
11501 handler = t1[op1];
11502 if (is_indirect_opcode(handler)) {
11503 t2 = ind_table(handler);
11504 for (op2 = 0; op2 < 32; op2++) {
11505 handler = t2[op2];
11506 if (is_indirect_opcode(handler)) {
11507 t3 = ind_table(handler);
11508 for (op3 = 0; op3 < 32; op3++) {
11509 handler = t3[op3];
11510 if (handler->count == 0)
11511 continue;
11512 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11513 "%016" PRIx64 " %" PRId64 "\n",
11514 op1, op2, op3, op1, (op3 << 5) | op2,
11515 handler->oname,
11516 handler->count, handler->count);
11517 }
11518 } else {
11519 if (handler->count == 0)
11520 continue;
11521 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11522 "%016" PRIx64 " %" PRId64 "\n",
11523 op1, op2, op1, op2, handler->oname,
11524 handler->count, handler->count);
11525 }
11526 }
11527 } else {
11528 if (handler->count == 0)
11529 continue;
11530 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11531 " %" PRId64 "\n",
11532 op1, op1, handler->oname,
11533 handler->count, handler->count);
11534 }
11535 }
11536 #endif
11537 }
11538
11539 /*****************************************************************************/
11540 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11541 {
11542 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11543 CPUState *cs = CPU(cpu);
11544 DisasContext ctx, *ctxp = &ctx;
11545 opc_handler_t **table, *handler;
11546 target_ulong pc_start;
11547 int num_insns;
11548 int max_insns;
11549
11550 pc_start = tb->pc;
11551 ctx.nip = pc_start;
11552 ctx.tb = tb;
11553 ctx.exception = POWERPC_EXCP_NONE;
11554 ctx.spr_cb = env->spr_cb;
11555 ctx.pr = msr_pr;
11556 ctx.mem_idx = env->dmmu_idx;
11557 ctx.dr = msr_dr;
11558 #if !defined(CONFIG_USER_ONLY)
11559 ctx.hv = msr_hv || !env->has_hv_mode;
11560 #endif
11561 ctx.insns_flags = env->insns_flags;
11562 ctx.insns_flags2 = env->insns_flags2;
11563 ctx.access_type = -1;
11564 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
11565 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11566 #if defined(TARGET_PPC64)
11567 ctx.sf_mode = msr_is_64bit(env, env->msr);
11568 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11569 #endif
11570 if (env->mmu_model == POWERPC_MMU_32B ||
11571 env->mmu_model == POWERPC_MMU_601 ||
11572 (env->mmu_model & POWERPC_MMU_64B))
11573 ctx.lazy_tlb_flush = true;
11574
11575 ctx.fpu_enabled = !!msr_fp;
11576 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11577 ctx.spe_enabled = !!msr_spe;
11578 else
11579 ctx.spe_enabled = false;
11580 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11581 ctx.altivec_enabled = !!msr_vr;
11582 else
11583 ctx.altivec_enabled = false;
11584 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11585 ctx.vsx_enabled = !!msr_vsx;
11586 } else {
11587 ctx.vsx_enabled = false;
11588 }
11589 #if defined(TARGET_PPC64)
11590 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11591 ctx.tm_enabled = !!msr_tm;
11592 } else {
11593 ctx.tm_enabled = false;
11594 }
11595 #endif
11596 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11597 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11598 else
11599 ctx.singlestep_enabled = 0;
11600 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11601 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11602 if (unlikely(cs->singlestep_enabled)) {
11603 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11604 }
11605 #if defined (DO_SINGLE_STEP) && 0
11606 /* Single step trace mode */
11607 msr_se = 1;
11608 #endif
11609 num_insns = 0;
11610 max_insns = tb->cflags & CF_COUNT_MASK;
11611 if (max_insns == 0) {
11612 max_insns = CF_COUNT_MASK;
11613 }
11614 if (max_insns > TCG_MAX_INSNS) {
11615 max_insns = TCG_MAX_INSNS;
11616 }
11617
11618 gen_tb_start(tb);
11619 tcg_clear_temp_count();
11620 /* Set env in case of segfault during code fetch */
11621 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11622 tcg_gen_insn_start(ctx.nip);
11623 num_insns++;
11624
11625 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11626 gen_debug_exception(ctxp);
11627 /* The address covered by the breakpoint must be included in
11628 [tb->pc, tb->pc + tb->size) in order to for it to be
11629 properly cleared -- thus we increment the PC here so that
11630 the logic setting tb->size below does the right thing. */
11631 ctx.nip += 4;
11632 break;
11633 }
11634
11635 LOG_DISAS("----------------\n");
11636 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11637 ctx.nip, ctx.mem_idx, (int)msr_ir);
11638 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11639 gen_io_start();
11640 if (unlikely(need_byteswap(&ctx))) {
11641 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11642 } else {
11643 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11644 }
11645 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11646 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11647 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11648 ctx.nip += 4;
11649 table = env->opcodes;
11650 handler = table[opc1(ctx.opcode)];
11651 if (is_indirect_opcode(handler)) {
11652 table = ind_table(handler);
11653 handler = table[opc2(ctx.opcode)];
11654 if (is_indirect_opcode(handler)) {
11655 table = ind_table(handler);
11656 handler = table[opc3(ctx.opcode)];
11657 }
11658 }
11659 /* Is opcode *REALLY* valid ? */
11660 if (unlikely(handler->handler == &gen_invalid)) {
11661 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11662 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11663 opc1(ctx.opcode), opc2(ctx.opcode),
11664 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11665 } else {
11666 uint32_t inval;
11667
11668 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11669 inval = handler->inval2;
11670 } else {
11671 inval = handler->inval1;
11672 }
11673
11674 if (unlikely((ctx.opcode & inval) != 0)) {
11675 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11676 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11677 ctx.opcode & inval, opc1(ctx.opcode),
11678 opc2(ctx.opcode), opc3(ctx.opcode),
11679 ctx.opcode, ctx.nip - 4);
11680 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11681 break;
11682 }
11683 }
11684 (*(handler->handler))(&ctx);
11685 #if defined(DO_PPC_STATISTICS)
11686 handler->count++;
11687 #endif
11688 /* Check trace mode exceptions */
11689 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11690 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11691 ctx.exception != POWERPC_SYSCALL &&
11692 ctx.exception != POWERPC_EXCP_TRAP &&
11693 ctx.exception != POWERPC_EXCP_BRANCH)) {
11694 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11695 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11696 (cs->singlestep_enabled) ||
11697 singlestep ||
11698 num_insns >= max_insns)) {
11699 /* if we reach a page boundary or are single stepping, stop
11700 * generation
11701 */
11702 break;
11703 }
11704 if (tcg_check_temp_count()) {
11705 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11706 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11707 ctx.opcode);
11708 exit(1);
11709 }
11710 }
11711 if (tb->cflags & CF_LAST_IO)
11712 gen_io_end();
11713 if (ctx.exception == POWERPC_EXCP_NONE) {
11714 gen_goto_tb(&ctx, 0, ctx.nip);
11715 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11716 if (unlikely(cs->singlestep_enabled)) {
11717 gen_debug_exception(ctxp);
11718 }
11719 /* Generate the return instruction */
11720 tcg_gen_exit_tb(0);
11721 }
11722 gen_tb_end(tb, num_insns);
11723
11724 tb->size = ctx.nip - pc_start;
11725 tb->icount = num_insns;
11726
11727 #if defined(DEBUG_DISAS)
11728 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11729 && qemu_log_in_addr_range(pc_start)) {
11730 int flags;
11731 flags = env->bfd_mach;
11732 flags |= ctx.le_mode << 16;
11733 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11734 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11735 qemu_log("\n");
11736 }
11737 #endif
11738 }
11739
11740 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11741 target_ulong *data)
11742 {
11743 env->nip = data[0];
11744 }
QEmu