hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  34
  35 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  36 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  37 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  38 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  39
  40 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  41 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  42
  43 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  44 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  45 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  46 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  47 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  48
  49 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  50 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  51
  52 /*
  53  * These are the definitions for the Modem Control Register
  54  */
  55 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  56 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  57 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  58 #define UART_MCR_RTS    0x02    /* RTS complement */
  59 #define UART_MCR_DTR    0x01    /* DTR complement */
  60
  61 /*
  62  * These are the definitions for the Modem Status Register
  63  */
  64 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  65 #define UART_MSR_RI     0x40    /* Ring Indicator */
  66 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  67 #define UART_MSR_CTS    0x10    /* Clear to Send */
  68 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  69 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  70 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  71 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  73
  74 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  75 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  76 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  77 #define UART_LSR_FE     0x08    /* Frame error indicator */
  78 #define UART_LSR_PE     0x04    /* Parity error indicator */
  79 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  80 #define UART_LSR_DR     0x01    /* Receiver data ready */
  81 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  82
  83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  84
  85 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  86 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  87 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  88 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  89
  90 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  91 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  92 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  93 #define UART_FCR_FE         0x01    /* FIFO Enable */
  94
  95 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  96
  97 #define XMIT_FIFO           0
  98 #define RECV_FIFO           1
  99 #define MAX_XMIT_RETRY      4
 100
 101 struct SerialFIFO {
 102     uint8_t data[UART_FIFO_LENGTH];
 103     uint8_t count;
 104     uint8_t itl;                        /* Interrupt Trigger Level */
 105     uint8_t tail;
 106     uint8_t head;
 107 } typedef SerialFIFO;
 108
 109 struct SerialState {
 110     uint16_t divider;
 111     uint8_t rbr; /* receive register */
 112     uint8_t thr; /* transmit holding register */
 113     uint8_t tsr; /* transmit shift register */
 114     uint8_t ier;
 115     uint8_t iir; /* read only */
 116     uint8_t lcr;
 117     uint8_t mcr;
 118     uint8_t lsr; /* read only */
 119     uint8_t msr; /* read only */
 120     uint8_t scr;
 121     uint8_t fcr;
 122     uint8_t fcr_vmstate; /* we can't write directly this value
 123                             it has side effects */
 124     /* NOTE: this hidden state is necessary for tx irq generation as
 125        it can be reset while reading iir */
 126     int thr_ipending;
 127     qemu_irq irq;
 128     CharDriverState *chr;
 129     int last_break_enable;
 130     int it_shift;
 131     int baudbase;
 132     int tsr_retry;
 133
 134     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 135     SerialFIFO recv_fifo;
 136     SerialFIFO xmit_fifo;
 137
 138     struct QEMUTimer *fifo_timeout_timer;
 139     int timeout_ipending;                   /* timeout interrupt pending state */
 140     struct QEMUTimer *transmit_timer;
 141
 142
 143     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 144     int poll_msl;
 145
 146     struct QEMUTimer *modem_status_poll;
 147 };
 148
 149 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 150
 151 static void fifo_clear(SerialState *s, int fifo)
 152 {
 153     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 154     memset(f->data, 0, UART_FIFO_LENGTH);
 155     f->count = 0;
 156     f->head = 0;
 157     f->tail = 0;
 158 }
 159
 160 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 161 {
 162     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 163
 164     f->data[f->head++] = chr;
 165
 166     if (f->head == UART_FIFO_LENGTH)
 167         f->head = 0;
 168     f->count++;
 169
 170     return 1;
 171 }
 172
 173 static uint8_t fifo_get(SerialState *s, int fifo)
 174 {
 175     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 176     uint8_t c;
 177
 178     if(f->count == 0)
 179         return 0;
 180
 181     c = f->data[f->tail++];
 182     if (f->tail == UART_FIFO_LENGTH)
 183         f->tail = 0;
 184     f->count--;
 185
 186     return c;
 187 }
 188
 189 static void serial_update_irq(SerialState *s)
 190 {
 191     uint8_t tmp_iir = UART_IIR_NO_INT;
 192
 193     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 194         tmp_iir = UART_IIR_RLSI;
 195     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 196         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 197          * this is not in the specification but is observed on existing
 198          * hardware.  */
 199         tmp_iir = UART_IIR_CTI;
 200     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR)) {
 201         if (!(s->fcr & UART_FCR_FE)) {
 202            tmp_iir = UART_IIR_RDI;
 203         } else if (s->recv_fifo.count >= s->recv_fifo.itl) {
 204            tmp_iir = UART_IIR_RDI;
 205         }
 206     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 207         tmp_iir = UART_IIR_THRI;
 208     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 209         tmp_iir = UART_IIR_MSI;
 210     }
 211
 212     s->iir = tmp_iir | (s->iir & 0xF0);
 213
 214     if (tmp_iir != UART_IIR_NO_INT) {
 215         qemu_irq_raise(s->irq);
 216     } else {
 217         qemu_irq_lower(s->irq);
 218     }
 219 }
 220
 221 static void serial_update_parameters(SerialState *s)
 222 {
 223     int speed, parity, data_bits, stop_bits, frame_size;
 224     QEMUSerialSetParams ssp;
 225
 226     if (s->divider == 0)
 227         return;
 228
 229     frame_size = 1;
 230     if (s->lcr & 0x08) {
 231         if (s->lcr & 0x10)
 232             parity = 'E';
 233         else
 234             parity = 'O';
 235     } else {
 236             parity = 'N';
 237             frame_size = 0;
 238     }
 239     if (s->lcr & 0x04)
 240         stop_bits = 2;
 241     else
 242         stop_bits = 1;
 243
 244     data_bits = (s->lcr & 0x03) + 5;
 245     frame_size += data_bits + stop_bits;
 246     speed = s->baudbase / s->divider;
 247     ssp.speed = speed;
 248     ssp.parity = parity;
 249     ssp.data_bits = data_bits;
 250     ssp.stop_bits = stop_bits;
 251     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 252     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 253 #if 0
 254     printf("speed=%d parity=%c data=%d stop=%d\n",
 255            speed, parity, data_bits, stop_bits);
 256 #endif
 257 }
 258
 259 static void serial_update_msl(SerialState *s)
 260 {
 261     uint8_t omsr;
 262     int flags;
 263
 264     qemu_del_timer(s->modem_status_poll);
 265
 266     if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 267         s->poll_msl = -1;
 268         return;
 269     }
 270
 271     omsr = s->msr;
 272
 273     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 274     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 275     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 276     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 277
 278     if (s->msr != omsr) {
 279          /* Set delta bits */
 280          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 281          /* UART_MSR_TERI only if change was from 1 -> 0 */
 282          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 283              s->msr &= ~UART_MSR_TERI;
 284          serial_update_irq(s);
 285     }
 286
 287     /* The real 16550A apparently has a 250ns response latency to line status changes.
 288        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 289
 290     if (s->poll_msl)
 291         qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
 292 }
 293
 294 static void serial_xmit(void *opaque)
 295 {
 296     SerialState *s = opaque;
 297     uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
 298
 299     if (s->tsr_retry <= 0) {
 300         if (s->fcr & UART_FCR_FE) {
 301             s->tsr = fifo_get(s,XMIT_FIFO);
 302             if (!s->xmit_fifo.count)
 303                 s->lsr |= UART_LSR_THRE;
 304         } else {
 305             s->tsr = s->thr;
 306             s->lsr |= UART_LSR_THRE;
 307         }
 308     }
 309
 310     if (s->mcr & UART_MCR_LOOP) {
 311         /* in loopback mode, say that we just received a char */
 312         serial_receive1(s, &s->tsr, 1);
 313     } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
 314         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 315             s->tsr_retry++;
 316             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 317             return;
 318         } else if (s->poll_msl < 0) {
 319             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 320             drop any further failed writes instantly, until we get one that goes through.
 321             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 322             s->tsr_retry = -1;
 323         }
 324     }
 325     else {
 326         s->tsr_retry = 0;
 327     }
 328
 329     s->last_xmit_ts = qemu_get_clock(vm_clock);
 330     if (!(s->lsr & UART_LSR_THRE))
 331         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 332
 333     if (s->lsr & UART_LSR_THRE) {
 334         s->lsr |= UART_LSR_TEMT;
 335         s->thr_ipending = 1;
 336         serial_update_irq(s);
 337     }
 338 }
 339
 340
 341 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 342 {
 343     SerialState *s = opaque;
 344
 345     addr &= 7;
 346 #ifdef DEBUG_SERIAL
 347     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 348 #endif
 349     switch(addr) {
 350     default:
 351     case 0:
 352         if (s->lcr & UART_LCR_DLAB) {
 353             s->divider = (s->divider & 0xff00) | val;
 354             serial_update_parameters(s);
 355         } else {
 356             s->thr = (uint8_t) val;
 357             if(s->fcr & UART_FCR_FE) {
 358                   fifo_put(s, XMIT_FIFO, s->thr);
 359             s->thr_ipending = 0;
 360                   s->lsr &= ~UART_LSR_TEMT;
 361             s->lsr &= ~UART_LSR_THRE;
 362             serial_update_irq(s);
 363             } else {
 364                   s->thr_ipending = 0;
 365                   s->lsr &= ~UART_LSR_THRE;
 366                   serial_update_irq(s);
 367             }
 368             serial_xmit(s);
 369         }
 370         break;
 371     case 1:
 372         if (s->lcr & UART_LCR_DLAB) {
 373             s->divider = (s->divider & 0x00ff) | (val << 8);
 374             serial_update_parameters(s);
 375         } else {
 376             s->ier = val & 0x0f;
 377             /* If the backend device is a real serial port, turn polling of the modem
 378                status lines on physical port on or off depending on UART_IER_MSI state */
 379             if (s->poll_msl >= 0) {
 380                 if (s->ier & UART_IER_MSI) {
 381                      s->poll_msl = 1;
 382                      serial_update_msl(s);
 383                 } else {
 384                      qemu_del_timer(s->modem_status_poll);
 385                      s->poll_msl = 0;
 386                 }
 387             }
 388             if (s->lsr & UART_LSR_THRE) {
 389                 s->thr_ipending = 1;
 390                 serial_update_irq(s);
 391             }
 392         }
 393         break;
 394     case 2:
 395         val = val & 0xFF;
 396
 397         if (s->fcr == val)
 398             break;
 399
 400         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 401         if ((val ^ s->fcr) & UART_FCR_FE)
 402             val |= UART_FCR_XFR | UART_FCR_RFR;
 403
 404         /* FIFO clear */
 405
 406         if (val & UART_FCR_RFR) {
 407             qemu_del_timer(s->fifo_timeout_timer);
 408             s->timeout_ipending=0;
 409             fifo_clear(s,RECV_FIFO);
 410         }
 411
 412         if (val & UART_FCR_XFR) {
 413             fifo_clear(s,XMIT_FIFO);
 414         }
 415
 416         if (val & UART_FCR_FE) {
 417             s->iir |= UART_IIR_FE;
 418             /* Set RECV_FIFO trigger Level */
 419             switch (val & 0xC0) {
 420             case UART_FCR_ITL_1:
 421                 s->recv_fifo.itl = 1;
 422                 break;
 423             case UART_FCR_ITL_2:
 424                 s->recv_fifo.itl = 4;
 425                 break;
 426             case UART_FCR_ITL_3:
 427                 s->recv_fifo.itl = 8;
 428                 break;
 429             case UART_FCR_ITL_4:
 430                 s->recv_fifo.itl = 14;
 431                 break;
 432             }
 433         } else
 434             s->iir &= ~UART_IIR_FE;
 435
 436         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 437         s->fcr = val & 0xC9;
 438         serial_update_irq(s);
 439         break;
 440     case 3:
 441         {
 442             int break_enable;
 443             s->lcr = val;
 444             serial_update_parameters(s);
 445             break_enable = (val >> 6) & 1;
 446             if (break_enable != s->last_break_enable) {
 447                 s->last_break_enable = break_enable;
 448                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 449                                &break_enable);
 450             }
 451         }
 452         break;
 453     case 4:
 454         {
 455             int flags;
 456             int old_mcr = s->mcr;
 457             s->mcr = val & 0x1f;
 458             if (val & UART_MCR_LOOP)
 459                 break;
 460
 461             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 462
 463                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 464
 465                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 466
 467                 if (val & UART_MCR_RTS)
 468                     flags |= CHR_TIOCM_RTS;
 469                 if (val & UART_MCR_DTR)
 470                     flags |= CHR_TIOCM_DTR;
 471
 472                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 473                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 474                    from the device/computer at the other end of the serial line */
 475                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
 476             }
 477         }
 478         break;
 479     case 5:
 480         break;
 481     case 6:
 482         break;
 483     case 7:
 484         s->scr = val;
 485         break;
 486     }
 487 }
 488
 489 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 490 {
 491     SerialState *s = opaque;
 492     uint32_t ret;
 493
 494     addr &= 7;
 495     switch(addr) {
 496     default:
 497     case 0:
 498         if (s->lcr & UART_LCR_DLAB) {
 499             ret = s->divider & 0xff;
 500         } else {
 501             if(s->fcr & UART_FCR_FE) {
 502                 ret = fifo_get(s,RECV_FIFO);
 503                 if (s->recv_fifo.count == 0)
 504                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 505                 else
 506                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 507                 s->timeout_ipending = 0;
 508             } else {
 509                 ret = s->rbr;
 510                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 511             }
 512             serial_update_irq(s);
 513             if (!(s->mcr & UART_MCR_LOOP)) {
 514                 /* in loopback mode, don't receive any data */
 515                 qemu_chr_accept_input(s->chr);
 516             }
 517         }
 518         break;
 519     case 1:
 520         if (s->lcr & UART_LCR_DLAB) {
 521             ret = (s->divider >> 8) & 0xff;
 522         } else {
 523             ret = s->ier;
 524         }
 525         break;
 526     case 2:
 527         ret = s->iir;
 528             s->thr_ipending = 0;
 529         serial_update_irq(s);
 530         break;
 531     case 3:
 532         ret = s->lcr;
 533         break;
 534     case 4:
 535         ret = s->mcr;
 536         break;
 537     case 5:
 538         ret = s->lsr;
 539         /* Clear break interrupt */
 540         if (s->lsr & UART_LSR_BI) {
 541             s->lsr &= ~UART_LSR_BI;
 542             serial_update_irq(s);
 543         }
 544         break;
 545     case 6:
 546         if (s->mcr & UART_MCR_LOOP) {
 547             /* in loopback, the modem output pins are connected to the
 548                inputs */
 549             ret = (s->mcr & 0x0c) << 4;
 550             ret |= (s->mcr & 0x02) << 3;
 551             ret |= (s->mcr & 0x01) << 5;
 552         } else {
 553             if (s->poll_msl >= 0)
 554                 serial_update_msl(s);
 555             ret = s->msr;
 556             /* Clear delta bits & msr int after read, if they were set */
 557             if (s->msr & UART_MSR_ANY_DELTA) {
 558                 s->msr &= 0xF0;
 559                 serial_update_irq(s);
 560             }
 561         }
 562         break;
 563     case 7:
 564         ret = s->scr;
 565         break;
 566     }
 567 #ifdef DEBUG_SERIAL
 568     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 569 #endif
 570     return ret;
 571 }
 572
 573 static int serial_can_receive(SerialState *s)
 574 {
 575     if(s->fcr & UART_FCR_FE) {
 576         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 577         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 578         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 579         effectively overriding the ITL that the guest has set. */
 580              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 581         else
 582              return 0;
 583     } else {
 584     return !(s->lsr & UART_LSR_DR);
 585     }
 586 }
 587
 588 static void serial_receive_break(SerialState *s)
 589 {
 590     s->rbr = 0;
 591     /* When the LSR_DR is set a null byte is pushed into the fifo */
 592     fifo_put(s, RECV_FIFO, '\0');
 593     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 594     serial_update_irq(s);
 595 }
 596
 597 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 598 static void fifo_timeout_int (void *opaque) {
 599     SerialState *s = opaque;
 600     if (s->recv_fifo.count) {
 601         s->timeout_ipending = 1;
 602         serial_update_irq(s);
 603     }
 604 }
 605
 606 static int serial_can_receive1(void *opaque)
 607 {
 608     SerialState *s = opaque;
 609     return serial_can_receive(s);
 610 }
 611
 612 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 613 {
 614     SerialState *s = opaque;
 615     if(s->fcr & UART_FCR_FE) {
 616         int i;
 617         for (i = 0; i < size; i++) {
 618             fifo_put(s, RECV_FIFO, buf[i]);
 619         }
 620         s->lsr |= UART_LSR_DR;
 621         /* call the timeout receive callback in 4 char transmit time */
 622         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 623     } else {
 624         s->rbr = buf[0];
 625         s->lsr |= UART_LSR_DR;
 626     }
 627     serial_update_irq(s);
 628 }
 629
 630 static void serial_event(void *opaque, int event)
 631 {
 632     SerialState *s = opaque;
 633 #ifdef DEBUG_SERIAL
 634     printf("serial: event %x\n", event);
 635 #endif
 636     if (event == CHR_EVENT_BREAK)
 637         serial_receive_break(s);
 638 }
 639
 640 static void serial_pre_save(const void *opaque)
 641 {
 642     SerialState *s = (void *)opaque;
 643     s->fcr_vmstate = s->fcr;
 644 }
 645
 646 static int serial_pre_load(void *opaque)
 647 {
 648     SerialState *s = opaque;
 649     s->fcr_vmstate = 0;
 650     return 0;
 651 }
 652
 653 static int serial_post_load(void *opaque)
 654 {
 655     SerialState *s = opaque;
 656
 657     /* Initialize fcr via setter to perform essential side-effects */
 658     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 659     return 0;
 660 }
 661
 662 static const VMStateDescription vmstate_serial = {
 663     .name = "serial",
 664     .version_id = 3,
 665     .minimum_version_id = 2,
 666     .pre_save = serial_pre_save,
 667     .pre_load = serial_pre_load,
 668     .post_load = serial_post_load,
 669     .fields      = (VMStateField []) {
 670         VMSTATE_UINT16_V(divider, SerialState, 2),
 671         VMSTATE_UINT8(rbr, SerialState),
 672         VMSTATE_UINT8(ier, SerialState),
 673         VMSTATE_UINT8(iir, SerialState),
 674         VMSTATE_UINT8(lcr, SerialState),
 675         VMSTATE_UINT8(mcr, SerialState),
 676         VMSTATE_UINT8(lsr, SerialState),
 677         VMSTATE_UINT8(msr, SerialState),
 678         VMSTATE_UINT8(scr, SerialState),
 679         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 680         VMSTATE_END_OF_LIST()
 681     }
 682 };
 683
 684 static void serial_reset(void *opaque)
 685 {
 686     SerialState *s = opaque;
 687
 688     s->rbr = 0;
 689     s->ier = 0;
 690     s->iir = UART_IIR_NO_INT;
 691     s->lcr = 0;
 692     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 693     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 694     /* Default to 9600 baud, no parity, one stop bit */
 695     s->divider = 0x0C;
 696     s->mcr = UART_MCR_OUT2;
 697     s->scr = 0;
 698     s->tsr_retry = 0;
 699     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9;
 700     s->poll_msl = 0;
 701
 702     fifo_clear(s,RECV_FIFO);
 703     fifo_clear(s,XMIT_FIFO);
 704
 705     s->last_xmit_ts = qemu_get_clock(vm_clock);
 706
 707     s->thr_ipending = 0;
 708     s->last_break_enable = 0;
 709     qemu_irq_lower(s->irq);
 710 }
 711
 712 static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase,
 713                              CharDriverState *chr)
 714 {
 715     s->irq = irq;
 716     s->baudbase = baudbase;
 717     s->chr = chr ?: qemu_chr_open("null", "null", NULL);
 718
 719     s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 720
 721     s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 722     s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 723
 724     qemu_register_reset(serial_reset, s);
 725     serial_reset(s);
 726
 727     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 728                           serial_event, s);
 729 }
 730
 731 /* If fd is zero, it means that the serial device uses the console */
 732 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 733                          CharDriverState *chr)
 734 {
 735     SerialState *s;
 736
 737     s = qemu_mallocz(sizeof(SerialState));
 738
 739     serial_init_core(s, irq, baudbase, chr);
 740
 741     vmstate_register(base, &vmstate_serial, s);
 742
 743     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 744     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 745     return s;
 746 }
 747
 748 /* Memory mapped interface */
 749 static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
 750 {
 751     SerialState *s = opaque;
 752
 753     return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
 754 }
 755
 756 static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
 757                              uint32_t value)
 758 {
 759     SerialState *s = opaque;
 760
 761     serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 762 }
 763
 764 static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
 765 {
 766     SerialState *s = opaque;
 767     uint32_t val;
 768
 769     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 770 #ifdef TARGET_WORDS_BIGENDIAN
 771     val = bswap16(val);
 772 #endif
 773     return val;
 774 }
 775
 776 static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
 777                              uint32_t value)
 778 {
 779     SerialState *s = opaque;
 780 #ifdef TARGET_WORDS_BIGENDIAN
 781     value = bswap16(value);
 782 #endif
 783     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 784 }
 785
 786 static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
 787 {
 788     SerialState *s = opaque;
 789     uint32_t val;
 790
 791     val = serial_ioport_read(s, addr >> s->it_shift);
 792 #ifdef TARGET_WORDS_BIGENDIAN
 793     val = bswap32(val);
 794 #endif
 795     return val;
 796 }
 797
 798 static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
 799                              uint32_t value)
 800 {
 801     SerialState *s = opaque;
 802 #ifdef TARGET_WORDS_BIGENDIAN
 803     value = bswap32(value);
 804 #endif
 805     serial_ioport_write(s, addr >> s->it_shift, value);
 806 }
 807
 808 static CPUReadMemoryFunc * const serial_mm_read[] = {
 809     &serial_mm_readb,
 810     &serial_mm_readw,
 811     &serial_mm_readl,
 812 };
 813
 814 static CPUWriteMemoryFunc * const serial_mm_write[] = {
 815     &serial_mm_writeb,
 816     &serial_mm_writew,
 817     &serial_mm_writel,
 818 };
 819
 820 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 821                              qemu_irq irq, int baudbase,
 822                              CharDriverState *chr, int ioregister)
 823 {
 824     SerialState *s;
 825     int s_io_memory;
 826
 827     s = qemu_mallocz(sizeof(SerialState));
 828
 829     s->it_shift = it_shift;
 830
 831     serial_init_core(s, irq, baudbase, chr);
 832     vmstate_register(base, &vmstate_serial, s);
 833
 834     if (ioregister) {
 835         s_io_memory = cpu_register_io_memory(serial_mm_read,
 836                                              serial_mm_write, s);
 837         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 838     }
 839     serial_update_msl(s);
 840     return s;
 841 }