4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "translate.h"
29 #include "qemu/host-utils.h"
31 #include "exec/gen-icount.h"
37 static TCGv_i64 cpu_X
[32];
38 static TCGv_i64 cpu_pc
;
39 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr
;
43 static TCGv_i64 cpu_exclusive_val
;
44 static TCGv_i64 cpu_exclusive_high
;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test
;
47 static TCGv_i32 cpu_exclusive_info
;
50 static const char *regnames
[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
58 A64_SHIFT_TYPE_LSL
= 0,
59 A64_SHIFT_TYPE_LSR
= 1,
60 A64_SHIFT_TYPE_ASR
= 2,
61 A64_SHIFT_TYPE_ROR
= 3
64 /* Table based decoder typedefs - used when the relevant bits for decode
65 * are too awkwardly scattered across the instruction (eg SIMD).
67 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
69 typedef struct AArch64DecodeTable
{
72 AArch64DecodeFn
*disas_fn
;
75 /* Function prototype for gen_ functions for calling Neon helpers */
76 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
78 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
85 /* initialize TCG globals. */
86 void a64_translate_init(void)
90 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
91 offsetof(CPUARMState
, pc
),
93 for (i
= 0; i
< 32; i
++) {
94 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
95 offsetof(CPUARMState
, xregs
[i
]),
99 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
100 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
101 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
102 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
104 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
105 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
106 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
107 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
108 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
109 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
110 #ifdef CONFIG_USER_ONLY
111 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
112 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
113 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
114 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
118 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
119 fprintf_function cpu_fprintf
, int flags
)
121 ARMCPU
*cpu
= ARM_CPU(cs
);
122 CPUARMState
*env
= &cpu
->env
;
123 uint32_t psr
= pstate_read(env
);
126 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
127 env
->pc
, env
->xregs
[31]);
128 for (i
= 0; i
< 31; i
++) {
129 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
131 cpu_fprintf(f
, "\n");
136 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
138 psr
& PSTATE_N
? 'N' : '-',
139 psr
& PSTATE_Z
? 'Z' : '-',
140 psr
& PSTATE_C
? 'C' : '-',
141 psr
& PSTATE_V
? 'V' : '-');
142 cpu_fprintf(f
, "\n");
144 if (flags
& CPU_DUMP_FPU
) {
146 for (i
= 0; i
< numvfpregs
; i
+= 2) {
147 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
148 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
149 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
151 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
152 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
153 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
156 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
157 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
161 static int get_mem_index(DisasContext
*s
)
163 #ifdef CONFIG_USER_ONLY
170 void gen_a64_set_pc_im(uint64_t val
)
172 tcg_gen_movi_i64(cpu_pc
, val
);
175 static void gen_exception(int excp
)
177 TCGv_i32 tmp
= tcg_temp_new_i32();
178 tcg_gen_movi_i32(tmp
, excp
);
179 gen_helper_exception(cpu_env
, tmp
);
180 tcg_temp_free_i32(tmp
);
183 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
185 gen_a64_set_pc_im(s
->pc
- offset
);
187 s
->is_jmp
= DISAS_EXC
;
190 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
192 /* No direct tb linking with singlestep or deterministic io */
193 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
197 /* Only link tbs from inside the same guest page */
198 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
205 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
207 TranslationBlock
*tb
;
210 if (use_goto_tb(s
, n
, dest
)) {
212 gen_a64_set_pc_im(dest
);
213 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
214 s
->is_jmp
= DISAS_TB_JUMP
;
216 gen_a64_set_pc_im(dest
);
217 if (s
->singlestep_enabled
) {
218 gen_exception(EXCP_DEBUG
);
221 s
->is_jmp
= DISAS_JUMP
;
225 static void unallocated_encoding(DisasContext
*s
)
227 gen_exception_insn(s
, 4, EXCP_UDEF
);
230 #define unsupported_encoding(s, insn) \
232 qemu_log_mask(LOG_UNIMP, \
233 "%s:%d: unsupported instruction encoding 0x%08x " \
234 "at pc=%016" PRIx64 "\n", \
235 __FILE__, __LINE__, insn, s->pc - 4); \
236 unallocated_encoding(s); \
239 static void init_tmp_a64_array(DisasContext
*s
)
241 #ifdef CONFIG_DEBUG_TCG
243 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
244 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
247 s
->tmp_a64_count
= 0;
250 static void free_tmp_a64(DisasContext
*s
)
253 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
254 tcg_temp_free_i64(s
->tmp_a64
[i
]);
256 init_tmp_a64_array(s
);
259 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
261 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
262 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
265 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
267 TCGv_i64 t
= new_tmp_a64(s
);
268 tcg_gen_movi_i64(t
, 0);
273 * Register access functions
275 * These functions are used for directly accessing a register in where
276 * changes to the final register value are likely to be made. If you
277 * need to use a register for temporary calculation (e.g. index type
278 * operations) use the read_* form.
280 * B1.2.1 Register mappings
282 * In instruction register encoding 31 can refer to ZR (zero register) or
283 * the SP (stack pointer) depending on context. In QEMU's case we map SP
284 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
285 * This is the point of the _sp forms.
287 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
290 return new_tmp_a64_zero(s
);
296 /* register access for when 31 == SP */
297 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
302 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
303 * representing the register contents. This TCGv is an auto-freed
304 * temporary so it need not be explicitly freed, and may be modified.
306 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
308 TCGv_i64 v
= new_tmp_a64(s
);
311 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
313 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
316 tcg_gen_movi_i64(v
, 0);
321 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
323 TCGv_i64 v
= new_tmp_a64(s
);
325 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
327 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
332 /* Return the offset into CPUARMState of an element of specified
333 * size, 'element' places in from the least significant end of
334 * the FP/vector register Qn.
336 static inline int vec_reg_offset(int regno
, int element
, TCGMemOp size
)
338 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
339 #ifdef HOST_WORDS_BIGENDIAN
340 /* This is complicated slightly because vfp.regs[2n] is
341 * still the low half and vfp.regs[2n+1] the high half
342 * of the 128 bit vector, even on big endian systems.
343 * Calculate the offset assuming a fully bigendian 128 bits,
344 * then XOR to account for the order of the two 64 bit halves.
346 offs
+= (16 - ((element
+ 1) * (1 << size
)));
349 offs
+= element
* (1 << size
);
354 /* Return the offset into CPUARMState of a slice (from
355 * the least significant end) of FP register Qn (ie
357 * (Note that this is not the same mapping as for A32; see cpu.h)
359 static inline int fp_reg_offset(int regno
, TCGMemOp size
)
361 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
362 #ifdef HOST_WORDS_BIGENDIAN
363 offs
+= (8 - (1 << size
));
368 /* Offset of the high half of the 128 bit vector Qn */
369 static inline int fp_reg_hi_offset(int regno
)
371 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
374 /* Convenience accessors for reading and writing single and double
375 * FP registers. Writing clears the upper parts of the associated
376 * 128 bit vector register, as required by the architecture.
377 * Note that unlike the GP register accessors, the values returned
378 * by the read functions must be manually freed.
380 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
382 TCGv_i64 v
= tcg_temp_new_i64();
384 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
388 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
390 TCGv_i32 v
= tcg_temp_new_i32();
392 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(reg
, MO_32
));
396 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
398 TCGv_i64 tcg_zero
= tcg_const_i64(0);
400 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
401 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(reg
));
402 tcg_temp_free_i64(tcg_zero
);
405 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
407 TCGv_i64 tmp
= tcg_temp_new_i64();
409 tcg_gen_extu_i32_i64(tmp
, v
);
410 write_fp_dreg(s
, reg
, tmp
);
411 tcg_temp_free_i64(tmp
);
414 static TCGv_ptr
get_fpstatus_ptr(void)
416 TCGv_ptr statusptr
= tcg_temp_new_ptr();
419 /* In A64 all instructions (both FP and Neon) use the FPCR;
420 * there is no equivalent of the A32 Neon "standard FPSCR value"
421 * and all operations use vfp.fp_status.
423 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
424 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
428 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
429 * than the 32 bit equivalent.
431 static inline void gen_set_NZ64(TCGv_i64 result
)
433 TCGv_i64 flag
= tcg_temp_new_i64();
435 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
436 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
437 tcg_gen_shri_i64(flag
, result
, 32);
438 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
439 tcg_temp_free_i64(flag
);
442 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
443 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
446 gen_set_NZ64(result
);
448 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
449 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
451 tcg_gen_movi_i32(cpu_CF
, 0);
452 tcg_gen_movi_i32(cpu_VF
, 0);
455 /* dest = T0 + T1; compute C, N, V and Z flags */
456 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
459 TCGv_i64 result
, flag
, tmp
;
460 result
= tcg_temp_new_i64();
461 flag
= tcg_temp_new_i64();
462 tmp
= tcg_temp_new_i64();
464 tcg_gen_movi_i64(tmp
, 0);
465 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
467 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
469 gen_set_NZ64(result
);
471 tcg_gen_xor_i64(flag
, result
, t0
);
472 tcg_gen_xor_i64(tmp
, t0
, t1
);
473 tcg_gen_andc_i64(flag
, flag
, tmp
);
474 tcg_temp_free_i64(tmp
);
475 tcg_gen_shri_i64(flag
, flag
, 32);
476 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
478 tcg_gen_mov_i64(dest
, result
);
479 tcg_temp_free_i64(result
);
480 tcg_temp_free_i64(flag
);
482 /* 32 bit arithmetic */
483 TCGv_i32 t0_32
= tcg_temp_new_i32();
484 TCGv_i32 t1_32
= tcg_temp_new_i32();
485 TCGv_i32 tmp
= tcg_temp_new_i32();
487 tcg_gen_movi_i32(tmp
, 0);
488 tcg_gen_trunc_i64_i32(t0_32
, t0
);
489 tcg_gen_trunc_i64_i32(t1_32
, t1
);
490 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
491 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
492 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
493 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
494 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
495 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
497 tcg_temp_free_i32(tmp
);
498 tcg_temp_free_i32(t0_32
);
499 tcg_temp_free_i32(t1_32
);
503 /* dest = T0 - T1; compute C, N, V and Z flags */
504 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
507 /* 64 bit arithmetic */
508 TCGv_i64 result
, flag
, tmp
;
510 result
= tcg_temp_new_i64();
511 flag
= tcg_temp_new_i64();
512 tcg_gen_sub_i64(result
, t0
, t1
);
514 gen_set_NZ64(result
);
516 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
517 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
519 tcg_gen_xor_i64(flag
, result
, t0
);
520 tmp
= tcg_temp_new_i64();
521 tcg_gen_xor_i64(tmp
, t0
, t1
);
522 tcg_gen_and_i64(flag
, flag
, tmp
);
523 tcg_temp_free_i64(tmp
);
524 tcg_gen_shri_i64(flag
, flag
, 32);
525 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
526 tcg_gen_mov_i64(dest
, result
);
527 tcg_temp_free_i64(flag
);
528 tcg_temp_free_i64(result
);
530 /* 32 bit arithmetic */
531 TCGv_i32 t0_32
= tcg_temp_new_i32();
532 TCGv_i32 t1_32
= tcg_temp_new_i32();
535 tcg_gen_trunc_i64_i32(t0_32
, t0
);
536 tcg_gen_trunc_i64_i32(t1_32
, t1
);
537 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
538 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
539 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
540 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
541 tmp
= tcg_temp_new_i32();
542 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
543 tcg_temp_free_i32(t0_32
);
544 tcg_temp_free_i32(t1_32
);
545 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
546 tcg_temp_free_i32(tmp
);
547 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
551 /* dest = T0 + T1 + CF; do not compute flags. */
552 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
554 TCGv_i64 flag
= tcg_temp_new_i64();
555 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
556 tcg_gen_add_i64(dest
, t0
, t1
);
557 tcg_gen_add_i64(dest
, dest
, flag
);
558 tcg_temp_free_i64(flag
);
561 tcg_gen_ext32u_i64(dest
, dest
);
565 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
566 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
569 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
570 result
= tcg_temp_new_i64();
571 cf_64
= tcg_temp_new_i64();
572 vf_64
= tcg_temp_new_i64();
573 tmp
= tcg_const_i64(0);
575 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
576 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
577 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
578 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
579 gen_set_NZ64(result
);
581 tcg_gen_xor_i64(vf_64
, result
, t0
);
582 tcg_gen_xor_i64(tmp
, t0
, t1
);
583 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
584 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
585 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
587 tcg_gen_mov_i64(dest
, result
);
589 tcg_temp_free_i64(tmp
);
590 tcg_temp_free_i64(vf_64
);
591 tcg_temp_free_i64(cf_64
);
592 tcg_temp_free_i64(result
);
594 TCGv_i32 t0_32
, t1_32
, tmp
;
595 t0_32
= tcg_temp_new_i32();
596 t1_32
= tcg_temp_new_i32();
597 tmp
= tcg_const_i32(0);
599 tcg_gen_trunc_i64_i32(t0_32
, t0
);
600 tcg_gen_trunc_i64_i32(t1_32
, t1
);
601 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
602 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
604 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
605 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
606 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
607 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
608 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
610 tcg_temp_free_i32(tmp
);
611 tcg_temp_free_i32(t1_32
);
612 tcg_temp_free_i32(t0_32
);
617 * Load/Store generators
621 * Store from GPR register to memory.
623 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
624 TCGv_i64 tcg_addr
, int size
, int memidx
)
627 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
630 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
631 TCGv_i64 tcg_addr
, int size
)
633 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
637 * Load from memory to GPR register
639 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
640 int size
, bool is_signed
, bool extend
, int memidx
)
642 TCGMemOp memop
= MO_TE
+ size
;
650 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
652 if (extend
&& is_signed
) {
654 tcg_gen_ext32u_i64(dest
, dest
);
658 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
659 int size
, bool is_signed
, bool extend
)
661 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
666 * Store from FP register to memory
668 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
670 /* This writes the bottom N bits of a 128 bit wide vector to memory */
671 TCGv_i64 tmp
= tcg_temp_new_i64();
672 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(srcidx
, MO_64
));
674 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
676 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
677 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
678 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
679 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(srcidx
));
680 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
681 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
682 tcg_temp_free_i64(tcg_hiaddr
);
685 tcg_temp_free_i64(tmp
);
689 * Load from memory to FP register
691 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
693 /* This always zero-extends and writes to a full 128 bit wide vector */
694 TCGv_i64 tmplo
= tcg_temp_new_i64();
698 TCGMemOp memop
= MO_TE
+ size
;
699 tmphi
= tcg_const_i64(0);
700 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
703 tmphi
= tcg_temp_new_i64();
704 tcg_hiaddr
= tcg_temp_new_i64();
706 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
707 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
708 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
709 tcg_temp_free_i64(tcg_hiaddr
);
712 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(destidx
, MO_64
));
713 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(destidx
));
715 tcg_temp_free_i64(tmplo
);
716 tcg_temp_free_i64(tmphi
);
720 * Vector load/store helpers.
722 * The principal difference between this and a FP load is that we don't
723 * zero extend as we are filling a partial chunk of the vector register.
724 * These functions don't support 128 bit loads/stores, which would be
725 * normal load/store operations.
727 * The _i32 versions are useful when operating on 32 bit quantities
728 * (eg for floating point single or using Neon helper functions).
731 /* Get value of an element within a vector register */
732 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
733 int element
, TCGMemOp memop
)
735 int vect_off
= vec_reg_offset(srcidx
, element
, memop
& MO_SIZE
);
738 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
741 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
744 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
747 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
750 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
753 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
757 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
760 g_assert_not_reached();
764 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
765 int element
, TCGMemOp memop
)
767 int vect_off
= vec_reg_offset(srcidx
, element
, memop
& MO_SIZE
);
770 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
773 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
776 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
779 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
783 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
786 g_assert_not_reached();
790 /* Set value of an element within a vector register */
791 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
792 int element
, TCGMemOp memop
)
794 int vect_off
= vec_reg_offset(destidx
, element
, memop
& MO_SIZE
);
797 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
800 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
803 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
806 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
809 g_assert_not_reached();
813 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
814 int destidx
, int element
, TCGMemOp memop
)
816 int vect_off
= vec_reg_offset(destidx
, element
, memop
& MO_SIZE
);
819 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
822 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
825 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
828 g_assert_not_reached();
832 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
833 * vector ops all need to do this).
835 static void clear_vec_high(DisasContext
*s
, int rd
)
837 TCGv_i64 tcg_zero
= tcg_const_i64(0);
839 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
840 tcg_temp_free_i64(tcg_zero
);
843 /* Store from vector register to memory */
844 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
845 TCGv_i64 tcg_addr
, int size
)
847 TCGMemOp memop
= MO_TE
+ size
;
848 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
850 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
851 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
853 tcg_temp_free_i64(tcg_tmp
);
856 /* Load from memory to vector register */
857 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
858 TCGv_i64 tcg_addr
, int size
)
860 TCGMemOp memop
= MO_TE
+ size
;
861 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
863 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
864 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
866 tcg_temp_free_i64(tcg_tmp
);
870 * This utility function is for doing register extension with an
871 * optional shift. You will likely want to pass a temporary for the
872 * destination register. See DecodeRegExtend() in the ARM ARM.
874 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
875 int option
, unsigned int shift
)
877 int extsize
= extract32(option
, 0, 2);
878 bool is_signed
= extract32(option
, 2, 1);
883 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
886 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
889 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
892 tcg_gen_mov_i64(tcg_out
, tcg_in
);
898 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
901 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
904 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
907 tcg_gen_mov_i64(tcg_out
, tcg_in
);
913 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
917 static inline void gen_check_sp_alignment(DisasContext
*s
)
919 /* The AArch64 architecture mandates that (if enabled via PSTATE
920 * or SCTLR bits) there is a check that SP is 16-aligned on every
921 * SP-relative load or store (with an exception generated if it is not).
922 * In line with general QEMU practice regarding misaligned accesses,
923 * we omit these checks for the sake of guest program performance.
924 * This function is provided as a hook so we can more easily add these
925 * checks in future (possibly as a "favour catching guest program bugs
926 * over speed" user selectable option).
931 * This provides a simple table based table lookup decoder. It is
932 * intended to be used when the relevant bits for decode are too
933 * awkwardly placed and switch/if based logic would be confusing and
934 * deeply nested. Since it's a linear search through the table, tables
935 * should be kept small.
937 * It returns the first handler where insn & mask == pattern, or
938 * NULL if there is no match.
939 * The table is terminated by an empty mask (i.e. 0)
941 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
944 const AArch64DecodeTable
*tptr
= table
;
947 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
948 return tptr
->disas_fn
;
956 * the instruction disassembly implemented here matches
957 * the instruction encoding classifications in chapter 3 (C3)
958 * of the ARM Architecture Reference Manual (DDI0487A_a)
961 /* C3.2.7 Unconditional branch (immediate)
963 * +----+-----------+-------------------------------------+
964 * | op | 0 0 1 0 1 | imm26 |
965 * +----+-----------+-------------------------------------+
967 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
969 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
971 if (insn
& (1 << 31)) {
972 /* C5.6.26 BL Branch with link */
973 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
976 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
977 gen_goto_tb(s
, 0, addr
);
980 /* C3.2.1 Compare & branch (immediate)
981 * 31 30 25 24 23 5 4 0
982 * +----+-------------+----+---------------------+--------+
983 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
984 * +----+-------------+----+---------------------+--------+
986 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
988 unsigned int sf
, op
, rt
;
993 sf
= extract32(insn
, 31, 1);
994 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
995 rt
= extract32(insn
, 0, 5);
996 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
998 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
999 label_match
= gen_new_label();
1001 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1002 tcg_cmp
, 0, label_match
);
1004 gen_goto_tb(s
, 0, s
->pc
);
1005 gen_set_label(label_match
);
1006 gen_goto_tb(s
, 1, addr
);
1009 /* C3.2.5 Test & branch (immediate)
1010 * 31 30 25 24 23 19 18 5 4 0
1011 * +----+-------------+----+-------+-------------+------+
1012 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1013 * +----+-------------+----+-------+-------------+------+
1015 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1017 unsigned int bit_pos
, op
, rt
;
1022 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1023 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1024 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1025 rt
= extract32(insn
, 0, 5);
1027 tcg_cmp
= tcg_temp_new_i64();
1028 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1029 label_match
= gen_new_label();
1030 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1031 tcg_cmp
, 0, label_match
);
1032 tcg_temp_free_i64(tcg_cmp
);
1033 gen_goto_tb(s
, 0, s
->pc
);
1034 gen_set_label(label_match
);
1035 gen_goto_tb(s
, 1, addr
);
1038 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1039 * 31 25 24 23 5 4 3 0
1040 * +---------------+----+---------------------+----+------+
1041 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1042 * +---------------+----+---------------------+----+------+
1044 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1049 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1050 unallocated_encoding(s
);
1053 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1054 cond
= extract32(insn
, 0, 4);
1057 /* genuinely conditional branches */
1058 int label_match
= gen_new_label();
1059 arm_gen_test_cc(cond
, label_match
);
1060 gen_goto_tb(s
, 0, s
->pc
);
1061 gen_set_label(label_match
);
1062 gen_goto_tb(s
, 1, addr
);
1064 /* 0xe and 0xf are both "always" conditions */
1065 gen_goto_tb(s
, 0, addr
);
1070 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1071 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1073 unsigned int selector
= crm
<< 3 | op2
;
1076 unallocated_encoding(s
);
1084 s
->is_jmp
= DISAS_WFI
;
1090 /* we treat all as NOP at least for now */
1093 /* default specified as NOP equivalent */
1098 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1100 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1103 /* CLREX, DSB, DMB, ISB */
1104 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1105 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1108 unallocated_encoding(s
);
1119 /* We don't emulate caches so barriers are no-ops */
1122 unallocated_encoding(s
);
1127 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1128 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1129 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1131 int op
= op1
<< 3 | op2
;
1133 case 0x05: /* SPSel */
1134 if (s
->current_pl
== 0) {
1135 unallocated_encoding(s
);
1139 case 0x1e: /* DAIFSet */
1140 case 0x1f: /* DAIFClear */
1142 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1143 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1144 gen_a64_set_pc_im(s
->pc
- 4);
1145 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1146 tcg_temp_free_i32(tcg_imm
);
1147 tcg_temp_free_i32(tcg_op
);
1148 s
->is_jmp
= DISAS_UPDATE
;
1152 unallocated_encoding(s
);
1157 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1159 TCGv_i32 tmp
= tcg_temp_new_i32();
1160 TCGv_i32 nzcv
= tcg_temp_new_i32();
1162 /* build bit 31, N */
1163 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1164 /* build bit 30, Z */
1165 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1166 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1167 /* build bit 29, C */
1168 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1169 /* build bit 28, V */
1170 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1171 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1172 /* generate result */
1173 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1175 tcg_temp_free_i32(nzcv
);
1176 tcg_temp_free_i32(tmp
);
1179 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1182 TCGv_i32 nzcv
= tcg_temp_new_i32();
1184 /* take NZCV from R[t] */
1185 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1188 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1190 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1191 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1193 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1194 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1196 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1197 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1198 tcg_temp_free_i32(nzcv
);
1201 /* C5.6.129 MRS - move from system register
1202 * C5.6.131 MSR (register) - move to system register
1205 * These are all essentially the same insn in 'read' and 'write'
1206 * versions, with varying op0 fields.
1208 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1209 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1210 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1212 const ARMCPRegInfo
*ri
;
1215 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1216 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1217 crn
, crm
, op0
, op1
, op2
));
1220 /* Unknown register; this might be a guest error or a QEMU
1221 * unimplemented feature.
1223 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1224 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1225 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1226 unallocated_encoding(s
);
1230 /* Check access permissions */
1231 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1232 unallocated_encoding(s
);
1237 /* Emit code to perform further access permissions checks at
1238 * runtime; this may result in an exception.
1241 gen_a64_set_pc_im(s
->pc
- 4);
1242 tmpptr
= tcg_const_ptr(ri
);
1243 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
);
1244 tcg_temp_free_ptr(tmpptr
);
1247 /* Handle special cases first */
1248 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1252 tcg_rt
= cpu_reg(s
, rt
);
1254 gen_get_nzcv(tcg_rt
);
1256 gen_set_nzcv(tcg_rt
);
1259 case ARM_CP_CURRENTEL
:
1260 /* Reads as current EL value from pstate, which is
1261 * guaranteed to be constant by the tb flags.
1263 tcg_rt
= cpu_reg(s
, rt
);
1264 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1270 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1274 tcg_rt
= cpu_reg(s
, rt
);
1277 if (ri
->type
& ARM_CP_CONST
) {
1278 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1279 } else if (ri
->readfn
) {
1281 tmpptr
= tcg_const_ptr(ri
);
1282 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1283 tcg_temp_free_ptr(tmpptr
);
1285 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1288 if (ri
->type
& ARM_CP_CONST
) {
1289 /* If not forbidden by access permissions, treat as WI */
1291 } else if (ri
->writefn
) {
1293 tmpptr
= tcg_const_ptr(ri
);
1294 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1295 tcg_temp_free_ptr(tmpptr
);
1297 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1301 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1302 /* I/O operations must end the TB here (whether read or write) */
1304 s
->is_jmp
= DISAS_UPDATE
;
1305 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1306 /* We default to ending the TB on a coprocessor register write,
1307 * but allow this to be suppressed by the register definition
1308 * (usually only necessary to work around guest bugs).
1310 s
->is_jmp
= DISAS_UPDATE
;
1315 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1316 * +---------------------+---+-----+-----+-------+-------+-----+------+
1317 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1318 * +---------------------+---+-----+-----+-------+-------+-----+------+
1320 static void disas_system(DisasContext
*s
, uint32_t insn
)
1322 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1323 l
= extract32(insn
, 21, 1);
1324 op0
= extract32(insn
, 19, 2);
1325 op1
= extract32(insn
, 16, 3);
1326 crn
= extract32(insn
, 12, 4);
1327 crm
= extract32(insn
, 8, 4);
1328 op2
= extract32(insn
, 5, 3);
1329 rt
= extract32(insn
, 0, 5);
1332 if (l
|| rt
!= 31) {
1333 unallocated_encoding(s
);
1337 case 2: /* C5.6.68 HINT */
1338 handle_hint(s
, insn
, op1
, op2
, crm
);
1340 case 3: /* CLREX, DSB, DMB, ISB */
1341 handle_sync(s
, insn
, op1
, op2
, crm
);
1343 case 4: /* C5.6.130 MSR (immediate) */
1344 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1347 unallocated_encoding(s
);
1352 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1355 /* C3.2.3 Exception generation
1357 * 31 24 23 21 20 5 4 2 1 0
1358 * +-----------------+-----+------------------------+-----+----+
1359 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1360 * +-----------------------+------------------------+----------+
1362 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1364 int opc
= extract32(insn
, 21, 3);
1365 int op2_ll
= extract32(insn
, 0, 5);
1369 /* SVC, HVC, SMC; since we don't support the Virtualization
1370 * or TrustZone extensions these all UNDEF except SVC.
1373 unallocated_encoding(s
);
1376 gen_exception_insn(s
, 0, EXCP_SWI
);
1380 unallocated_encoding(s
);
1384 gen_exception_insn(s
, 0, EXCP_BKPT
);
1388 unallocated_encoding(s
);
1392 unsupported_encoding(s
, insn
);
1395 if (op2_ll
< 1 || op2_ll
> 3) {
1396 unallocated_encoding(s
);
1399 /* DCPS1, DCPS2, DCPS3 */
1400 unsupported_encoding(s
, insn
);
1403 unallocated_encoding(s
);
1408 /* C3.2.7 Unconditional branch (register)
1409 * 31 25 24 21 20 16 15 10 9 5 4 0
1410 * +---------------+-------+-------+-------+------+-------+
1411 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1412 * +---------------+-------+-------+-------+------+-------+
1414 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1416 unsigned int opc
, op2
, op3
, rn
, op4
;
1418 opc
= extract32(insn
, 21, 4);
1419 op2
= extract32(insn
, 16, 5);
1420 op3
= extract32(insn
, 10, 6);
1421 rn
= extract32(insn
, 5, 5);
1422 op4
= extract32(insn
, 0, 5);
1424 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1425 unallocated_encoding(s
);
1434 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1439 unallocated_encoding(s
);
1441 unsupported_encoding(s
, insn
);
1445 unallocated_encoding(s
);
1449 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1450 s
->is_jmp
= DISAS_JUMP
;
1453 /* C3.2 Branches, exception generating and system instructions */
1454 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1456 switch (extract32(insn
, 25, 7)) {
1457 case 0x0a: case 0x0b:
1458 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1459 disas_uncond_b_imm(s
, insn
);
1461 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1462 disas_comp_b_imm(s
, insn
);
1464 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1465 disas_test_b_imm(s
, insn
);
1467 case 0x2a: /* Conditional branch (immediate) */
1468 disas_cond_b_imm(s
, insn
);
1470 case 0x6a: /* Exception generation / System */
1471 if (insn
& (1 << 24)) {
1472 disas_system(s
, insn
);
1477 case 0x6b: /* Unconditional branch (register) */
1478 disas_uncond_b_reg(s
, insn
);
1481 unallocated_encoding(s
);
1487 * Load/Store exclusive instructions are implemented by remembering
1488 * the value/address loaded, and seeing if these are the same
1489 * when the store is performed. This is not actually the architecturally
1490 * mandated semantics, but it works for typical guest code sequences
1491 * and avoids having to monitor regular stores.
1493 * In system emulation mode only one CPU will be running at once, so
1494 * this sequence is effectively atomic. In user emulation mode we
1495 * throw an exception and handle the atomic operation elsewhere.
1497 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1498 TCGv_i64 addr
, int size
, bool is_pair
)
1500 TCGv_i64 tmp
= tcg_temp_new_i64();
1501 TCGMemOp memop
= MO_TE
+ size
;
1503 g_assert(size
<= 3);
1504 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1507 TCGv_i64 addr2
= tcg_temp_new_i64();
1508 TCGv_i64 hitmp
= tcg_temp_new_i64();
1510 g_assert(size
>= 2);
1511 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1512 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1513 tcg_temp_free_i64(addr2
);
1514 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1515 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1516 tcg_temp_free_i64(hitmp
);
1519 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1520 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1522 tcg_temp_free_i64(tmp
);
1523 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1526 #ifdef CONFIG_USER_ONLY
1527 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1528 TCGv_i64 addr
, int size
, int is_pair
)
1530 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1531 tcg_gen_movi_i32(cpu_exclusive_info
,
1532 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1533 gen_exception_insn(s
, 4, EXCP_STREX
);
1536 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1537 TCGv_i64 inaddr
, int size
, int is_pair
)
1539 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1540 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1543 * [addr + datasize] = {Rt2};
1549 * env->exclusive_addr = -1;
1551 int fail_label
= gen_new_label();
1552 int done_label
= gen_new_label();
1553 TCGv_i64 addr
= tcg_temp_local_new_i64();
1556 /* Copy input into a local temp so it is not trashed when the
1557 * basic block ends at the branch insn.
1559 tcg_gen_mov_i64(addr
, inaddr
);
1560 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1562 tmp
= tcg_temp_new_i64();
1563 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1564 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1565 tcg_temp_free_i64(tmp
);
1568 TCGv_i64 addrhi
= tcg_temp_new_i64();
1569 TCGv_i64 tmphi
= tcg_temp_new_i64();
1571 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1572 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1573 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1575 tcg_temp_free_i64(tmphi
);
1576 tcg_temp_free_i64(addrhi
);
1579 /* We seem to still have the exclusive monitor, so do the store */
1580 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1582 TCGv_i64 addrhi
= tcg_temp_new_i64();
1584 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1585 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1586 get_mem_index(s
), MO_TE
+ size
);
1587 tcg_temp_free_i64(addrhi
);
1590 tcg_temp_free_i64(addr
);
1592 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1593 tcg_gen_br(done_label
);
1594 gen_set_label(fail_label
);
1595 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1596 gen_set_label(done_label
);
1597 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1602 /* C3.3.6 Load/store exclusive
1604 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1605 * +-----+-------------+----+---+----+------+----+-------+------+------+
1606 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1607 * +-----+-------------+----+---+----+------+----+-------+------+------+
1609 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1610 * L: 0 -> store, 1 -> load
1611 * o2: 0 -> exclusive, 1 -> not
1612 * o1: 0 -> single register, 1 -> register pair
1613 * o0: 1 -> load-acquire/store-release, 0 -> not
1615 * o0 == 0 AND o2 == 1 is un-allocated
1616 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1618 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1620 int rt
= extract32(insn
, 0, 5);
1621 int rn
= extract32(insn
, 5, 5);
1622 int rt2
= extract32(insn
, 10, 5);
1623 int is_lasr
= extract32(insn
, 15, 1);
1624 int rs
= extract32(insn
, 16, 5);
1625 int is_pair
= extract32(insn
, 21, 1);
1626 int is_store
= !extract32(insn
, 22, 1);
1627 int is_excl
= !extract32(insn
, 23, 1);
1628 int size
= extract32(insn
, 30, 2);
1631 if ((!is_excl
&& !is_lasr
) ||
1632 (is_pair
&& size
< 2)) {
1633 unallocated_encoding(s
);
1638 gen_check_sp_alignment(s
);
1640 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1642 /* Note that since TCG is single threaded load-acquire/store-release
1643 * semantics require no extra if (is_lasr) { ... } handling.
1648 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1650 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1653 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1655 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1657 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1660 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1661 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1663 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1665 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1672 * C3.3.5 Load register (literal)
1674 * 31 30 29 27 26 25 24 23 5 4 0
1675 * +-----+-------+---+-----+-------------------+-------+
1676 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1677 * +-----+-------+---+-----+-------------------+-------+
1679 * V: 1 -> vector (simd/fp)
1680 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1681 * 10-> 32 bit signed, 11 -> prefetch
1682 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1684 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1686 int rt
= extract32(insn
, 0, 5);
1687 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1688 bool is_vector
= extract32(insn
, 26, 1);
1689 int opc
= extract32(insn
, 30, 2);
1690 bool is_signed
= false;
1692 TCGv_i64 tcg_rt
, tcg_addr
;
1696 unallocated_encoding(s
);
1702 /* PRFM (literal) : prefetch */
1705 size
= 2 + extract32(opc
, 0, 1);
1706 is_signed
= extract32(opc
, 1, 1);
1709 tcg_rt
= cpu_reg(s
, rt
);
1711 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1713 do_fp_ld(s
, rt
, tcg_addr
, size
);
1715 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1717 tcg_temp_free_i64(tcg_addr
);
1721 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1722 * C5.6.81 LDP (Load Pair - non vector)
1723 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1724 * C5.6.176 STNP (Store Pair - non-temporal hint)
1725 * C5.6.177 STP (Store Pair - non vector)
1726 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1727 * C6.3.165 LDP (Load Pair of SIMD&FP)
1728 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1729 * C6.3.284 STP (Store Pair of SIMD&FP)
1731 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1732 * +-----+-------+---+---+-------+---+-----------------------------+
1733 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1734 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1736 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1738 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1739 * V: 0 -> GPR, 1 -> Vector
1740 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1741 * 10 -> signed offset, 11 -> pre-index
1742 * L: 0 -> Store 1 -> Load
1744 * Rt, Rt2 = GPR or SIMD registers to be stored
1745 * Rn = general purpose register containing address
1746 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1748 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1750 int rt
= extract32(insn
, 0, 5);
1751 int rn
= extract32(insn
, 5, 5);
1752 int rt2
= extract32(insn
, 10, 5);
1753 int64_t offset
= sextract32(insn
, 15, 7);
1754 int index
= extract32(insn
, 23, 2);
1755 bool is_vector
= extract32(insn
, 26, 1);
1756 bool is_load
= extract32(insn
, 22, 1);
1757 int opc
= extract32(insn
, 30, 2);
1759 bool is_signed
= false;
1760 bool postindex
= false;
1763 TCGv_i64 tcg_addr
; /* calculated address */
1767 unallocated_encoding(s
);
1774 size
= 2 + extract32(opc
, 1, 1);
1775 is_signed
= extract32(opc
, 0, 1);
1776 if (!is_load
&& is_signed
) {
1777 unallocated_encoding(s
);
1783 case 1: /* post-index */
1788 /* signed offset with "non-temporal" hint. Since we don't emulate
1789 * caches we don't care about hints to the cache system about
1790 * data access patterns, and handle this identically to plain
1794 /* There is no non-temporal-hint version of LDPSW */
1795 unallocated_encoding(s
);
1800 case 2: /* signed offset, rn not updated */
1803 case 3: /* pre-index */
1812 gen_check_sp_alignment(s
);
1815 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1818 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1823 do_fp_ld(s
, rt
, tcg_addr
, size
);
1825 do_fp_st(s
, rt
, tcg_addr
, size
);
1828 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1830 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1832 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1835 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1838 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1840 do_fp_st(s
, rt2
, tcg_addr
, size
);
1843 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1845 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1847 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1853 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1855 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1857 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1862 * C3.3.8 Load/store (immediate post-indexed)
1863 * C3.3.9 Load/store (immediate pre-indexed)
1864 * C3.3.12 Load/store (unscaled immediate)
1866 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1867 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1868 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1869 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1871 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1873 * V = 0 -> non-vector
1874 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1875 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1877 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1879 int rt
= extract32(insn
, 0, 5);
1880 int rn
= extract32(insn
, 5, 5);
1881 int imm9
= sextract32(insn
, 12, 9);
1882 int opc
= extract32(insn
, 22, 2);
1883 int size
= extract32(insn
, 30, 2);
1884 int idx
= extract32(insn
, 10, 2);
1885 bool is_signed
= false;
1886 bool is_store
= false;
1887 bool is_extended
= false;
1888 bool is_unpriv
= (idx
== 2);
1889 bool is_vector
= extract32(insn
, 26, 1);
1896 size
|= (opc
& 2) << 1;
1897 if (size
> 4 || is_unpriv
) {
1898 unallocated_encoding(s
);
1901 is_store
= ((opc
& 1) == 0);
1903 if (size
== 3 && opc
== 2) {
1904 /* PRFM - prefetch */
1906 unallocated_encoding(s
);
1911 if (opc
== 3 && size
> 1) {
1912 unallocated_encoding(s
);
1915 is_store
= (opc
== 0);
1916 is_signed
= opc
& (1<<1);
1917 is_extended
= (size
< 3) && (opc
& 1);
1937 gen_check_sp_alignment(s
);
1939 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1942 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1947 do_fp_st(s
, rt
, tcg_addr
, size
);
1949 do_fp_ld(s
, rt
, tcg_addr
, size
);
1952 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1953 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
1956 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
1958 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
1959 is_signed
, is_extended
, memidx
);
1964 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1966 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1968 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
1973 * C3.3.10 Load/store (register offset)
1975 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1976 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1977 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1978 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1981 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1982 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1984 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1985 * opc<0>: 0 -> store, 1 -> load
1986 * V: 1 -> vector/simd
1987 * opt: extend encoding (see DecodeRegExtend)
1988 * S: if S=1 then scale (essentially index by sizeof(size))
1989 * Rt: register to transfer into/out of
1990 * Rn: address register or SP for base
1991 * Rm: offset register or ZR for offset
1993 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
1995 int rt
= extract32(insn
, 0, 5);
1996 int rn
= extract32(insn
, 5, 5);
1997 int shift
= extract32(insn
, 12, 1);
1998 int rm
= extract32(insn
, 16, 5);
1999 int opc
= extract32(insn
, 22, 2);
2000 int opt
= extract32(insn
, 13, 3);
2001 int size
= extract32(insn
, 30, 2);
2002 bool is_signed
= false;
2003 bool is_store
= false;
2004 bool is_extended
= false;
2005 bool is_vector
= extract32(insn
, 26, 1);
2010 if (extract32(opt
, 1, 1) == 0) {
2011 unallocated_encoding(s
);
2016 size
|= (opc
& 2) << 1;
2018 unallocated_encoding(s
);
2021 is_store
= !extract32(opc
, 0, 1);
2023 if (size
== 3 && opc
== 2) {
2024 /* PRFM - prefetch */
2027 if (opc
== 3 && size
> 1) {
2028 unallocated_encoding(s
);
2031 is_store
= (opc
== 0);
2032 is_signed
= extract32(opc
, 1, 1);
2033 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2037 gen_check_sp_alignment(s
);
2039 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2041 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2042 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2044 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2048 do_fp_st(s
, rt
, tcg_addr
, size
);
2050 do_fp_ld(s
, rt
, tcg_addr
, size
);
2053 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2055 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2057 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2063 * C3.3.13 Load/store (unsigned immediate)
2065 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2066 * +----+-------+---+-----+-----+------------+-------+------+
2067 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2068 * +----+-------+---+-----+-----+------------+-------+------+
2071 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2072 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2074 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2075 * opc<0>: 0 -> store, 1 -> load
2076 * Rn: base address register (inc SP)
2077 * Rt: target register
2079 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2081 int rt
= extract32(insn
, 0, 5);
2082 int rn
= extract32(insn
, 5, 5);
2083 unsigned int imm12
= extract32(insn
, 10, 12);
2084 bool is_vector
= extract32(insn
, 26, 1);
2085 int size
= extract32(insn
, 30, 2);
2086 int opc
= extract32(insn
, 22, 2);
2087 unsigned int offset
;
2092 bool is_signed
= false;
2093 bool is_extended
= false;
2096 size
|= (opc
& 2) << 1;
2098 unallocated_encoding(s
);
2101 is_store
= !extract32(opc
, 0, 1);
2103 if (size
== 3 && opc
== 2) {
2104 /* PRFM - prefetch */
2107 if (opc
== 3 && size
> 1) {
2108 unallocated_encoding(s
);
2111 is_store
= (opc
== 0);
2112 is_signed
= extract32(opc
, 1, 1);
2113 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2117 gen_check_sp_alignment(s
);
2119 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2120 offset
= imm12
<< size
;
2121 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2125 do_fp_st(s
, rt
, tcg_addr
, size
);
2127 do_fp_ld(s
, rt
, tcg_addr
, size
);
2130 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2132 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2134 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2139 /* Load/store register (all forms) */
2140 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2142 switch (extract32(insn
, 24, 2)) {
2144 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2145 disas_ldst_reg_roffset(s
, insn
);
2147 /* Load/store register (unscaled immediate)
2148 * Load/store immediate pre/post-indexed
2149 * Load/store register unprivileged
2151 disas_ldst_reg_imm9(s
, insn
);
2155 disas_ldst_reg_unsigned_imm(s
, insn
);
2158 unallocated_encoding(s
);
2163 /* C3.3.1 AdvSIMD load/store multiple structures
2165 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2166 * +---+---+---------------+---+-------------+--------+------+------+------+
2167 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2168 * +---+---+---------------+---+-------------+--------+------+------+------+
2170 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2172 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2173 * +---+---+---------------+---+---+---------+--------+------+------+------+
2174 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2175 * +---+---+---------------+---+---+---------+--------+------+------+------+
2177 * Rt: first (or only) SIMD&FP register to be transferred
2178 * Rn: base address or SP
2179 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2181 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2183 int rt
= extract32(insn
, 0, 5);
2184 int rn
= extract32(insn
, 5, 5);
2185 int size
= extract32(insn
, 10, 2);
2186 int opcode
= extract32(insn
, 12, 4);
2187 bool is_store
= !extract32(insn
, 22, 1);
2188 bool is_postidx
= extract32(insn
, 23, 1);
2189 bool is_q
= extract32(insn
, 30, 1);
2190 TCGv_i64 tcg_addr
, tcg_rn
;
2192 int ebytes
= 1 << size
;
2193 int elements
= (is_q
? 128 : 64) / (8 << size
);
2194 int rpt
; /* num iterations */
2195 int selem
; /* structure elements */
2198 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2199 unallocated_encoding(s
);
2203 /* From the shared decode logic */
2234 unallocated_encoding(s
);
2238 if (size
== 3 && !is_q
&& selem
!= 1) {
2240 unallocated_encoding(s
);
2245 gen_check_sp_alignment(s
);
2248 tcg_rn
= cpu_reg_sp(s
, rn
);
2249 tcg_addr
= tcg_temp_new_i64();
2250 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2252 for (r
= 0; r
< rpt
; r
++) {
2254 for (e
= 0; e
< elements
; e
++) {
2255 int tt
= (rt
+ r
) % 32;
2257 for (xs
= 0; xs
< selem
; xs
++) {
2259 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2261 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2263 /* For non-quad operations, setting a slice of the low
2264 * 64 bits of the register clears the high 64 bits (in
2265 * the ARM ARM pseudocode this is implicit in the fact
2266 * that 'rval' is a 64 bit wide variable). We optimize
2267 * by noticing that we only need to do this the first
2268 * time we touch a register.
2270 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2271 clear_vec_high(s
, tt
);
2274 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2281 int rm
= extract32(insn
, 16, 5);
2283 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2285 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2288 tcg_temp_free_i64(tcg_addr
);
2291 /* C3.3.3 AdvSIMD load/store single structure
2293 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2294 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2295 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2296 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2298 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2300 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2301 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2302 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2303 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2305 * Rt: first (or only) SIMD&FP register to be transferred
2306 * Rn: base address or SP
2307 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2308 * index = encoded in Q:S:size dependent on size
2310 * lane_size = encoded in R, opc
2311 * transfer width = encoded in opc, S, size
2313 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2315 int rt
= extract32(insn
, 0, 5);
2316 int rn
= extract32(insn
, 5, 5);
2317 int size
= extract32(insn
, 10, 2);
2318 int S
= extract32(insn
, 12, 1);
2319 int opc
= extract32(insn
, 13, 3);
2320 int R
= extract32(insn
, 21, 1);
2321 int is_load
= extract32(insn
, 22, 1);
2322 int is_postidx
= extract32(insn
, 23, 1);
2323 int is_q
= extract32(insn
, 30, 1);
2325 int scale
= extract32(opc
, 1, 2);
2326 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2327 bool replicate
= false;
2328 int index
= is_q
<< 3 | S
<< 2 | size
;
2330 TCGv_i64 tcg_addr
, tcg_rn
;
2334 if (!is_load
|| S
) {
2335 unallocated_encoding(s
);
2344 if (extract32(size
, 0, 1)) {
2345 unallocated_encoding(s
);
2351 if (extract32(size
, 1, 1)) {
2352 unallocated_encoding(s
);
2355 if (!extract32(size
, 0, 1)) {
2359 unallocated_encoding(s
);
2367 g_assert_not_reached();
2370 ebytes
= 1 << scale
;
2373 gen_check_sp_alignment(s
);
2376 tcg_rn
= cpu_reg_sp(s
, rn
);
2377 tcg_addr
= tcg_temp_new_i64();
2378 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2380 for (xs
= 0; xs
< selem
; xs
++) {
2382 /* Load and replicate to all elements */
2384 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2386 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2387 get_mem_index(s
), MO_TE
+ scale
);
2390 mulconst
= 0x0101010101010101ULL
;
2393 mulconst
= 0x0001000100010001ULL
;
2396 mulconst
= 0x0000000100000001ULL
;
2402 g_assert_not_reached();
2405 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2407 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2409 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2411 clear_vec_high(s
, rt
);
2413 tcg_temp_free_i64(tcg_tmp
);
2415 /* Load/store one element per register */
2417 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2419 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2422 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2427 int rm
= extract32(insn
, 16, 5);
2429 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2431 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2434 tcg_temp_free_i64(tcg_addr
);
2437 /* C3.3 Loads and stores */
2438 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2440 switch (extract32(insn
, 24, 6)) {
2441 case 0x08: /* Load/store exclusive */
2442 disas_ldst_excl(s
, insn
);
2444 case 0x18: case 0x1c: /* Load register (literal) */
2445 disas_ld_lit(s
, insn
);
2447 case 0x28: case 0x29:
2448 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2449 disas_ldst_pair(s
, insn
);
2451 case 0x38: case 0x39:
2452 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2453 disas_ldst_reg(s
, insn
);
2455 case 0x0c: /* AdvSIMD load/store multiple structures */
2456 disas_ldst_multiple_struct(s
, insn
);
2458 case 0x0d: /* AdvSIMD load/store single structure */
2459 disas_ldst_single_struct(s
, insn
);
2462 unallocated_encoding(s
);
2467 /* C3.4.6 PC-rel. addressing
2468 * 31 30 29 28 24 23 5 4 0
2469 * +----+-------+-----------+-------------------+------+
2470 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2471 * +----+-------+-----------+-------------------+------+
2473 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2475 unsigned int page
, rd
;
2479 page
= extract32(insn
, 31, 1);
2480 /* SignExtend(immhi:immlo) -> offset */
2481 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2482 rd
= extract32(insn
, 0, 5);
2486 /* ADRP (page based) */
2491 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2495 * C3.4.1 Add/subtract (immediate)
2497 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2498 * +--+--+--+-----------+-----+-------------+-----+-----+
2499 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2500 * +--+--+--+-----------+-----+-------------+-----+-----+
2502 * sf: 0 -> 32bit, 1 -> 64bit
2503 * op: 0 -> add , 1 -> sub
2505 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2507 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2509 int rd
= extract32(insn
, 0, 5);
2510 int rn
= extract32(insn
, 5, 5);
2511 uint64_t imm
= extract32(insn
, 10, 12);
2512 int shift
= extract32(insn
, 22, 2);
2513 bool setflags
= extract32(insn
, 29, 1);
2514 bool sub_op
= extract32(insn
, 30, 1);
2515 bool is_64bit
= extract32(insn
, 31, 1);
2517 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2518 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2519 TCGv_i64 tcg_result
;
2528 unallocated_encoding(s
);
2532 tcg_result
= tcg_temp_new_i64();
2535 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2537 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2540 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2542 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2544 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2546 tcg_temp_free_i64(tcg_imm
);
2550 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2552 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2555 tcg_temp_free_i64(tcg_result
);
2558 /* The input should be a value in the bottom e bits (with higher
2559 * bits zero); returns that value replicated into every element
2560 * of size e in a 64 bit integer.
2562 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2572 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2573 static inline uint64_t bitmask64(unsigned int length
)
2575 assert(length
> 0 && length
<= 64);
2576 return ~0ULL >> (64 - length
);
2579 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2580 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2581 * value (ie should cause a guest UNDEF exception), and true if they are
2582 * valid, in which case the decoded bit pattern is written to result.
2584 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2585 unsigned int imms
, unsigned int immr
)
2588 unsigned e
, levels
, s
, r
;
2591 assert(immn
< 2 && imms
< 64 && immr
< 64);
2593 /* The bit patterns we create here are 64 bit patterns which
2594 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2595 * 64 bits each. Each element contains the same value: a run
2596 * of between 1 and e-1 non-zero bits, rotated within the
2597 * element by between 0 and e-1 bits.
2599 * The element size and run length are encoded into immn (1 bit)
2600 * and imms (6 bits) as follows:
2601 * 64 bit elements: immn = 1, imms = <length of run - 1>
2602 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2603 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2604 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2605 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2606 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2607 * Notice that immn = 0, imms = 11111x is the only combination
2608 * not covered by one of the above options; this is reserved.
2609 * Further, <length of run - 1> all-ones is a reserved pattern.
2611 * In all cases the rotation is by immr % e (and immr is 6 bits).
2614 /* First determine the element size */
2615 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2617 /* This is the immn == 0, imms == 0x11111x case */
2627 /* <length of run - 1> mustn't be all-ones. */
2631 /* Create the value of one element: s+1 set bits rotated
2632 * by r within the element (which is e bits wide)...
2634 mask
= bitmask64(s
+ 1);
2635 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2636 /* ...then replicate the element over the whole 64 bit value */
2637 mask
= bitfield_replicate(mask
, e
);
2642 /* C3.4.4 Logical (immediate)
2643 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2644 * +----+-----+-------------+---+------+------+------+------+
2645 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2646 * +----+-----+-------------+---+------+------+------+------+
2648 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2650 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2651 TCGv_i64 tcg_rd
, tcg_rn
;
2653 bool is_and
= false;
2655 sf
= extract32(insn
, 31, 1);
2656 opc
= extract32(insn
, 29, 2);
2657 is_n
= extract32(insn
, 22, 1);
2658 immr
= extract32(insn
, 16, 6);
2659 imms
= extract32(insn
, 10, 6);
2660 rn
= extract32(insn
, 5, 5);
2661 rd
= extract32(insn
, 0, 5);
2664 unallocated_encoding(s
);
2668 if (opc
== 0x3) { /* ANDS */
2669 tcg_rd
= cpu_reg(s
, rd
);
2671 tcg_rd
= cpu_reg_sp(s
, rd
);
2673 tcg_rn
= cpu_reg(s
, rn
);
2675 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2676 /* some immediate field values are reserved */
2677 unallocated_encoding(s
);
2682 wmask
&= 0xffffffff;
2686 case 0x3: /* ANDS */
2688 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2692 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2695 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2698 assert(FALSE
); /* must handle all above */
2702 if (!sf
&& !is_and
) {
2703 /* zero extend final result; we know we can skip this for AND
2704 * since the immediate had the high 32 bits clear.
2706 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2709 if (opc
== 3) { /* ANDS */
2710 gen_logic_CC(sf
, tcg_rd
);
2715 * C3.4.5 Move wide (immediate)
2717 * 31 30 29 28 23 22 21 20 5 4 0
2718 * +--+-----+-------------+-----+----------------+------+
2719 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2720 * +--+-----+-------------+-----+----------------+------+
2722 * sf: 0 -> 32 bit, 1 -> 64 bit
2723 * opc: 00 -> N, 10 -> Z, 11 -> K
2724 * hw: shift/16 (0,16, and sf only 32, 48)
2726 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2728 int rd
= extract32(insn
, 0, 5);
2729 uint64_t imm
= extract32(insn
, 5, 16);
2730 int sf
= extract32(insn
, 31, 1);
2731 int opc
= extract32(insn
, 29, 2);
2732 int pos
= extract32(insn
, 21, 2) << 4;
2733 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2736 if (!sf
&& (pos
>= 32)) {
2737 unallocated_encoding(s
);
2751 tcg_gen_movi_i64(tcg_rd
, imm
);
2754 tcg_imm
= tcg_const_i64(imm
);
2755 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2756 tcg_temp_free_i64(tcg_imm
);
2758 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2762 unallocated_encoding(s
);
2768 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2769 * +----+-----+-------------+---+------+------+------+------+
2770 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2771 * +----+-----+-------------+---+------+------+------+------+
2773 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2775 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2776 TCGv_i64 tcg_rd
, tcg_tmp
;
2778 sf
= extract32(insn
, 31, 1);
2779 opc
= extract32(insn
, 29, 2);
2780 n
= extract32(insn
, 22, 1);
2781 ri
= extract32(insn
, 16, 6);
2782 si
= extract32(insn
, 10, 6);
2783 rn
= extract32(insn
, 5, 5);
2784 rd
= extract32(insn
, 0, 5);
2785 bitsize
= sf
? 64 : 32;
2787 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2788 unallocated_encoding(s
);
2792 tcg_rd
= cpu_reg(s
, rd
);
2793 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2795 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2797 if (opc
!= 1) { /* SBFM or UBFM */
2798 tcg_gen_movi_i64(tcg_rd
, 0);
2801 /* do the bit move operation */
2803 /* Wd<s-r:0> = Wn<s:r> */
2804 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2806 len
= (si
- ri
) + 1;
2808 /* Wd<32+s-r,32-r> = Wn<s:0> */
2813 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2815 if (opc
== 0) { /* SBFM - sign extend the destination field */
2816 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2817 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2820 if (!sf
) { /* zero extend final result */
2821 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2826 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2827 * +----+------+-------------+---+----+------+--------+------+------+
2828 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2829 * +----+------+-------------+---+----+------+--------+------+------+
2831 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2833 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2835 sf
= extract32(insn
, 31, 1);
2836 n
= extract32(insn
, 22, 1);
2837 rm
= extract32(insn
, 16, 5);
2838 imm
= extract32(insn
, 10, 6);
2839 rn
= extract32(insn
, 5, 5);
2840 rd
= extract32(insn
, 0, 5);
2841 op21
= extract32(insn
, 29, 2);
2842 op0
= extract32(insn
, 21, 1);
2843 bitsize
= sf
? 64 : 32;
2845 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2846 unallocated_encoding(s
);
2848 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2850 tcg_rd
= cpu_reg(s
, rd
);
2853 /* OPTME: we can special case rm==rn as a rotate */
2854 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2855 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2856 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2857 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2858 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2860 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2863 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2864 * so an extract from bit 0 is a special case.
2867 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2869 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2876 /* C3.4 Data processing - immediate */
2877 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2879 switch (extract32(insn
, 23, 6)) {
2880 case 0x20: case 0x21: /* PC-rel. addressing */
2881 disas_pc_rel_adr(s
, insn
);
2883 case 0x22: case 0x23: /* Add/subtract (immediate) */
2884 disas_add_sub_imm(s
, insn
);
2886 case 0x24: /* Logical (immediate) */
2887 disas_logic_imm(s
, insn
);
2889 case 0x25: /* Move wide (immediate) */
2890 disas_movw_imm(s
, insn
);
2892 case 0x26: /* Bitfield */
2893 disas_bitfield(s
, insn
);
2895 case 0x27: /* Extract */
2896 disas_extract(s
, insn
);
2899 unallocated_encoding(s
);
2904 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2905 * Note that it is the caller's responsibility to ensure that the
2906 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2907 * mandated semantics for out of range shifts.
2909 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2910 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
2912 switch (shift_type
) {
2913 case A64_SHIFT_TYPE_LSL
:
2914 tcg_gen_shl_i64(dst
, src
, shift_amount
);
2916 case A64_SHIFT_TYPE_LSR
:
2917 tcg_gen_shr_i64(dst
, src
, shift_amount
);
2919 case A64_SHIFT_TYPE_ASR
:
2921 tcg_gen_ext32s_i64(dst
, src
);
2923 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
2925 case A64_SHIFT_TYPE_ROR
:
2927 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
2930 t0
= tcg_temp_new_i32();
2931 t1
= tcg_temp_new_i32();
2932 tcg_gen_trunc_i64_i32(t0
, src
);
2933 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
2934 tcg_gen_rotr_i32(t0
, t0
, t1
);
2935 tcg_gen_extu_i32_i64(dst
, t0
);
2936 tcg_temp_free_i32(t0
);
2937 tcg_temp_free_i32(t1
);
2941 assert(FALSE
); /* all shift types should be handled */
2945 if (!sf
) { /* zero extend final result */
2946 tcg_gen_ext32u_i64(dst
, dst
);
2950 /* Shift a TCGv src by immediate, put result in dst.
2951 * The shift amount must be in range (this should always be true as the
2952 * relevant instructions will UNDEF on bad shift immediates).
2954 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2955 enum a64_shift_type shift_type
, unsigned int shift_i
)
2957 assert(shift_i
< (sf
? 64 : 32));
2960 tcg_gen_mov_i64(dst
, src
);
2962 TCGv_i64 shift_const
;
2964 shift_const
= tcg_const_i64(shift_i
);
2965 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
2966 tcg_temp_free_i64(shift_const
);
2970 /* C3.5.10 Logical (shifted register)
2971 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2972 * +----+-----+-----------+-------+---+------+--------+------+------+
2973 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2974 * +----+-----+-----------+-------+---+------+--------+------+------+
2976 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
2978 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
2979 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
2981 sf
= extract32(insn
, 31, 1);
2982 opc
= extract32(insn
, 29, 2);
2983 shift_type
= extract32(insn
, 22, 2);
2984 invert
= extract32(insn
, 21, 1);
2985 rm
= extract32(insn
, 16, 5);
2986 shift_amount
= extract32(insn
, 10, 6);
2987 rn
= extract32(insn
, 5, 5);
2988 rd
= extract32(insn
, 0, 5);
2990 if (!sf
&& (shift_amount
& (1 << 5))) {
2991 unallocated_encoding(s
);
2995 tcg_rd
= cpu_reg(s
, rd
);
2997 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
2998 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
2999 * register-register MOV and MVN, so it is worth special casing.
3001 tcg_rm
= cpu_reg(s
, rm
);
3003 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3005 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3009 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3011 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3017 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3020 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3023 tcg_rn
= cpu_reg(s
, rn
);
3025 switch (opc
| (invert
<< 2)) {
3028 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3031 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3034 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3038 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3041 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3044 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3052 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3056 gen_logic_CC(sf
, tcg_rd
);
3061 * C3.5.1 Add/subtract (extended register)
3063 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3064 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3065 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3066 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3068 * sf: 0 -> 32bit, 1 -> 64bit
3069 * op: 0 -> add , 1 -> sub
3072 * option: extension type (see DecodeRegExtend)
3073 * imm3: optional shift to Rm
3075 * Rd = Rn + LSL(extend(Rm), amount)
3077 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3079 int rd
= extract32(insn
, 0, 5);
3080 int rn
= extract32(insn
, 5, 5);
3081 int imm3
= extract32(insn
, 10, 3);
3082 int option
= extract32(insn
, 13, 3);
3083 int rm
= extract32(insn
, 16, 5);
3084 bool setflags
= extract32(insn
, 29, 1);
3085 bool sub_op
= extract32(insn
, 30, 1);
3086 bool sf
= extract32(insn
, 31, 1);
3088 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3090 TCGv_i64 tcg_result
;
3093 unallocated_encoding(s
);
3097 /* non-flag setting ops may use SP */
3099 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3100 tcg_rd
= cpu_reg_sp(s
, rd
);
3102 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3103 tcg_rd
= cpu_reg(s
, rd
);
3106 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3107 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3109 tcg_result
= tcg_temp_new_i64();
3113 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3115 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3119 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3121 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3126 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3128 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3131 tcg_temp_free_i64(tcg_result
);
3135 * C3.5.2 Add/subtract (shifted register)
3137 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3138 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3139 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3140 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3142 * sf: 0 -> 32bit, 1 -> 64bit
3143 * op: 0 -> add , 1 -> sub
3145 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3146 * imm6: Shift amount to apply to Rm before the add/sub
3148 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3150 int rd
= extract32(insn
, 0, 5);
3151 int rn
= extract32(insn
, 5, 5);
3152 int imm6
= extract32(insn
, 10, 6);
3153 int rm
= extract32(insn
, 16, 5);
3154 int shift_type
= extract32(insn
, 22, 2);
3155 bool setflags
= extract32(insn
, 29, 1);
3156 bool sub_op
= extract32(insn
, 30, 1);
3157 bool sf
= extract32(insn
, 31, 1);
3159 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3160 TCGv_i64 tcg_rn
, tcg_rm
;
3161 TCGv_i64 tcg_result
;
3163 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3164 unallocated_encoding(s
);
3168 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3169 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3171 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3173 tcg_result
= tcg_temp_new_i64();
3177 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3179 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3183 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3185 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3190 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3192 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3195 tcg_temp_free_i64(tcg_result
);
3198 /* C3.5.9 Data-processing (3 source)
3200 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3201 +--+------+-----------+------+------+----+------+------+------+
3202 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3203 +--+------+-----------+------+------+----+------+------+------+
3206 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3208 int rd
= extract32(insn
, 0, 5);
3209 int rn
= extract32(insn
, 5, 5);
3210 int ra
= extract32(insn
, 10, 5);
3211 int rm
= extract32(insn
, 16, 5);
3212 int op_id
= (extract32(insn
, 29, 3) << 4) |
3213 (extract32(insn
, 21, 3) << 1) |
3214 extract32(insn
, 15, 1);
3215 bool sf
= extract32(insn
, 31, 1);
3216 bool is_sub
= extract32(op_id
, 0, 1);
3217 bool is_high
= extract32(op_id
, 2, 1);
3218 bool is_signed
= false;
3223 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3225 case 0x42: /* SMADDL */
3226 case 0x43: /* SMSUBL */
3227 case 0x44: /* SMULH */
3230 case 0x0: /* MADD (32bit) */
3231 case 0x1: /* MSUB (32bit) */
3232 case 0x40: /* MADD (64bit) */
3233 case 0x41: /* MSUB (64bit) */
3234 case 0x4a: /* UMADDL */
3235 case 0x4b: /* UMSUBL */
3236 case 0x4c: /* UMULH */
3239 unallocated_encoding(s
);
3244 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3245 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3246 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3247 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3250 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3252 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3255 tcg_temp_free_i64(low_bits
);
3259 tcg_op1
= tcg_temp_new_i64();
3260 tcg_op2
= tcg_temp_new_i64();
3261 tcg_tmp
= tcg_temp_new_i64();
3264 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3265 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3268 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3269 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3271 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3272 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3276 if (ra
== 31 && !is_sub
) {
3277 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3278 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3280 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3282 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3284 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3289 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3292 tcg_temp_free_i64(tcg_op1
);
3293 tcg_temp_free_i64(tcg_op2
);
3294 tcg_temp_free_i64(tcg_tmp
);
3297 /* C3.5.3 - Add/subtract (with carry)
3298 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3299 * +--+--+--+------------------------+------+---------+------+-----+
3300 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3301 * +--+--+--+------------------------+------+---------+------+-----+
3305 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3307 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3308 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3310 if (extract32(insn
, 10, 6) != 0) {
3311 unallocated_encoding(s
);
3315 sf
= extract32(insn
, 31, 1);
3316 op
= extract32(insn
, 30, 1);
3317 setflags
= extract32(insn
, 29, 1);
3318 rm
= extract32(insn
, 16, 5);
3319 rn
= extract32(insn
, 5, 5);
3320 rd
= extract32(insn
, 0, 5);
3322 tcg_rd
= cpu_reg(s
, rd
);
3323 tcg_rn
= cpu_reg(s
, rn
);
3326 tcg_y
= new_tmp_a64(s
);
3327 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3329 tcg_y
= cpu_reg(s
, rm
);
3333 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3335 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3339 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3340 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3341 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3342 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3343 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3346 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3348 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3349 int label_continue
= -1;
3350 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3352 if (!extract32(insn
, 29, 1)) {
3353 unallocated_encoding(s
);
3356 if (insn
& (1 << 10 | 1 << 4)) {
3357 unallocated_encoding(s
);
3360 sf
= extract32(insn
, 31, 1);
3361 op
= extract32(insn
, 30, 1);
3362 is_imm
= extract32(insn
, 11, 1);
3363 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3364 cond
= extract32(insn
, 12, 4);
3365 rn
= extract32(insn
, 5, 5);
3366 nzcv
= extract32(insn
, 0, 4);
3368 if (cond
< 0x0e) { /* not always */
3369 int label_match
= gen_new_label();
3370 label_continue
= gen_new_label();
3371 arm_gen_test_cc(cond
, label_match
);
3373 tcg_tmp
= tcg_temp_new_i64();
3374 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3375 gen_set_nzcv(tcg_tmp
);
3376 tcg_temp_free_i64(tcg_tmp
);
3377 tcg_gen_br(label_continue
);
3378 gen_set_label(label_match
);
3380 /* match, or condition is always */
3382 tcg_y
= new_tmp_a64(s
);
3383 tcg_gen_movi_i64(tcg_y
, y
);
3385 tcg_y
= cpu_reg(s
, y
);
3387 tcg_rn
= cpu_reg(s
, rn
);
3389 tcg_tmp
= tcg_temp_new_i64();
3391 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3393 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3395 tcg_temp_free_i64(tcg_tmp
);
3397 if (cond
< 0x0e) { /* continue */
3398 gen_set_label(label_continue
);
3402 /* C3.5.6 Conditional select
3403 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3404 * +----+----+---+-----------------+------+------+-----+------+------+
3405 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3406 * +----+----+---+-----------------+------+------+-----+------+------+
3408 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3410 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3411 TCGv_i64 tcg_rd
, tcg_src
;
3413 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3414 /* S == 1 or op2<1> == 1 */
3415 unallocated_encoding(s
);
3418 sf
= extract32(insn
, 31, 1);
3419 else_inv
= extract32(insn
, 30, 1);
3420 rm
= extract32(insn
, 16, 5);
3421 cond
= extract32(insn
, 12, 4);
3422 else_inc
= extract32(insn
, 10, 1);
3423 rn
= extract32(insn
, 5, 5);
3424 rd
= extract32(insn
, 0, 5);
3427 /* silly no-op write; until we use movcond we must special-case
3428 * this to avoid a dead temporary across basic blocks.
3433 tcg_rd
= cpu_reg(s
, rd
);
3435 if (cond
>= 0x0e) { /* condition "always" */
3436 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3437 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3439 /* OPTME: we could use movcond here, at the cost of duplicating
3440 * a lot of the arm_gen_test_cc() logic.
3442 int label_match
= gen_new_label();
3443 int label_continue
= gen_new_label();
3445 arm_gen_test_cc(cond
, label_match
);
3447 tcg_src
= cpu_reg(s
, rm
);
3449 if (else_inv
&& else_inc
) {
3450 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3451 } else if (else_inv
) {
3452 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3453 } else if (else_inc
) {
3454 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3456 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3459 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3461 tcg_gen_br(label_continue
);
3463 gen_set_label(label_match
);
3464 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3465 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3467 gen_set_label(label_continue
);
3471 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3472 unsigned int rn
, unsigned int rd
)
3474 TCGv_i64 tcg_rd
, tcg_rn
;
3475 tcg_rd
= cpu_reg(s
, rd
);
3476 tcg_rn
= cpu_reg(s
, rn
);
3479 gen_helper_clz64(tcg_rd
, tcg_rn
);
3481 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3482 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3483 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3484 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3485 tcg_temp_free_i32(tcg_tmp32
);
3489 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3490 unsigned int rn
, unsigned int rd
)
3492 TCGv_i64 tcg_rd
, tcg_rn
;
3493 tcg_rd
= cpu_reg(s
, rd
);
3494 tcg_rn
= cpu_reg(s
, rn
);
3497 gen_helper_cls64(tcg_rd
, tcg_rn
);
3499 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3500 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3501 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3502 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3503 tcg_temp_free_i32(tcg_tmp32
);
3507 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3508 unsigned int rn
, unsigned int rd
)
3510 TCGv_i64 tcg_rd
, tcg_rn
;
3511 tcg_rd
= cpu_reg(s
, rd
);
3512 tcg_rn
= cpu_reg(s
, rn
);
3515 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3517 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3518 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3519 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3520 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3521 tcg_temp_free_i32(tcg_tmp32
);
3525 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3526 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3527 unsigned int rn
, unsigned int rd
)
3530 unallocated_encoding(s
);
3533 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3536 /* C5.6.149 REV with sf==0, opcode==2
3537 * C5.6.151 REV32 (sf==1, opcode==2)
3539 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3540 unsigned int rn
, unsigned int rd
)
3542 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3545 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3546 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3548 /* bswap32_i64 requires zero high word */
3549 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3550 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3551 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3552 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3553 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3555 tcg_temp_free_i64(tcg_tmp
);
3557 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3558 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3562 /* C5.6.150 REV16 (opcode==1) */
3563 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3564 unsigned int rn
, unsigned int rd
)
3566 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3567 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3568 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3570 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3571 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3573 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3574 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3575 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3576 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3579 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3580 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3581 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3582 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3584 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3585 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3586 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3589 tcg_temp_free_i64(tcg_tmp
);
3592 /* C3.5.7 Data-processing (1 source)
3593 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3594 * +----+---+---+-----------------+---------+--------+------+------+
3595 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3596 * +----+---+---+-----------------+---------+--------+------+------+
3598 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3600 unsigned int sf
, opcode
, rn
, rd
;
3602 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3603 unallocated_encoding(s
);
3607 sf
= extract32(insn
, 31, 1);
3608 opcode
= extract32(insn
, 10, 6);
3609 rn
= extract32(insn
, 5, 5);
3610 rd
= extract32(insn
, 0, 5);
3614 handle_rbit(s
, sf
, rn
, rd
);
3617 handle_rev16(s
, sf
, rn
, rd
);
3620 handle_rev32(s
, sf
, rn
, rd
);
3623 handle_rev64(s
, sf
, rn
, rd
);
3626 handle_clz(s
, sf
, rn
, rd
);
3629 handle_cls(s
, sf
, rn
, rd
);
3634 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3635 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3637 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3638 tcg_rd
= cpu_reg(s
, rd
);
3640 if (!sf
&& is_signed
) {
3641 tcg_n
= new_tmp_a64(s
);
3642 tcg_m
= new_tmp_a64(s
);
3643 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3644 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3646 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3647 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3651 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3653 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3656 if (!sf
) { /* zero extend final result */
3657 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3661 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3662 static void handle_shift_reg(DisasContext
*s
,
3663 enum a64_shift_type shift_type
, unsigned int sf
,
3664 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3666 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3667 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3668 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3670 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3671 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3672 tcg_temp_free_i64(tcg_shift
);
3675 /* C3.5.8 Data-processing (2 source)
3676 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3677 * +----+---+---+-----------------+------+--------+------+------+
3678 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3679 * +----+---+---+-----------------+------+--------+------+------+
3681 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3683 unsigned int sf
, rm
, opcode
, rn
, rd
;
3684 sf
= extract32(insn
, 31, 1);
3685 rm
= extract32(insn
, 16, 5);
3686 opcode
= extract32(insn
, 10, 6);
3687 rn
= extract32(insn
, 5, 5);
3688 rd
= extract32(insn
, 0, 5);
3690 if (extract32(insn
, 29, 1)) {
3691 unallocated_encoding(s
);
3697 handle_div(s
, false, sf
, rm
, rn
, rd
);
3700 handle_div(s
, true, sf
, rm
, rn
, rd
);
3703 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3706 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3709 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3712 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3721 case 23: /* CRC32 */
3722 unsupported_encoding(s
, insn
);
3725 unallocated_encoding(s
);
3730 /* C3.5 Data processing - register */
3731 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3733 switch (extract32(insn
, 24, 5)) {
3734 case 0x0a: /* Logical (shifted register) */
3735 disas_logic_reg(s
, insn
);
3737 case 0x0b: /* Add/subtract */
3738 if (insn
& (1 << 21)) { /* (extended register) */
3739 disas_add_sub_ext_reg(s
, insn
);
3741 disas_add_sub_reg(s
, insn
);
3744 case 0x1b: /* Data-processing (3 source) */
3745 disas_data_proc_3src(s
, insn
);
3748 switch (extract32(insn
, 21, 3)) {
3749 case 0x0: /* Add/subtract (with carry) */
3750 disas_adc_sbc(s
, insn
);
3752 case 0x2: /* Conditional compare */
3753 disas_cc(s
, insn
); /* both imm and reg forms */
3755 case 0x4: /* Conditional select */
3756 disas_cond_select(s
, insn
);
3758 case 0x6: /* Data-processing */
3759 if (insn
& (1 << 30)) { /* (1 source) */
3760 disas_data_proc_1src(s
, insn
);
3761 } else { /* (2 source) */
3762 disas_data_proc_2src(s
, insn
);
3766 unallocated_encoding(s
);
3771 unallocated_encoding(s
);
3776 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3777 unsigned int rn
, unsigned int rm
,
3778 bool cmp_with_zero
, bool signal_all_nans
)
3780 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3781 TCGv_ptr fpst
= get_fpstatus_ptr();
3784 TCGv_i64 tcg_vn
, tcg_vm
;
3786 tcg_vn
= read_fp_dreg(s
, rn
);
3787 if (cmp_with_zero
) {
3788 tcg_vm
= tcg_const_i64(0);
3790 tcg_vm
= read_fp_dreg(s
, rm
);
3792 if (signal_all_nans
) {
3793 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3795 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3797 tcg_temp_free_i64(tcg_vn
);
3798 tcg_temp_free_i64(tcg_vm
);
3800 TCGv_i32 tcg_vn
, tcg_vm
;
3802 tcg_vn
= read_fp_sreg(s
, rn
);
3803 if (cmp_with_zero
) {
3804 tcg_vm
= tcg_const_i32(0);
3806 tcg_vm
= read_fp_sreg(s
, rm
);
3808 if (signal_all_nans
) {
3809 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3811 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3813 tcg_temp_free_i32(tcg_vn
);
3814 tcg_temp_free_i32(tcg_vm
);
3817 tcg_temp_free_ptr(fpst
);
3819 gen_set_nzcv(tcg_flags
);
3821 tcg_temp_free_i64(tcg_flags
);
3824 /* C3.6.22 Floating point compare
3825 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3826 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3827 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3828 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3830 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3832 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3834 mos
= extract32(insn
, 29, 3);
3835 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3836 rm
= extract32(insn
, 16, 5);
3837 op
= extract32(insn
, 14, 2);
3838 rn
= extract32(insn
, 5, 5);
3839 opc
= extract32(insn
, 3, 2);
3840 op2r
= extract32(insn
, 0, 3);
3842 if (mos
|| op
|| op2r
|| type
> 1) {
3843 unallocated_encoding(s
);
3847 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
3850 /* C3.6.23 Floating point conditional compare
3851 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3852 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3853 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
3854 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3856 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
3858 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
3860 int label_continue
= -1;
3862 mos
= extract32(insn
, 29, 3);
3863 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3864 rm
= extract32(insn
, 16, 5);
3865 cond
= extract32(insn
, 12, 4);
3866 rn
= extract32(insn
, 5, 5);
3867 op
= extract32(insn
, 4, 1);
3868 nzcv
= extract32(insn
, 0, 4);
3870 if (mos
|| type
> 1) {
3871 unallocated_encoding(s
);
3875 if (cond
< 0x0e) { /* not always */
3876 int label_match
= gen_new_label();
3877 label_continue
= gen_new_label();
3878 arm_gen_test_cc(cond
, label_match
);
3880 tcg_flags
= tcg_const_i64(nzcv
<< 28);
3881 gen_set_nzcv(tcg_flags
);
3882 tcg_temp_free_i64(tcg_flags
);
3883 tcg_gen_br(label_continue
);
3884 gen_set_label(label_match
);
3887 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
3890 gen_set_label(label_continue
);
3894 /* copy src FP register to dst FP register; type specifies single or double */
3895 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
3898 TCGv_i64 v
= read_fp_dreg(s
, src
);
3899 write_fp_dreg(s
, dst
, v
);
3900 tcg_temp_free_i64(v
);
3902 TCGv_i32 v
= read_fp_sreg(s
, src
);
3903 write_fp_sreg(s
, dst
, v
);
3904 tcg_temp_free_i32(v
);
3908 /* C3.6.24 Floating point conditional select
3909 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
3910 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3911 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
3912 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3914 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
3916 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
3917 int label_continue
= -1;
3919 mos
= extract32(insn
, 29, 3);
3920 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3921 rm
= extract32(insn
, 16, 5);
3922 cond
= extract32(insn
, 12, 4);
3923 rn
= extract32(insn
, 5, 5);
3924 rd
= extract32(insn
, 0, 5);
3926 if (mos
|| type
> 1) {
3927 unallocated_encoding(s
);
3931 if (cond
< 0x0e) { /* not always */
3932 int label_match
= gen_new_label();
3933 label_continue
= gen_new_label();
3934 arm_gen_test_cc(cond
, label_match
);
3936 gen_mov_fp2fp(s
, type
, rd
, rm
);
3937 tcg_gen_br(label_continue
);
3938 gen_set_label(label_match
);
3941 gen_mov_fp2fp(s
, type
, rd
, rn
);
3943 if (cond
< 0x0e) { /* continue */
3944 gen_set_label(label_continue
);
3948 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
3949 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
3955 fpst
= get_fpstatus_ptr();
3956 tcg_op
= read_fp_sreg(s
, rn
);
3957 tcg_res
= tcg_temp_new_i32();
3960 case 0x0: /* FMOV */
3961 tcg_gen_mov_i32(tcg_res
, tcg_op
);
3963 case 0x1: /* FABS */
3964 gen_helper_vfp_abss(tcg_res
, tcg_op
);
3966 case 0x2: /* FNEG */
3967 gen_helper_vfp_negs(tcg_res
, tcg_op
);
3969 case 0x3: /* FSQRT */
3970 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
3972 case 0x8: /* FRINTN */
3973 case 0x9: /* FRINTP */
3974 case 0xa: /* FRINTM */
3975 case 0xb: /* FRINTZ */
3976 case 0xc: /* FRINTA */
3978 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
3980 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3981 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3983 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3984 tcg_temp_free_i32(tcg_rmode
);
3987 case 0xe: /* FRINTX */
3988 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
3990 case 0xf: /* FRINTI */
3991 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3997 write_fp_sreg(s
, rd
, tcg_res
);
3999 tcg_temp_free_ptr(fpst
);
4000 tcg_temp_free_i32(tcg_op
);
4001 tcg_temp_free_i32(tcg_res
);
4004 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4005 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4011 fpst
= get_fpstatus_ptr();
4012 tcg_op
= read_fp_dreg(s
, rn
);
4013 tcg_res
= tcg_temp_new_i64();
4016 case 0x0: /* FMOV */
4017 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4019 case 0x1: /* FABS */
4020 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4022 case 0x2: /* FNEG */
4023 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4025 case 0x3: /* FSQRT */
4026 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4028 case 0x8: /* FRINTN */
4029 case 0x9: /* FRINTP */
4030 case 0xa: /* FRINTM */
4031 case 0xb: /* FRINTZ */
4032 case 0xc: /* FRINTA */
4034 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4036 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4037 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4039 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4040 tcg_temp_free_i32(tcg_rmode
);
4043 case 0xe: /* FRINTX */
4044 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4046 case 0xf: /* FRINTI */
4047 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4053 write_fp_dreg(s
, rd
, tcg_res
);
4055 tcg_temp_free_ptr(fpst
);
4056 tcg_temp_free_i64(tcg_op
);
4057 tcg_temp_free_i64(tcg_res
);
4060 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4061 int rd
, int rn
, int dtype
, int ntype
)
4066 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4068 /* Single to double */
4069 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4070 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4071 write_fp_dreg(s
, rd
, tcg_rd
);
4072 tcg_temp_free_i64(tcg_rd
);
4074 /* Single to half */
4075 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4076 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4077 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4078 write_fp_sreg(s
, rd
, tcg_rd
);
4079 tcg_temp_free_i32(tcg_rd
);
4081 tcg_temp_free_i32(tcg_rn
);
4086 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4087 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4089 /* Double to single */
4090 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4092 /* Double to half */
4093 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4094 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4096 write_fp_sreg(s
, rd
, tcg_rd
);
4097 tcg_temp_free_i32(tcg_rd
);
4098 tcg_temp_free_i64(tcg_rn
);
4103 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4104 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4106 /* Half to single */
4107 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4108 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4109 write_fp_sreg(s
, rd
, tcg_rd
);
4110 tcg_temp_free_i32(tcg_rd
);
4112 /* Half to double */
4113 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4114 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4115 write_fp_dreg(s
, rd
, tcg_rd
);
4116 tcg_temp_free_i64(tcg_rd
);
4118 tcg_temp_free_i32(tcg_rn
);
4126 /* C3.6.25 Floating point data-processing (1 source)
4127 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4128 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4129 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4130 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4132 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4134 int type
= extract32(insn
, 22, 2);
4135 int opcode
= extract32(insn
, 15, 6);
4136 int rn
= extract32(insn
, 5, 5);
4137 int rd
= extract32(insn
, 0, 5);
4140 case 0x4: case 0x5: case 0x7:
4142 /* FCVT between half, single and double precision */
4143 int dtype
= extract32(opcode
, 0, 2);
4144 if (type
== 2 || dtype
== type
) {
4145 unallocated_encoding(s
);
4148 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4154 /* 32-to-32 and 64-to-64 ops */
4157 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4160 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4163 unallocated_encoding(s
);
4167 unallocated_encoding(s
);
4172 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4173 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4174 int rd
, int rn
, int rm
)
4181 tcg_res
= tcg_temp_new_i32();
4182 fpst
= get_fpstatus_ptr();
4183 tcg_op1
= read_fp_sreg(s
, rn
);
4184 tcg_op2
= read_fp_sreg(s
, rm
);
4187 case 0x0: /* FMUL */
4188 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4190 case 0x1: /* FDIV */
4191 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4193 case 0x2: /* FADD */
4194 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4196 case 0x3: /* FSUB */
4197 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4199 case 0x4: /* FMAX */
4200 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4202 case 0x5: /* FMIN */
4203 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4205 case 0x6: /* FMAXNM */
4206 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4208 case 0x7: /* FMINNM */
4209 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4211 case 0x8: /* FNMUL */
4212 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4213 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4217 write_fp_sreg(s
, rd
, tcg_res
);
4219 tcg_temp_free_ptr(fpst
);
4220 tcg_temp_free_i32(tcg_op1
);
4221 tcg_temp_free_i32(tcg_op2
);
4222 tcg_temp_free_i32(tcg_res
);
4225 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4226 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4227 int rd
, int rn
, int rm
)
4234 tcg_res
= tcg_temp_new_i64();
4235 fpst
= get_fpstatus_ptr();
4236 tcg_op1
= read_fp_dreg(s
, rn
);
4237 tcg_op2
= read_fp_dreg(s
, rm
);
4240 case 0x0: /* FMUL */
4241 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4243 case 0x1: /* FDIV */
4244 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4246 case 0x2: /* FADD */
4247 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4249 case 0x3: /* FSUB */
4250 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4252 case 0x4: /* FMAX */
4253 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4255 case 0x5: /* FMIN */
4256 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4258 case 0x6: /* FMAXNM */
4259 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4261 case 0x7: /* FMINNM */
4262 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4264 case 0x8: /* FNMUL */
4265 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4266 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4270 write_fp_dreg(s
, rd
, tcg_res
);
4272 tcg_temp_free_ptr(fpst
);
4273 tcg_temp_free_i64(tcg_op1
);
4274 tcg_temp_free_i64(tcg_op2
);
4275 tcg_temp_free_i64(tcg_res
);
4278 /* C3.6.26 Floating point data-processing (2 source)
4279 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4280 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4281 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4282 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4284 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4286 int type
= extract32(insn
, 22, 2);
4287 int rd
= extract32(insn
, 0, 5);
4288 int rn
= extract32(insn
, 5, 5);
4289 int rm
= extract32(insn
, 16, 5);
4290 int opcode
= extract32(insn
, 12, 4);
4293 unallocated_encoding(s
);
4299 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4302 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4305 unallocated_encoding(s
);
4309 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4310 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4311 int rd
, int rn
, int rm
, int ra
)
4313 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4314 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4315 TCGv_ptr fpst
= get_fpstatus_ptr();
4317 tcg_op1
= read_fp_sreg(s
, rn
);
4318 tcg_op2
= read_fp_sreg(s
, rm
);
4319 tcg_op3
= read_fp_sreg(s
, ra
);
4321 /* These are fused multiply-add, and must be done as one
4322 * floating point operation with no rounding between the
4323 * multiplication and addition steps.
4324 * NB that doing the negations here as separate steps is
4325 * correct : an input NaN should come out with its sign bit
4326 * flipped if it is a negated-input.
4329 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4333 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4336 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4338 write_fp_sreg(s
, rd
, tcg_res
);
4340 tcg_temp_free_ptr(fpst
);
4341 tcg_temp_free_i32(tcg_op1
);
4342 tcg_temp_free_i32(tcg_op2
);
4343 tcg_temp_free_i32(tcg_op3
);
4344 tcg_temp_free_i32(tcg_res
);
4347 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4348 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4349 int rd
, int rn
, int rm
, int ra
)
4351 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4352 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4353 TCGv_ptr fpst
= get_fpstatus_ptr();
4355 tcg_op1
= read_fp_dreg(s
, rn
);
4356 tcg_op2
= read_fp_dreg(s
, rm
);
4357 tcg_op3
= read_fp_dreg(s
, ra
);
4359 /* These are fused multiply-add, and must be done as one
4360 * floating point operation with no rounding between the
4361 * multiplication and addition steps.
4362 * NB that doing the negations here as separate steps is
4363 * correct : an input NaN should come out with its sign bit
4364 * flipped if it is a negated-input.
4367 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4371 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4374 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4376 write_fp_dreg(s
, rd
, tcg_res
);
4378 tcg_temp_free_ptr(fpst
);
4379 tcg_temp_free_i64(tcg_op1
);
4380 tcg_temp_free_i64(tcg_op2
);
4381 tcg_temp_free_i64(tcg_op3
);
4382 tcg_temp_free_i64(tcg_res
);
4385 /* C3.6.27 Floating point data-processing (3 source)
4386 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4387 * +---+---+---+-----------+------+----+------+----+------+------+------+
4388 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4389 * +---+---+---+-----------+------+----+------+----+------+------+------+
4391 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4393 int type
= extract32(insn
, 22, 2);
4394 int rd
= extract32(insn
, 0, 5);
4395 int rn
= extract32(insn
, 5, 5);
4396 int ra
= extract32(insn
, 10, 5);
4397 int rm
= extract32(insn
, 16, 5);
4398 bool o0
= extract32(insn
, 15, 1);
4399 bool o1
= extract32(insn
, 21, 1);
4403 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4406 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4409 unallocated_encoding(s
);
4413 /* C3.6.28 Floating point immediate
4414 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4415 * +---+---+---+-----------+------+---+------------+-------+------+------+
4416 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4417 * +---+---+---+-----------+------+---+------------+-------+------+------+
4419 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4421 int rd
= extract32(insn
, 0, 5);
4422 int imm8
= extract32(insn
, 13, 8);
4423 int is_double
= extract32(insn
, 22, 2);
4427 if (is_double
> 1) {
4428 unallocated_encoding(s
);
4432 /* The imm8 encodes the sign bit, enough bits to represent
4433 * an exponent in the range 01....1xx to 10....0xx,
4434 * and the most significant 4 bits of the mantissa; see
4435 * VFPExpandImm() in the v8 ARM ARM.
4438 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4439 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4440 extract32(imm8
, 0, 6);
4443 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4444 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4445 (extract32(imm8
, 0, 6) << 3);
4449 tcg_res
= tcg_const_i64(imm
);
4450 write_fp_dreg(s
, rd
, tcg_res
);
4451 tcg_temp_free_i64(tcg_res
);
4454 /* Handle floating point <=> fixed point conversions. Note that we can
4455 * also deal with fp <=> integer conversions as a special case (scale == 64)
4456 * OPTME: consider handling that special case specially or at least skipping
4457 * the call to scalbn in the helpers for zero shifts.
4459 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4460 bool itof
, int rmode
, int scale
, int sf
, int type
)
4462 bool is_signed
= !(opcode
& 1);
4463 bool is_double
= type
;
4464 TCGv_ptr tcg_fpstatus
;
4467 tcg_fpstatus
= get_fpstatus_ptr();
4469 tcg_shift
= tcg_const_i32(64 - scale
);
4472 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4474 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4477 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4479 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4482 tcg_int
= tcg_extend
;
4486 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4488 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4489 tcg_shift
, tcg_fpstatus
);
4491 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4492 tcg_shift
, tcg_fpstatus
);
4494 write_fp_dreg(s
, rd
, tcg_double
);
4495 tcg_temp_free_i64(tcg_double
);
4497 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4499 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4500 tcg_shift
, tcg_fpstatus
);
4502 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4503 tcg_shift
, tcg_fpstatus
);
4505 write_fp_sreg(s
, rd
, tcg_single
);
4506 tcg_temp_free_i32(tcg_single
);
4509 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4512 if (extract32(opcode
, 2, 1)) {
4513 /* There are too many rounding modes to all fit into rmode,
4514 * so FCVTA[US] is a special case.
4516 rmode
= FPROUNDING_TIEAWAY
;
4519 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4521 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4524 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4527 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4528 tcg_shift
, tcg_fpstatus
);
4530 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4531 tcg_shift
, tcg_fpstatus
);
4535 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4536 tcg_shift
, tcg_fpstatus
);
4538 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4539 tcg_shift
, tcg_fpstatus
);
4542 tcg_temp_free_i64(tcg_double
);
4544 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4547 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4548 tcg_shift
, tcg_fpstatus
);
4550 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4551 tcg_shift
, tcg_fpstatus
);
4554 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4556 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4557 tcg_shift
, tcg_fpstatus
);
4559 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4560 tcg_shift
, tcg_fpstatus
);
4562 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4563 tcg_temp_free_i32(tcg_dest
);
4565 tcg_temp_free_i32(tcg_single
);
4568 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4569 tcg_temp_free_i32(tcg_rmode
);
4572 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4576 tcg_temp_free_ptr(tcg_fpstatus
);
4577 tcg_temp_free_i32(tcg_shift
);
4580 /* C3.6.29 Floating point <-> fixed point conversions
4581 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4582 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4583 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4584 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4586 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4588 int rd
= extract32(insn
, 0, 5);
4589 int rn
= extract32(insn
, 5, 5);
4590 int scale
= extract32(insn
, 10, 6);
4591 int opcode
= extract32(insn
, 16, 3);
4592 int rmode
= extract32(insn
, 19, 2);
4593 int type
= extract32(insn
, 22, 2);
4594 bool sbit
= extract32(insn
, 29, 1);
4595 bool sf
= extract32(insn
, 31, 1);
4598 if (sbit
|| (type
> 1)
4599 || (!sf
&& scale
< 32)) {
4600 unallocated_encoding(s
);
4604 switch ((rmode
<< 3) | opcode
) {
4605 case 0x2: /* SCVTF */
4606 case 0x3: /* UCVTF */
4609 case 0x18: /* FCVTZS */
4610 case 0x19: /* FCVTZU */
4614 unallocated_encoding(s
);
4618 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4621 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4623 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4624 * without conversion.
4628 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4634 TCGv_i64 tmp
= tcg_temp_new_i64();
4635 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4636 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(rd
, MO_64
));
4637 tcg_gen_movi_i64(tmp
, 0);
4638 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
4639 tcg_temp_free_i64(tmp
);
4645 TCGv_i64 tmp
= tcg_const_i64(0);
4646 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(rd
, MO_64
));
4647 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
4648 tcg_temp_free_i64(tmp
);
4652 /* 64 bit to top half. */
4653 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(rd
));
4657 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4662 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_32
));
4666 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_64
));
4669 /* 64 bits from top half */
4670 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(rn
));
4676 /* C3.6.30 Floating point <-> integer conversions
4677 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4678 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4679 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4680 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4682 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4684 int rd
= extract32(insn
, 0, 5);
4685 int rn
= extract32(insn
, 5, 5);
4686 int opcode
= extract32(insn
, 16, 3);
4687 int rmode
= extract32(insn
, 19, 2);
4688 int type
= extract32(insn
, 22, 2);
4689 bool sbit
= extract32(insn
, 29, 1);
4690 bool sf
= extract32(insn
, 31, 1);
4693 unallocated_encoding(s
);
4699 bool itof
= opcode
& 1;
4702 unallocated_encoding(s
);
4706 switch (sf
<< 3 | type
<< 1 | rmode
) {
4707 case 0x0: /* 32 bit */
4708 case 0xa: /* 64 bit */
4709 case 0xd: /* 64 bit to top half of quad */
4712 /* all other sf/type/rmode combinations are invalid */
4713 unallocated_encoding(s
);
4717 handle_fmov(s
, rd
, rn
, type
, itof
);
4719 /* actual FP conversions */
4720 bool itof
= extract32(opcode
, 1, 1);
4722 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4723 unallocated_encoding(s
);
4727 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4731 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4732 * 31 30 29 28 25 24 0
4733 * +---+---+---+---------+-----------------------------+
4734 * | | 0 | | 1 1 1 1 | |
4735 * +---+---+---+---------+-----------------------------+
4737 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4739 if (extract32(insn
, 24, 1)) {
4740 /* Floating point data-processing (3 source) */
4741 disas_fp_3src(s
, insn
);
4742 } else if (extract32(insn
, 21, 1) == 0) {
4743 /* Floating point to fixed point conversions */
4744 disas_fp_fixed_conv(s
, insn
);
4746 switch (extract32(insn
, 10, 2)) {
4748 /* Floating point conditional compare */
4749 disas_fp_ccomp(s
, insn
);
4752 /* Floating point data-processing (2 source) */
4753 disas_fp_2src(s
, insn
);
4756 /* Floating point conditional select */
4757 disas_fp_csel(s
, insn
);
4760 switch (ctz32(extract32(insn
, 12, 4))) {
4761 case 0: /* [15:12] == xxx1 */
4762 /* Floating point immediate */
4763 disas_fp_imm(s
, insn
);
4765 case 1: /* [15:12] == xx10 */
4766 /* Floating point compare */
4767 disas_fp_compare(s
, insn
);
4769 case 2: /* [15:12] == x100 */
4770 /* Floating point data-processing (1 source) */
4771 disas_fp_1src(s
, insn
);
4773 case 3: /* [15:12] == 1000 */
4774 unallocated_encoding(s
);
4776 default: /* [15:12] == 0000 */
4777 /* Floating point <-> integer conversions */
4778 disas_fp_int_conv(s
, insn
);
4786 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
4789 /* Extract 64 bits from the middle of two concatenated 64 bit
4790 * vector register slices left:right. The extracted bits start
4791 * at 'pos' bits into the right (least significant) side.
4792 * We return the result in tcg_right, and guarantee not to
4795 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4796 assert(pos
> 0 && pos
< 64);
4798 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
4799 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
4800 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
4802 tcg_temp_free_i64(tcg_tmp
);
4806 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
4807 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4808 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
4809 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4811 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
4813 int is_q
= extract32(insn
, 30, 1);
4814 int op2
= extract32(insn
, 22, 2);
4815 int imm4
= extract32(insn
, 11, 4);
4816 int rm
= extract32(insn
, 16, 5);
4817 int rn
= extract32(insn
, 5, 5);
4818 int rd
= extract32(insn
, 0, 5);
4819 int pos
= imm4
<< 3;
4820 TCGv_i64 tcg_resl
, tcg_resh
;
4822 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
4823 unallocated_encoding(s
);
4827 tcg_resh
= tcg_temp_new_i64();
4828 tcg_resl
= tcg_temp_new_i64();
4830 /* Vd gets bits starting at pos bits into Vm:Vn. This is
4831 * either extracting 128 bits from a 128:128 concatenation, or
4832 * extracting 64 bits from a 64:64 concatenation.
4835 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
4837 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
4838 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4840 tcg_gen_movi_i64(tcg_resh
, 0);
4847 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
4848 EltPosns
*elt
= eltposns
;
4855 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
4857 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
4860 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4861 tcg_hh
= tcg_temp_new_i64();
4862 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
4863 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
4864 tcg_temp_free_i64(tcg_hh
);
4868 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4869 tcg_temp_free_i64(tcg_resl
);
4870 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4871 tcg_temp_free_i64(tcg_resh
);
4875 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
4876 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
4877 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
4878 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
4880 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
4882 int op2
= extract32(insn
, 22, 2);
4883 int is_q
= extract32(insn
, 30, 1);
4884 int rm
= extract32(insn
, 16, 5);
4885 int rn
= extract32(insn
, 5, 5);
4886 int rd
= extract32(insn
, 0, 5);
4887 int is_tblx
= extract32(insn
, 12, 1);
4888 int len
= extract32(insn
, 13, 2);
4889 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
4890 TCGv_i32 tcg_regno
, tcg_numregs
;
4893 unallocated_encoding(s
);
4897 /* This does a table lookup: for every byte element in the input
4898 * we index into a table formed from up to four vector registers,
4899 * and then the output is the result of the lookups. Our helper
4900 * function does the lookup operation for a single 64 bit part of
4903 tcg_resl
= tcg_temp_new_i64();
4904 tcg_resh
= tcg_temp_new_i64();
4907 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4909 tcg_gen_movi_i64(tcg_resl
, 0);
4911 if (is_tblx
&& is_q
) {
4912 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4914 tcg_gen_movi_i64(tcg_resh
, 0);
4917 tcg_idx
= tcg_temp_new_i64();
4918 tcg_regno
= tcg_const_i32(rn
);
4919 tcg_numregs
= tcg_const_i32(len
+ 1);
4920 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
4921 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
4922 tcg_regno
, tcg_numregs
);
4924 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
4925 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
4926 tcg_regno
, tcg_numregs
);
4928 tcg_temp_free_i64(tcg_idx
);
4929 tcg_temp_free_i32(tcg_regno
);
4930 tcg_temp_free_i32(tcg_numregs
);
4932 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4933 tcg_temp_free_i64(tcg_resl
);
4934 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4935 tcg_temp_free_i64(tcg_resh
);
4938 /* C3.6.3 ZIP/UZP/TRN
4939 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
4940 * +---+---+-------------+------+---+------+---+------------------+------+
4941 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
4942 * +---+---+-------------+------+---+------+---+------------------+------+
4944 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
4946 int rd
= extract32(insn
, 0, 5);
4947 int rn
= extract32(insn
, 5, 5);
4948 int rm
= extract32(insn
, 16, 5);
4949 int size
= extract32(insn
, 22, 2);
4950 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
4951 * bit 2 indicates 1 vs 2 variant of the insn.
4953 int opcode
= extract32(insn
, 12, 2);
4954 bool part
= extract32(insn
, 14, 1);
4955 bool is_q
= extract32(insn
, 30, 1);
4956 int esize
= 8 << size
;
4958 int datasize
= is_q
? 128 : 64;
4959 int elements
= datasize
/ esize
;
4960 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
4962 if (opcode
== 0 || (size
== 3 && !is_q
)) {
4963 unallocated_encoding(s
);
4967 tcg_resl
= tcg_const_i64(0);
4968 tcg_resh
= tcg_const_i64(0);
4969 tcg_res
= tcg_temp_new_i64();
4971 for (i
= 0; i
< elements
; i
++) {
4973 case 1: /* UZP1/2 */
4975 int midpoint
= elements
/ 2;
4977 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
4979 read_vec_element(s
, tcg_res
, rm
,
4980 2 * (i
- midpoint
) + part
, size
);
4984 case 2: /* TRN1/2 */
4986 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
4988 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
4991 case 3: /* ZIP1/2 */
4993 int base
= part
* elements
/ 2;
4995 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
4997 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5002 g_assert_not_reached();
5007 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5008 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5010 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5011 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5015 tcg_temp_free_i64(tcg_res
);
5017 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5018 tcg_temp_free_i64(tcg_resl
);
5019 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5020 tcg_temp_free_i64(tcg_resh
);
5023 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5024 int opc
, bool is_min
, TCGv_ptr fpst
)
5026 /* Helper function for disas_simd_across_lanes: do a single precision
5027 * min/max operation on the specified two inputs,
5028 * and return the result in tcg_elt1.
5032 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5034 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5039 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5041 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5046 /* C3.6.4 AdvSIMD across lanes
5047 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5048 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5049 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5050 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5052 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5054 int rd
= extract32(insn
, 0, 5);
5055 int rn
= extract32(insn
, 5, 5);
5056 int size
= extract32(insn
, 22, 2);
5057 int opcode
= extract32(insn
, 12, 5);
5058 bool is_q
= extract32(insn
, 30, 1);
5059 bool is_u
= extract32(insn
, 29, 1);
5061 bool is_min
= false;
5065 TCGv_i64 tcg_res
, tcg_elt
;
5068 case 0x1b: /* ADDV */
5070 unallocated_encoding(s
);
5074 case 0x3: /* SADDLV, UADDLV */
5075 case 0xa: /* SMAXV, UMAXV */
5076 case 0x1a: /* SMINV, UMINV */
5077 if (size
== 3 || (size
== 2 && !is_q
)) {
5078 unallocated_encoding(s
);
5082 case 0xc: /* FMAXNMV, FMINNMV */
5083 case 0xf: /* FMAXV, FMINV */
5084 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5085 unallocated_encoding(s
);
5088 /* Bit 1 of size field encodes min vs max, and actual size is always
5089 * 32 bits: adjust the size variable so following code can rely on it
5091 is_min
= extract32(size
, 1, 1);
5096 unallocated_encoding(s
);
5101 elements
= (is_q
? 128 : 64) / esize
;
5103 tcg_res
= tcg_temp_new_i64();
5104 tcg_elt
= tcg_temp_new_i64();
5106 /* These instructions operate across all lanes of a vector
5107 * to produce a single result. We can guarantee that a 64
5108 * bit intermediate is sufficient:
5109 * + for [US]ADDLV the maximum element size is 32 bits, and
5110 * the result type is 64 bits
5111 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5112 * same as the element size, which is 32 bits at most
5113 * For the integer operations we can choose to work at 64
5114 * or 32 bits and truncate at the end; for simplicity
5115 * we use 64 bits always. The floating point
5116 * ops do require 32 bit intermediates, though.
5119 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5121 for (i
= 1; i
< elements
; i
++) {
5122 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5125 case 0x03: /* SADDLV / UADDLV */
5126 case 0x1b: /* ADDV */
5127 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5129 case 0x0a: /* SMAXV / UMAXV */
5130 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5132 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5134 case 0x1a: /* SMINV / UMINV */
5135 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5137 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5141 g_assert_not_reached();
5146 /* Floating point ops which work on 32 bit (single) intermediates.
5147 * Note that correct NaN propagation requires that we do these
5148 * operations in exactly the order specified by the pseudocode.
5150 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5151 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5152 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5153 TCGv_ptr fpst
= get_fpstatus_ptr();
5155 assert(esize
== 32);
5156 assert(elements
== 4);
5158 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5159 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5160 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5161 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5163 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5165 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5166 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5167 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5168 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5170 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5172 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5174 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5175 tcg_temp_free_i32(tcg_elt1
);
5176 tcg_temp_free_i32(tcg_elt2
);
5177 tcg_temp_free_i32(tcg_elt3
);
5178 tcg_temp_free_ptr(fpst
);
5181 tcg_temp_free_i64(tcg_elt
);
5183 /* Now truncate the result to the width required for the final output */
5184 if (opcode
== 0x03) {
5185 /* SADDLV, UADDLV: result is 2*esize */
5191 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5194 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5197 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5202 g_assert_not_reached();
5205 write_fp_dreg(s
, rd
, tcg_res
);
5206 tcg_temp_free_i64(tcg_res
);
5209 /* C6.3.31 DUP (Element, Vector)
5211 * 31 30 29 21 20 16 15 10 9 5 4 0
5212 * +---+---+-------------------+--------+-------------+------+------+
5213 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5214 * +---+---+-------------------+--------+-------------+------+------+
5216 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5218 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5221 int size
= ctz32(imm5
);
5222 int esize
= 8 << size
;
5223 int elements
= (is_q
? 128 : 64) / esize
;
5227 if (size
> 3 || (size
== 3 && !is_q
)) {
5228 unallocated_encoding(s
);
5232 index
= imm5
>> (size
+ 1);
5234 tmp
= tcg_temp_new_i64();
5235 read_vec_element(s
, tmp
, rn
, index
, size
);
5237 for (i
= 0; i
< elements
; i
++) {
5238 write_vec_element(s
, tmp
, rd
, i
, size
);
5242 clear_vec_high(s
, rd
);
5245 tcg_temp_free_i64(tmp
);
5248 /* C6.3.31 DUP (element, scalar)
5249 * 31 21 20 16 15 10 9 5 4 0
5250 * +-----------------------+--------+-------------+------+------+
5251 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5252 * +-----------------------+--------+-------------+------+------+
5254 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5257 int size
= ctz32(imm5
);
5262 unallocated_encoding(s
);
5266 index
= imm5
>> (size
+ 1);
5268 /* This instruction just extracts the specified element and
5269 * zero-extends it into the bottom of the destination register.
5271 tmp
= tcg_temp_new_i64();
5272 read_vec_element(s
, tmp
, rn
, index
, size
);
5273 write_fp_dreg(s
, rd
, tmp
);
5274 tcg_temp_free_i64(tmp
);
5277 /* C6.3.32 DUP (General)
5279 * 31 30 29 21 20 16 15 10 9 5 4 0
5280 * +---+---+-------------------+--------+-------------+------+------+
5281 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5282 * +---+---+-------------------+--------+-------------+------+------+
5284 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5286 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5289 int size
= ctz32(imm5
);
5290 int esize
= 8 << size
;
5291 int elements
= (is_q
? 128 : 64)/esize
;
5294 if (size
> 3 || ((size
== 3) && !is_q
)) {
5295 unallocated_encoding(s
);
5298 for (i
= 0; i
< elements
; i
++) {
5299 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5302 clear_vec_high(s
, rd
);
5306 /* C6.3.150 INS (Element)
5308 * 31 21 20 16 15 14 11 10 9 5 4 0
5309 * +-----------------------+--------+------------+---+------+------+
5310 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5311 * +-----------------------+--------+------------+---+------+------+
5313 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5314 * index: encoded in imm5<4:size+1>
5316 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5319 int size
= ctz32(imm5
);
5320 int src_index
, dst_index
;
5324 unallocated_encoding(s
);
5327 dst_index
= extract32(imm5
, 1+size
, 5);
5328 src_index
= extract32(imm4
, size
, 4);
5330 tmp
= tcg_temp_new_i64();
5332 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5333 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5335 tcg_temp_free_i64(tmp
);
5339 /* C6.3.151 INS (General)
5341 * 31 21 20 16 15 10 9 5 4 0
5342 * +-----------------------+--------+-------------+------+------+
5343 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5344 * +-----------------------+--------+-------------+------+------+
5346 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5347 * index: encoded in imm5<4:size+1>
5349 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5351 int size
= ctz32(imm5
);
5355 unallocated_encoding(s
);
5359 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5360 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5364 * C6.3.321 UMOV (General)
5365 * C6.3.237 SMOV (General)
5367 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5368 * +---+---+-------------------+--------+-------------+------+------+
5369 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5370 * +---+---+-------------------+--------+-------------+------+------+
5372 * U: unsigned when set
5373 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5375 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5376 int rn
, int rd
, int imm5
)
5378 int size
= ctz32(imm5
);
5382 /* Check for UnallocatedEncodings */
5384 if (size
> 2 || (size
== 2 && !is_q
)) {
5385 unallocated_encoding(s
);
5390 || (size
< 3 && is_q
)
5391 || (size
== 3 && !is_q
)) {
5392 unallocated_encoding(s
);
5396 element
= extract32(imm5
, 1+size
, 4);
5398 tcg_rd
= cpu_reg(s
, rd
);
5399 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5400 if (is_signed
&& !is_q
) {
5401 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5405 /* C3.6.5 AdvSIMD copy
5406 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5407 * +---+---+----+-----------------+------+---+------+---+------+------+
5408 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5409 * +---+---+----+-----------------+------+---+------+---+------+------+
5411 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5413 int rd
= extract32(insn
, 0, 5);
5414 int rn
= extract32(insn
, 5, 5);
5415 int imm4
= extract32(insn
, 11, 4);
5416 int op
= extract32(insn
, 29, 1);
5417 int is_q
= extract32(insn
, 30, 1);
5418 int imm5
= extract32(insn
, 16, 5);
5423 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5425 unallocated_encoding(s
);
5430 /* DUP (element - vector) */
5431 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5435 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5440 handle_simd_insg(s
, rd
, rn
, imm5
);
5442 unallocated_encoding(s
);
5447 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5448 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5451 unallocated_encoding(s
);
5457 /* C3.6.6 AdvSIMD modified immediate
5458 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5459 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5460 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5461 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5463 * There are a number of operations that can be carried out here:
5464 * MOVI - move (shifted) imm into register
5465 * MVNI - move inverted (shifted) imm into register
5466 * ORR - bitwise OR of (shifted) imm with register
5467 * BIC - bitwise clear of (shifted) imm with register
5469 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5471 int rd
= extract32(insn
, 0, 5);
5472 int cmode
= extract32(insn
, 12, 4);
5473 int cmode_3_1
= extract32(cmode
, 1, 3);
5474 int cmode_0
= extract32(cmode
, 0, 1);
5475 int o2
= extract32(insn
, 11, 1);
5476 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5477 bool is_neg
= extract32(insn
, 29, 1);
5478 bool is_q
= extract32(insn
, 30, 1);
5480 TCGv_i64 tcg_rd
, tcg_imm
;
5483 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5484 unallocated_encoding(s
);
5488 /* See AdvSIMDExpandImm() in ARM ARM */
5489 switch (cmode_3_1
) {
5490 case 0: /* Replicate(Zeros(24):imm8, 2) */
5491 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5492 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5493 case 3: /* Replicate(imm8:Zeros(24), 2) */
5495 int shift
= cmode_3_1
* 8;
5496 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5499 case 4: /* Replicate(Zeros(8):imm8, 4) */
5500 case 5: /* Replicate(imm8:Zeros(8), 4) */
5502 int shift
= (cmode_3_1
& 0x1) * 8;
5503 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5508 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5509 imm
= (abcdefgh
<< 16) | 0xffff;
5511 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5512 imm
= (abcdefgh
<< 8) | 0xff;
5514 imm
= bitfield_replicate(imm
, 32);
5517 if (!cmode_0
&& !is_neg
) {
5518 imm
= bitfield_replicate(abcdefgh
, 8);
5519 } else if (!cmode_0
&& is_neg
) {
5522 for (i
= 0; i
< 8; i
++) {
5523 if ((abcdefgh
) & (1 << i
)) {
5524 imm
|= 0xffULL
<< (i
* 8);
5527 } else if (cmode_0
) {
5529 imm
= (abcdefgh
& 0x3f) << 48;
5530 if (abcdefgh
& 0x80) {
5531 imm
|= 0x8000000000000000ULL
;
5533 if (abcdefgh
& 0x40) {
5534 imm
|= 0x3fc0000000000000ULL
;
5536 imm
|= 0x4000000000000000ULL
;
5539 imm
= (abcdefgh
& 0x3f) << 19;
5540 if (abcdefgh
& 0x80) {
5543 if (abcdefgh
& 0x40) {
5554 if (cmode_3_1
!= 7 && is_neg
) {
5558 tcg_imm
= tcg_const_i64(imm
);
5559 tcg_rd
= new_tmp_a64(s
);
5561 for (i
= 0; i
< 2; i
++) {
5562 int foffs
= i
? fp_reg_hi_offset(rd
) : fp_reg_offset(rd
, MO_64
);
5564 if (i
== 1 && !is_q
) {
5565 /* non-quad ops clear high half of vector */
5566 tcg_gen_movi_i64(tcg_rd
, 0);
5567 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5568 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5571 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5574 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5578 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5580 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5583 tcg_temp_free_i64(tcg_imm
);
5586 /* C3.6.7 AdvSIMD scalar copy
5587 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5588 * +-----+----+-----------------+------+---+------+---+------+------+
5589 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5590 * +-----+----+-----------------+------+---+------+---+------+------+
5592 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5594 int rd
= extract32(insn
, 0, 5);
5595 int rn
= extract32(insn
, 5, 5);
5596 int imm4
= extract32(insn
, 11, 4);
5597 int imm5
= extract32(insn
, 16, 5);
5598 int op
= extract32(insn
, 29, 1);
5600 if (op
!= 0 || imm4
!= 0) {
5601 unallocated_encoding(s
);
5605 /* DUP (element, scalar) */
5606 handle_simd_dupes(s
, rd
, rn
, imm5
);
5609 /* C3.6.8 AdvSIMD scalar pairwise
5610 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5611 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5612 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5613 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5615 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5617 int u
= extract32(insn
, 29, 1);
5618 int size
= extract32(insn
, 22, 2);
5619 int opcode
= extract32(insn
, 12, 5);
5620 int rn
= extract32(insn
, 5, 5);
5621 int rd
= extract32(insn
, 0, 5);
5624 /* For some ops (the FP ones), size[1] is part of the encoding.
5625 * For ADDP strictly it is not but size[1] is always 1 for valid
5628 opcode
|= (extract32(size
, 1, 1) << 5);
5631 case 0x3b: /* ADDP */
5632 if (u
|| size
!= 3) {
5633 unallocated_encoding(s
);
5636 TCGV_UNUSED_PTR(fpst
);
5638 case 0xc: /* FMAXNMP */
5639 case 0xd: /* FADDP */
5640 case 0xf: /* FMAXP */
5641 case 0x2c: /* FMINNMP */
5642 case 0x2f: /* FMINP */
5643 /* FP op, size[0] is 32 or 64 bit */
5645 unallocated_encoding(s
);
5648 size
= extract32(size
, 0, 1) ? 3 : 2;
5649 fpst
= get_fpstatus_ptr();
5652 unallocated_encoding(s
);
5657 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5658 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5659 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5661 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5662 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5665 case 0x3b: /* ADDP */
5666 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5668 case 0xc: /* FMAXNMP */
5669 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5671 case 0xd: /* FADDP */
5672 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5674 case 0xf: /* FMAXP */
5675 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5677 case 0x2c: /* FMINNMP */
5678 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5680 case 0x2f: /* FMINP */
5681 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5684 g_assert_not_reached();
5687 write_fp_dreg(s
, rd
, tcg_res
);
5689 tcg_temp_free_i64(tcg_op1
);
5690 tcg_temp_free_i64(tcg_op2
);
5691 tcg_temp_free_i64(tcg_res
);
5693 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5694 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5695 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5697 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
5698 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
5701 case 0xc: /* FMAXNMP */
5702 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5704 case 0xd: /* FADDP */
5705 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5707 case 0xf: /* FMAXP */
5708 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5710 case 0x2c: /* FMINNMP */
5711 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5713 case 0x2f: /* FMINP */
5714 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5717 g_assert_not_reached();
5720 write_fp_sreg(s
, rd
, tcg_res
);
5722 tcg_temp_free_i32(tcg_op1
);
5723 tcg_temp_free_i32(tcg_op2
);
5724 tcg_temp_free_i32(tcg_res
);
5727 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
5728 tcg_temp_free_ptr(fpst
);
5733 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
5735 * This code is handles the common shifting code and is used by both
5736 * the vector and scalar code.
5738 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5739 TCGv_i64 tcg_rnd
, bool accumulate
,
5740 bool is_u
, int size
, int shift
)
5742 bool extended_result
= false;
5743 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
5745 TCGv_i64 tcg_src_hi
;
5747 if (round
&& size
== 3) {
5748 extended_result
= true;
5749 ext_lshift
= 64 - shift
;
5750 tcg_src_hi
= tcg_temp_new_i64();
5751 } else if (shift
== 64) {
5752 if (!accumulate
&& is_u
) {
5753 /* result is zero */
5754 tcg_gen_movi_i64(tcg_res
, 0);
5759 /* Deal with the rounding step */
5761 if (extended_result
) {
5762 TCGv_i64 tcg_zero
= tcg_const_i64(0);
5764 /* take care of sign extending tcg_res */
5765 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
5766 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5767 tcg_src
, tcg_src_hi
,
5770 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5774 tcg_temp_free_i64(tcg_zero
);
5776 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
5780 /* Now do the shift right */
5781 if (round
&& extended_result
) {
5782 /* extended case, >64 bit precision required */
5783 if (ext_lshift
== 0) {
5784 /* special case, only high bits matter */
5785 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
5787 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5788 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
5789 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
5794 /* essentially shifting in 64 zeros */
5795 tcg_gen_movi_i64(tcg_src
, 0);
5797 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5801 /* effectively extending the sign-bit */
5802 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
5804 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
5810 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
5812 tcg_gen_mov_i64(tcg_res
, tcg_src
);
5815 if (extended_result
) {
5816 tcg_temp_free_i64(tcg_src_hi
);
5820 /* Common SHL/SLI - Shift left with an optional insert */
5821 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5822 bool insert
, int shift
)
5824 if (insert
) { /* SLI */
5825 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
5827 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
5831 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
5832 static void handle_scalar_simd_shri(DisasContext
*s
,
5833 bool is_u
, int immh
, int immb
,
5834 int opcode
, int rn
, int rd
)
5837 int immhb
= immh
<< 3 | immb
;
5838 int shift
= 2 * (8 << size
) - immhb
;
5839 bool accumulate
= false;
5845 if (!extract32(immh
, 3, 1)) {
5846 unallocated_encoding(s
);
5851 case 0x02: /* SSRA / USRA (accumulate) */
5854 case 0x04: /* SRSHR / URSHR (rounding) */
5857 case 0x06: /* SRSRA / URSRA (accum + rounding) */
5858 accumulate
= round
= true;
5863 uint64_t round_const
= 1ULL << (shift
- 1);
5864 tcg_round
= tcg_const_i64(round_const
);
5866 TCGV_UNUSED_I64(tcg_round
);
5869 tcg_rn
= read_fp_dreg(s
, rn
);
5870 tcg_rd
= accumulate
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
5872 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
5873 accumulate
, is_u
, size
, shift
);
5875 write_fp_dreg(s
, rd
, tcg_rd
);
5877 tcg_temp_free_i64(tcg_rn
);
5878 tcg_temp_free_i64(tcg_rd
);
5880 tcg_temp_free_i64(tcg_round
);
5884 /* SHL/SLI - Scalar shift left */
5885 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
5886 int immh
, int immb
, int opcode
,
5889 int size
= 32 - clz32(immh
) - 1;
5890 int immhb
= immh
<< 3 | immb
;
5891 int shift
= immhb
- (8 << size
);
5892 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
5893 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
5895 if (!extract32(immh
, 3, 1)) {
5896 unallocated_encoding(s
);
5900 tcg_rn
= read_fp_dreg(s
, rn
);
5901 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
5903 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
5905 write_fp_dreg(s
, rd
, tcg_rd
);
5907 tcg_temp_free_i64(tcg_rn
);
5908 tcg_temp_free_i64(tcg_rd
);
5911 /* C3.6.9 AdvSIMD scalar shift by immediate
5912 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
5913 * +-----+---+-------------+------+------+--------+---+------+------+
5914 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
5915 * +-----+---+-------------+------+------+--------+---+------+------+
5917 * This is the scalar version so it works on a fixed sized registers
5919 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
5921 int rd
= extract32(insn
, 0, 5);
5922 int rn
= extract32(insn
, 5, 5);
5923 int opcode
= extract32(insn
, 11, 5);
5924 int immb
= extract32(insn
, 16, 3);
5925 int immh
= extract32(insn
, 19, 4);
5926 bool is_u
= extract32(insn
, 29, 1);
5929 case 0x00: /* SSHR / USHR */
5930 case 0x02: /* SSRA / USRA */
5931 case 0x04: /* SRSHR / URSHR */
5932 case 0x06: /* SRSRA / URSRA */
5933 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
5935 case 0x0a: /* SHL / SLI */
5936 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
5939 unsupported_encoding(s
, insn
);
5944 /* C3.6.10 AdvSIMD scalar three different
5945 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5946 * +-----+---+-----------+------+---+------+--------+-----+------+------+
5947 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
5948 * +-----+---+-----------+------+---+------+--------+-----+------+------+
5950 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
5952 bool is_u
= extract32(insn
, 29, 1);
5953 int size
= extract32(insn
, 22, 2);
5954 int opcode
= extract32(insn
, 12, 4);
5955 int rm
= extract32(insn
, 16, 5);
5956 int rn
= extract32(insn
, 5, 5);
5957 int rd
= extract32(insn
, 0, 5);
5960 unallocated_encoding(s
);
5965 case 0x9: /* SQDMLAL, SQDMLAL2 */
5966 case 0xb: /* SQDMLSL, SQDMLSL2 */
5967 case 0xd: /* SQDMULL, SQDMULL2 */
5968 if (size
== 0 || size
== 3) {
5969 unallocated_encoding(s
);
5974 unallocated_encoding(s
);
5979 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5980 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5981 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5983 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
5984 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
5986 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
5987 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
5990 case 0xd: /* SQDMULL, SQDMULL2 */
5992 case 0xb: /* SQDMLSL, SQDMLSL2 */
5993 tcg_gen_neg_i64(tcg_res
, tcg_res
);
5995 case 0x9: /* SQDMLAL, SQDMLAL2 */
5996 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
5997 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6001 g_assert_not_reached();
6004 write_fp_dreg(s
, rd
, tcg_res
);
6006 tcg_temp_free_i64(tcg_op1
);
6007 tcg_temp_free_i64(tcg_op2
);
6008 tcg_temp_free_i64(tcg_res
);
6010 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6011 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6012 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6014 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6015 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6017 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6018 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6021 case 0xd: /* SQDMULL, SQDMULL2 */
6023 case 0xb: /* SQDMLSL, SQDMLSL2 */
6024 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6026 case 0x9: /* SQDMLAL, SQDMLAL2 */
6028 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6029 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6030 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6032 tcg_temp_free_i64(tcg_op3
);
6036 g_assert_not_reached();
6039 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6040 write_fp_dreg(s
, rd
, tcg_res
);
6042 tcg_temp_free_i32(tcg_op1
);
6043 tcg_temp_free_i32(tcg_op2
);
6044 tcg_temp_free_i64(tcg_res
);
6048 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6049 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6051 /* Handle 64x64->64 opcodes which are shared between the scalar
6052 * and vector 3-same groups. We cover every opcode where size == 3
6053 * is valid in either the three-reg-same (integer, not pairwise)
6054 * or scalar-three-reg-same groups. (Some opcodes are not yet
6060 case 0x1: /* SQADD */
6062 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6064 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6067 case 0x5: /* SQSUB */
6069 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6071 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6074 case 0x6: /* CMGT, CMHI */
6075 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6076 * We implement this using setcond (test) and then negating.
6078 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6080 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6081 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6083 case 0x7: /* CMGE, CMHS */
6084 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6086 case 0x11: /* CMTST, CMEQ */
6091 /* CMTST : test is "if (X & Y != 0)". */
6092 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6093 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6094 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6096 case 0x8: /* SSHL, USHL */
6098 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6100 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6103 case 0x9: /* SQSHL, UQSHL */
6105 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6107 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6110 case 0xa: /* SRSHL, URSHL */
6112 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6114 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6117 case 0xb: /* SQRSHL, UQRSHL */
6119 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6121 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6124 case 0x10: /* ADD, SUB */
6126 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6128 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6132 g_assert_not_reached();
6136 /* Handle the 3-same-operands float operations; shared by the scalar
6137 * and vector encodings. The caller must filter out any encodings
6138 * not allocated for the encoding it is dealing with.
6140 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6141 int fpopcode
, int rd
, int rn
, int rm
)
6144 TCGv_ptr fpst
= get_fpstatus_ptr();
6146 for (pass
= 0; pass
< elements
; pass
++) {
6149 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6150 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6151 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6153 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6154 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6157 case 0x39: /* FMLS */
6158 /* As usual for ARM, separate negation for fused multiply-add */
6159 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6161 case 0x19: /* FMLA */
6162 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6163 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6166 case 0x18: /* FMAXNM */
6167 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6169 case 0x1a: /* FADD */
6170 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6172 case 0x1b: /* FMULX */
6173 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6175 case 0x1c: /* FCMEQ */
6176 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6178 case 0x1e: /* FMAX */
6179 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6181 case 0x1f: /* FRECPS */
6182 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6184 case 0x38: /* FMINNM */
6185 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6187 case 0x3a: /* FSUB */
6188 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6190 case 0x3e: /* FMIN */
6191 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6193 case 0x3f: /* FRSQRTS */
6194 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6196 case 0x5b: /* FMUL */
6197 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6199 case 0x5c: /* FCMGE */
6200 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6202 case 0x5d: /* FACGE */
6203 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6205 case 0x5f: /* FDIV */
6206 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6208 case 0x7a: /* FABD */
6209 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6210 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6212 case 0x7c: /* FCMGT */
6213 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6215 case 0x7d: /* FACGT */
6216 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6219 g_assert_not_reached();
6222 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6224 tcg_temp_free_i64(tcg_res
);
6225 tcg_temp_free_i64(tcg_op1
);
6226 tcg_temp_free_i64(tcg_op2
);
6229 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6230 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6231 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6233 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6234 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
6237 case 0x39: /* FMLS */
6238 /* As usual for ARM, separate negation for fused multiply-add */
6239 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6241 case 0x19: /* FMLA */
6242 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6243 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
6246 case 0x1a: /* FADD */
6247 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6249 case 0x1b: /* FMULX */
6250 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6252 case 0x1c: /* FCMEQ */
6253 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6255 case 0x1e: /* FMAX */
6256 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6258 case 0x1f: /* FRECPS */
6259 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6261 case 0x18: /* FMAXNM */
6262 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6264 case 0x38: /* FMINNM */
6265 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6267 case 0x3a: /* FSUB */
6268 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6270 case 0x3e: /* FMIN */
6271 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6273 case 0x3f: /* FRSQRTS */
6274 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6276 case 0x5b: /* FMUL */
6277 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6279 case 0x5c: /* FCMGE */
6280 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6282 case 0x5d: /* FACGE */
6283 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6285 case 0x5f: /* FDIV */
6286 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6288 case 0x7a: /* FABD */
6289 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6290 gen_helper_vfp_abss(tcg_res
, tcg_res
);
6292 case 0x7c: /* FCMGT */
6293 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6295 case 0x7d: /* FACGT */
6296 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6299 g_assert_not_reached();
6302 if (elements
== 1) {
6303 /* scalar single so clear high part */
6304 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6306 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
6307 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
6308 tcg_temp_free_i64(tcg_tmp
);
6310 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6313 tcg_temp_free_i32(tcg_res
);
6314 tcg_temp_free_i32(tcg_op1
);
6315 tcg_temp_free_i32(tcg_op2
);
6319 tcg_temp_free_ptr(fpst
);
6321 if ((elements
<< size
) < 4) {
6322 /* scalar, or non-quad vector op */
6323 clear_vec_high(s
, rd
);
6327 /* C3.6.11 AdvSIMD scalar three same
6328 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
6329 * +-----+---+-----------+------+---+------+--------+---+------+------+
6330 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
6331 * +-----+---+-----------+------+---+------+--------+---+------+------+
6333 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
6335 int rd
= extract32(insn
, 0, 5);
6336 int rn
= extract32(insn
, 5, 5);
6337 int opcode
= extract32(insn
, 11, 5);
6338 int rm
= extract32(insn
, 16, 5);
6339 int size
= extract32(insn
, 22, 2);
6340 bool u
= extract32(insn
, 29, 1);
6343 if (opcode
>= 0x18) {
6344 /* Floating point: U, size[1] and opcode indicate operation */
6345 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
6347 case 0x1b: /* FMULX */
6348 case 0x1f: /* FRECPS */
6349 case 0x3f: /* FRSQRTS */
6350 case 0x5d: /* FACGE */
6351 case 0x7d: /* FACGT */
6352 case 0x1c: /* FCMEQ */
6353 case 0x5c: /* FCMGE */
6354 case 0x7c: /* FCMGT */
6355 case 0x7a: /* FABD */
6358 unallocated_encoding(s
);
6362 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
6367 case 0x1: /* SQADD, UQADD */
6368 case 0x5: /* SQSUB, UQSUB */
6369 case 0x9: /* SQSHL, UQSHL */
6370 case 0xb: /* SQRSHL, UQRSHL */
6372 case 0x8: /* SSHL, USHL */
6373 case 0xa: /* SRSHL, URSHL */
6374 case 0x6: /* CMGT, CMHI */
6375 case 0x7: /* CMGE, CMHS */
6376 case 0x11: /* CMTST, CMEQ */
6377 case 0x10: /* ADD, SUB (vector) */
6379 unallocated_encoding(s
);
6383 case 0x16: /* SQDMULH, SQRDMULH (vector) */
6384 if (size
!= 1 && size
!= 2) {
6385 unallocated_encoding(s
);
6390 unallocated_encoding(s
);
6394 tcg_rd
= tcg_temp_new_i64();
6397 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6398 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
6400 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
6401 tcg_temp_free_i64(tcg_rn
);
6402 tcg_temp_free_i64(tcg_rm
);
6404 /* Do a single operation on the lowest element in the vector.
6405 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
6406 * no side effects for all these operations.
6407 * OPTME: special-purpose helpers would avoid doing some
6408 * unnecessary work in the helper for the 8 and 16 bit cases.
6410 NeonGenTwoOpEnvFn
*genenvfn
;
6411 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
6412 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
6413 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
6415 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
6416 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
6419 case 0x1: /* SQADD, UQADD */
6421 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6422 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
6423 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
6424 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
6426 genenvfn
= fns
[size
][u
];
6429 case 0x5: /* SQSUB, UQSUB */
6431 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6432 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
6433 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
6434 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
6436 genenvfn
= fns
[size
][u
];
6439 case 0x9: /* SQSHL, UQSHL */
6441 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6442 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
6443 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
6444 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
6446 genenvfn
= fns
[size
][u
];
6449 case 0xb: /* SQRSHL, UQRSHL */
6451 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6452 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
6453 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
6454 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
6456 genenvfn
= fns
[size
][u
];
6459 case 0x16: /* SQDMULH, SQRDMULH */
6461 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
6462 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
6463 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
6465 assert(size
== 1 || size
== 2);
6466 genenvfn
= fns
[size
- 1][u
];
6470 g_assert_not_reached();
6473 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
6474 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
6475 tcg_temp_free_i32(tcg_rd32
);
6476 tcg_temp_free_i32(tcg_rn
);
6477 tcg_temp_free_i32(tcg_rm
);
6480 write_fp_dreg(s
, rd
, tcg_rd
);
6482 tcg_temp_free_i64(tcg_rd
);
6485 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
6486 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
)
6488 /* Handle 64->64 opcodes which are shared between the scalar and
6489 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
6490 * is valid in either group and also the double-precision fp ops.
6496 /* This opcode is shared with CNT and RBIT but we have earlier
6497 * enforced that size == 3 if and only if this is the NOT insn.
6499 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
6501 case 0xa: /* CMLT */
6502 /* 64 bit integer comparison against zero, result is
6503 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
6508 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
6509 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6511 case 0x8: /* CMGT, CMGE */
6512 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
6514 case 0x9: /* CMEQ, CMLE */
6515 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
6517 case 0xb: /* ABS, NEG */
6519 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
6521 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6522 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
6523 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
6525 tcg_temp_free_i64(tcg_zero
);
6528 case 0x2f: /* FABS */
6529 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
6531 case 0x6f: /* FNEG */
6532 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
6535 g_assert_not_reached();
6539 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
6540 bool is_scalar
, bool is_u
, bool is_q
,
6541 int size
, int rn
, int rd
)
6543 bool is_double
= (size
== 3);
6544 TCGv_ptr fpst
= get_fpstatus_ptr();
6547 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6548 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6549 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6550 NeonGenTwoDoubleOPFn
*genfn
;
6555 case 0x2e: /* FCMLT (zero) */
6558 case 0x2c: /* FCMGT (zero) */
6559 genfn
= gen_helper_neon_cgt_f64
;
6561 case 0x2d: /* FCMEQ (zero) */
6562 genfn
= gen_helper_neon_ceq_f64
;
6564 case 0x6d: /* FCMLE (zero) */
6567 case 0x6c: /* FCMGE (zero) */
6568 genfn
= gen_helper_neon_cge_f64
;
6571 g_assert_not_reached();
6574 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
6575 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6577 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
6579 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
6581 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6584 clear_vec_high(s
, rd
);
6587 tcg_temp_free_i64(tcg_res
);
6588 tcg_temp_free_i64(tcg_zero
);
6589 tcg_temp_free_i64(tcg_op
);
6591 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6592 TCGv_i32 tcg_zero
= tcg_const_i32(0);
6593 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6594 NeonGenTwoSingleOPFn
*genfn
;
6596 int pass
, maxpasses
;
6599 case 0x2e: /* FCMLT (zero) */
6602 case 0x2c: /* FCMGT (zero) */
6603 genfn
= gen_helper_neon_cgt_f32
;
6605 case 0x2d: /* FCMEQ (zero) */
6606 genfn
= gen_helper_neon_ceq_f32
;
6608 case 0x6d: /* FCMLE (zero) */
6611 case 0x6c: /* FCMGE (zero) */
6612 genfn
= gen_helper_neon_cge_f32
;
6615 g_assert_not_reached();
6621 maxpasses
= is_q
? 4 : 2;
6624 for (pass
= 0; pass
< maxpasses
; pass
++) {
6625 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6627 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
6629 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
6632 write_fp_sreg(s
, rd
, tcg_res
);
6634 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6637 tcg_temp_free_i32(tcg_res
);
6638 tcg_temp_free_i32(tcg_zero
);
6639 tcg_temp_free_i32(tcg_op
);
6640 if (!is_q
&& !is_scalar
) {
6641 clear_vec_high(s
, rd
);
6645 tcg_temp_free_ptr(fpst
);
6648 /* C3.6.12 AdvSIMD scalar two reg misc
6649 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6650 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6651 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
6652 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6654 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
6656 int rd
= extract32(insn
, 0, 5);
6657 int rn
= extract32(insn
, 5, 5);
6658 int opcode
= extract32(insn
, 12, 5);
6659 int size
= extract32(insn
, 22, 2);
6660 bool u
= extract32(insn
, 29, 1);
6663 case 0xa: /* CMLT */
6665 unallocated_encoding(s
);
6669 case 0x8: /* CMGT, CMGE */
6670 case 0x9: /* CMEQ, CMLE */
6671 case 0xb: /* ABS, NEG */
6673 unallocated_encoding(s
);
6680 /* Floating point: U, size[1] and opcode indicate operation;
6681 * size[0] indicates single or double precision.
6683 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
6684 size
= extract32(size
, 0, 1) ? 3 : 2;
6686 case 0x2c: /* FCMGT (zero) */
6687 case 0x2d: /* FCMEQ (zero) */
6688 case 0x2e: /* FCMLT (zero) */
6689 case 0x6c: /* FCMGE (zero) */
6690 case 0x6d: /* FCMLE (zero) */
6691 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
6693 case 0x1a: /* FCVTNS */
6694 case 0x1b: /* FCVTMS */
6695 case 0x1c: /* FCVTAS */
6696 case 0x1d: /* SCVTF */
6697 case 0x3a: /* FCVTPS */
6698 case 0x3b: /* FCVTZS */
6699 case 0x3d: /* FRECPE */
6700 case 0x3f: /* FRECPX */
6701 case 0x56: /* FCVTXN, FCVTXN2 */
6702 case 0x5a: /* FCVTNU */
6703 case 0x5b: /* FCVTMU */
6704 case 0x5c: /* FCVTAU */
6705 case 0x5d: /* UCVTF */
6706 case 0x7a: /* FCVTPU */
6707 case 0x7b: /* FCVTZU */
6708 case 0x7d: /* FRSQRTE */
6709 unsupported_encoding(s
, insn
);
6712 unallocated_encoding(s
);
6717 /* Other categories of encoding in this class:
6718 * + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64
6719 * + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2:
6720 * narrowing saturate ops: size 64/32/16 -> 32/16/8
6722 unsupported_encoding(s
, insn
);
6727 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6728 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6730 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
);
6731 write_fp_dreg(s
, rd
, tcg_rd
);
6732 tcg_temp_free_i64(tcg_rd
);
6733 tcg_temp_free_i64(tcg_rn
);
6735 /* the 'size might not be 64' ops aren't implemented yet */
6736 g_assert_not_reached();
6740 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
6741 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
6742 int immh
, int immb
, int opcode
, int rn
, int rd
)
6744 int size
= 32 - clz32(immh
) - 1;
6745 int immhb
= immh
<< 3 | immb
;
6746 int shift
= 2 * (8 << size
) - immhb
;
6747 bool accumulate
= false;
6749 int dsize
= is_q
? 128 : 64;
6750 int esize
= 8 << size
;
6751 int elements
= dsize
/esize
;
6752 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
6753 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6754 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6758 if (extract32(immh
, 3, 1) && !is_q
) {
6759 unallocated_encoding(s
);
6763 if (size
> 3 && !is_q
) {
6764 unallocated_encoding(s
);
6769 case 0x02: /* SSRA / USRA (accumulate) */
6772 case 0x04: /* SRSHR / URSHR (rounding) */
6775 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6776 accumulate
= round
= true;
6781 uint64_t round_const
= 1ULL << (shift
- 1);
6782 tcg_round
= tcg_const_i64(round_const
);
6784 TCGV_UNUSED_I64(tcg_round
);
6787 for (i
= 0; i
< elements
; i
++) {
6788 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
6790 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
6793 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6794 accumulate
, is_u
, size
, shift
);
6796 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
6800 clear_vec_high(s
, rd
);
6804 tcg_temp_free_i64(tcg_round
);
6808 /* SHL/SLI - Vector shift left */
6809 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
6810 int immh
, int immb
, int opcode
, int rn
, int rd
)
6812 int size
= 32 - clz32(immh
) - 1;
6813 int immhb
= immh
<< 3 | immb
;
6814 int shift
= immhb
- (8 << size
);
6815 int dsize
= is_q
? 128 : 64;
6816 int esize
= 8 << size
;
6817 int elements
= dsize
/esize
;
6818 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6819 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6822 if (extract32(immh
, 3, 1) && !is_q
) {
6823 unallocated_encoding(s
);
6827 if (size
> 3 && !is_q
) {
6828 unallocated_encoding(s
);
6832 for (i
= 0; i
< elements
; i
++) {
6833 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
6835 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
6838 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6840 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
6844 clear_vec_high(s
, rd
);
6848 /* USHLL/SHLL - Vector shift left with widening */
6849 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
6850 int immh
, int immb
, int opcode
, int rn
, int rd
)
6852 int size
= 32 - clz32(immh
) - 1;
6853 int immhb
= immh
<< 3 | immb
;
6854 int shift
= immhb
- (8 << size
);
6856 int esize
= 8 << size
;
6857 int elements
= dsize
/esize
;
6858 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6859 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6863 unallocated_encoding(s
);
6867 /* For the LL variants the store is larger than the load,
6868 * so if rd == rn we would overwrite parts of our input.
6869 * So load everything right now and use shifts in the main loop.
6871 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
6873 for (i
= 0; i
< elements
; i
++) {
6874 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
6875 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
6876 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
6877 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
6882 /* C3.6.14 AdvSIMD shift by immediate
6883 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6884 * +---+---+---+-------------+------+------+--------+---+------+------+
6885 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6886 * +---+---+---+-------------+------+------+--------+---+------+------+
6888 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
6890 int rd
= extract32(insn
, 0, 5);
6891 int rn
= extract32(insn
, 5, 5);
6892 int opcode
= extract32(insn
, 11, 5);
6893 int immb
= extract32(insn
, 16, 3);
6894 int immh
= extract32(insn
, 19, 4);
6895 bool is_u
= extract32(insn
, 29, 1);
6896 bool is_q
= extract32(insn
, 30, 1);
6899 case 0x00: /* SSHR / USHR */
6900 case 0x02: /* SSRA / USRA (accumulate) */
6901 case 0x04: /* SRSHR / URSHR (rounding) */
6902 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6903 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6905 case 0x0a: /* SHL / SLI */
6906 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6908 case 0x14: /* SSHLL / USHLL */
6909 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6912 /* We don't currently implement any of the Narrow or saturating shifts;
6913 * nor do we implement the fixed-point conversions in this
6914 * encoding group (SCVTF, FCVTZS, UCVTF, FCVTZU).
6916 unsupported_encoding(s
, insn
);
6921 /* Generate code to do a "long" addition or subtraction, ie one done in
6922 * TCGv_i64 on vector lanes twice the width specified by size.
6924 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
6925 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
6927 static NeonGenTwo64OpFn
* const fns
[3][2] = {
6928 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
6929 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
6930 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
6932 NeonGenTwo64OpFn
*genfn
;
6935 genfn
= fns
[size
][is_sub
];
6936 genfn(tcg_res
, tcg_op1
, tcg_op2
);
6939 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
6940 int opcode
, int rd
, int rn
, int rm
)
6942 /* 3-reg-different widening insns: 64 x 64 -> 128 */
6943 TCGv_i64 tcg_res
[2];
6946 tcg_res
[0] = tcg_temp_new_i64();
6947 tcg_res
[1] = tcg_temp_new_i64();
6949 /* Does this op do an adding accumulate, a subtracting accumulate,
6950 * or no accumulate at all?
6968 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
6969 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
6972 /* size == 2 means two 32x32->64 operations; this is worth special
6973 * casing because we can generally handle it inline.
6976 for (pass
= 0; pass
< 2; pass
++) {
6977 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6978 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6979 TCGv_i64 tcg_passres
;
6980 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
6982 int elt
= pass
+ is_q
* 2;
6984 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
6985 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
6988 tcg_passres
= tcg_res
[pass
];
6990 tcg_passres
= tcg_temp_new_i64();
6994 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
6995 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
6997 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
6998 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7000 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7001 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7003 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
7004 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
7006 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
7007 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
7008 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
7010 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
7011 tcg_temp_free_i64(tcg_tmp1
);
7012 tcg_temp_free_i64(tcg_tmp2
);
7015 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7016 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7017 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
7018 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7020 case 9: /* SQDMLAL, SQDMLAL2 */
7021 case 11: /* SQDMLSL, SQDMLSL2 */
7022 case 13: /* SQDMULL, SQDMULL2 */
7023 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7024 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
7025 tcg_passres
, tcg_passres
);
7028 g_assert_not_reached();
7031 if (opcode
== 9 || opcode
== 11) {
7032 /* saturating accumulate ops */
7034 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
7036 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
7037 tcg_res
[pass
], tcg_passres
);
7038 } else if (accop
> 0) {
7039 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
7040 } else if (accop
< 0) {
7041 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
7045 tcg_temp_free_i64(tcg_passres
);
7048 tcg_temp_free_i64(tcg_op1
);
7049 tcg_temp_free_i64(tcg_op2
);
7052 /* size 0 or 1, generally helper functions */
7053 for (pass
= 0; pass
< 2; pass
++) {
7054 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7055 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7056 TCGv_i64 tcg_passres
;
7057 int elt
= pass
+ is_q
* 2;
7059 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
7060 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
7063 tcg_passres
= tcg_res
[pass
];
7065 tcg_passres
= tcg_temp_new_i64();
7069 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7070 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7072 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
7073 static NeonGenWidenFn
* const widenfns
[2][2] = {
7074 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
7075 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
7077 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
7079 widenfn(tcg_op2_64
, tcg_op2
);
7080 widenfn(tcg_passres
, tcg_op1
);
7081 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
7082 tcg_passres
, tcg_op2_64
);
7083 tcg_temp_free_i64(tcg_op2_64
);
7086 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7087 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7090 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
7092 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7096 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
7098 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
7102 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7103 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7104 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
7107 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
7109 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
7113 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
7115 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7119 case 9: /* SQDMLAL, SQDMLAL2 */
7120 case 11: /* SQDMLSL, SQDMLSL2 */
7121 case 13: /* SQDMULL, SQDMULL2 */
7123 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7124 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
7125 tcg_passres
, tcg_passres
);
7128 g_assert_not_reached();
7130 tcg_temp_free_i32(tcg_op1
);
7131 tcg_temp_free_i32(tcg_op2
);
7134 if (opcode
== 9 || opcode
== 11) {
7135 /* saturating accumulate ops */
7137 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
7139 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
7143 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
7144 tcg_res
[pass
], tcg_passres
);
7146 tcg_temp_free_i64(tcg_passres
);
7151 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
7152 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
7153 tcg_temp_free_i64(tcg_res
[0]);
7154 tcg_temp_free_i64(tcg_res
[1]);
7157 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
7158 int opcode
, int rd
, int rn
, int rm
)
7160 TCGv_i64 tcg_res
[2];
7161 int part
= is_q
? 2 : 0;
7164 for (pass
= 0; pass
< 2; pass
++) {
7165 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7166 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7167 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
7168 static NeonGenWidenFn
* const widenfns
[3][2] = {
7169 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
7170 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
7171 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
7173 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
7175 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7176 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
7177 widenfn(tcg_op2_wide
, tcg_op2
);
7178 tcg_temp_free_i32(tcg_op2
);
7179 tcg_res
[pass
] = tcg_temp_new_i64();
7180 gen_neon_addl(size
, (opcode
== 3),
7181 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
7182 tcg_temp_free_i64(tcg_op1
);
7183 tcg_temp_free_i64(tcg_op2_wide
);
7186 for (pass
= 0; pass
< 2; pass
++) {
7187 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
7188 tcg_temp_free_i64(tcg_res
[pass
]);
7192 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
7194 tcg_gen_shri_i64(in
, in
, 32);
7195 tcg_gen_trunc_i64_i32(res
, in
);
7198 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
7200 tcg_gen_addi_i64(in
, in
, 1U << 31);
7201 do_narrow_high_u32(res
, in
);
7204 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
7205 int opcode
, int rd
, int rn
, int rm
)
7207 TCGv_i32 tcg_res
[2];
7208 int part
= is_q
? 2 : 0;
7211 for (pass
= 0; pass
< 2; pass
++) {
7212 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7213 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7214 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
7215 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
7216 { gen_helper_neon_narrow_high_u8
,
7217 gen_helper_neon_narrow_round_high_u8
},
7218 { gen_helper_neon_narrow_high_u16
,
7219 gen_helper_neon_narrow_round_high_u16
},
7220 { do_narrow_high_u32
, do_narrow_round_high_u32
},
7222 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
7224 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7225 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7227 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
7229 tcg_temp_free_i64(tcg_op1
);
7230 tcg_temp_free_i64(tcg_op2
);
7232 tcg_res
[pass
] = tcg_temp_new_i32();
7233 gennarrow(tcg_res
[pass
], tcg_wideres
);
7234 tcg_temp_free_i64(tcg_wideres
);
7237 for (pass
= 0; pass
< 2; pass
++) {
7238 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
7239 tcg_temp_free_i32(tcg_res
[pass
]);
7242 clear_vec_high(s
, rd
);
7246 /* C3.6.15 AdvSIMD three different
7247 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7248 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
7249 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7250 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
7252 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7254 /* Instructions in this group fall into three basic classes
7255 * (in each case with the operation working on each element in
7256 * the input vectors):
7257 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
7259 * (2) wide 64 x 128 -> 128
7260 * (3) narrowing 128 x 128 -> 64
7261 * Here we do initial decode, catch unallocated cases and
7262 * dispatch to separate functions for each class.
7264 int is_q
= extract32(insn
, 30, 1);
7265 int is_u
= extract32(insn
, 29, 1);
7266 int size
= extract32(insn
, 22, 2);
7267 int opcode
= extract32(insn
, 12, 4);
7268 int rm
= extract32(insn
, 16, 5);
7269 int rn
= extract32(insn
, 5, 5);
7270 int rd
= extract32(insn
, 0, 5);
7273 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
7274 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
7275 /* 64 x 128 -> 128 */
7277 unallocated_encoding(s
);
7280 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
7282 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
7283 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
7284 /* 128 x 128 -> 64 */
7286 unallocated_encoding(s
);
7289 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
7291 case 14: /* PMULL, PMULL2 */
7292 if (is_u
|| size
== 1 || size
== 2) {
7293 unallocated_encoding(s
);
7296 unsupported_encoding(s
, insn
);
7298 case 9: /* SQDMLAL, SQDMLAL2 */
7299 case 11: /* SQDMLSL, SQDMLSL2 */
7300 case 13: /* SQDMULL, SQDMULL2 */
7301 if (is_u
|| size
== 0) {
7302 unallocated_encoding(s
);
7306 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7307 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7308 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7309 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7310 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7311 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7312 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
7313 /* 64 x 64 -> 128 */
7315 unallocated_encoding(s
);
7318 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
7321 /* opcode 15 not allocated */
7322 unallocated_encoding(s
);
7327 /* Logic op (opcode == 3) subgroup of C3.6.16. */
7328 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
7330 int rd
= extract32(insn
, 0, 5);
7331 int rn
= extract32(insn
, 5, 5);
7332 int rm
= extract32(insn
, 16, 5);
7333 int size
= extract32(insn
, 22, 2);
7334 bool is_u
= extract32(insn
, 29, 1);
7335 bool is_q
= extract32(insn
, 30, 1);
7336 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7337 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7338 TCGv_i64 tcg_res
[2];
7341 tcg_res
[0] = tcg_temp_new_i64();
7342 tcg_res
[1] = tcg_temp_new_i64();
7344 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
7345 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7346 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7351 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7354 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7357 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7360 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7365 /* B* ops need res loaded to operate on */
7366 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
7371 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7373 case 1: /* BSL bitwise select */
7374 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
7375 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
7376 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
7378 case 2: /* BIT, bitwise insert if true */
7379 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
7380 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
7381 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
7383 case 3: /* BIF, bitwise insert if false */
7384 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
7385 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
7386 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
7392 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
7394 tcg_gen_movi_i64(tcg_res
[1], 0);
7396 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
7398 tcg_temp_free_i64(tcg_op1
);
7399 tcg_temp_free_i64(tcg_op2
);
7400 tcg_temp_free_i64(tcg_res
[0]);
7401 tcg_temp_free_i64(tcg_res
[1]);
7404 /* Helper functions for 32 bit comparisons */
7405 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7407 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
7410 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7412 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
7415 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7417 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
7420 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7422 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
7425 /* Pairwise op subgroup of C3.6.16.
7427 * This is called directly or via the handle_3same_float for float pairwise
7428 * operations where the opcode and size are calculated differently.
7430 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
7431 int size
, int rn
, int rm
, int rd
)
7436 /* Floating point operations need fpst */
7437 if (opcode
>= 0x58) {
7438 fpst
= get_fpstatus_ptr();
7440 TCGV_UNUSED_PTR(fpst
);
7443 /* These operations work on the concatenated rm:rn, with each pair of
7444 * adjacent elements being operated on to produce an element in the result.
7447 TCGv_i64 tcg_res
[2];
7449 for (pass
= 0; pass
< 2; pass
++) {
7450 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7451 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7452 int passreg
= (pass
== 0) ? rn
: rm
;
7454 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
7455 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
7456 tcg_res
[pass
] = tcg_temp_new_i64();
7459 case 0x17: /* ADDP */
7460 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7462 case 0x58: /* FMAXNMP */
7463 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7465 case 0x5a: /* FADDP */
7466 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7468 case 0x5e: /* FMAXP */
7469 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7471 case 0x78: /* FMINNMP */
7472 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7474 case 0x7e: /* FMINP */
7475 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7478 g_assert_not_reached();
7481 tcg_temp_free_i64(tcg_op1
);
7482 tcg_temp_free_i64(tcg_op2
);
7485 for (pass
= 0; pass
< 2; pass
++) {
7486 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
7487 tcg_temp_free_i64(tcg_res
[pass
]);
7490 int maxpass
= is_q
? 4 : 2;
7491 TCGv_i32 tcg_res
[4];
7493 for (pass
= 0; pass
< maxpass
; pass
++) {
7494 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7495 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7496 NeonGenTwoOpFn
*genfn
= NULL
;
7497 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
7498 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
7500 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
7501 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
7502 tcg_res
[pass
] = tcg_temp_new_i32();
7505 case 0x17: /* ADDP */
7507 static NeonGenTwoOpFn
* const fns
[3] = {
7508 gen_helper_neon_padd_u8
,
7509 gen_helper_neon_padd_u16
,
7515 case 0x14: /* SMAXP, UMAXP */
7517 static NeonGenTwoOpFn
* const fns
[3][2] = {
7518 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
7519 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
7520 { gen_max_s32
, gen_max_u32
},
7522 genfn
= fns
[size
][u
];
7525 case 0x15: /* SMINP, UMINP */
7527 static NeonGenTwoOpFn
* const fns
[3][2] = {
7528 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
7529 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
7530 { gen_min_s32
, gen_min_u32
},
7532 genfn
= fns
[size
][u
];
7535 /* The FP operations are all on single floats (32 bit) */
7536 case 0x58: /* FMAXNMP */
7537 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7539 case 0x5a: /* FADDP */
7540 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7542 case 0x5e: /* FMAXP */
7543 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7545 case 0x78: /* FMINNMP */
7546 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7548 case 0x7e: /* FMINP */
7549 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
7552 g_assert_not_reached();
7555 /* FP ops called directly, otherwise call now */
7557 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7560 tcg_temp_free_i32(tcg_op1
);
7561 tcg_temp_free_i32(tcg_op2
);
7564 for (pass
= 0; pass
< maxpass
; pass
++) {
7565 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
7566 tcg_temp_free_i32(tcg_res
[pass
]);
7569 clear_vec_high(s
, rd
);
7573 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
7574 tcg_temp_free_ptr(fpst
);
7578 /* Floating point op subgroup of C3.6.16. */
7579 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
7581 /* For floating point ops, the U, size[1] and opcode bits
7582 * together indicate the operation. size[0] indicates single
7585 int fpopcode
= extract32(insn
, 11, 5)
7586 | (extract32(insn
, 23, 1) << 5)
7587 | (extract32(insn
, 29, 1) << 6);
7588 int is_q
= extract32(insn
, 30, 1);
7589 int size
= extract32(insn
, 22, 1);
7590 int rm
= extract32(insn
, 16, 5);
7591 int rn
= extract32(insn
, 5, 5);
7592 int rd
= extract32(insn
, 0, 5);
7594 int datasize
= is_q
? 128 : 64;
7595 int esize
= 32 << size
;
7596 int elements
= datasize
/ esize
;
7598 if (size
== 1 && !is_q
) {
7599 unallocated_encoding(s
);
7604 case 0x58: /* FMAXNMP */
7605 case 0x5a: /* FADDP */
7606 case 0x5e: /* FMAXP */
7607 case 0x78: /* FMINNMP */
7608 case 0x7e: /* FMINP */
7609 if (size
&& !is_q
) {
7610 unallocated_encoding(s
);
7613 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
7616 case 0x1b: /* FMULX */
7617 case 0x1f: /* FRECPS */
7618 case 0x3f: /* FRSQRTS */
7619 case 0x5d: /* FACGE */
7620 case 0x7d: /* FACGT */
7621 case 0x19: /* FMLA */
7622 case 0x39: /* FMLS */
7623 case 0x18: /* FMAXNM */
7624 case 0x1a: /* FADD */
7625 case 0x1c: /* FCMEQ */
7626 case 0x1e: /* FMAX */
7627 case 0x38: /* FMINNM */
7628 case 0x3a: /* FSUB */
7629 case 0x3e: /* FMIN */
7630 case 0x5b: /* FMUL */
7631 case 0x5c: /* FCMGE */
7632 case 0x5f: /* FDIV */
7633 case 0x7a: /* FABD */
7634 case 0x7c: /* FCMGT */
7635 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
7638 unallocated_encoding(s
);
7643 /* Integer op subgroup of C3.6.16. */
7644 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
7646 int is_q
= extract32(insn
, 30, 1);
7647 int u
= extract32(insn
, 29, 1);
7648 int size
= extract32(insn
, 22, 2);
7649 int opcode
= extract32(insn
, 11, 5);
7650 int rm
= extract32(insn
, 16, 5);
7651 int rn
= extract32(insn
, 5, 5);
7652 int rd
= extract32(insn
, 0, 5);
7656 case 0x13: /* MUL, PMUL */
7657 if (u
&& size
!= 0) {
7658 unallocated_encoding(s
);
7662 case 0x0: /* SHADD, UHADD */
7663 case 0x2: /* SRHADD, URHADD */
7664 case 0x4: /* SHSUB, UHSUB */
7665 case 0xc: /* SMAX, UMAX */
7666 case 0xd: /* SMIN, UMIN */
7667 case 0xe: /* SABD, UABD */
7668 case 0xf: /* SABA, UABA */
7669 case 0x12: /* MLA, MLS */
7671 unallocated_encoding(s
);
7675 case 0x16: /* SQDMULH, SQRDMULH */
7676 if (size
== 0 || size
== 3) {
7677 unallocated_encoding(s
);
7682 if (size
== 3 && !is_q
) {
7683 unallocated_encoding(s
);
7690 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
7691 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7692 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7693 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7695 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7696 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7698 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
7700 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7702 tcg_temp_free_i64(tcg_res
);
7703 tcg_temp_free_i64(tcg_op1
);
7704 tcg_temp_free_i64(tcg_op2
);
7707 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
7708 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7709 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7710 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7711 NeonGenTwoOpFn
*genfn
= NULL
;
7712 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
7714 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7715 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7718 case 0x0: /* SHADD, UHADD */
7720 static NeonGenTwoOpFn
* const fns
[3][2] = {
7721 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
7722 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
7723 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
7725 genfn
= fns
[size
][u
];
7728 case 0x1: /* SQADD, UQADD */
7730 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7731 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7732 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7733 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7735 genenvfn
= fns
[size
][u
];
7738 case 0x2: /* SRHADD, URHADD */
7740 static NeonGenTwoOpFn
* const fns
[3][2] = {
7741 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
7742 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
7743 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
7745 genfn
= fns
[size
][u
];
7748 case 0x4: /* SHSUB, UHSUB */
7750 static NeonGenTwoOpFn
* const fns
[3][2] = {
7751 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
7752 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
7753 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
7755 genfn
= fns
[size
][u
];
7758 case 0x5: /* SQSUB, UQSUB */
7760 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7761 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7762 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7763 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7765 genenvfn
= fns
[size
][u
];
7768 case 0x6: /* CMGT, CMHI */
7770 static NeonGenTwoOpFn
* const fns
[3][2] = {
7771 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
7772 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
7773 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
7775 genfn
= fns
[size
][u
];
7778 case 0x7: /* CMGE, CMHS */
7780 static NeonGenTwoOpFn
* const fns
[3][2] = {
7781 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
7782 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
7783 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
7785 genfn
= fns
[size
][u
];
7788 case 0x8: /* SSHL, USHL */
7790 static NeonGenTwoOpFn
* const fns
[3][2] = {
7791 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
7792 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
7793 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
7795 genfn
= fns
[size
][u
];
7798 case 0x9: /* SQSHL, UQSHL */
7800 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7801 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7802 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7803 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7805 genenvfn
= fns
[size
][u
];
7808 case 0xa: /* SRSHL, URSHL */
7810 static NeonGenTwoOpFn
* const fns
[3][2] = {
7811 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
7812 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
7813 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
7815 genfn
= fns
[size
][u
];
7818 case 0xb: /* SQRSHL, UQRSHL */
7820 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7821 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7822 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7823 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7825 genenvfn
= fns
[size
][u
];
7828 case 0xc: /* SMAX, UMAX */
7830 static NeonGenTwoOpFn
* const fns
[3][2] = {
7831 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
7832 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
7833 { gen_max_s32
, gen_max_u32
},
7835 genfn
= fns
[size
][u
];
7839 case 0xd: /* SMIN, UMIN */
7841 static NeonGenTwoOpFn
* const fns
[3][2] = {
7842 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
7843 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
7844 { gen_min_s32
, gen_min_u32
},
7846 genfn
= fns
[size
][u
];
7849 case 0xe: /* SABD, UABD */
7850 case 0xf: /* SABA, UABA */
7852 static NeonGenTwoOpFn
* const fns
[3][2] = {
7853 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
7854 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
7855 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
7857 genfn
= fns
[size
][u
];
7860 case 0x10: /* ADD, SUB */
7862 static NeonGenTwoOpFn
* const fns
[3][2] = {
7863 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
7864 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
7865 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
7867 genfn
= fns
[size
][u
];
7870 case 0x11: /* CMTST, CMEQ */
7872 static NeonGenTwoOpFn
* const fns
[3][2] = {
7873 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
7874 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
7875 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
7877 genfn
= fns
[size
][u
];
7880 case 0x13: /* MUL, PMUL */
7884 genfn
= gen_helper_neon_mul_p8
;
7887 /* fall through : MUL */
7888 case 0x12: /* MLA, MLS */
7890 static NeonGenTwoOpFn
* const fns
[3] = {
7891 gen_helper_neon_mul_u8
,
7892 gen_helper_neon_mul_u16
,
7898 case 0x16: /* SQDMULH, SQRDMULH */
7900 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7901 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7902 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7904 assert(size
== 1 || size
== 2);
7905 genenvfn
= fns
[size
- 1][u
];
7909 g_assert_not_reached();
7913 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
7915 genfn(tcg_res
, tcg_op1
, tcg_op2
);
7918 if (opcode
== 0xf || opcode
== 0x12) {
7919 /* SABA, UABA, MLA, MLS: accumulating ops */
7920 static NeonGenTwoOpFn
* const fns
[3][2] = {
7921 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
7922 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
7923 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
7925 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
7927 genfn
= fns
[size
][is_sub
];
7928 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
7929 genfn(tcg_res
, tcg_res
, tcg_op1
);
7932 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7934 tcg_temp_free_i32(tcg_res
);
7935 tcg_temp_free_i32(tcg_op1
);
7936 tcg_temp_free_i32(tcg_op2
);
7941 clear_vec_high(s
, rd
);
7945 /* C3.6.16 AdvSIMD three same
7946 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7947 * +---+---+---+-----------+------+---+------+--------+---+------+------+
7948 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7949 * +---+---+---+-----------+------+---+------+--------+---+------+------+
7951 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
7953 int opcode
= extract32(insn
, 11, 5);
7956 case 0x3: /* logic ops */
7957 disas_simd_3same_logic(s
, insn
);
7959 case 0x17: /* ADDP */
7960 case 0x14: /* SMAXP, UMAXP */
7961 case 0x15: /* SMINP, UMINP */
7963 /* Pairwise operations */
7964 int is_q
= extract32(insn
, 30, 1);
7965 int u
= extract32(insn
, 29, 1);
7966 int size
= extract32(insn
, 22, 2);
7967 int rm
= extract32(insn
, 16, 5);
7968 int rn
= extract32(insn
, 5, 5);
7969 int rd
= extract32(insn
, 0, 5);
7970 if (opcode
== 0x17) {
7971 if (u
|| (size
== 3 && !is_q
)) {
7972 unallocated_encoding(s
);
7977 unallocated_encoding(s
);
7981 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
7985 /* floating point ops, sz[1] and U are part of opcode */
7986 disas_simd_3same_float(s
, insn
);
7989 disas_simd_3same_int(s
, insn
);
7994 static void handle_2misc_narrow(DisasContext
*s
, int opcode
, bool u
, bool is_q
,
7995 int size
, int rn
, int rd
)
7997 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7998 * in the source becomes a size element in the destination).
8001 TCGv_i32 tcg_res
[2];
8002 int destelt
= is_q
? 2 : 0;
8004 for (pass
= 0; pass
< 2; pass
++) {
8005 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8006 NeonGenNarrowFn
*genfn
= NULL
;
8007 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
8009 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8010 tcg_res
[pass
] = tcg_temp_new_i32();
8013 case 0x12: /* XTN, SQXTUN */
8015 static NeonGenNarrowFn
* const xtnfns
[3] = {
8016 gen_helper_neon_narrow_u8
,
8017 gen_helper_neon_narrow_u16
,
8018 tcg_gen_trunc_i64_i32
,
8020 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
8021 gen_helper_neon_unarrow_sat8
,
8022 gen_helper_neon_unarrow_sat16
,
8023 gen_helper_neon_unarrow_sat32
,
8026 genenvfn
= sqxtunfns
[size
];
8028 genfn
= xtnfns
[size
];
8032 case 0x14: /* SQXTN, UQXTN */
8034 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
8035 { gen_helper_neon_narrow_sat_s8
,
8036 gen_helper_neon_narrow_sat_u8
},
8037 { gen_helper_neon_narrow_sat_s16
,
8038 gen_helper_neon_narrow_sat_u16
},
8039 { gen_helper_neon_narrow_sat_s32
,
8040 gen_helper_neon_narrow_sat_u32
},
8042 genenvfn
= fns
[size
][u
];
8046 g_assert_not_reached();
8050 genfn(tcg_res
[pass
], tcg_op
);
8052 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
8055 tcg_temp_free_i64(tcg_op
);
8058 for (pass
= 0; pass
< 2; pass
++) {
8059 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
8060 tcg_temp_free_i32(tcg_res
[pass
]);
8063 clear_vec_high(s
, rd
);
8067 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
8068 bool is_q
, int size
, int rn
, int rd
)
8070 int op
= (opcode
<< 1) | u
;
8071 int opsz
= op
+ size
;
8072 int grp_size
= 3 - opsz
;
8073 int dsize
= is_q
? 128 : 64;
8077 unallocated_encoding(s
);
8082 /* Special case bytes, use bswap op on each group of elements */
8083 int groups
= dsize
/ (8 << grp_size
);
8085 for (i
= 0; i
< groups
; i
++) {
8086 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8088 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
8091 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
8094 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
8097 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
8100 g_assert_not_reached();
8102 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
8103 tcg_temp_free_i64(tcg_tmp
);
8106 clear_vec_high(s
, rd
);
8109 int revmask
= (1 << grp_size
) - 1;
8110 int esize
= 8 << size
;
8111 int elements
= dsize
/ esize
;
8112 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8113 TCGv_i64 tcg_rd
= tcg_const_i64(0);
8114 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
8116 for (i
= 0; i
< elements
; i
++) {
8117 int e_rev
= (i
& 0xf) ^ revmask
;
8118 int off
= e_rev
* esize
;
8119 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8121 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
8122 tcg_rn
, off
- 64, esize
);
8124 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
8127 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
8128 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
8130 tcg_temp_free_i64(tcg_rd_hi
);
8131 tcg_temp_free_i64(tcg_rd
);
8132 tcg_temp_free_i64(tcg_rn
);
8136 /* C3.6.17 AdvSIMD two reg misc
8137 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8138 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
8139 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8140 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
8142 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8144 int size
= extract32(insn
, 22, 2);
8145 int opcode
= extract32(insn
, 12, 5);
8146 bool u
= extract32(insn
, 29, 1);
8147 bool is_q
= extract32(insn
, 30, 1);
8148 int rn
= extract32(insn
, 5, 5);
8149 int rd
= extract32(insn
, 0, 5);
8152 case 0x0: /* REV64, REV32 */
8153 case 0x1: /* REV16 */
8154 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
8156 case 0x5: /* CNT, NOT, RBIT */
8157 if (u
&& size
== 0) {
8158 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
8161 } else if (u
&& size
== 1) {
8164 } else if (!u
&& size
== 0) {
8168 unallocated_encoding(s
);
8170 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
8171 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
8173 unallocated_encoding(s
);
8176 handle_2misc_narrow(s
, opcode
, u
, is_q
, size
, rn
, rd
);
8178 case 0x2: /* SADDLP, UADDLP */
8179 case 0x4: /* CLS, CLZ */
8180 case 0x6: /* SADALP, UADALP */
8182 unallocated_encoding(s
);
8185 unsupported_encoding(s
, insn
);
8187 case 0x13: /* SHLL, SHLL2 */
8188 if (u
== 0 || size
== 3) {
8189 unallocated_encoding(s
);
8192 unsupported_encoding(s
, insn
);
8194 case 0xa: /* CMLT */
8196 unallocated_encoding(s
);
8200 case 0x8: /* CMGT, CMGE */
8201 case 0x9: /* CMEQ, CMLE */
8202 case 0xb: /* ABS, NEG */
8203 if (size
== 3 && !is_q
) {
8204 unallocated_encoding(s
);
8208 case 0x3: /* SUQADD, USQADD */
8209 case 0x7: /* SQABS, SQNEG */
8210 if (size
== 3 && !is_q
) {
8211 unallocated_encoding(s
);
8214 unsupported_encoding(s
, insn
);
8220 /* Floating point: U, size[1] and opcode indicate operation;
8221 * size[0] indicates single or double precision.
8223 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8224 size
= extract32(size
, 0, 1) ? 3 : 2;
8226 case 0x2f: /* FABS */
8227 case 0x6f: /* FNEG */
8228 if (size
== 3 && !is_q
) {
8229 unallocated_encoding(s
);
8233 case 0x2c: /* FCMGT (zero) */
8234 case 0x2d: /* FCMEQ (zero) */
8235 case 0x2e: /* FCMLT (zero) */
8236 case 0x6c: /* FCMGE (zero) */
8237 case 0x6d: /* FCMLE (zero) */
8238 if (size
== 3 && !is_q
) {
8239 unallocated_encoding(s
);
8242 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
8244 case 0x16: /* FCVTN, FCVTN2 */
8245 case 0x17: /* FCVTL, FCVTL2 */
8246 case 0x18: /* FRINTN */
8247 case 0x19: /* FRINTM */
8248 case 0x1a: /* FCVTNS */
8249 case 0x1b: /* FCVTMS */
8250 case 0x1c: /* FCVTAS */
8251 case 0x1d: /* SCVTF */
8252 case 0x38: /* FRINTP */
8253 case 0x39: /* FRINTZ */
8254 case 0x3a: /* FCVTPS */
8255 case 0x3b: /* FCVTZS */
8256 case 0x3c: /* URECPE */
8257 case 0x3d: /* FRECPE */
8258 case 0x56: /* FCVTXN, FCVTXN2 */
8259 case 0x58: /* FRINTA */
8260 case 0x59: /* FRINTX */
8261 case 0x5a: /* FCVTNU */
8262 case 0x5b: /* FCVTMU */
8263 case 0x5c: /* FCVTAU */
8264 case 0x5d: /* UCVTF */
8265 case 0x79: /* FRINTI */
8266 case 0x7a: /* FCVTPU */
8267 case 0x7b: /* FCVTZU */
8268 case 0x7c: /* URSQRTE */
8269 case 0x7d: /* FRSQRTE */
8270 case 0x7f: /* FSQRT */
8271 unsupported_encoding(s
, insn
);
8274 unallocated_encoding(s
);
8280 unallocated_encoding(s
);
8285 /* All 64-bit element operations can be shared with scalar 2misc */
8288 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8289 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8290 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8292 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8294 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
);
8296 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8298 tcg_temp_free_i64(tcg_res
);
8299 tcg_temp_free_i64(tcg_op
);
8304 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
8305 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8306 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8309 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
8312 /* Special cases for 32 bit elements */
8314 case 0xa: /* CMLT */
8315 /* 32 bit integer comparison against zero, result is
8316 * test ? (2^32 - 1) : 0. We implement via setcond(test)
8321 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
8322 tcg_gen_neg_i32(tcg_res
, tcg_res
);
8324 case 0x8: /* CMGT, CMGE */
8325 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
8327 case 0x9: /* CMEQ, CMLE */
8328 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
8330 case 0xb: /* ABS, NEG */
8332 tcg_gen_neg_i32(tcg_res
, tcg_op
);
8334 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8335 tcg_gen_neg_i32(tcg_res
, tcg_op
);
8336 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
8337 tcg_zero
, tcg_op
, tcg_res
);
8338 tcg_temp_free_i32(tcg_zero
);
8341 case 0x2f: /* FABS */
8342 gen_helper_vfp_abss(tcg_res
, tcg_op
);
8344 case 0x6f: /* FNEG */
8345 gen_helper_vfp_negs(tcg_res
, tcg_op
);
8348 g_assert_not_reached();
8351 /* Use helpers for 8 and 16 bit elements */
8353 case 0x5: /* CNT, RBIT */
8354 /* For these two insns size is part of the opcode specifier
8355 * (handled earlier); they always operate on byte elements.
8358 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
8360 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
8363 case 0x8: /* CMGT, CMGE */
8364 case 0x9: /* CMEQ, CMLE */
8365 case 0xa: /* CMLT */
8367 static NeonGenTwoOpFn
* const fns
[3][2] = {
8368 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
8369 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
8370 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
8372 NeonGenTwoOpFn
*genfn
;
8375 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8377 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
8378 comp
= (opcode
- 0x8) * 2 + u
;
8379 /* ...but LE, LT are implemented as reverse GE, GT */
8380 reverse
= (comp
> 2);
8384 genfn
= fns
[comp
][size
];
8386 genfn(tcg_res
, tcg_zero
, tcg_op
);
8388 genfn(tcg_res
, tcg_op
, tcg_zero
);
8390 tcg_temp_free_i32(tcg_zero
);
8393 case 0xb: /* ABS, NEG */
8395 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8397 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
8399 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
8401 tcg_temp_free_i32(tcg_zero
);
8404 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
8406 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
8411 g_assert_not_reached();
8415 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8417 tcg_temp_free_i32(tcg_res
);
8418 tcg_temp_free_i32(tcg_op
);
8422 clear_vec_high(s
, rd
);
8426 /* C3.6.13 AdvSIMD scalar x indexed element
8427 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
8428 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
8429 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
8430 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
8431 * C3.6.18 AdvSIMD vector x indexed element
8432 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
8433 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
8434 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
8435 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
8437 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
8439 /* This encoding has two kinds of instruction:
8440 * normal, where we perform elt x idxelt => elt for each
8441 * element in the vector
8442 * long, where we perform elt x idxelt and generate a result of
8443 * double the width of the input element
8444 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
8446 bool is_scalar
= extract32(insn
, 28, 1);
8447 bool is_q
= extract32(insn
, 30, 1);
8448 bool u
= extract32(insn
, 29, 1);
8449 int size
= extract32(insn
, 22, 2);
8450 int l
= extract32(insn
, 21, 1);
8451 int m
= extract32(insn
, 20, 1);
8452 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
8453 int rm
= extract32(insn
, 16, 4);
8454 int opcode
= extract32(insn
, 12, 4);
8455 int h
= extract32(insn
, 11, 1);
8456 int rn
= extract32(insn
, 5, 5);
8457 int rd
= extract32(insn
, 0, 5);
8458 bool is_long
= false;
8466 if (!u
|| is_scalar
) {
8467 unallocated_encoding(s
);
8471 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8472 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8473 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
8475 unallocated_encoding(s
);
8480 case 0x3: /* SQDMLAL, SQDMLAL2 */
8481 case 0x7: /* SQDMLSL, SQDMLSL2 */
8482 case 0xb: /* SQDMULL, SQDMULL2 */
8485 case 0xc: /* SQDMULH */
8486 case 0xd: /* SQRDMULH */
8488 unallocated_encoding(s
);
8493 if (u
|| is_scalar
) {
8494 unallocated_encoding(s
);
8498 case 0x1: /* FMLA */
8499 case 0x5: /* FMLS */
8501 unallocated_encoding(s
);
8505 case 0x9: /* FMUL, FMULX */
8506 if (!extract32(size
, 1, 1)) {
8507 unallocated_encoding(s
);
8513 unallocated_encoding(s
);
8518 /* low bit of size indicates single/double */
8519 size
= extract32(size
, 0, 1) ? 3 : 2;
8524 unallocated_encoding(s
);
8533 index
= h
<< 2 | l
<< 1 | m
;
8540 unallocated_encoding(s
);
8546 fpst
= get_fpstatus_ptr();
8548 TCGV_UNUSED_PTR(fpst
);
8552 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
8555 assert(is_fp
&& is_q
&& !is_long
);
8557 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
8559 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8560 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8561 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8563 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8566 case 0x5: /* FMLS */
8567 /* As usual for ARM, separate negation for fused multiply-add */
8568 gen_helper_vfp_negd(tcg_op
, tcg_op
);
8570 case 0x1: /* FMLA */
8571 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8572 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
8574 case 0x9: /* FMUL, FMULX */
8576 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
8578 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
8582 g_assert_not_reached();
8585 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8586 tcg_temp_free_i64(tcg_op
);
8587 tcg_temp_free_i64(tcg_res
);
8591 clear_vec_high(s
, rd
);
8594 tcg_temp_free_i64(tcg_idx
);
8595 } else if (!is_long
) {
8596 /* 32 bit floating point, or 16 or 32 bit integer.
8597 * For the 16 bit scalar case we use the usual Neon helpers and
8598 * rely on the fact that 0 op 0 == 0 with no side effects.
8600 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
8601 int pass
, maxpasses
;
8606 maxpasses
= is_q
? 4 : 2;
8609 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
8611 if (size
== 1 && !is_scalar
) {
8612 /* The simplest way to handle the 16x16 indexed ops is to duplicate
8613 * the index into both halves of the 32 bit tcg_idx and then use
8614 * the usual Neon helpers.
8616 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
8619 for (pass
= 0; pass
< maxpasses
; pass
++) {
8620 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8621 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8623 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
8630 static NeonGenTwoOpFn
* const fns
[2][2] = {
8631 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
8632 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
8634 NeonGenTwoOpFn
*genfn
;
8635 bool is_sub
= opcode
== 0x4;
8638 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
8640 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
8642 if (opcode
== 0x8) {
8645 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8646 genfn
= fns
[size
- 1][is_sub
];
8647 genfn(tcg_res
, tcg_op
, tcg_res
);
8650 case 0x5: /* FMLS */
8651 /* As usual for ARM, separate negation for fused multiply-add */
8652 gen_helper_vfp_negs(tcg_op
, tcg_op
);
8654 case 0x1: /* FMLA */
8655 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8656 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
8658 case 0x9: /* FMUL, FMULX */
8660 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
8662 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
8665 case 0xc: /* SQDMULH */
8667 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
8670 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
8674 case 0xd: /* SQRDMULH */
8676 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
8679 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
8684 g_assert_not_reached();
8688 write_fp_sreg(s
, rd
, tcg_res
);
8690 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8693 tcg_temp_free_i32(tcg_op
);
8694 tcg_temp_free_i32(tcg_res
);
8697 tcg_temp_free_i32(tcg_idx
);
8700 clear_vec_high(s
, rd
);
8703 /* long ops: 16x16->32 or 32x32->64 */
8704 TCGv_i64 tcg_res
[2];
8706 bool satop
= extract32(opcode
, 0, 1);
8707 TCGMemOp memop
= MO_32
;
8714 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
8716 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
8718 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8719 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8720 TCGv_i64 tcg_passres
;
8726 passelt
= pass
+ (is_q
* 2);
8729 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
8731 tcg_res
[pass
] = tcg_temp_new_i64();
8733 if (opcode
== 0xa || opcode
== 0xb) {
8734 /* Non-accumulating ops */
8735 tcg_passres
= tcg_res
[pass
];
8737 tcg_passres
= tcg_temp_new_i64();
8740 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
8741 tcg_temp_free_i64(tcg_op
);
8744 /* saturating, doubling */
8745 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8746 tcg_passres
, tcg_passres
);
8749 if (opcode
== 0xa || opcode
== 0xb) {
8753 /* Accumulating op: handle accumulate step */
8754 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8757 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8758 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8760 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8761 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8763 case 0x7: /* SQDMLSL, SQDMLSL2 */
8764 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8766 case 0x3: /* SQDMLAL, SQDMLAL2 */
8767 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8772 g_assert_not_reached();
8774 tcg_temp_free_i64(tcg_passres
);
8776 tcg_temp_free_i64(tcg_idx
);
8779 clear_vec_high(s
, rd
);
8782 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
8785 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
8788 /* The simplest way to handle the 16x16 indexed ops is to
8789 * duplicate the index into both halves of the 32 bit tcg_idx
8790 * and then use the usual Neon helpers.
8792 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
8795 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8796 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8797 TCGv_i64 tcg_passres
;
8800 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8802 read_vec_element_i32(s
, tcg_op
, rn
,
8803 pass
+ (is_q
* 2), MO_32
);
8806 tcg_res
[pass
] = tcg_temp_new_i64();
8808 if (opcode
== 0xa || opcode
== 0xb) {
8809 /* Non-accumulating ops */
8810 tcg_passres
= tcg_res
[pass
];
8812 tcg_passres
= tcg_temp_new_i64();
8815 if (memop
& MO_SIGN
) {
8816 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
8818 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
8821 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8822 tcg_passres
, tcg_passres
);
8824 tcg_temp_free_i32(tcg_op
);
8826 if (opcode
== 0xa || opcode
== 0xb) {
8830 /* Accumulating op: handle accumulate step */
8831 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8834 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8835 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
8838 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8839 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
8842 case 0x7: /* SQDMLSL, SQDMLSL2 */
8843 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8845 case 0x3: /* SQDMLAL, SQDMLAL2 */
8846 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8851 g_assert_not_reached();
8853 tcg_temp_free_i64(tcg_passres
);
8855 tcg_temp_free_i32(tcg_idx
);
8858 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
8863 tcg_res
[1] = tcg_const_i64(0);
8866 for (pass
= 0; pass
< 2; pass
++) {
8867 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8868 tcg_temp_free_i64(tcg_res
[pass
]);
8872 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8873 tcg_temp_free_ptr(fpst
);
8877 /* C3.6.19 Crypto AES
8878 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
8879 * +-----------------+------+-----------+--------+-----+------+------+
8880 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
8881 * +-----------------+------+-----------+--------+-----+------+------+
8883 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
8885 unsupported_encoding(s
, insn
);
8888 /* C3.6.20 Crypto three-reg SHA
8889 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
8890 * +-----------------+------+---+------+---+--------+-----+------+------+
8891 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
8892 * +-----------------+------+---+------+---+--------+-----+------+------+
8894 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
8896 unsupported_encoding(s
, insn
);
8899 /* C3.6.21 Crypto two-reg SHA
8900 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
8901 * +-----------------+------+-----------+--------+-----+------+------+
8902 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
8903 * +-----------------+------+-----------+--------+-----+------+------+
8905 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
8907 unsupported_encoding(s
, insn
);
8910 /* C3.6 Data processing - SIMD, inc Crypto
8912 * As the decode gets a little complex we are using a table based
8913 * approach for this part of the decode.
8915 static const AArch64DecodeTable data_proc_simd
[] = {
8916 /* pattern , mask , fn */
8917 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
8918 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
8919 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
8920 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
8921 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
8922 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
8923 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
8924 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
8925 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
8926 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
8927 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
8928 { 0x2e000000, 0xbf208400, disas_simd_ext
},
8929 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
8930 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
8931 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
8932 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
8933 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
8934 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
8935 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
8936 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
8937 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
8938 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
8939 { 0x00000000, 0x00000000, NULL
}
8942 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
8944 /* Note that this is called with all non-FP cases from
8945 * table C3-6 so it must UNDEF for entries not specifically
8946 * allocated to instructions in that table.
8948 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
8952 unallocated_encoding(s
);
8956 /* C3.6 Data processing - SIMD and floating point */
8957 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
8959 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
8960 disas_data_proc_fp(s
, insn
);
8962 /* SIMD, including crypto */
8963 disas_data_proc_simd(s
, insn
);
8967 /* C3.1 A64 instruction index by encoding */
8968 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
8972 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
8976 switch (extract32(insn
, 25, 4)) {
8977 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
8978 unallocated_encoding(s
);
8980 case 0x8: case 0x9: /* Data processing - immediate */
8981 disas_data_proc_imm(s
, insn
);
8983 case 0xa: case 0xb: /* Branch, exception generation and system insns */
8984 disas_b_exc_sys(s
, insn
);
8989 case 0xe: /* Loads and stores */
8990 disas_ldst(s
, insn
);
8993 case 0xd: /* Data processing - register */
8994 disas_data_proc_reg(s
, insn
);
8997 case 0xf: /* Data processing - SIMD and floating point */
8998 disas_data_proc_simd_fp(s
, insn
);
9001 assert(FALSE
); /* all 15 cases should be handled above */
9005 /* if we allocated any temporaries, free them here */
9009 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
9010 TranslationBlock
*tb
,
9013 CPUState
*cs
= CPU(cpu
);
9014 CPUARMState
*env
= &cpu
->env
;
9015 DisasContext dc1
, *dc
= &dc1
;
9017 uint16_t *gen_opc_end
;
9019 target_ulong pc_start
;
9020 target_ulong next_page_start
;
9028 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
9030 dc
->is_jmp
= DISAS_NEXT
;
9032 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
9038 dc
->condexec_mask
= 0;
9039 dc
->condexec_cond
= 0;
9040 #if !defined(CONFIG_USER_ONLY)
9041 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
9043 dc
->vfp_enabled
= 0;
9046 dc
->cp_regs
= cpu
->cp_regs
;
9047 dc
->current_pl
= arm_current_pl(env
);
9049 init_tmp_a64_array(dc
);
9051 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
9054 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9055 if (max_insns
== 0) {
9056 max_insns
= CF_COUNT_MASK
;
9061 tcg_clear_temp_count();
9064 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9065 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9066 if (bp
->pc
== dc
->pc
) {
9067 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
9068 /* Advance PC so that clearing the breakpoint will
9069 invalidate this TB. */
9071 goto done_generating
;
9077 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9081 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9084 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
9085 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
9086 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
9089 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
9093 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
9094 tcg_gen_debug_insn_start(dc
->pc
);
9097 disas_a64_insn(env
, dc
);
9099 if (tcg_check_temp_count()) {
9100 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
9104 /* Translation stops when a conditional branch is encountered.
9105 * Otherwise the subsequent code could get translated several times.
9106 * Also stop translation when a page boundary is reached. This
9107 * ensures prefetch aborts occur at the right place.
9110 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
9111 !cs
->singlestep_enabled
&&
9113 dc
->pc
< next_page_start
&&
9114 num_insns
< max_insns
);
9116 if (tb
->cflags
& CF_LAST_IO
) {
9120 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
9121 /* Note that this means single stepping WFI doesn't halt the CPU.
9122 * For conditional branch insns this is harmless unreachable code as
9123 * gen_goto_tb() has already handled emitting the debug exception
9124 * (and thus a tb-jump is not possible when singlestepping).
9126 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
9127 if (dc
->is_jmp
!= DISAS_JUMP
) {
9128 gen_a64_set_pc_im(dc
->pc
);
9130 gen_exception(EXCP_DEBUG
);
9132 switch (dc
->is_jmp
) {
9134 gen_goto_tb(dc
, 1, dc
->pc
);
9138 gen_a64_set_pc_im(dc
->pc
);
9141 /* indicate that the hash table must be used to find the next TB */
9149 /* This is a special case because we don't want to just halt the CPU
9150 * if trying to debug across a WFI.
9152 gen_a64_set_pc_im(dc
->pc
);
9153 gen_helper_wfi(cpu_env
);
9159 gen_tb_end(tb
, num_insns
);
9160 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
9163 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9164 qemu_log("----------------\n");
9165 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9166 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
9167 4 | (dc
->bswap_code
<< 1));
9172 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9175 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9178 tb
->size
= dc
->pc
- pc_start
;
9179 tb
->icount
= num_insns
;