target-arm/helper.c

   1 #include "cpu.h"
   2 #include "exec/gdbstub.h"
   3 #include "helper.h"
   4 #include "qemu/host-utils.h"
   5 #include "sysemu/arch_init.h"
   6 #include "sysemu/sysemu.h"
   7 #include "qemu/bitops.h"
   8 #include "qemu/crc32c.h"
   9 #include <zlib.h> /* For crc32 */
  10
  11 #ifndef CONFIG_USER_ONLY
  12 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
  13                                 int access_type, int is_user,
  14                                 hwaddr *phys_ptr, int *prot,
  15                                 target_ulong *page_size);
  16 #endif
  17
  18 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  19 {
  20     int nregs;
  21
  22     /* VFP data registers are always little-endian.  */
  23     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  24     if (reg < nregs) {
  25         stfq_le_p(buf, env->vfp.regs[reg]);
  26         return 8;
  27     }
  28     if (arm_feature(env, ARM_FEATURE_NEON)) {
  29         /* Aliases for Q regs.  */
  30         nregs += 16;
  31         if (reg < nregs) {
  32             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  33             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  34             return 16;
  35         }
  36     }
  37     switch (reg - nregs) {
  38     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  39     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  40     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  41     }
  42     return 0;
  43 }
  44
  45 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  46 {
  47     int nregs;
  48
  49     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  50     if (reg < nregs) {
  51         env->vfp.regs[reg] = ldfq_le_p(buf);
  52         return 8;
  53     }
  54     if (arm_feature(env, ARM_FEATURE_NEON)) {
  55         nregs += 16;
  56         if (reg < nregs) {
  57             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  58             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  59             return 16;
  60         }
  61     }
  62     switch (reg - nregs) {
  63     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  64     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  65     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  66     }
  67     return 0;
  68 }
  69
  70 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  71 {
  72     switch (reg) {
  73     case 0 ... 31:
  74         /* 128 bit FP register */
  75         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  76         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  77         return 16;
  78     case 32:
  79         /* FPSR */
  80         stl_p(buf, vfp_get_fpsr(env));
  81         return 4;
  82     case 33:
  83         /* FPCR */
  84         stl_p(buf, vfp_get_fpcr(env));
  85         return 4;
  86     default:
  87         return 0;
  88     }
  89 }
  90
  91 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  92 {
  93     switch (reg) {
  94     case 0 ... 31:
  95         /* 128 bit FP register */
  96         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
  97         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
  98         return 16;
  99     case 32:
 100         /* FPSR */
 101         vfp_set_fpsr(env, ldl_p(buf));
 102         return 4;
 103     case 33:
 104         /* FPCR */
 105         vfp_set_fpcr(env, ldl_p(buf));
 106         return 4;
 107     default:
 108         return 0;
 109     }
 110 }
 111
 112 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 113 {
 114     if (cpreg_field_is_64bit(ri)) {
 115         return CPREG_FIELD64(env, ri);
 116     } else {
 117         return CPREG_FIELD32(env, ri);
 118     }
 119 }
 120
 121 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 122                       uint64_t value)
 123 {
 124     if (cpreg_field_is_64bit(ri)) {
 125         CPREG_FIELD64(env, ri) = value;
 126     } else {
 127         CPREG_FIELD32(env, ri) = value;
 128     }
 129 }
 130
 131 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 132 {
 133     /* Raw read of a coprocessor register (as needed for migration, etc). */
 134     if (ri->type & ARM_CP_CONST) {
 135         return ri->resetvalue;
 136     } else if (ri->raw_readfn) {
 137         return ri->raw_readfn(env, ri);
 138     } else if (ri->readfn) {
 139         return ri->readfn(env, ri);
 140     } else {
 141         return raw_read(env, ri);
 142     }
 143 }
 144
 145 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 146                              uint64_t v)
 147 {
 148     /* Raw write of a coprocessor register (as needed for migration, etc).
 149      * Note that constant registers are treated as write-ignored; the
 150      * caller should check for success by whether a readback gives the
 151      * value written.
 152      */
 153     if (ri->type & ARM_CP_CONST) {
 154         return;
 155     } else if (ri->raw_writefn) {
 156         ri->raw_writefn(env, ri, v);
 157     } else if (ri->writefn) {
 158         ri->writefn(env, ri, v);
 159     } else {
 160         raw_write(env, ri, v);
 161     }
 162 }
 163
 164 bool write_cpustate_to_list(ARMCPU *cpu)
 165 {
 166     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 167     int i;
 168     bool ok = true;
 169
 170     for (i = 0; i < cpu->cpreg_array_len; i++) {
 171         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 172         const ARMCPRegInfo *ri;
 173
 174         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 175         if (!ri) {
 176             ok = false;
 177             continue;
 178         }
 179         if (ri->type & ARM_CP_NO_MIGRATE) {
 180             continue;
 181         }
 182         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 183     }
 184     return ok;
 185 }
 186
 187 bool write_list_to_cpustate(ARMCPU *cpu)
 188 {
 189     int i;
 190     bool ok = true;
 191
 192     for (i = 0; i < cpu->cpreg_array_len; i++) {
 193         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 194         uint64_t v = cpu->cpreg_values[i];
 195         const ARMCPRegInfo *ri;
 196
 197         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 198         if (!ri) {
 199             ok = false;
 200             continue;
 201         }
 202         if (ri->type & ARM_CP_NO_MIGRATE) {
 203             continue;
 204         }
 205         /* Write value and confirm it reads back as written
 206          * (to catch read-only registers and partially read-only
 207          * registers where the incoming migration value doesn't match)
 208          */
 209         write_raw_cp_reg(&cpu->env, ri, v);
 210         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 211             ok = false;
 212         }
 213     }
 214     return ok;
 215 }
 216
 217 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 218 {
 219     ARMCPU *cpu = opaque;
 220     uint64_t regidx;
 221     const ARMCPRegInfo *ri;
 222
 223     regidx = *(uint32_t *)key;
 224     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 225
 226     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 227         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 228         /* The value array need not be initialized at this point */
 229         cpu->cpreg_array_len++;
 230     }
 231 }
 232
 233 static void count_cpreg(gpointer key, gpointer opaque)
 234 {
 235     ARMCPU *cpu = opaque;
 236     uint64_t regidx;
 237     const ARMCPRegInfo *ri;
 238
 239     regidx = *(uint32_t *)key;
 240     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 241
 242     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 243         cpu->cpreg_array_len++;
 244     }
 245 }
 246
 247 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 248 {
 249     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 250     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 251
 252     if (aidx > bidx) {
 253         return 1;
 254     }
 255     if (aidx < bidx) {
 256         return -1;
 257     }
 258     return 0;
 259 }
 260
 261 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 262 {
 263     GList **plist = udata;
 264
 265     *plist = g_list_prepend(*plist, key);
 266 }
 267
 268 void init_cpreg_list(ARMCPU *cpu)
 269 {
 270     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 271      * Note that we require cpreg_tuples[] to be sorted by key ID.
 272      */
 273     GList *keys = NULL;
 274     int arraylen;
 275
 276     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 277
 278     keys = g_list_sort(keys, cpreg_key_compare);
 279
 280     cpu->cpreg_array_len = 0;
 281
 282     g_list_foreach(keys, count_cpreg, cpu);
 283
 284     arraylen = cpu->cpreg_array_len;
 285     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 286     cpu->cpreg_values = g_new(uint64_t, arraylen);
 287     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 288     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 289     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 290     cpu->cpreg_array_len = 0;
 291
 292     g_list_foreach(keys, add_cpreg_to_list, cpu);
 293
 294     assert(cpu->cpreg_array_len == arraylen);
 295
 296     g_list_free(keys);
 297 }
 298
 299 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 300 {
 301     env->cp15.c3 = value;
 302     tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
 303 }
 304
 305 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 306 {
 307     if (env->cp15.c13_fcse != value) {
 308         /* Unlike real hardware the qemu TLB uses virtual addresses,
 309          * not modified virtual addresses, so this causes a TLB flush.
 310          */
 311         tlb_flush(env, 1);
 312         env->cp15.c13_fcse = value;
 313     }
 314 }
 315
 316 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 317                              uint64_t value)
 318 {
 319     if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
 320         /* For VMSA (when not using the LPAE long descriptor page table
 321          * format) this register includes the ASID, so do a TLB flush.
 322          * For PMSA it is purely a process ID and no action is needed.
 323          */
 324         tlb_flush(env, 1);
 325     }
 326     env->cp15.c13_context = value;
 327 }
 328
 329 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 330                           uint64_t value)
 331 {
 332     /* Invalidate all (TLBIALL) */
 333     tlb_flush(env, 1);
 334 }
 335
 336 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 337                           uint64_t value)
 338 {
 339     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 340     tlb_flush_page(env, value & TARGET_PAGE_MASK);
 341 }
 342
 343 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 344                            uint64_t value)
 345 {
 346     /* Invalidate by ASID (TLBIASID) */
 347     tlb_flush(env, value == 0);
 348 }
 349
 350 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 351                            uint64_t value)
 352 {
 353     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 354     tlb_flush_page(env, value & TARGET_PAGE_MASK);
 355 }
 356
 357 static const ARMCPRegInfo cp_reginfo[] = {
 358     /* DBGDIDR: just RAZ. In particular this means the "debug architecture
 359      * version" bits will read as a reserved value, which should cause
 360      * Linux to not try to use the debug hardware.
 361      */
 362     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 363       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 364     /* MMU Domain access control / MPU write buffer control */
 365     { .name = "DACR", .cp = 15,
 366       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 367       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 368       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 369     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 370       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 371       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 372     { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
 373       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
 374       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 375     /* ??? This covers not just the impdef TLB lockdown registers but also
 376      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 377      */
 378     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 379       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 380     /* MMU TLB control. Note that the wildcarding means we cover not just
 381      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 382      */
 383     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 384       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 385       .type = ARM_CP_NO_MIGRATE },
 386     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 387       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 388       .type = ARM_CP_NO_MIGRATE },
 389     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 390       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 391       .type = ARM_CP_NO_MIGRATE },
 392     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 393       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 394       .type = ARM_CP_NO_MIGRATE },
 395     /* Cache maintenance ops; some of this space may be overridden later. */
 396     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 397       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 398       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 399     REGINFO_SENTINEL
 400 };
 401
 402 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 403     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 404      * over-broad.
 405      */
 406     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 407       .access = PL1_W, .type = ARM_CP_WFI },
 408     REGINFO_SENTINEL
 409 };
 410
 411 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 412     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 413      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 414      */
 415     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 416       .access = PL1_W, .type = ARM_CP_WFI },
 417     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 418      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 419      * OMAPCP will override this space.
 420      */
 421     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 422       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 423       .resetvalue = 0 },
 424     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 425       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 426       .resetvalue = 0 },
 427     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 428     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 429       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 430       .resetvalue = 0 },
 431     REGINFO_SENTINEL
 432 };
 433
 434 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 435                         uint64_t value)
 436 {
 437     if (env->cp15.c1_coproc != value) {
 438         env->cp15.c1_coproc = value;
 439         /* ??? Is this safe when called from within a TB?  */
 440         tb_flush(env);
 441     }
 442 }
 443
 444 static const ARMCPRegInfo v6_cp_reginfo[] = {
 445     /* prefetch by MVA in v6, NOP in v7 */
 446     { .name = "MVA_prefetch",
 447       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 448       .access = PL1_W, .type = ARM_CP_NOP },
 449     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 450       .access = PL0_W, .type = ARM_CP_NOP },
 451     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 452       .access = PL0_W, .type = ARM_CP_NOP },
 453     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 454       .access = PL0_W, .type = ARM_CP_NOP },
 455     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 456       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 457       .resetvalue = 0, },
 458     /* Watchpoint Fault Address Register : should actually only be present
 459      * for 1136, 1176, 11MPCore.
 460      */
 461     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 462       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 463     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 464       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 465       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 466       .resetvalue = 0, .writefn = cpacr_write },
 467     REGINFO_SENTINEL
 468 };
 469
 470 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 471 {
 472     /* Perfomance monitor registers user accessibility is controlled
 473      * by PMUSERENR.
 474      */
 475     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 476         return CP_ACCESS_TRAP;
 477     }
 478     return CP_ACCESS_OK;
 479 }
 480
 481 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 482                        uint64_t value)
 483 {
 484     /* only the DP, X, D and E bits are writable */
 485     env->cp15.c9_pmcr &= ~0x39;
 486     env->cp15.c9_pmcr |= (value & 0x39);
 487 }
 488
 489 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 490                             uint64_t value)
 491 {
 492     value &= (1 << 31);
 493     env->cp15.c9_pmcnten |= value;
 494 }
 495
 496 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 497                              uint64_t value)
 498 {
 499     value &= (1 << 31);
 500     env->cp15.c9_pmcnten &= ~value;
 501 }
 502
 503 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 504                          uint64_t value)
 505 {
 506     env->cp15.c9_pmovsr &= ~value;
 507 }
 508
 509 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 510                              uint64_t value)
 511 {
 512     env->cp15.c9_pmxevtyper = value & 0xff;
 513 }
 514
 515 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 516                             uint64_t value)
 517 {
 518     env->cp15.c9_pmuserenr = value & 1;
 519 }
 520
 521 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 522                              uint64_t value)
 523 {
 524     /* We have no event counters so only the C bit can be changed */
 525     value &= (1 << 31);
 526     env->cp15.c9_pminten |= value;
 527 }
 528
 529 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 530                              uint64_t value)
 531 {
 532     value &= (1 << 31);
 533     env->cp15.c9_pminten &= ~value;
 534 }
 535
 536 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 537                        uint64_t value)
 538 {
 539     /* Note that even though the AArch64 view of this register has bits
 540      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 541      * architectural requirements for bits which are RES0 only in some
 542      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 543      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 544      */
 545     env->cp15.c12_vbar = value & ~0x1Ful;
 546 }
 547
 548 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 549 {
 550     ARMCPU *cpu = arm_env_get_cpu(env);
 551     return cpu->ccsidr[env->cp15.c0_cssel];
 552 }
 553
 554 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 555                          uint64_t value)
 556 {
 557     env->cp15.c0_cssel = value & 0xf;
 558 }
 559
 560 static const ARMCPRegInfo v7_cp_reginfo[] = {
 561     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
 562      * debug components
 563      */
 564     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
 565       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 566     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
 567       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 568     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 569     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 570       .access = PL1_W, .type = ARM_CP_NOP },
 571     /* Performance monitors are implementation defined in v7,
 572      * but with an ARM recommended set of registers, which we
 573      * follow (although we don't actually implement any counters)
 574      *
 575      * Performance registers fall into three categories:
 576      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 577      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 578      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 579      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 580      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 581      */
 582     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 583       .access = PL0_RW, .resetvalue = 0,
 584       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 585       .writefn = pmcntenset_write,
 586       .accessfn = pmreg_access,
 587       .raw_writefn = raw_write },
 588     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 589       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 590       .accessfn = pmreg_access,
 591       .writefn = pmcntenclr_write,
 592       .type = ARM_CP_NO_MIGRATE },
 593     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 594       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 595       .accessfn = pmreg_access,
 596       .writefn = pmovsr_write,
 597       .raw_writefn = raw_write },
 598     /* Unimplemented so WI. */
 599     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 600       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 601     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 602      * We choose to RAZ/WI.
 603      */
 604     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 605       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 606       .accessfn = pmreg_access },
 607     /* Unimplemented, RAZ/WI. */
 608     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 609       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 610       .accessfn = pmreg_access },
 611     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 612       .access = PL0_RW,
 613       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 614       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 615       .raw_writefn = raw_write },
 616     /* Unimplemented, RAZ/WI. */
 617     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 618       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 619       .accessfn = pmreg_access },
 620     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 621       .access = PL0_R | PL1_RW,
 622       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 623       .resetvalue = 0,
 624       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 625     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 626       .access = PL1_RW,
 627       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 628       .resetvalue = 0,
 629       .writefn = pmintenset_write, .raw_writefn = raw_write },
 630     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 631       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 632       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 633       .resetvalue = 0, .writefn = pmintenclr_write, },
 634     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 635       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 636       .access = PL1_RW, .writefn = vbar_write,
 637       .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
 638       .resetvalue = 0 },
 639     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 640       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 641       .resetvalue = 0, },
 642     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 643       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 644       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 645     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 646       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 647       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 648       .writefn = csselr_write, .resetvalue = 0 },
 649     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 650      * just RAZ for all cores:
 651      */
 652     { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
 653       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 654     /* MAIR can just read-as-written because we don't implement caches
 655      * and so don't need to care about memory attributes.
 656      */
 657     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 658       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 659       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 660       .resetvalue = 0 },
 661     /* For non-long-descriptor page tables these are PRRR and NMRR;
 662      * regardless they still act as reads-as-written for QEMU.
 663      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 664      * definition.
 665      */
 666     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 667       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 668       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 669       .resetfn = arm_cp_reset_ignore },
 670     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 671       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 672       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 673       .resetfn = arm_cp_reset_ignore },
 674     REGINFO_SENTINEL
 675 };
 676
 677 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 678                         uint64_t value)
 679 {
 680     value &= 1;
 681     env->teecr = value;
 682 }
 683
 684 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 685 {
 686     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 687         return CP_ACCESS_TRAP;
 688     }
 689     return CP_ACCESS_OK;
 690 }
 691
 692 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 693     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 694       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 695       .resetvalue = 0,
 696       .writefn = teecr_write },
 697     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 698       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 699       .accessfn = teehbr_access, .resetvalue = 0 },
 700     REGINFO_SENTINEL
 701 };
 702
 703 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 704     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 705       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 706       .access = PL0_RW,
 707       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 708     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 709       .access = PL0_RW,
 710       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 711       .resetfn = arm_cp_reset_ignore },
 712     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 713       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 714       .access = PL0_R|PL1_W,
 715       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 716     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 717       .access = PL0_R|PL1_W,
 718       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 719       .resetfn = arm_cp_reset_ignore },
 720     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 721       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 722       .access = PL1_RW,
 723       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 724     REGINFO_SENTINEL
 725 };
 726
 727 #ifndef CONFIG_USER_ONLY
 728
 729 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 730 {
 731     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 732     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 733         return CP_ACCESS_TRAP;
 734     }
 735     return CP_ACCESS_OK;
 736 }
 737
 738 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 739 {
 740     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 741     if (arm_current_pl(env) == 0 &&
 742         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 743         return CP_ACCESS_TRAP;
 744     }
 745     return CP_ACCESS_OK;
 746 }
 747
 748 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 749 {
 750     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 751      * EL0[PV]TEN is zero.
 752      */
 753     if (arm_current_pl(env) == 0 &&
 754         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 755         return CP_ACCESS_TRAP;
 756     }
 757     return CP_ACCESS_OK;
 758 }
 759
 760 static CPAccessResult gt_pct_access(CPUARMState *env,
 761                                          const ARMCPRegInfo *ri)
 762 {
 763     return gt_counter_access(env, GTIMER_PHYS);
 764 }
 765
 766 static CPAccessResult gt_vct_access(CPUARMState *env,
 767                                          const ARMCPRegInfo *ri)
 768 {
 769     return gt_counter_access(env, GTIMER_VIRT);
 770 }
 771
 772 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 773 {
 774     return gt_timer_access(env, GTIMER_PHYS);
 775 }
 776
 777 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 778 {
 779     return gt_timer_access(env, GTIMER_VIRT);
 780 }
 781
 782 static uint64_t gt_get_countervalue(CPUARMState *env)
 783 {
 784     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
 785 }
 786
 787 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 788 {
 789     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
 790
 791     if (gt->ctl & 1) {
 792         /* Timer enabled: calculate and set current ISTATUS, irq, and
 793          * reset timer to when ISTATUS next has to change
 794          */
 795         uint64_t count = gt_get_countervalue(&cpu->env);
 796         /* Note that this must be unsigned 64 bit arithmetic: */
 797         int istatus = count >= gt->cval;
 798         uint64_t nexttick;
 799
 800         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
 801         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
 802                      (istatus && !(gt->ctl & 2)));
 803         if (istatus) {
 804             /* Next transition is when count rolls back over to zero */
 805             nexttick = UINT64_MAX;
 806         } else {
 807             /* Next transition is when we hit cval */
 808             nexttick = gt->cval;
 809         }
 810         /* Note that the desired next expiry time might be beyond the
 811          * signed-64-bit range of a QEMUTimer -- in this case we just
 812          * set the timer for as far in the future as possible. When the
 813          * timer expires we will reset the timer for any remaining period.
 814          */
 815         if (nexttick > INT64_MAX / GTIMER_SCALE) {
 816             nexttick = INT64_MAX / GTIMER_SCALE;
 817         }
 818         timer_mod(cpu->gt_timer[timeridx], nexttick);
 819     } else {
 820         /* Timer disabled: ISTATUS and timer output always clear */
 821         gt->ctl &= ~4;
 822         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
 823         timer_del(cpu->gt_timer[timeridx]);
 824     }
 825 }
 826
 827 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 828 {
 829     ARMCPU *cpu = arm_env_get_cpu(env);
 830     int timeridx = ri->opc1 & 1;
 831
 832     timer_del(cpu->gt_timer[timeridx]);
 833 }
 834
 835 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 836 {
 837     return gt_get_countervalue(env);
 838 }
 839
 840 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 841                           uint64_t value)
 842 {
 843     int timeridx = ri->opc1 & 1;
 844
 845     env->cp15.c14_timer[timeridx].cval = value;
 846     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
 847 }
 848
 849 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 850 {
 851     int timeridx = ri->crm & 1;
 852
 853     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
 854                       gt_get_countervalue(env));
 855 }
 856
 857 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 858                           uint64_t value)
 859 {
 860     int timeridx = ri->crm & 1;
 861
 862     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
 863         + sextract64(value, 0, 32);
 864     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
 865 }
 866
 867 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 868                          uint64_t value)
 869 {
 870     ARMCPU *cpu = arm_env_get_cpu(env);
 871     int timeridx = ri->crm & 1;
 872     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
 873
 874     env->cp15.c14_timer[timeridx].ctl = value & 3;
 875     if ((oldval ^ value) & 1) {
 876         /* Enable toggled */
 877         gt_recalc_timer(cpu, timeridx);
 878     } else if ((oldval & value) & 2) {
 879         /* IMASK toggled: don't need to recalculate,
 880          * just set the interrupt line based on ISTATUS
 881          */
 882         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
 883                      (oldval & 4) && (value & 2));
 884     }
 885 }
 886
 887 void arm_gt_ptimer_cb(void *opaque)
 888 {
 889     ARMCPU *cpu = opaque;
 890
 891     gt_recalc_timer(cpu, GTIMER_PHYS);
 892 }
 893
 894 void arm_gt_vtimer_cb(void *opaque)
 895 {
 896     ARMCPU *cpu = opaque;
 897
 898     gt_recalc_timer(cpu, GTIMER_VIRT);
 899 }
 900
 901 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
 902     /* Note that CNTFRQ is purely reads-as-written for the benefit
 903      * of software; writing it doesn't actually change the timer frequency.
 904      * Our reset value matches the fixed frequency we implement the timer at.
 905      */
 906     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
 907       .type = ARM_CP_NO_MIGRATE,
 908       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
 909       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
 910       .resetfn = arm_cp_reset_ignore,
 911     },
 912     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
 913       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
 914       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
 915       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
 916       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
 917     },
 918     /* overall control: mostly access permissions */
 919     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
 920       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
 921       .access = PL1_RW,
 922       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
 923       .resetvalue = 0,
 924     },
 925     /* per-timer control */
 926     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
 927       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
 928       .accessfn = gt_ptimer_access,
 929       .fieldoffset = offsetoflow32(CPUARMState,
 930                                    cp15.c14_timer[GTIMER_PHYS].ctl),
 931       .resetfn = arm_cp_reset_ignore,
 932       .writefn = gt_ctl_write, .raw_writefn = raw_write,
 933     },
 934     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
 935       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
 936       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
 937       .accessfn = gt_ptimer_access,
 938       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
 939       .resetvalue = 0,
 940       .writefn = gt_ctl_write, .raw_writefn = raw_write,
 941     },
 942     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
 943       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
 944       .accessfn = gt_vtimer_access,
 945       .fieldoffset = offsetoflow32(CPUARMState,
 946                                    cp15.c14_timer[GTIMER_VIRT].ctl),
 947       .resetfn = arm_cp_reset_ignore,
 948       .writefn = gt_ctl_write, .raw_writefn = raw_write,
 949     },
 950     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
 951       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
 952       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
 953       .accessfn = gt_vtimer_access,
 954       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
 955       .resetvalue = 0,
 956       .writefn = gt_ctl_write, .raw_writefn = raw_write,
 957     },
 958     /* TimerValue views: a 32 bit downcounting view of the underlying state */
 959     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
 960       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
 961       .accessfn = gt_ptimer_access,
 962       .readfn = gt_tval_read, .writefn = gt_tval_write,
 963     },
 964     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
 965       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
 966       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
 967       .readfn = gt_tval_read, .writefn = gt_tval_write,
 968     },
 969     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
 970       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
 971       .accessfn = gt_vtimer_access,
 972       .readfn = gt_tval_read, .writefn = gt_tval_write,
 973     },
 974     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
 975       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
 976       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
 977       .readfn = gt_tval_read, .writefn = gt_tval_write,
 978     },
 979     /* The counter itself */
 980     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
 981       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
 982       .accessfn = gt_pct_access,
 983       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
 984     },
 985     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
 986       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
 987       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
 988       .accessfn = gt_pct_access,
 989       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
 990     },
 991     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
 992       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
 993       .accessfn = gt_vct_access,
 994       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
 995     },
 996     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
 997       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
 998       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
 999       .accessfn = gt_vct_access,
1000       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1001     },
1002     /* Comparison value, indicating when the timer goes off */
1003     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1004       .access = PL1_RW | PL0_R,
1005       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1006       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1007       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1008       .writefn = gt_cval_write, .raw_writefn = raw_write,
1009     },
1010     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1011       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1012       .access = PL1_RW | PL0_R,
1013       .type = ARM_CP_IO,
1014       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1015       .resetvalue = 0, .accessfn = gt_vtimer_access,
1016       .writefn = gt_cval_write, .raw_writefn = raw_write,
1017     },
1018     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1019       .access = PL1_RW | PL0_R,
1020       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1021       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1022       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1023       .writefn = gt_cval_write, .raw_writefn = raw_write,
1024     },
1025     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1026       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1027       .access = PL1_RW | PL0_R,
1028       .type = ARM_CP_IO,
1029       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1030       .resetvalue = 0, .accessfn = gt_vtimer_access,
1031       .writefn = gt_cval_write, .raw_writefn = raw_write,
1032     },
1033     REGINFO_SENTINEL
1034 };
1035
1036 #else
1037 /* In user-mode none of the generic timer registers are accessible,
1038  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1039  * so instead just don't register any of them.
1040  */
1041 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1042     REGINFO_SENTINEL
1043 };
1044
1045 #endif
1046
1047 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1048 {
1049     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1050         env->cp15.c7_par = value;
1051     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1052         env->cp15.c7_par = value & 0xfffff6ff;
1053     } else {
1054         env->cp15.c7_par = value & 0xfffff1ff;
1055     }
1056 }
1057
1058 #ifndef CONFIG_USER_ONLY
1059 /* get_phys_addr() isn't present for user-mode-only targets */
1060
1061 /* Return true if extended addresses are enabled, ie this is an
1062  * LPAE implementation and we are using the long-descriptor translation
1063  * table format because the TTBCR EAE bit is set.
1064  */
1065 static inline bool extended_addresses_enabled(CPUARMState *env)
1066 {
1067     return arm_feature(env, ARM_FEATURE_LPAE)
1068         && (env->cp15.c2_control & (1U << 31));
1069 }
1070
1071 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1072 {
1073     if (ri->opc2 & 4) {
1074         /* Other states are only available with TrustZone; in
1075          * a non-TZ implementation these registers don't exist
1076          * at all, which is an Uncategorized trap. This underdecoding
1077          * is safe because the reginfo is NO_MIGRATE.
1078          */
1079         return CP_ACCESS_TRAP_UNCATEGORIZED;
1080     }
1081     return CP_ACCESS_OK;
1082 }
1083
1084 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1085 {
1086     hwaddr phys_addr;
1087     target_ulong page_size;
1088     int prot;
1089     int ret, is_user = ri->opc2 & 2;
1090     int access_type = ri->opc2 & 1;
1091
1092     ret = get_phys_addr(env, value, access_type, is_user,
1093                         &phys_addr, &prot, &page_size);
1094     if (extended_addresses_enabled(env)) {
1095         /* ret is a DFSR/IFSR value for the long descriptor
1096          * translation table format, but with WnR always clear.
1097          * Convert it to a 64-bit PAR.
1098          */
1099         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1100         if (ret == 0) {
1101             par64 |= phys_addr & ~0xfffULL;
1102             /* We don't set the ATTR or SH fields in the PAR. */
1103         } else {
1104             par64 |= 1; /* F */
1105             par64 |= (ret & 0x3f) << 1; /* FS */
1106             /* Note that S2WLK and FSTAGE are always zero, because we don't
1107              * implement virtualization and therefore there can't be a stage 2
1108              * fault.
1109              */
1110         }
1111         env->cp15.c7_par = par64;
1112         env->cp15.c7_par_hi = par64 >> 32;
1113     } else {
1114         /* ret is a DFSR/IFSR value for the short descriptor
1115          * translation table format (with WnR always clear).
1116          * Convert it to a 32-bit PAR.
1117          */
1118         if (ret == 0) {
1119             /* We do not set any attribute bits in the PAR */
1120             if (page_size == (1 << 24)
1121                 && arm_feature(env, ARM_FEATURE_V7)) {
1122                 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1123             } else {
1124                 env->cp15.c7_par = phys_addr & 0xfffff000;
1125             }
1126         } else {
1127             env->cp15.c7_par = ((ret & (1 << 10)) >> 5) |
1128                 ((ret & (1 << 12)) >> 6) |
1129                 ((ret & 0xf) << 1) | 1;
1130         }
1131         env->cp15.c7_par_hi = 0;
1132     }
1133 }
1134 #endif
1135
1136 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1137     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1138       .access = PL1_RW, .resetvalue = 0,
1139       .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1140       .writefn = par_write },
1141 #ifndef CONFIG_USER_ONLY
1142     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1143       .access = PL1_W, .accessfn = ats_access,
1144       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1145 #endif
1146     REGINFO_SENTINEL
1147 };
1148
1149 /* Return basic MPU access permission bits.  */
1150 static uint32_t simple_mpu_ap_bits(uint32_t val)
1151 {
1152     uint32_t ret;
1153     uint32_t mask;
1154     int i;
1155     ret = 0;
1156     mask = 3;
1157     for (i = 0; i < 16; i += 2) {
1158         ret |= (val >> i) & mask;
1159         mask <<= 2;
1160     }
1161     return ret;
1162 }
1163
1164 /* Pad basic MPU access permission bits to extended format.  */
1165 static uint32_t extended_mpu_ap_bits(uint32_t val)
1166 {
1167     uint32_t ret;
1168     uint32_t mask;
1169     int i;
1170     ret = 0;
1171     mask = 3;
1172     for (i = 0; i < 16; i += 2) {
1173         ret |= (val & mask) << i;
1174         mask <<= 2;
1175     }
1176     return ret;
1177 }
1178
1179 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1180                                  uint64_t value)
1181 {
1182     env->cp15.c5_data = extended_mpu_ap_bits(value);
1183 }
1184
1185 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1186 {
1187     return simple_mpu_ap_bits(env->cp15.c5_data);
1188 }
1189
1190 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1191                                  uint64_t value)
1192 {
1193     env->cp15.c5_insn = extended_mpu_ap_bits(value);
1194 }
1195
1196 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1197 {
1198     return simple_mpu_ap_bits(env->cp15.c5_insn);
1199 }
1200
1201 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1202     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1203       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1204       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1205       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1206     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1207       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1208       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1209       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1210     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1211       .access = PL1_RW,
1212       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1213     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1214       .access = PL1_RW,
1215       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1216     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1217       .access = PL1_RW,
1218       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1219     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1220       .access = PL1_RW,
1221       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1222     /* Protection region base and size registers */
1223     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1224       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1225       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1226     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1227       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1228       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1229     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1230       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1231       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1232     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1233       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1234       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1235     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1236       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1237       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1238     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1239       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1240       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1241     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1242       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1243       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1244     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1245       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1246       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1247     REGINFO_SENTINEL
1248 };
1249
1250 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1251                                  uint64_t value)
1252 {
1253     int maskshift = extract32(value, 0, 3);
1254
1255     if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1256         value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1257     } else {
1258         value &= 7;
1259     }
1260     /* Note that we always calculate c2_mask and c2_base_mask, but
1261      * they are only used for short-descriptor tables (ie if EAE is 0);
1262      * for long-descriptor tables the TTBCR fields are used differently
1263      * and the c2_mask and c2_base_mask values are meaningless.
1264      */
1265     env->cp15.c2_control = value;
1266     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1267     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1268 }
1269
1270 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1271                              uint64_t value)
1272 {
1273     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1274         /* With LPAE the TTBCR could result in a change of ASID
1275          * via the TTBCR.A1 bit, so do a TLB flush.
1276          */
1277         tlb_flush(env, 1);
1278     }
1279     vmsa_ttbcr_raw_write(env, ri, value);
1280 }
1281
1282 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1283 {
1284     env->cp15.c2_base_mask = 0xffffc000u;
1285     env->cp15.c2_control = 0;
1286     env->cp15.c2_mask = 0;
1287 }
1288
1289 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1290                                uint64_t value)
1291 {
1292     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1293     tlb_flush(env, 1);
1294     env->cp15.c2_control = value;
1295 }
1296
1297 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1298                             uint64_t value)
1299 {
1300     /* 64 bit accesses to the TTBRs can change the ASID and so we
1301      * must flush the TLB.
1302      */
1303     if (cpreg_field_is_64bit(ri)) {
1304         tlb_flush(env, 1);
1305     }
1306     raw_write(env, ri, value);
1307 }
1308
1309 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1310     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1311       .access = PL1_RW,
1312       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1313     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1314       .access = PL1_RW,
1315       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1316     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1317       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1318       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1319       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1320     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1321       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1322       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1323       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1324     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1325       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1326       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1327       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1328       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1329     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1330       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1331       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1332       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1333     { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1334       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1335       .resetvalue = 0, },
1336     REGINFO_SENTINEL
1337 };
1338
1339 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1340                                 uint64_t value)
1341 {
1342     env->cp15.c15_ticonfig = value & 0xe7;
1343     /* The OS_TYPE bit in this register changes the reported CPUID! */
1344     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1345         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1346 }
1347
1348 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1349                                 uint64_t value)
1350 {
1351     env->cp15.c15_threadid = value & 0xffff;
1352 }
1353
1354 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1355                            uint64_t value)
1356 {
1357     /* Wait-for-interrupt (deprecated) */
1358     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1359 }
1360
1361 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1362                                   uint64_t value)
1363 {
1364     /* On OMAP there are registers indicating the max/min index of dcache lines
1365      * containing a dirty line; cache flush operations have to reset these.
1366      */
1367     env->cp15.c15_i_max = 0x000;
1368     env->cp15.c15_i_min = 0xff0;
1369 }
1370
1371 static const ARMCPRegInfo omap_cp_reginfo[] = {
1372     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1373       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1374       .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1375     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1376       .access = PL1_RW, .type = ARM_CP_NOP },
1377     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1378       .access = PL1_RW,
1379       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1380       .writefn = omap_ticonfig_write },
1381     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1382       .access = PL1_RW,
1383       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1384     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1385       .access = PL1_RW, .resetvalue = 0xff0,
1386       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1387     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1388       .access = PL1_RW,
1389       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1390       .writefn = omap_threadid_write },
1391     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1392       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1393       .type = ARM_CP_NO_MIGRATE,
1394       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1395     /* TODO: Peripheral port remap register:
1396      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1397      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1398      * when MMU is off.
1399      */
1400     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1401       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1402       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1403       .writefn = omap_cachemaint_write },
1404     { .name = "C9", .cp = 15, .crn = 9,
1405       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1406       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1407     REGINFO_SENTINEL
1408 };
1409
1410 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1411                               uint64_t value)
1412 {
1413     value &= 0x3fff;
1414     if (env->cp15.c15_cpar != value) {
1415         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1416         tb_flush(env);
1417         env->cp15.c15_cpar = value;
1418     }
1419 }
1420
1421 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1422     { .name = "XSCALE_CPAR",
1423       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1424       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1425       .writefn = xscale_cpar_write, },
1426     { .name = "XSCALE_AUXCR",
1427       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1428       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1429       .resetvalue = 0, },
1430     REGINFO_SENTINEL
1431 };
1432
1433 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1434     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1435      * implementation of this implementation-defined space.
1436      * Ideally this should eventually disappear in favour of actually
1437      * implementing the correct behaviour for all cores.
1438      */
1439     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1440       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1441       .access = PL1_RW,
1442       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1443       .resetvalue = 0 },
1444     REGINFO_SENTINEL
1445 };
1446
1447 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1448     /* Cache status: RAZ because we have no cache so it's always clean */
1449     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1450       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1451       .resetvalue = 0 },
1452     REGINFO_SENTINEL
1453 };
1454
1455 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1456     /* We never have a a block transfer operation in progress */
1457     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1458       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1459       .resetvalue = 0 },
1460     /* The cache ops themselves: these all NOP for QEMU */
1461     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1462       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1463     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1464       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1465     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1466       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1467     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1468       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1469     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1470       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1471     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1472       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1473     REGINFO_SENTINEL
1474 };
1475
1476 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1477     /* The cache test-and-clean instructions always return (1 << 30)
1478      * to indicate that there are no dirty cache lines.
1479      */
1480     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1481       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1482       .resetvalue = (1 << 30) },
1483     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1484       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1485       .resetvalue = (1 << 30) },
1486     REGINFO_SENTINEL
1487 };
1488
1489 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1490     /* Ignore ReadBuffer accesses */
1491     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1492       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1493       .access = PL1_RW, .resetvalue = 0,
1494       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1495     REGINFO_SENTINEL
1496 };
1497
1498 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1499 {
1500     CPUState *cs = CPU(arm_env_get_cpu(env));
1501     uint32_t mpidr = cs->cpu_index;
1502     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1503      * in later ARM ARM versions), or any of the higher affinity level fields,
1504      * so these bits always RAZ.
1505      */
1506     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1507         mpidr |= (1U << 31);
1508         /* Cores which are uniprocessor (non-coherent)
1509          * but still implement the MP extensions set
1510          * bit 30. (For instance, A9UP.) However we do
1511          * not currently model any of those cores.
1512          */
1513     }
1514     return mpidr;
1515 }
1516
1517 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1518     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1519       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1520       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1521     REGINFO_SENTINEL
1522 };
1523
1524 static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri)
1525 {
1526     return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1527 }
1528
1529 static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri,
1530                         uint64_t value)
1531 {
1532     env->cp15.c7_par_hi = value >> 32;
1533     env->cp15.c7_par = value;
1534 }
1535
1536 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1537 {
1538     env->cp15.c7_par_hi = 0;
1539     env->cp15.c7_par = 0;
1540 }
1541
1542 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1543     /* NOP AMAIR0/1: the override is because these clash with the rather
1544      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1545      */
1546     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1547       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1548       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1549       .resetvalue = 0 },
1550     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1551     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1552       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1553       .resetvalue = 0 },
1554     /* 64 bit access versions of the (dummy) debug registers */
1555     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1556       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1557     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1558       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1559     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1560       .access = PL1_RW, .type = ARM_CP_64BIT,
1561       .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1562     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1563       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1564       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1565       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1566     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1567       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1568       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1569       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1570     REGINFO_SENTINEL
1571 };
1572
1573 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1574 {
1575     return vfp_get_fpcr(env);
1576 }
1577
1578 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1579                             uint64_t value)
1580 {
1581     vfp_set_fpcr(env, value);
1582 }
1583
1584 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1585 {
1586     return vfp_get_fpsr(env);
1587 }
1588
1589 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1590                             uint64_t value)
1591 {
1592     vfp_set_fpsr(env, value);
1593 }
1594
1595 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1596                                           const ARMCPRegInfo *ri)
1597 {
1598     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1599      * SCTLR_EL1.UCI is set.
1600      */
1601     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1602         return CP_ACCESS_TRAP;
1603     }
1604     return CP_ACCESS_OK;
1605 }
1606
1607 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1608                                uint64_t value)
1609 {
1610     /* Invalidate by VA (AArch64 version) */
1611     uint64_t pageaddr = value << 12;
1612     tlb_flush_page(env, pageaddr);
1613 }
1614
1615 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1616                                 uint64_t value)
1617 {
1618     /* Invalidate by VA, all ASIDs (AArch64 version) */
1619     uint64_t pageaddr = value << 12;
1620     tlb_flush_page(env, pageaddr);
1621 }
1622
1623 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1624                                  uint64_t value)
1625 {
1626     /* Invalidate by ASID (AArch64 version) */
1627     int asid = extract64(value, 48, 16);
1628     tlb_flush(env, asid == 0);
1629 }
1630
1631 static const ARMCPRegInfo v8_cp_reginfo[] = {
1632     /* Minimal set of EL0-visible registers. This will need to be expanded
1633      * significantly for system emulation of AArch64 CPUs.
1634      */
1635     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1636       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1637       .access = PL0_RW, .type = ARM_CP_NZCV },
1638     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1639       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1640       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1641     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1642       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1643       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1644     /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1645      * For system mode the DZP bit here will need to be computed, not constant.
1646      */
1647     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1648       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1649       .access = PL0_R, .type = ARM_CP_CONST,
1650       .resetvalue = 0x10 },
1651     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1652       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1653       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1654     /* Cache ops: all NOPs since we don't emulate caches */
1655     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1656       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1657       .access = PL1_W, .type = ARM_CP_NOP },
1658     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1659       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1660       .access = PL1_W, .type = ARM_CP_NOP },
1661     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1662       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1663       .access = PL0_W, .type = ARM_CP_NOP,
1664       .accessfn = aa64_cacheop_access },
1665     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1666       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1667       .access = PL1_W, .type = ARM_CP_NOP },
1668     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1669       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1670       .access = PL1_W, .type = ARM_CP_NOP },
1671     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1672       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1673       .access = PL0_W, .type = ARM_CP_NOP,
1674       .accessfn = aa64_cacheop_access },
1675     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1676       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1677       .access = PL1_W, .type = ARM_CP_NOP },
1678     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1679       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1680       .access = PL0_W, .type = ARM_CP_NOP,
1681       .accessfn = aa64_cacheop_access },
1682     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1683       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1684       .access = PL0_W, .type = ARM_CP_NOP,
1685       .accessfn = aa64_cacheop_access },
1686     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1687       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1688       .access = PL1_W, .type = ARM_CP_NOP },
1689     /* TLBI operations */
1690     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1691       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1692       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1693       .writefn = tlbiall_write },
1694     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1695       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1696       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1697       .writefn = tlbi_aa64_va_write },
1698     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1699       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1700       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1701       .writefn = tlbi_aa64_asid_write },
1702     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1703       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1704       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1705       .writefn = tlbi_aa64_vaa_write },
1706     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1707       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1708       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1709       .writefn = tlbi_aa64_va_write },
1710     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1711       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1712       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1713       .writefn = tlbi_aa64_vaa_write },
1714     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1715       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1716       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1717       .writefn = tlbiall_write },
1718     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1719       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1720       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1721       .writefn = tlbi_aa64_va_write },
1722     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1723       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1724       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1725       .writefn = tlbi_aa64_asid_write },
1726     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1727       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1728       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1729       .writefn = tlbi_aa64_vaa_write },
1730     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1731       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1732       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1733       .writefn = tlbi_aa64_va_write },
1734     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1735       .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1736       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1737       .writefn = tlbi_aa64_vaa_write },
1738     /* Dummy implementation of monitor debug system control register:
1739      * we don't support debug.
1740      */
1741     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
1742       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
1743       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1744     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1745     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
1746       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1747       .access = PL1_W, .type = ARM_CP_NOP },
1748     REGINFO_SENTINEL
1749 };
1750
1751 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1752                         uint64_t value)
1753 {
1754     env->cp15.c1_sys = value;
1755     /* ??? Lots of these bits are not implemented.  */
1756     /* This may enable/disable the MMU, so do a TLB flush.  */
1757     tlb_flush(env, 1);
1758 }
1759
1760 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1761 {
1762     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1763      * but the AArch32 CTR has its own reginfo struct)
1764      */
1765     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
1766         return CP_ACCESS_TRAP;
1767     }
1768     return CP_ACCESS_OK;
1769 }
1770
1771 static void define_aarch64_debug_regs(ARMCPU *cpu)
1772 {
1773     /* Define breakpoint and watchpoint registers. These do nothing
1774      * but read as written, for now.
1775      */
1776     int i;
1777
1778     for (i = 0; i < 16; i++) {
1779         ARMCPRegInfo dbgregs[] = {
1780             { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
1781               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
1782               .access = PL1_RW,
1783               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
1784             { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
1785               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
1786               .access = PL1_RW,
1787               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
1788             { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
1789               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
1790               .access = PL1_RW,
1791               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
1792             { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
1793               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
1794               .access = PL1_RW,
1795               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
1796                REGINFO_SENTINEL
1797         };
1798         define_arm_cp_regs(cpu, dbgregs);
1799     }
1800 }
1801
1802 void register_cp_regs_for_features(ARMCPU *cpu)
1803 {
1804     /* Register all the coprocessor registers based on feature bits */
1805     CPUARMState *env = &cpu->env;
1806     if (arm_feature(env, ARM_FEATURE_M)) {
1807         /* M profile has no coprocessor registers */
1808         return;
1809     }
1810
1811     define_arm_cp_regs(cpu, cp_reginfo);
1812     if (arm_feature(env, ARM_FEATURE_V6)) {
1813         /* The ID registers all have impdef reset values */
1814         ARMCPRegInfo v6_idregs[] = {
1815             { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1816               .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1817               .resetvalue = cpu->id_pfr0 },
1818             { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1819               .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1820               .resetvalue = cpu->id_pfr1 },
1821             { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1822               .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1823               .resetvalue = cpu->id_dfr0 },
1824             { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1825               .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1826               .resetvalue = cpu->id_afr0 },
1827             { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1828               .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1829               .resetvalue = cpu->id_mmfr0 },
1830             { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1831               .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1832               .resetvalue = cpu->id_mmfr1 },
1833             { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1834               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1835               .resetvalue = cpu->id_mmfr2 },
1836             { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1837               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1838               .resetvalue = cpu->id_mmfr3 },
1839             { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1840               .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1841               .resetvalue = cpu->id_isar0 },
1842             { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1843               .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1844               .resetvalue = cpu->id_isar1 },
1845             { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1846               .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1847               .resetvalue = cpu->id_isar2 },
1848             { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1849               .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1850               .resetvalue = cpu->id_isar3 },
1851             { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1852               .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1853               .resetvalue = cpu->id_isar4 },
1854             { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1855               .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1856               .resetvalue = cpu->id_isar5 },
1857             /* 6..7 are as yet unallocated and must RAZ */
1858             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1859               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1860               .resetvalue = 0 },
1861             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1862               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1863               .resetvalue = 0 },
1864             REGINFO_SENTINEL
1865         };
1866         define_arm_cp_regs(cpu, v6_idregs);
1867         define_arm_cp_regs(cpu, v6_cp_reginfo);
1868     } else {
1869         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1870     }
1871     if (arm_feature(env, ARM_FEATURE_V6K)) {
1872         define_arm_cp_regs(cpu, v6k_cp_reginfo);
1873     }
1874     if (arm_feature(env, ARM_FEATURE_V7)) {
1875         /* v7 performance monitor control register: same implementor
1876          * field as main ID register, and we implement no event counters.
1877          */
1878         ARMCPRegInfo pmcr = {
1879             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1880             .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1881             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1882             .accessfn = pmreg_access, .writefn = pmcr_write,
1883             .raw_writefn = raw_write,
1884         };
1885         ARMCPRegInfo clidr = {
1886             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
1887             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1888             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1889         };
1890         define_one_arm_cp_reg(cpu, &pmcr);
1891         define_one_arm_cp_reg(cpu, &clidr);
1892         define_arm_cp_regs(cpu, v7_cp_reginfo);
1893     } else {
1894         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1895     }
1896     if (arm_feature(env, ARM_FEATURE_V8)) {
1897         /* AArch64 ID registers, which all have impdef reset values */
1898         ARMCPRegInfo v8_idregs[] = {
1899             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
1900               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
1901               .access = PL1_R, .type = ARM_CP_CONST,
1902               .resetvalue = cpu->id_aa64pfr0 },
1903             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
1904               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
1905               .access = PL1_R, .type = ARM_CP_CONST,
1906               .resetvalue = cpu->id_aa64pfr1},
1907             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
1908               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
1909               .access = PL1_R, .type = ARM_CP_CONST,
1910               .resetvalue = cpu->id_aa64dfr0 },
1911             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
1912               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
1913               .access = PL1_R, .type = ARM_CP_CONST,
1914               .resetvalue = cpu->id_aa64dfr1 },
1915             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
1916               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
1917               .access = PL1_R, .type = ARM_CP_CONST,
1918               .resetvalue = cpu->id_aa64afr0 },
1919             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
1920               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
1921               .access = PL1_R, .type = ARM_CP_CONST,
1922               .resetvalue = cpu->id_aa64afr1 },
1923             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
1924               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
1925               .access = PL1_R, .type = ARM_CP_CONST,
1926               .resetvalue = cpu->id_aa64isar0 },
1927             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
1928               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
1929               .access = PL1_R, .type = ARM_CP_CONST,
1930               .resetvalue = cpu->id_aa64isar1 },
1931             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
1932               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
1933               .access = PL1_R, .type = ARM_CP_CONST,
1934               .resetvalue = cpu->id_aa64mmfr0 },
1935             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
1936               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
1937               .access = PL1_R, .type = ARM_CP_CONST,
1938               .resetvalue = cpu->id_aa64mmfr1 },
1939             REGINFO_SENTINEL
1940         };
1941         define_arm_cp_regs(cpu, v8_idregs);
1942         define_arm_cp_regs(cpu, v8_cp_reginfo);
1943         define_aarch64_debug_regs(cpu);
1944     }
1945     if (arm_feature(env, ARM_FEATURE_MPU)) {
1946         /* These are the MPU registers prior to PMSAv6. Any new
1947          * PMSA core later than the ARM946 will require that we
1948          * implement the PMSAv6 or PMSAv7 registers, which are
1949          * completely different.
1950          */
1951         assert(!arm_feature(env, ARM_FEATURE_V6));
1952         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1953     } else {
1954         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1955     }
1956     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1957         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1958     }
1959     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1960         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1961     }
1962     if (arm_feature(env, ARM_FEATURE_VAPA)) {
1963         define_arm_cp_regs(cpu, vapa_cp_reginfo);
1964     }
1965     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1966         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1967     }
1968     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1969         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1970     }
1971     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1972         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1973     }
1974     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1975         define_arm_cp_regs(cpu, omap_cp_reginfo);
1976     }
1977     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1978         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1979     }
1980     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1981         define_arm_cp_regs(cpu, xscale_cp_reginfo);
1982     }
1983     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1984         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1985     }
1986     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1987         define_arm_cp_regs(cpu, lpae_cp_reginfo);
1988     }
1989     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1990      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1991      * be read-only (ie write causes UNDEF exception).
1992      */
1993     {
1994         ARMCPRegInfo id_cp_reginfo[] = {
1995             /* Note that the MIDR isn't a simple constant register because
1996              * of the TI925 behaviour where writes to another register can
1997              * cause the MIDR value to change.
1998              *
1999              * Unimplemented registers in the c15 0 0 0 space default to
2000              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2001              * and friends override accordingly.
2002              */
2003             { .name = "MIDR",
2004               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2005               .access = PL1_R, .resetvalue = cpu->midr,
2006               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2007               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2008               .type = ARM_CP_OVERRIDE },
2009             { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
2010               .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
2011               .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
2012             { .name = "CTR",
2013               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2014               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2015             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2016               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2017               .access = PL0_R, .accessfn = ctr_el0_access,
2018               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2019             { .name = "TCMTR",
2020               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2021               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2022             { .name = "TLBTR",
2023               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2024               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2025             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2026             { .name = "DUMMY",
2027               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2028               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2029             { .name = "DUMMY",
2030               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2031               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2032             { .name = "DUMMY",
2033               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2034               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2035             { .name = "DUMMY",
2036               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2037               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2038             { .name = "DUMMY",
2039               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2040               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2041             REGINFO_SENTINEL
2042         };
2043         ARMCPRegInfo crn0_wi_reginfo = {
2044             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2045             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2046             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2047         };
2048         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2049             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2050             ARMCPRegInfo *r;
2051             /* Register the blanket "writes ignored" value first to cover the
2052              * whole space. Then update the specific ID registers to allow write
2053              * access, so that they ignore writes rather than causing them to
2054              * UNDEF.
2055              */
2056             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2057             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2058                 r->access = PL1_RW;
2059             }
2060         }
2061         define_arm_cp_regs(cpu, id_cp_reginfo);
2062     }
2063
2064     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2065         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2066     }
2067
2068     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2069         ARMCPRegInfo auxcr = {
2070             .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
2071             .access = PL1_RW, .type = ARM_CP_CONST,
2072             .resetvalue = cpu->reset_auxcr
2073         };
2074         define_one_arm_cp_reg(cpu, &auxcr);
2075     }
2076
2077     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2078         ARMCPRegInfo cbar = {
2079             .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2080             .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2081             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
2082         };
2083         define_one_arm_cp_reg(cpu, &cbar);
2084     }
2085
2086     /* Generic registers whose values depend on the implementation */
2087     {
2088         ARMCPRegInfo sctlr = {
2089             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2090             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2091             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2092             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2093             .raw_writefn = raw_write,
2094         };
2095         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2096             /* Normally we would always end the TB on an SCTLR write, but Linux
2097              * arch/arm/mach-pxa/sleep.S expects two instructions following
2098              * an MMU enable to execute from cache.  Imitate this behaviour.
2099              */
2100             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2101         }
2102         define_one_arm_cp_reg(cpu, &sctlr);
2103     }
2104 }
2105
2106 ARMCPU *cpu_arm_init(const char *cpu_model)
2107 {
2108     ARMCPU *cpu;
2109     ObjectClass *oc;
2110
2111     oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
2112     if (!oc) {
2113         return NULL;
2114     }
2115     cpu = ARM_CPU(object_new(object_class_get_name(oc)));
2116
2117     /* TODO this should be set centrally, once possible */
2118     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
2119
2120     return cpu;
2121 }
2122
2123 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2124 {
2125     CPUState *cs = CPU(cpu);
2126     CPUARMState *env = &cpu->env;
2127
2128     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2129         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2130                                  aarch64_fpu_gdb_set_reg,
2131                                  34, "aarch64-fpu.xml", 0);
2132     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2133         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2134                                  51, "arm-neon.xml", 0);
2135     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2136         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2137                                  35, "arm-vfp3.xml", 0);
2138     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2139         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2140                                  19, "arm-vfp.xml", 0);
2141     }
2142 }
2143
2144 /* Sort alphabetically by type name, except for "any". */
2145 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2146 {
2147     ObjectClass *class_a = (ObjectClass *)a;
2148     ObjectClass *class_b = (ObjectClass *)b;
2149     const char *name_a, *name_b;
2150
2151     name_a = object_class_get_name(class_a);
2152     name_b = object_class_get_name(class_b);
2153     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2154         return 1;
2155     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2156         return -1;
2157     } else {
2158         return strcmp(name_a, name_b);
2159     }
2160 }
2161
2162 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2163 {
2164     ObjectClass *oc = data;
2165     CPUListState *s = user_data;
2166     const char *typename;
2167     char *name;
2168
2169     typename = object_class_get_name(oc);
2170     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2171     (*s->cpu_fprintf)(s->file, "  %s\n",
2172                       name);
2173     g_free(name);
2174 }
2175
2176 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2177 {
2178     CPUListState s = {
2179         .file = f,
2180         .cpu_fprintf = cpu_fprintf,
2181     };
2182     GSList *list;
2183
2184     list = object_class_get_list(TYPE_ARM_CPU, false);
2185     list = g_slist_sort(list, arm_cpu_list_compare);
2186     (*cpu_fprintf)(f, "Available CPUs:\n");
2187     g_slist_foreach(list, arm_cpu_list_entry, &s);
2188     g_slist_free(list);
2189 #ifdef CONFIG_KVM
2190     /* The 'host' CPU type is dynamically registered only if KVM is
2191      * enabled, so we have to special-case it here:
2192      */
2193     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2194 #endif
2195 }
2196
2197 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2198 {
2199     ObjectClass *oc = data;
2200     CpuDefinitionInfoList **cpu_list = user_data;
2201     CpuDefinitionInfoList *entry;
2202     CpuDefinitionInfo *info;
2203     const char *typename;
2204
2205     typename = object_class_get_name(oc);
2206     info = g_malloc0(sizeof(*info));
2207     info->name = g_strndup(typename,
2208                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2209
2210     entry = g_malloc0(sizeof(*entry));
2211     entry->value = info;
2212     entry->next = *cpu_list;
2213     *cpu_list = entry;
2214 }
2215
2216 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2217 {
2218     CpuDefinitionInfoList *cpu_list = NULL;
2219     GSList *list;
2220
2221     list = object_class_get_list(TYPE_ARM_CPU, false);
2222     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2223     g_slist_free(list);
2224
2225     return cpu_list;
2226 }
2227
2228 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2229                                    void *opaque, int state,
2230                                    int crm, int opc1, int opc2)
2231 {
2232     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2233      * add a single reginfo struct to the hash table.
2234      */
2235     uint32_t *key = g_new(uint32_t, 1);
2236     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2237     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2238     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2239         /* The AArch32 view of a shared register sees the lower 32 bits
2240          * of a 64 bit backing field. It is not migratable as the AArch64
2241          * view handles that. AArch64 also handles reset.
2242          * We assume it is a cp15 register.
2243          */
2244         r2->cp = 15;
2245         r2->type |= ARM_CP_NO_MIGRATE;
2246         r2->resetfn = arm_cp_reset_ignore;
2247 #ifdef HOST_WORDS_BIGENDIAN
2248         if (r2->fieldoffset) {
2249             r2->fieldoffset += sizeof(uint32_t);
2250         }
2251 #endif
2252     }
2253     if (state == ARM_CP_STATE_AA64) {
2254         /* To allow abbreviation of ARMCPRegInfo
2255          * definitions, we treat cp == 0 as equivalent to
2256          * the value for "standard guest-visible sysreg".
2257          */
2258         if (r->cp == 0) {
2259             r2->cp = CP_REG_ARM64_SYSREG_CP;
2260         }
2261         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2262                                   r2->opc0, opc1, opc2);
2263     } else {
2264         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2265     }
2266     if (opaque) {
2267         r2->opaque = opaque;
2268     }
2269     /* reginfo passed to helpers is correct for the actual access,
2270      * and is never ARM_CP_STATE_BOTH:
2271      */
2272     r2->state = state;
2273     /* Make sure reginfo passed to helpers for wildcarded regs
2274      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2275      */
2276     r2->crm = crm;
2277     r2->opc1 = opc1;
2278     r2->opc2 = opc2;
2279     /* By convention, for wildcarded registers only the first
2280      * entry is used for migration; the others are marked as
2281      * NO_MIGRATE so we don't try to transfer the register
2282      * multiple times. Special registers (ie NOP/WFI) are
2283      * never migratable.
2284      */
2285     if ((r->type & ARM_CP_SPECIAL) ||
2286         ((r->crm == CP_ANY) && crm != 0) ||
2287         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2288         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2289         r2->type |= ARM_CP_NO_MIGRATE;
2290     }
2291
2292     /* Overriding of an existing definition must be explicitly
2293      * requested.
2294      */
2295     if (!(r->type & ARM_CP_OVERRIDE)) {
2296         ARMCPRegInfo *oldreg;
2297         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2298         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2299             fprintf(stderr, "Register redefined: cp=%d %d bit "
2300                     "crn=%d crm=%d opc1=%d opc2=%d, "
2301                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2302                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2303                     oldreg->name, r2->name);
2304             g_assert_not_reached();
2305         }
2306     }
2307     g_hash_table_insert(cpu->cp_regs, key, r2);
2308 }
2309
2310
2311 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2312                                        const ARMCPRegInfo *r, void *opaque)
2313 {
2314     /* Define implementations of coprocessor registers.
2315      * We store these in a hashtable because typically
2316      * there are less than 150 registers in a space which
2317      * is 16*16*16*8*8 = 262144 in size.
2318      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2319      * If a register is defined twice then the second definition is
2320      * used, so this can be used to define some generic registers and
2321      * then override them with implementation specific variations.
2322      * At least one of the original and the second definition should
2323      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2324      * against accidental use.
2325      *
2326      * The state field defines whether the register is to be
2327      * visible in the AArch32 or AArch64 execution state. If the
2328      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2329      * reginfo structure for the AArch32 view, which sees the lower
2330      * 32 bits of the 64 bit register.
2331      *
2332      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2333      * be wildcarded. AArch64 registers are always considered to be 64
2334      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2335      * the register, if any.
2336      */
2337     int crm, opc1, opc2, state;
2338     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2339     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2340     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2341     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2342     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2343     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2344     /* 64 bit registers have only CRm and Opc1 fields */
2345     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2346     /* op0 only exists in the AArch64 encodings */
2347     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2348     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2349     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2350     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2351      * encodes a minimum access level for the register. We roll this
2352      * runtime check into our general permission check code, so check
2353      * here that the reginfo's specified permissions are strict enough
2354      * to encompass the generic architectural permission check.
2355      */
2356     if (r->state != ARM_CP_STATE_AA32) {
2357         int mask = 0;
2358         switch (r->opc1) {
2359         case 0: case 1: case 2:
2360             /* min_EL EL1 */
2361             mask = PL1_RW;
2362             break;
2363         case 3:
2364             /* min_EL EL0 */
2365             mask = PL0_RW;
2366             break;
2367         case 4:
2368             /* min_EL EL2 */
2369             mask = PL2_RW;
2370             break;
2371         case 5:
2372             /* unallocated encoding, so not possible */
2373             assert(false);
2374             break;
2375         case 6:
2376             /* min_EL EL3 */
2377             mask = PL3_RW;
2378             break;
2379         case 7:
2380             /* min_EL EL1, secure mode only (we don't check the latter) */
2381             mask = PL1_RW;
2382             break;
2383         default:
2384             /* broken reginfo with out-of-range opc1 */
2385             assert(false);
2386             break;
2387         }
2388         /* assert our permissions are not too lax (stricter is fine) */
2389         assert((r->access & ~mask) == 0);
2390     }
2391
2392     /* Check that the register definition has enough info to handle
2393      * reads and writes if they are permitted.
2394      */
2395     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2396         if (r->access & PL3_R) {
2397             assert(r->fieldoffset || r->readfn);
2398         }
2399         if (r->access & PL3_W) {
2400             assert(r->fieldoffset || r->writefn);
2401         }
2402     }
2403     /* Bad type field probably means missing sentinel at end of reg list */
2404     assert(cptype_valid(r->type));
2405     for (crm = crmmin; crm <= crmmax; crm++) {
2406         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2407             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2408                 for (state = ARM_CP_STATE_AA32;
2409                      state <= ARM_CP_STATE_AA64; state++) {
2410                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2411                         continue;
2412                     }
2413                     add_cpreg_to_hashtable(cpu, r, opaque, state,
2414                                            crm, opc1, opc2);
2415                 }
2416             }
2417         }
2418     }
2419 }
2420
2421 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2422                                     const ARMCPRegInfo *regs, void *opaque)
2423 {
2424     /* Define a whole list of registers */
2425     const ARMCPRegInfo *r;
2426     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2427         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2428     }
2429 }
2430
2431 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2432 {
2433     return g_hash_table_lookup(cpregs, &encoded_cp);
2434 }
2435
2436 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2437                          uint64_t value)
2438 {
2439     /* Helper coprocessor write function for write-ignore registers */
2440 }
2441
2442 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2443 {
2444     /* Helper coprocessor write function for read-as-zero registers */
2445     return 0;
2446 }
2447
2448 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2449 {
2450     /* Helper coprocessor reset function for do-nothing-on-reset registers */
2451 }
2452
2453 static int bad_mode_switch(CPUARMState *env, int mode)
2454 {
2455     /* Return true if it is not valid for us to switch to
2456      * this CPU mode (ie all the UNPREDICTABLE cases in
2457      * the ARM ARM CPSRWriteByInstr pseudocode).
2458      */
2459     switch (mode) {
2460     case ARM_CPU_MODE_USR:
2461     case ARM_CPU_MODE_SYS:
2462     case ARM_CPU_MODE_SVC:
2463     case ARM_CPU_MODE_ABT:
2464     case ARM_CPU_MODE_UND:
2465     case ARM_CPU_MODE_IRQ:
2466     case ARM_CPU_MODE_FIQ:
2467         return 0;
2468     default:
2469         return 1;
2470     }
2471 }
2472
2473 uint32_t cpsr_read(CPUARMState *env)
2474 {
2475     int ZF;
2476     ZF = (env->ZF == 0);
2477     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2478         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2479         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2480         | ((env->condexec_bits & 0xfc) << 8)
2481         | (env->GE << 16) | env->daif;
2482 }
2483
2484 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2485 {
2486     if (mask & CPSR_NZCV) {
2487         env->ZF = (~val) & CPSR_Z;
2488         env->NF = val;
2489         env->CF = (val >> 29) & 1;
2490         env->VF = (val << 3) & 0x80000000;
2491     }
2492     if (mask & CPSR_Q)
2493         env->QF = ((val & CPSR_Q) != 0);
2494     if (mask & CPSR_T)
2495         env->thumb = ((val & CPSR_T) != 0);
2496     if (mask & CPSR_IT_0_1) {
2497         env->condexec_bits &= ~3;
2498         env->condexec_bits |= (val >> 25) & 3;
2499     }
2500     if (mask & CPSR_IT_2_7) {
2501         env->condexec_bits &= 3;
2502         env->condexec_bits |= (val >> 8) & 0xfc;
2503     }
2504     if (mask & CPSR_GE) {
2505         env->GE = (val >> 16) & 0xf;
2506     }
2507
2508     env->daif &= ~(CPSR_AIF & mask);
2509     env->daif |= val & CPSR_AIF & mask;
2510
2511     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2512         if (bad_mode_switch(env, val & CPSR_M)) {
2513             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2514              * We choose to ignore the attempt and leave the CPSR M field
2515              * untouched.
2516              */
2517             mask &= ~CPSR_M;
2518         } else {
2519             switch_mode(env, val & CPSR_M);
2520         }
2521     }
2522     mask &= ~CACHED_CPSR_BITS;
2523     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2524 }
2525
2526 /* Sign/zero extend */
2527 uint32_t HELPER(sxtb16)(uint32_t x)
2528 {
2529     uint32_t res;
2530     res = (uint16_t)(int8_t)x;
2531     res |= (uint32_t)(int8_t)(x >> 16) << 16;
2532     return res;
2533 }
2534
2535 uint32_t HELPER(uxtb16)(uint32_t x)
2536 {
2537     uint32_t res;
2538     res = (uint16_t)(uint8_t)x;
2539     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2540     return res;
2541 }
2542
2543 uint32_t HELPER(clz)(uint32_t x)
2544 {
2545     return clz32(x);
2546 }
2547
2548 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2549 {
2550     if (den == 0)
2551       return 0;
2552     if (num == INT_MIN && den == -1)
2553       return INT_MIN;
2554     return num / den;
2555 }
2556
2557 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2558 {
2559     if (den == 0)
2560       return 0;
2561     return num / den;
2562 }
2563
2564 uint32_t HELPER(rbit)(uint32_t x)
2565 {
2566     x =  ((x & 0xff000000) >> 24)
2567        | ((x & 0x00ff0000) >> 8)
2568        | ((x & 0x0000ff00) << 8)
2569        | ((x & 0x000000ff) << 24);
2570     x =  ((x & 0xf0f0f0f0) >> 4)
2571        | ((x & 0x0f0f0f0f) << 4);
2572     x =  ((x & 0x88888888) >> 3)
2573        | ((x & 0x44444444) >> 1)
2574        | ((x & 0x22222222) << 1)
2575        | ((x & 0x11111111) << 3);
2576     return x;
2577 }
2578
2579 #if defined(CONFIG_USER_ONLY)
2580
2581 void arm_cpu_do_interrupt(CPUState *cs)
2582 {
2583     ARMCPU *cpu = ARM_CPU(cs);
2584     CPUARMState *env = &cpu->env;
2585
2586     env->exception_index = -1;
2587 }
2588
2589 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2590                               int mmu_idx)
2591 {
2592     if (rw == 2) {
2593         env->exception_index = EXCP_PREFETCH_ABORT;
2594         env->cp15.c6_insn = address;
2595     } else {
2596         env->exception_index = EXCP_DATA_ABORT;
2597         env->cp15.c6_data = address;
2598     }
2599     return 1;
2600 }
2601
2602 /* These should probably raise undefined insn exceptions.  */
2603 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2604 {
2605     cpu_abort(env, "v7m_mrs %d\n", reg);
2606 }
2607
2608 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2609 {
2610     cpu_abort(env, "v7m_mrs %d\n", reg);
2611     return 0;
2612 }
2613
2614 void switch_mode(CPUARMState *env, int mode)
2615 {
2616     if (mode != ARM_CPU_MODE_USR)
2617         cpu_abort(env, "Tried to switch out of user mode\n");
2618 }
2619
2620 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2621 {
2622     cpu_abort(env, "banked r13 write\n");
2623 }
2624
2625 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2626 {
2627     cpu_abort(env, "banked r13 read\n");
2628     return 0;
2629 }
2630
2631 #else
2632
2633 /* Map CPU modes onto saved register banks.  */
2634 int bank_number(int mode)
2635 {
2636     switch (mode) {
2637     case ARM_CPU_MODE_USR:
2638     case ARM_CPU_MODE_SYS:
2639         return 0;
2640     case ARM_CPU_MODE_SVC:
2641         return 1;
2642     case ARM_CPU_MODE_ABT:
2643         return 2;
2644     case ARM_CPU_MODE_UND:
2645         return 3;
2646     case ARM_CPU_MODE_IRQ:
2647         return 4;
2648     case ARM_CPU_MODE_FIQ:
2649         return 5;
2650     }
2651     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2652 }
2653
2654 void switch_mode(CPUARMState *env, int mode)
2655 {
2656     int old_mode;
2657     int i;
2658
2659     old_mode = env->uncached_cpsr & CPSR_M;
2660     if (mode == old_mode)
2661         return;
2662
2663     if (old_mode == ARM_CPU_MODE_FIQ) {
2664         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2665         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2666     } else if (mode == ARM_CPU_MODE_FIQ) {
2667         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2668         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2669     }
2670
2671     i = bank_number(old_mode);
2672     env->banked_r13[i] = env->regs[13];
2673     env->banked_r14[i] = env->regs[14];
2674     env->banked_spsr[i] = env->spsr;
2675
2676     i = bank_number(mode);
2677     env->regs[13] = env->banked_r13[i];
2678     env->regs[14] = env->banked_r14[i];
2679     env->spsr = env->banked_spsr[i];
2680 }
2681
2682 static void v7m_push(CPUARMState *env, uint32_t val)
2683 {
2684     CPUState *cs = ENV_GET_CPU(env);
2685     env->regs[13] -= 4;
2686     stl_phys(cs->as, env->regs[13], val);
2687 }
2688
2689 static uint32_t v7m_pop(CPUARMState *env)
2690 {
2691     CPUState *cs = ENV_GET_CPU(env);
2692     uint32_t val;
2693     val = ldl_phys(cs->as, env->regs[13]);
2694     env->regs[13] += 4;
2695     return val;
2696 }
2697
2698 /* Switch to V7M main or process stack pointer.  */
2699 static void switch_v7m_sp(CPUARMState *env, int process)
2700 {
2701     uint32_t tmp;
2702     if (env->v7m.current_sp != process) {
2703         tmp = env->v7m.other_sp;
2704         env->v7m.other_sp = env->regs[13];
2705         env->regs[13] = tmp;
2706         env->v7m.current_sp = process;
2707     }
2708 }
2709
2710 static void do_v7m_exception_exit(CPUARMState *env)
2711 {
2712     uint32_t type;
2713     uint32_t xpsr;
2714
2715     type = env->regs[15];
2716     if (env->v7m.exception != 0)
2717         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2718
2719     /* Switch to the target stack.  */
2720     switch_v7m_sp(env, (type & 4) != 0);
2721     /* Pop registers.  */
2722     env->regs[0] = v7m_pop(env);
2723     env->regs[1] = v7m_pop(env);
2724     env->regs[2] = v7m_pop(env);
2725     env->regs[3] = v7m_pop(env);
2726     env->regs[12] = v7m_pop(env);
2727     env->regs[14] = v7m_pop(env);
2728     env->regs[15] = v7m_pop(env);
2729     xpsr = v7m_pop(env);
2730     xpsr_write(env, xpsr, 0xfffffdff);
2731     /* Undo stack alignment.  */
2732     if (xpsr & 0x200)
2733         env->regs[13] |= 4;
2734     /* ??? The exception return type specifies Thread/Handler mode.  However
2735        this is also implied by the xPSR value. Not sure what to do
2736        if there is a mismatch.  */
2737     /* ??? Likewise for mismatches between the CONTROL register and the stack
2738        pointer.  */
2739 }
2740
2741 /* Exception names for debug logging; note that not all of these
2742  * precisely correspond to architectural exceptions.
2743  */
2744 static const char * const excnames[] = {
2745     [EXCP_UDEF] = "Undefined Instruction",
2746     [EXCP_SWI] = "SVC",
2747     [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2748     [EXCP_DATA_ABORT] = "Data Abort",
2749     [EXCP_IRQ] = "IRQ",
2750     [EXCP_FIQ] = "FIQ",
2751     [EXCP_BKPT] = "Breakpoint",
2752     [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2753     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2754     [EXCP_STREX] = "QEMU intercept of STREX",
2755 };
2756
2757 static inline void arm_log_exception(int idx)
2758 {
2759     if (qemu_loglevel_mask(CPU_LOG_INT)) {
2760         const char *exc = NULL;
2761
2762         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2763             exc = excnames[idx];
2764         }
2765         if (!exc) {
2766             exc = "unknown";
2767         }
2768         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2769     }
2770 }
2771
2772 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2773 {
2774     ARMCPU *cpu = ARM_CPU(cs);
2775     CPUARMState *env = &cpu->env;
2776     uint32_t xpsr = xpsr_read(env);
2777     uint32_t lr;
2778     uint32_t addr;
2779
2780     arm_log_exception(env->exception_index);
2781
2782     lr = 0xfffffff1;
2783     if (env->v7m.current_sp)
2784         lr |= 4;
2785     if (env->v7m.exception == 0)
2786         lr |= 8;
2787
2788     /* For exceptions we just mark as pending on the NVIC, and let that
2789        handle it.  */
2790     /* TODO: Need to escalate if the current priority is higher than the
2791        one we're raising.  */
2792     switch (env->exception_index) {
2793     case EXCP_UDEF:
2794         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2795         return;
2796     case EXCP_SWI:
2797         /* The PC already points to the next instruction.  */
2798         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2799         return;
2800     case EXCP_PREFETCH_ABORT:
2801     case EXCP_DATA_ABORT:
2802         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2803         return;
2804     case EXCP_BKPT:
2805         if (semihosting_enabled) {
2806             int nr;
2807             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2808             if (nr == 0xab) {
2809                 env->regs[15] += 2;
2810                 env->regs[0] = do_arm_semihosting(env);
2811                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2812                 return;
2813             }
2814         }
2815         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2816         return;
2817     case EXCP_IRQ:
2818         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2819         break;
2820     case EXCP_EXCEPTION_EXIT:
2821         do_v7m_exception_exit(env);
2822         return;
2823     default:
2824         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2825         return; /* Never happens.  Keep compiler happy.  */
2826     }
2827
2828     /* Align stack pointer.  */
2829     /* ??? Should only do this if Configuration Control Register
2830        STACKALIGN bit is set.  */
2831     if (env->regs[13] & 4) {
2832         env->regs[13] -= 4;
2833         xpsr |= 0x200;
2834     }
2835     /* Switch to the handler mode.  */
2836     v7m_push(env, xpsr);
2837     v7m_push(env, env->regs[15]);
2838     v7m_push(env, env->regs[14]);
2839     v7m_push(env, env->regs[12]);
2840     v7m_push(env, env->regs[3]);
2841     v7m_push(env, env->regs[2]);
2842     v7m_push(env, env->regs[1]);
2843     v7m_push(env, env->regs[0]);
2844     switch_v7m_sp(env, 0);
2845     /* Clear IT bits */
2846     env->condexec_bits = 0;
2847     env->regs[14] = lr;
2848     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
2849     env->regs[15] = addr & 0xfffffffe;
2850     env->thumb = addr & 1;
2851 }
2852
2853 /* Handle a CPU exception.  */
2854 void arm_cpu_do_interrupt(CPUState *cs)
2855 {
2856     ARMCPU *cpu = ARM_CPU(cs);
2857     CPUARMState *env = &cpu->env;
2858     uint32_t addr;
2859     uint32_t mask;
2860     int new_mode;
2861     uint32_t offset;
2862
2863     assert(!IS_M(env));
2864
2865     arm_log_exception(env->exception_index);
2866
2867     /* TODO: Vectored interrupt controller.  */
2868     switch (env->exception_index) {
2869     case EXCP_UDEF:
2870         new_mode = ARM_CPU_MODE_UND;
2871         addr = 0x04;
2872         mask = CPSR_I;
2873         if (env->thumb)
2874             offset = 2;
2875         else
2876             offset = 4;
2877         break;
2878     case EXCP_SWI:
2879         if (semihosting_enabled) {
2880             /* Check for semihosting interrupt.  */
2881             if (env->thumb) {
2882                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2883                     & 0xff;
2884             } else {
2885                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2886                     & 0xffffff;
2887             }
2888             /* Only intercept calls from privileged modes, to provide some
2889                semblance of security.  */
2890             if (((mask == 0x123456 && !env->thumb)
2891                     || (mask == 0xab && env->thumb))
2892                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2893                 env->regs[0] = do_arm_semihosting(env);
2894                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2895                 return;
2896             }
2897         }
2898         new_mode = ARM_CPU_MODE_SVC;
2899         addr = 0x08;
2900         mask = CPSR_I;
2901         /* The PC already points to the next instruction.  */
2902         offset = 0;
2903         break;
2904     case EXCP_BKPT:
2905         /* See if this is a semihosting syscall.  */
2906         if (env->thumb && semihosting_enabled) {
2907             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2908             if (mask == 0xab
2909                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2910                 env->regs[15] += 2;
2911                 env->regs[0] = do_arm_semihosting(env);
2912                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2913                 return;
2914             }
2915         }
2916         env->cp15.c5_insn = 2;
2917         /* Fall through to prefetch abort.  */
2918     case EXCP_PREFETCH_ABORT:
2919         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2920                       env->cp15.c5_insn, env->cp15.c6_insn);
2921         new_mode = ARM_CPU_MODE_ABT;
2922         addr = 0x0c;
2923         mask = CPSR_A | CPSR_I;
2924         offset = 4;
2925         break;
2926     case EXCP_DATA_ABORT:
2927         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2928                       env->cp15.c5_data, env->cp15.c6_data);
2929         new_mode = ARM_CPU_MODE_ABT;
2930         addr = 0x10;
2931         mask = CPSR_A | CPSR_I;
2932         offset = 8;
2933         break;
2934     case EXCP_IRQ:
2935         new_mode = ARM_CPU_MODE_IRQ;
2936         addr = 0x18;
2937         /* Disable IRQ and imprecise data aborts.  */
2938         mask = CPSR_A | CPSR_I;
2939         offset = 4;
2940         break;
2941     case EXCP_FIQ:
2942         new_mode = ARM_CPU_MODE_FIQ;
2943         addr = 0x1c;
2944         /* Disable FIQ, IRQ and imprecise data aborts.  */
2945         mask = CPSR_A | CPSR_I | CPSR_F;
2946         offset = 4;
2947         break;
2948     default:
2949         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2950         return; /* Never happens.  Keep compiler happy.  */
2951     }
2952     /* High vectors.  */
2953     if (env->cp15.c1_sys & SCTLR_V) {
2954         /* when enabled, base address cannot be remapped.  */
2955         addr += 0xffff0000;
2956     } else {
2957         /* ARM v7 architectures provide a vector base address register to remap
2958          * the interrupt vector table.
2959          * This register is only followed in non-monitor mode, and has a secure
2960          * and un-secure copy. Since the cpu is always in a un-secure operation
2961          * and is never in monitor mode this feature is always active.
2962          * Note: only bits 31:5 are valid.
2963          */
2964         addr += env->cp15.c12_vbar;
2965     }
2966     switch_mode (env, new_mode);
2967     env->spsr = cpsr_read(env);
2968     /* Clear IT bits.  */
2969     env->condexec_bits = 0;
2970     /* Switch to the new mode, and to the correct instruction set.  */
2971     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2972     env->daif |= mask;
2973     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2974      * and we should just guard the thumb mode on V4 */
2975     if (arm_feature(env, ARM_FEATURE_V4T)) {
2976         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
2977     }
2978     env->regs[14] = env->regs[15] + offset;
2979     env->regs[15] = addr;
2980     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2981 }
2982
2983 /* Check section/page access permissions.
2984    Returns the page protection flags, or zero if the access is not
2985    permitted.  */
2986 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2987                            int access_type, int is_user)
2988 {
2989   int prot_ro;
2990
2991   if (domain_prot == 3) {
2992     return PAGE_READ | PAGE_WRITE;
2993   }
2994
2995   if (access_type == 1)
2996       prot_ro = 0;
2997   else
2998       prot_ro = PAGE_READ;
2999
3000   switch (ap) {
3001   case 0:
3002       if (arm_feature(env, ARM_FEATURE_V7)) {
3003           return 0;
3004       }
3005       if (access_type == 1)
3006           return 0;
3007       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3008       case SCTLR_S:
3009           return is_user ? 0 : PAGE_READ;
3010       case SCTLR_R:
3011           return PAGE_READ;
3012       default:
3013           return 0;
3014       }
3015   case 1:
3016       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3017   case 2:
3018       if (is_user)
3019           return prot_ro;
3020       else
3021           return PAGE_READ | PAGE_WRITE;
3022   case 3:
3023       return PAGE_READ | PAGE_WRITE;
3024   case 4: /* Reserved.  */
3025       return 0;
3026   case 5:
3027       return is_user ? 0 : prot_ro;
3028   case 6:
3029       return prot_ro;
3030   case 7:
3031       if (!arm_feature (env, ARM_FEATURE_V6K))
3032           return 0;
3033       return prot_ro;
3034   default:
3035       abort();
3036   }
3037 }
3038
3039 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
3040 {
3041     uint32_t table;
3042
3043     if (address & env->cp15.c2_mask)
3044         table = env->cp15.ttbr1_el1 & 0xffffc000;
3045     else
3046         table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3047
3048     table |= (address >> 18) & 0x3ffc;
3049     return table;
3050 }
3051
3052 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3053                             int is_user, hwaddr *phys_ptr,
3054                             int *prot, target_ulong *page_size)
3055 {
3056     CPUState *cs = ENV_GET_CPU(env);
3057     int code;
3058     uint32_t table;
3059     uint32_t desc;
3060     int type;
3061     int ap;
3062     int domain;
3063     int domain_prot;
3064     hwaddr phys_addr;
3065
3066     /* Pagetable walk.  */
3067     /* Lookup l1 descriptor.  */
3068     table = get_level1_table_address(env, address);
3069     desc = ldl_phys(cs->as, table);
3070     type = (desc & 3);
3071     domain = (desc >> 5) & 0x0f;
3072     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3073     if (type == 0) {
3074         /* Section translation fault.  */
3075         code = 5;
3076         goto do_fault;
3077     }
3078     if (domain_prot == 0 || domain_prot == 2) {
3079         if (type == 2)
3080             code = 9; /* Section domain fault.  */
3081         else
3082             code = 11; /* Page domain fault.  */
3083         goto do_fault;
3084     }
3085     if (type == 2) {
3086         /* 1Mb section.  */
3087         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3088         ap = (desc >> 10) & 3;
3089         code = 13;
3090         *page_size = 1024 * 1024;
3091     } else {
3092         /* Lookup l2 entry.  */
3093         if (type == 1) {
3094             /* Coarse pagetable.  */
3095             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3096         } else {
3097             /* Fine pagetable.  */
3098             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3099         }
3100         desc = ldl_phys(cs->as, table);
3101         switch (desc & 3) {
3102         case 0: /* Page translation fault.  */
3103             code = 7;
3104             goto do_fault;
3105         case 1: /* 64k page.  */
3106             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3107             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3108             *page_size = 0x10000;
3109             break;
3110         case 2: /* 4k page.  */
3111             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3112             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3113             *page_size = 0x1000;
3114             break;
3115         case 3: /* 1k page.  */
3116             if (type == 1) {
3117                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3118                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3119                 } else {
3120                     /* Page translation fault.  */
3121                     code = 7;
3122                     goto do_fault;
3123                 }
3124             } else {
3125                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3126             }
3127             ap = (desc >> 4) & 3;
3128             *page_size = 0x400;
3129             break;
3130         default:
3131             /* Never happens, but compiler isn't smart enough to tell.  */
3132             abort();
3133         }
3134         code = 15;
3135     }
3136     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3137     if (!*prot) {
3138         /* Access permission fault.  */
3139         goto do_fault;
3140     }
3141     *prot |= PAGE_EXEC;
3142     *phys_ptr = phys_addr;
3143     return 0;
3144 do_fault:
3145     return code | (domain << 4);
3146 }
3147
3148 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3149                             int is_user, hwaddr *phys_ptr,
3150                             int *prot, target_ulong *page_size)
3151 {
3152     CPUState *cs = ENV_GET_CPU(env);
3153     int code;
3154     uint32_t table;
3155     uint32_t desc;
3156     uint32_t xn;
3157     uint32_t pxn = 0;
3158     int type;
3159     int ap;
3160     int domain = 0;
3161     int domain_prot;
3162     hwaddr phys_addr;
3163
3164     /* Pagetable walk.  */
3165     /* Lookup l1 descriptor.  */
3166     table = get_level1_table_address(env, address);
3167     desc = ldl_phys(cs->as, table);
3168     type = (desc & 3);
3169     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3170         /* Section translation fault, or attempt to use the encoding
3171          * which is Reserved on implementations without PXN.
3172          */
3173         code = 5;
3174         goto do_fault;
3175     }
3176     if ((type == 1) || !(desc & (1 << 18))) {
3177         /* Page or Section.  */
3178         domain = (desc >> 5) & 0x0f;
3179     }
3180     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3181     if (domain_prot == 0 || domain_prot == 2) {
3182         if (type != 1) {
3183             code = 9; /* Section domain fault.  */
3184         } else {
3185             code = 11; /* Page domain fault.  */
3186         }
3187         goto do_fault;
3188     }
3189     if (type != 1) {
3190         if (desc & (1 << 18)) {
3191             /* Supersection.  */
3192             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3193             *page_size = 0x1000000;
3194         } else {
3195             /* Section.  */
3196             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3197             *page_size = 0x100000;
3198         }
3199         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3200         xn = desc & (1 << 4);
3201         pxn = desc & 1;
3202         code = 13;
3203     } else {
3204         if (arm_feature(env, ARM_FEATURE_PXN)) {
3205             pxn = (desc >> 2) & 1;
3206         }
3207         /* Lookup l2 entry.  */
3208         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3209         desc = ldl_phys(cs->as, table);
3210         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3211         switch (desc & 3) {
3212         case 0: /* Page translation fault.  */
3213             code = 7;
3214             goto do_fault;
3215         case 1: /* 64k page.  */
3216             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3217             xn = desc & (1 << 15);
3218             *page_size = 0x10000;
3219             break;
3220         case 2: case 3: /* 4k page.  */
3221             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3222             xn = desc & 1;
3223             *page_size = 0x1000;
3224             break;
3225         default:
3226             /* Never happens, but compiler isn't smart enough to tell.  */
3227             abort();
3228         }
3229         code = 15;
3230     }
3231     if (domain_prot == 3) {
3232         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3233     } else {
3234         if (pxn && !is_user) {
3235             xn = 1;
3236         }
3237         if (xn && access_type == 2)
3238             goto do_fault;
3239
3240         /* The simplified model uses AP[0] as an access control bit.  */
3241         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3242             /* Access flag fault.  */
3243             code = (code == 15) ? 6 : 3;
3244             goto do_fault;
3245         }
3246         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3247         if (!*prot) {
3248             /* Access permission fault.  */
3249             goto do_fault;
3250         }
3251         if (!xn) {
3252             *prot |= PAGE_EXEC;
3253         }
3254     }
3255     *phys_ptr = phys_addr;
3256     return 0;
3257 do_fault:
3258     return code | (domain << 4);
3259 }
3260
3261 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3262  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3263  */
3264 typedef enum {
3265     translation_fault = 1,
3266     access_fault = 2,
3267     permission_fault = 3,
3268 } MMUFaultType;
3269
3270 static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
3271                               int access_type, int is_user,
3272                               hwaddr *phys_ptr, int *prot,
3273                               target_ulong *page_size_ptr)
3274 {
3275     CPUState *cs = ENV_GET_CPU(env);
3276     /* Read an LPAE long-descriptor translation table. */
3277     MMUFaultType fault_type = translation_fault;
3278     uint32_t level = 1;
3279     uint32_t epd;
3280     uint32_t tsz;
3281     uint64_t ttbr;
3282     int ttbr_select;
3283     int n;
3284     hwaddr descaddr;
3285     uint32_t tableattrs;
3286     target_ulong page_size;
3287     uint32_t attrs;
3288
3289     /* Determine whether this address is in the region controlled by
3290      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3291      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3292      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3293      */
3294     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
3295     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
3296     if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
3297         /* there is a ttbr0 region and we are in it (high bits all zero) */
3298         ttbr_select = 0;
3299     } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
3300         /* there is a ttbr1 region and we are in it (high bits all one) */
3301         ttbr_select = 1;
3302     } else if (!t0sz) {
3303         /* ttbr0 region is "everything not in the ttbr1 region" */
3304         ttbr_select = 0;
3305     } else if (!t1sz) {
3306         /* ttbr1 region is "everything not in the ttbr0 region" */
3307         ttbr_select = 1;
3308     } else {
3309         /* in the gap between the two regions, this is a Translation fault */
3310         fault_type = translation_fault;
3311         goto do_fault;
3312     }
3313
3314     /* Note that QEMU ignores shareability and cacheability attributes,
3315      * so we don't need to do anything with the SH, ORGN, IRGN fields
3316      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
3317      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3318      * implement any ASID-like capability so we can ignore it (instead
3319      * we will always flush the TLB any time the ASID is changed).
3320      */
3321     if (ttbr_select == 0) {
3322         ttbr = env->cp15.ttbr0_el1;
3323         epd = extract32(env->cp15.c2_control, 7, 1);
3324         tsz = t0sz;
3325     } else {
3326         ttbr = env->cp15.ttbr1_el1;
3327         epd = extract32(env->cp15.c2_control, 23, 1);
3328         tsz = t1sz;
3329     }
3330
3331     if (epd) {
3332         /* Translation table walk disabled => Translation fault on TLB miss */
3333         goto do_fault;
3334     }
3335
3336     /* If the region is small enough we will skip straight to a 2nd level
3337      * lookup. This affects the number of bits of the address used in
3338      * combination with the TTBR to find the first descriptor. ('n' here
3339      * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3340      * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3341      */
3342     if (tsz > 1) {
3343         level = 2;
3344         n = 14 - tsz;
3345     } else {
3346         n = 5 - tsz;
3347     }
3348
3349     /* Clear the vaddr bits which aren't part of the within-region address,
3350      * so that we don't have to special case things when calculating the
3351      * first descriptor address.
3352      */
3353     address &= (0xffffffffU >> tsz);
3354
3355     /* Now we can extract the actual base address from the TTBR */
3356     descaddr = extract64(ttbr, 0, 40);
3357     descaddr &= ~((1ULL << n) - 1);
3358
3359     tableattrs = 0;
3360     for (;;) {
3361         uint64_t descriptor;
3362
3363         descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3364         descriptor = ldq_phys(cs->as, descaddr);
3365         if (!(descriptor & 1) ||
3366             (!(descriptor & 2) && (level == 3))) {
3367             /* Invalid, or the Reserved level 3 encoding */
3368             goto do_fault;
3369         }
3370         descaddr = descriptor & 0xfffffff000ULL;
3371
3372         if ((descriptor & 2) && (level < 3)) {
3373             /* Table entry. The top five bits are attributes which  may
3374              * propagate down through lower levels of the table (and
3375              * which are all arranged so that 0 means "no effect", so
3376              * we can gather them up by ORing in the bits at each level).
3377              */
3378             tableattrs |= extract64(descriptor, 59, 5);
3379             level++;
3380             continue;
3381         }
3382         /* Block entry at level 1 or 2, or page entry at level 3.
3383          * These are basically the same thing, although the number
3384          * of bits we pull in from the vaddr varies.
3385          */
3386         page_size = (1 << (39 - (9 * level)));
3387         descaddr |= (address & (page_size - 1));
3388         /* Extract attributes from the descriptor and merge with table attrs */
3389         attrs = extract64(descriptor, 2, 10)
3390             | (extract64(descriptor, 52, 12) << 10);
3391         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3392         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3393         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3394          * means "force PL1 access only", which means forcing AP[1] to 0.
3395          */
3396         if (extract32(tableattrs, 2, 1)) {
3397             attrs &= ~(1 << 4);
3398         }
3399         /* Since we're always in the Non-secure state, NSTable is ignored. */
3400         break;
3401     }
3402     /* Here descaddr is the final physical address, and attributes
3403      * are all in attrs.
3404      */
3405     fault_type = access_fault;
3406     if ((attrs & (1 << 8)) == 0) {
3407         /* Access flag */
3408         goto do_fault;
3409     }
3410     fault_type = permission_fault;
3411     if (is_user && !(attrs & (1 << 4))) {
3412         /* Unprivileged access not enabled */
3413         goto do_fault;
3414     }
3415     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3416     if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3417         /* XN or PXN */
3418         if (access_type == 2) {
3419             goto do_fault;
3420         }
3421         *prot &= ~PAGE_EXEC;
3422     }
3423     if (attrs & (1 << 5)) {
3424         /* Write access forbidden */
3425         if (access_type == 1) {
3426             goto do_fault;
3427         }
3428         *prot &= ~PAGE_WRITE;
3429     }
3430
3431     *phys_ptr = descaddr;
3432     *page_size_ptr = page_size;
3433     return 0;
3434
3435 do_fault:
3436     /* Long-descriptor format IFSR/DFSR value */
3437     return (1 << 9) | (fault_type << 2) | level;
3438 }
3439
3440 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3441                              int access_type, int is_user,
3442                              hwaddr *phys_ptr, int *prot)
3443 {
3444     int n;
3445     uint32_t mask;
3446     uint32_t base;
3447
3448     *phys_ptr = address;
3449     for (n = 7; n >= 0; n--) {
3450         base = env->cp15.c6_region[n];
3451         if ((base & 1) == 0)
3452             continue;
3453         mask = 1 << ((base >> 1) & 0x1f);
3454         /* Keep this shift separate from the above to avoid an
3455            (undefined) << 32.  */
3456         mask = (mask << 1) - 1;
3457         if (((base ^ address) & ~mask) == 0)
3458             break;
3459     }
3460     if (n < 0)
3461         return 2;
3462
3463     if (access_type == 2) {
3464         mask = env->cp15.c5_insn;
3465     } else {
3466         mask = env->cp15.c5_data;
3467     }
3468     mask = (mask >> (n * 4)) & 0xf;
3469     switch (mask) {
3470     case 0:
3471         return 1;
3472     case 1:
3473         if (is_user)
3474           return 1;
3475         *prot = PAGE_READ | PAGE_WRITE;
3476         break;
3477     case 2:
3478         *prot = PAGE_READ;
3479         if (!is_user)
3480             *prot |= PAGE_WRITE;
3481         break;
3482     case 3:
3483         *prot = PAGE_READ | PAGE_WRITE;
3484         break;
3485     case 5:
3486         if (is_user)
3487             return 1;
3488         *prot = PAGE_READ;
3489         break;
3490     case 6:
3491         *prot = PAGE_READ;
3492         break;
3493     default:
3494         /* Bad permission.  */
3495         return 1;
3496     }
3497     *prot |= PAGE_EXEC;
3498     return 0;
3499 }
3500
3501 /* get_phys_addr - get the physical address for this virtual address
3502  *
3503  * Find the physical address corresponding to the given virtual address,
3504  * by doing a translation table walk on MMU based systems or using the
3505  * MPU state on MPU based systems.
3506  *
3507  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3508  * prot and page_size are not filled in, and the return value provides
3509  * information on why the translation aborted, in the format of a
3510  * DFSR/IFSR fault register, with the following caveats:
3511  *  * we honour the short vs long DFSR format differences.
3512  *  * the WnR bit is never set (the caller must do this).
3513  *  * for MPU based systems we don't bother to return a full FSR format
3514  *    value.
3515  *
3516  * @env: CPUARMState
3517  * @address: virtual address to get physical address for
3518  * @access_type: 0 for read, 1 for write, 2 for execute
3519  * @is_user: 0 for privileged access, 1 for user
3520  * @phys_ptr: set to the physical address corresponding to the virtual address
3521  * @prot: set to the permissions for the page containing phys_ptr
3522  * @page_size: set to the size of the page containing phys_ptr
3523  */
3524 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
3525                                 int access_type, int is_user,
3526                                 hwaddr *phys_ptr, int *prot,
3527                                 target_ulong *page_size)
3528 {
3529     /* Fast Context Switch Extension.  */
3530     if (address < 0x02000000)
3531         address += env->cp15.c13_fcse;
3532
3533     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
3534         /* MMU/MPU disabled.  */
3535         *phys_ptr = address;
3536         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3537         *page_size = TARGET_PAGE_SIZE;
3538         return 0;
3539     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
3540         *page_size = TARGET_PAGE_SIZE;
3541         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3542                                  prot);
3543     } else if (extended_addresses_enabled(env)) {
3544         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3545                                   prot, page_size);
3546     } else if (env->cp15.c1_sys & SCTLR_XP) {
3547         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3548                                 prot, page_size);
3549     } else {
3550         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3551                                 prot, page_size);
3552     }
3553 }
3554
3555 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
3556                               int access_type, int mmu_idx)
3557 {
3558     hwaddr phys_addr;
3559     target_ulong page_size;
3560     int prot;
3561     int ret, is_user;
3562
3563     is_user = mmu_idx == MMU_USER_IDX;
3564     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3565                         &page_size);
3566     if (ret == 0) {
3567         /* Map a single [sub]page.  */
3568         phys_addr &= ~(hwaddr)0x3ff;
3569         address &= ~(uint32_t)0x3ff;
3570         tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
3571         return 0;
3572     }
3573
3574     if (access_type == 2) {
3575         env->cp15.c5_insn = ret;
3576         env->cp15.c6_insn = address;
3577         env->exception_index = EXCP_PREFETCH_ABORT;
3578     } else {
3579         env->cp15.c5_data = ret;
3580         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3581             env->cp15.c5_data |= (1 << 11);
3582         env->cp15.c6_data = address;
3583         env->exception_index = EXCP_DATA_ABORT;
3584     }
3585     return 1;
3586 }
3587
3588 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3589 {
3590     ARMCPU *cpu = ARM_CPU(cs);
3591     hwaddr phys_addr;
3592     target_ulong page_size;
3593     int prot;
3594     int ret;
3595
3596     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3597
3598     if (ret != 0) {
3599         return -1;
3600     }
3601
3602     return phys_addr;
3603 }
3604
3605 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3606 {
3607     if ((env->uncached_cpsr & CPSR_M) == mode) {
3608         env->regs[13] = val;
3609     } else {
3610         env->banked_r13[bank_number(mode)] = val;
3611     }
3612 }
3613
3614 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3615 {
3616     if ((env->uncached_cpsr & CPSR_M) == mode) {
3617         return env->regs[13];
3618     } else {
3619         return env->banked_r13[bank_number(mode)];
3620     }
3621 }
3622
3623 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3624 {
3625     switch (reg) {
3626     case 0: /* APSR */
3627         return xpsr_read(env) & 0xf8000000;
3628     case 1: /* IAPSR */
3629         return xpsr_read(env) & 0xf80001ff;
3630     case 2: /* EAPSR */
3631         return xpsr_read(env) & 0xff00fc00;
3632     case 3: /* xPSR */
3633         return xpsr_read(env) & 0xff00fdff;
3634     case 5: /* IPSR */
3635         return xpsr_read(env) & 0x000001ff;
3636     case 6: /* EPSR */
3637         return xpsr_read(env) & 0x0700fc00;
3638     case 7: /* IEPSR */
3639         return xpsr_read(env) & 0x0700edff;
3640     case 8: /* MSP */
3641         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3642     case 9: /* PSP */
3643         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3644     case 16: /* PRIMASK */
3645         return (env->daif & PSTATE_I) != 0;
3646     case 17: /* BASEPRI */
3647     case 18: /* BASEPRI_MAX */
3648         return env->v7m.basepri;
3649     case 19: /* FAULTMASK */
3650         return (env->daif & PSTATE_F) != 0;
3651     case 20: /* CONTROL */
3652         return env->v7m.control;
3653     default:
3654         /* ??? For debugging only.  */
3655         cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3656         return 0;
3657     }
3658 }
3659
3660 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3661 {
3662     switch (reg) {
3663     case 0: /* APSR */
3664         xpsr_write(env, val, 0xf8000000);
3665         break;
3666     case 1: /* IAPSR */
3667         xpsr_write(env, val, 0xf8000000);
3668         break;
3669     case 2: /* EAPSR */
3670         xpsr_write(env, val, 0xfe00fc00);
3671         break;
3672     case 3: /* xPSR */
3673         xpsr_write(env, val, 0xfe00fc00);
3674         break;
3675     case 5: /* IPSR */
3676         /* IPSR bits are readonly.  */
3677         break;
3678     case 6: /* EPSR */
3679         xpsr_write(env, val, 0x0600fc00);
3680         break;
3681     case 7: /* IEPSR */
3682         xpsr_write(env, val, 0x0600fc00);
3683         break;
3684     case 8: /* MSP */
3685         if (env->v7m.current_sp)
3686             env->v7m.other_sp = val;
3687         else
3688             env->regs[13] = val;
3689         break;
3690     case 9: /* PSP */
3691         if (env->v7m.current_sp)
3692             env->regs[13] = val;
3693         else
3694             env->v7m.other_sp = val;
3695         break;
3696     case 16: /* PRIMASK */
3697         if (val & 1) {
3698             env->daif |= PSTATE_I;
3699         } else {
3700             env->daif &= ~PSTATE_I;
3701         }
3702         break;
3703     case 17: /* BASEPRI */
3704         env->v7m.basepri = val & 0xff;
3705         break;
3706     case 18: /* BASEPRI_MAX */
3707         val &= 0xff;
3708         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3709             env->v7m.basepri = val;
3710         break;
3711     case 19: /* FAULTMASK */
3712         if (val & 1) {
3713             env->daif |= PSTATE_F;
3714         } else {
3715             env->daif &= ~PSTATE_F;
3716         }
3717         break;
3718     case 20: /* CONTROL */
3719         env->v7m.control = val & 3;
3720         switch_v7m_sp(env, (val & 2) != 0);
3721         break;
3722     default:
3723         /* ??? For debugging only.  */
3724         cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3725         return;
3726     }
3727 }
3728
3729 #endif
3730
3731 /* Note that signed overflow is undefined in C.  The following routines are
3732    careful to use unsigned types where modulo arithmetic is required.
3733    Failure to do so _will_ break on newer gcc.  */
3734
3735 /* Signed saturating arithmetic.  */
3736
3737 /* Perform 16-bit signed saturating addition.  */
3738 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3739 {
3740     uint16_t res;
3741
3742     res = a + b;
3743     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3744         if (a & 0x8000)
3745             res = 0x8000;
3746         else
3747             res = 0x7fff;
3748     }
3749     return res;
3750 }
3751
3752 /* Perform 8-bit signed saturating addition.  */
3753 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3754 {
3755     uint8_t res;
3756
3757     res = a + b;
3758     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3759         if (a & 0x80)
3760             res = 0x80;
3761         else
3762             res = 0x7f;
3763     }
3764     return res;
3765 }
3766
3767 /* Perform 16-bit signed saturating subtraction.  */
3768 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3769 {
3770     uint16_t res;
3771
3772     res = a - b;
3773     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3774         if (a & 0x8000)
3775             res = 0x8000;
3776         else
3777             res = 0x7fff;
3778     }
3779     return res;
3780 }
3781
3782 /* Perform 8-bit signed saturating subtraction.  */
3783 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3784 {
3785     uint8_t res;
3786
3787     res = a - b;
3788     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3789         if (a & 0x80)
3790             res = 0x80;
3791         else
3792             res = 0x7f;
3793     }
3794     return res;
3795 }
3796
3797 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3798 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3799 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
3800 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
3801 #define PFX q
3802
3803 #include "op_addsub.h"
3804
3805 /* Unsigned saturating arithmetic.  */
3806 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
3807 {
3808     uint16_t res;
3809     res = a + b;
3810     if (res < a)
3811         res = 0xffff;
3812     return res;
3813 }
3814
3815 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
3816 {
3817     if (a > b)
3818         return a - b;
3819     else
3820         return 0;
3821 }
3822
3823 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3824 {
3825     uint8_t res;
3826     res = a + b;
3827     if (res < a)
3828         res = 0xff;
3829     return res;
3830 }
3831
3832 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3833 {
3834     if (a > b)
3835         return a - b;
3836     else
3837         return 0;
3838 }
3839
3840 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3841 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3842 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
3843 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
3844 #define PFX uq
3845
3846 #include "op_addsub.h"
3847
3848 /* Signed modulo arithmetic.  */
3849 #define SARITH16(a, b, n, op) do { \
3850     int32_t sum; \
3851     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3852     RESULT(sum, n, 16); \
3853     if (sum >= 0) \
3854         ge |= 3 << (n * 2); \
3855     } while(0)
3856
3857 #define SARITH8(a, b, n, op) do { \
3858     int32_t sum; \
3859     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3860     RESULT(sum, n, 8); \
3861     if (sum >= 0) \
3862         ge |= 1 << n; \
3863     } while(0)
3864
3865
3866 #define ADD16(a, b, n) SARITH16(a, b, n, +)
3867 #define SUB16(a, b, n) SARITH16(a, b, n, -)
3868 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
3869 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
3870 #define PFX s
3871 #define ARITH_GE
3872
3873 #include "op_addsub.h"
3874
3875 /* Unsigned modulo arithmetic.  */
3876 #define ADD16(a, b, n) do { \
3877     uint32_t sum; \
3878     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3879     RESULT(sum, n, 16); \
3880     if ((sum >> 16) == 1) \
3881         ge |= 3 << (n * 2); \
3882     } while(0)
3883
3884 #define ADD8(a, b, n) do { \
3885     uint32_t sum; \
3886     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3887     RESULT(sum, n, 8); \
3888     if ((sum >> 8) == 1) \
3889         ge |= 1 << n; \
3890     } while(0)
3891
3892 #define SUB16(a, b, n) do { \
3893     uint32_t sum; \
3894     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3895     RESULT(sum, n, 16); \
3896     if ((sum >> 16) == 0) \
3897         ge |= 3 << (n * 2); \
3898     } while(0)
3899
3900 #define SUB8(a, b, n) do { \
3901     uint32_t sum; \
3902     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3903     RESULT(sum, n, 8); \
3904     if ((sum >> 8) == 0) \
3905         ge |= 1 << n; \
3906     } while(0)
3907
3908 #define PFX u
3909 #define ARITH_GE
3910
3911 #include "op_addsub.h"
3912
3913 /* Halved signed arithmetic.  */
3914 #define ADD16(a, b, n) \
3915   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3916 #define SUB16(a, b, n) \
3917   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3918 #define ADD8(a, b, n) \
3919   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3920 #define SUB8(a, b, n) \
3921   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3922 #define PFX sh
3923
3924 #include "op_addsub.h"
3925
3926 /* Halved unsigned arithmetic.  */
3927 #define ADD16(a, b, n) \
3928   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3929 #define SUB16(a, b, n) \
3930   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3931 #define ADD8(a, b, n) \
3932   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3933 #define SUB8(a, b, n) \
3934   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3935 #define PFX uh
3936
3937 #include "op_addsub.h"
3938
3939 static inline uint8_t do_usad(uint8_t a, uint8_t b)
3940 {
3941     if (a > b)
3942         return a - b;
3943     else
3944         return b - a;
3945 }
3946
3947 /* Unsigned sum of absolute byte differences.  */
3948 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3949 {
3950     uint32_t sum;
3951     sum = do_usad(a, b);
3952     sum += do_usad(a >> 8, b >> 8);
3953     sum += do_usad(a >> 16, b >>16);
3954     sum += do_usad(a >> 24, b >> 24);
3955     return sum;
3956 }
3957
3958 /* For ARMv6 SEL instruction.  */
3959 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3960 {
3961     uint32_t mask;
3962
3963     mask = 0;
3964     if (flags & 1)
3965         mask |= 0xff;
3966     if (flags & 2)
3967         mask |= 0xff00;
3968     if (flags & 4)
3969         mask |= 0xff0000;
3970     if (flags & 8)
3971         mask |= 0xff000000;
3972     return (a & mask) | (b & ~mask);
3973 }
3974
3975 /* VFP support.  We follow the convention used for VFP instructions:
3976    Single precision routines have a "s" suffix, double precision a
3977    "d" suffix.  */
3978
3979 /* Convert host exception flags to vfp form.  */
3980 static inline int vfp_exceptbits_from_host(int host_bits)
3981 {
3982     int target_bits = 0;
3983
3984     if (host_bits & float_flag_invalid)
3985         target_bits |= 1;
3986     if (host_bits & float_flag_divbyzero)
3987         target_bits |= 2;
3988     if (host_bits & float_flag_overflow)
3989         target_bits |= 4;
3990     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
3991         target_bits |= 8;
3992     if (host_bits & float_flag_inexact)
3993         target_bits |= 0x10;
3994     if (host_bits & float_flag_input_denormal)
3995         target_bits |= 0x80;
3996     return target_bits;
3997 }
3998
3999 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4000 {
4001     int i;
4002     uint32_t fpscr;
4003
4004     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4005             | (env->vfp.vec_len << 16)
4006             | (env->vfp.vec_stride << 20);
4007     i = get_float_exception_flags(&env->vfp.fp_status);
4008     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4009     fpscr |= vfp_exceptbits_from_host(i);
4010     return fpscr;
4011 }
4012
4013 uint32_t vfp_get_fpscr(CPUARMState *env)
4014 {
4015     return HELPER(vfp_get_fpscr)(env);
4016 }
4017
4018 /* Convert vfp exception flags to target form.  */
4019 static inline int vfp_exceptbits_to_host(int target_bits)
4020 {
4021     int host_bits = 0;
4022
4023     if (target_bits & 1)
4024         host_bits |= float_flag_invalid;
4025     if (target_bits & 2)
4026         host_bits |= float_flag_divbyzero;
4027     if (target_bits & 4)
4028         host_bits |= float_flag_overflow;
4029     if (target_bits & 8)
4030         host_bits |= float_flag_underflow;
4031     if (target_bits & 0x10)
4032         host_bits |= float_flag_inexact;
4033     if (target_bits & 0x80)
4034         host_bits |= float_flag_input_denormal;
4035     return host_bits;
4036 }
4037
4038 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4039 {
4040     int i;
4041     uint32_t changed;
4042
4043     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4044     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4045     env->vfp.vec_len = (val >> 16) & 7;
4046     env->vfp.vec_stride = (val >> 20) & 3;
4047
4048     changed ^= val;
4049     if (changed & (3 << 22)) {
4050         i = (val >> 22) & 3;
4051         switch (i) {
4052         case FPROUNDING_TIEEVEN:
4053             i = float_round_nearest_even;
4054             break;
4055         case FPROUNDING_POSINF:
4056             i = float_round_up;
4057             break;
4058         case FPROUNDING_NEGINF:
4059             i = float_round_down;
4060             break;
4061         case FPROUNDING_ZERO:
4062             i = float_round_to_zero;
4063             break;
4064         }
4065         set_float_rounding_mode(i, &env->vfp.fp_status);
4066     }
4067     if (changed & (1 << 24)) {
4068         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4069         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4070     }
4071     if (changed & (1 << 25))
4072         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4073
4074     i = vfp_exceptbits_to_host(val);
4075     set_float_exception_flags(i, &env->vfp.fp_status);
4076     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4077 }
4078
4079 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4080 {
4081     HELPER(vfp_set_fpscr)(env, val);
4082 }
4083
4084 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4085
4086 #define VFP_BINOP(name) \
4087 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4088 { \
4089     float_status *fpst = fpstp; \
4090     return float32_ ## name(a, b, fpst); \
4091 } \
4092 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4093 { \
4094     float_status *fpst = fpstp; \
4095     return float64_ ## name(a, b, fpst); \
4096 }
4097 VFP_BINOP(add)
4098 VFP_BINOP(sub)
4099 VFP_BINOP(mul)
4100 VFP_BINOP(div)
4101 VFP_BINOP(min)
4102 VFP_BINOP(max)
4103 VFP_BINOP(minnum)
4104 VFP_BINOP(maxnum)
4105 #undef VFP_BINOP
4106
4107 float32 VFP_HELPER(neg, s)(float32 a)
4108 {
4109     return float32_chs(a);
4110 }
4111
4112 float64 VFP_HELPER(neg, d)(float64 a)
4113 {
4114     return float64_chs(a);
4115 }
4116
4117 float32 VFP_HELPER(abs, s)(float32 a)
4118 {
4119     return float32_abs(a);
4120 }
4121
4122 float64 VFP_HELPER(abs, d)(float64 a)
4123 {
4124     return float64_abs(a);
4125 }
4126
4127 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4128 {
4129     return float32_sqrt(a, &env->vfp.fp_status);
4130 }
4131
4132 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4133 {
4134     return float64_sqrt(a, &env->vfp.fp_status);
4135 }
4136
4137 /* XXX: check quiet/signaling case */
4138 #define DO_VFP_cmp(p, type) \
4139 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4140 { \
4141     uint32_t flags; \
4142     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4143     case 0: flags = 0x6; break; \
4144     case -1: flags = 0x8; break; \
4145     case 1: flags = 0x2; break; \
4146     default: case 2: flags = 0x3; break; \
4147     } \
4148     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4149         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4150 } \
4151 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4152 { \
4153     uint32_t flags; \
4154     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4155     case 0: flags = 0x6; break; \
4156     case -1: flags = 0x8; break; \
4157     case 1: flags = 0x2; break; \
4158     default: case 2: flags = 0x3; break; \
4159     } \
4160     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4161         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4162 }
4163 DO_VFP_cmp(s, float32)
4164 DO_VFP_cmp(d, float64)
4165 #undef DO_VFP_cmp
4166
4167 /* Integer to float and float to integer conversions */
4168
4169 #define CONV_ITOF(name, fsz, sign) \
4170     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4171 { \
4172     float_status *fpst = fpstp; \
4173     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4174 }
4175
4176 #define CONV_FTOI(name, fsz, sign, round) \
4177 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4178 { \
4179     float_status *fpst = fpstp; \
4180     if (float##fsz##_is_any_nan(x)) { \
4181         float_raise(float_flag_invalid, fpst); \
4182         return 0; \
4183     } \
4184     return float##fsz##_to_##sign##int32##round(x, fpst); \
4185 }
4186
4187 #define FLOAT_CONVS(name, p, fsz, sign) \
4188 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4189 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4190 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4191
4192 FLOAT_CONVS(si, s, 32, )
4193 FLOAT_CONVS(si, d, 64, )
4194 FLOAT_CONVS(ui, s, 32, u)
4195 FLOAT_CONVS(ui, d, 64, u)
4196
4197 #undef CONV_ITOF
4198 #undef CONV_FTOI
4199 #undef FLOAT_CONVS
4200
4201 /* floating point conversion */
4202 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4203 {
4204     float64 r = float32_to_float64(x, &env->vfp.fp_status);
4205     /* ARM requires that S<->D conversion of any kind of NaN generates
4206      * a quiet NaN by forcing the most significant frac bit to 1.
4207      */
4208     return float64_maybe_silence_nan(r);
4209 }
4210
4211 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4212 {
4213     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
4214     /* ARM requires that S<->D conversion of any kind of NaN generates
4215      * a quiet NaN by forcing the most significant frac bit to 1.
4216      */
4217     return float32_maybe_silence_nan(r);
4218 }
4219
4220 /* VFP3 fixed point conversion.  */
4221 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4222 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
4223                                      void *fpstp) \
4224 { \
4225     float_status *fpst = fpstp; \
4226     float##fsz tmp; \
4227     tmp = itype##_to_##float##fsz(x, fpst); \
4228     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4229 }
4230
4231 /* Notice that we want only input-denormal exception flags from the
4232  * scalbn operation: the other possible flags (overflow+inexact if
4233  * we overflow to infinity, output-denormal) aren't correct for the
4234  * complete scale-and-convert operation.
4235  */
4236 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4237 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4238                                              uint32_t shift, \
4239                                              void *fpstp) \
4240 { \
4241     float_status *fpst = fpstp; \
4242     int old_exc_flags = get_float_exception_flags(fpst); \
4243     float##fsz tmp; \
4244     if (float##fsz##_is_any_nan(x)) { \
4245         float_raise(float_flag_invalid, fpst); \
4246         return 0; \
4247     } \
4248     tmp = float##fsz##_scalbn(x, shift, fpst); \
4249     old_exc_flags |= get_float_exception_flags(fpst) \
4250         & float_flag_input_denormal; \
4251     set_float_exception_flags(old_exc_flags, fpst); \
4252     return float##fsz##_to_##itype##round(tmp, fpst); \
4253 }
4254
4255 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
4256 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4257 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4258 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4259
4260 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
4261 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4262 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4263
4264 VFP_CONV_FIX(sh, d, 64, 64, int16)
4265 VFP_CONV_FIX(sl, d, 64, 64, int32)
4266 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4267 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4268 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4269 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4270 VFP_CONV_FIX(sh, s, 32, 32, int16)
4271 VFP_CONV_FIX(sl, s, 32, 32, int32)
4272 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4273 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4274 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4275 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4276 #undef VFP_CONV_FIX
4277 #undef VFP_CONV_FIX_FLOAT
4278 #undef VFP_CONV_FLOAT_FIX_ROUND
4279
4280 /* Set the current fp rounding mode and return the old one.
4281  * The argument is a softfloat float_round_ value.
4282  */
4283 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4284 {
4285     float_status *fp_status = &env->vfp.fp_status;
4286
4287     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4288     set_float_rounding_mode(rmode, fp_status);
4289
4290     return prev_rmode;
4291 }
4292
4293 /* Set the current fp rounding mode in the standard fp status and return
4294  * the old one. This is for NEON instructions that need to change the
4295  * rounding mode but wish to use the standard FPSCR values for everything
4296  * else. Always set the rounding mode back to the correct value after
4297  * modifying it.
4298  * The argument is a softfloat float_round_ value.
4299  */
4300 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4301 {
4302     float_status *fp_status = &env->vfp.standard_fp_status;
4303
4304     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4305     set_float_rounding_mode(rmode, fp_status);
4306
4307     return prev_rmode;
4308 }
4309
4310 /* Half precision conversions.  */
4311 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4312 {
4313     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4314     float32 r = float16_to_float32(make_float16(a), ieee, s);
4315     if (ieee) {
4316         return float32_maybe_silence_nan(r);
4317     }
4318     return r;
4319 }
4320
4321 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4322 {
4323     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4324     float16 r = float32_to_float16(a, ieee, s);
4325     if (ieee) {
4326         r = float16_maybe_silence_nan(r);
4327     }
4328     return float16_val(r);
4329 }
4330
4331 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4332 {
4333     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4334 }
4335
4336 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4337 {
4338     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4339 }
4340
4341 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4342 {
4343     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4344 }
4345
4346 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4347 {
4348     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4349 }
4350
4351 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4352 {
4353     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4354     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4355     if (ieee) {
4356         return float64_maybe_silence_nan(r);
4357     }
4358     return r;
4359 }
4360
4361 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4362 {
4363     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4364     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4365     if (ieee) {
4366         r = float16_maybe_silence_nan(r);
4367     }
4368     return float16_val(r);
4369 }
4370
4371 #define float32_two make_float32(0x40000000)
4372 #define float32_three make_float32(0x40400000)
4373 #define float32_one_point_five make_float32(0x3fc00000)
4374
4375 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4376 {
4377     float_status *s = &env->vfp.standard_fp_status;
4378     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4379         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4380         if (!(float32_is_zero(a) || float32_is_zero(b))) {
4381             float_raise(float_flag_input_denormal, s);
4382         }
4383         return float32_two;
4384     }
4385     return float32_sub(float32_two, float32_mul(a, b, s), s);
4386 }
4387
4388 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4389 {
4390     float_status *s = &env->vfp.standard_fp_status;
4391     float32 product;
4392     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4393         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4394         if (!(float32_is_zero(a) || float32_is_zero(b))) {
4395             float_raise(float_flag_input_denormal, s);
4396         }
4397         return float32_one_point_five;
4398     }
4399     product = float32_mul(a, b, s);
4400     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4401 }
4402
4403 /* NEON helpers.  */
4404
4405 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4406  * int->float conversions at run-time.  */
4407 #define float64_256 make_float64(0x4070000000000000LL)
4408 #define float64_512 make_float64(0x4080000000000000LL)
4409
4410 /* The algorithm that must be used to calculate the estimate
4411  * is specified by the ARM ARM.
4412  */
4413 static float64 recip_estimate(float64 a, CPUARMState *env)
4414 {
4415     /* These calculations mustn't set any fp exception flags,
4416      * so we use a local copy of the fp_status.
4417      */
4418     float_status dummy_status = env->vfp.standard_fp_status;
4419     float_status *s = &dummy_status;
4420     /* q = (int)(a * 512.0) */
4421     float64 q = float64_mul(float64_512, a, s);
4422     int64_t q_int = float64_to_int64_round_to_zero(q, s);
4423
4424     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4425     q = int64_to_float64(q_int, s);
4426     q = float64_add(q, float64_half, s);
4427     q = float64_div(q, float64_512, s);
4428     q = float64_div(float64_one, q, s);
4429
4430     /* s = (int)(256.0 * r + 0.5) */
4431     q = float64_mul(q, float64_256, s);
4432     q = float64_add(q, float64_half, s);
4433     q_int = float64_to_int64_round_to_zero(q, s);
4434
4435     /* return (double)s / 256.0 */
4436     return float64_div(int64_to_float64(q_int, s), float64_256, s);
4437 }
4438
4439 float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4440 {
4441     float_status *s = &env->vfp.standard_fp_status;
4442     float64 f64;
4443     uint32_t val32 = float32_val(a);
4444
4445     int result_exp;
4446     int a_exp = (val32  & 0x7f800000) >> 23;
4447     int sign = val32 & 0x80000000;
4448
4449     if (float32_is_any_nan(a)) {
4450         if (float32_is_signaling_nan(a)) {
4451             float_raise(float_flag_invalid, s);
4452         }
4453         return float32_default_nan;
4454     } else if (float32_is_infinity(a)) {
4455         return float32_set_sign(float32_zero, float32_is_neg(a));
4456     } else if (float32_is_zero_or_denormal(a)) {
4457         if (!float32_is_zero(a)) {
4458             float_raise(float_flag_input_denormal, s);
4459         }
4460         float_raise(float_flag_divbyzero, s);
4461         return float32_set_sign(float32_infinity, float32_is_neg(a));
4462     } else if (a_exp >= 253) {
4463         float_raise(float_flag_underflow, s);
4464         return float32_set_sign(float32_zero, float32_is_neg(a));
4465     }
4466
4467     f64 = make_float64((0x3feULL << 52)
4468                        | ((int64_t)(val32 & 0x7fffff) << 29));
4469
4470     result_exp = 253 - a_exp;
4471
4472     f64 = recip_estimate(f64, env);
4473
4474     val32 = sign
4475         | ((result_exp & 0xff) << 23)
4476         | ((float64_val(f64) >> 29) & 0x7fffff);
4477     return make_float32(val32);
4478 }
4479
4480 /* The algorithm that must be used to calculate the estimate
4481  * is specified by the ARM ARM.
4482  */
4483 static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
4484 {
4485     /* These calculations mustn't set any fp exception flags,
4486      * so we use a local copy of the fp_status.
4487      */
4488     float_status dummy_status = env->vfp.standard_fp_status;
4489     float_status *s = &dummy_status;
4490     float64 q;
4491     int64_t q_int;
4492
4493     if (float64_lt(a, float64_half, s)) {
4494         /* range 0.25 <= a < 0.5 */
4495
4496         /* a in units of 1/512 rounded down */
4497         /* q0 = (int)(a * 512.0);  */
4498         q = float64_mul(float64_512, a, s);
4499         q_int = float64_to_int64_round_to_zero(q, s);
4500
4501         /* reciprocal root r */
4502         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
4503         q = int64_to_float64(q_int, s);
4504         q = float64_add(q, float64_half, s);
4505         q = float64_div(q, float64_512, s);
4506         q = float64_sqrt(q, s);
4507         q = float64_div(float64_one, q, s);
4508     } else {
4509         /* range 0.5 <= a < 1.0 */
4510
4511         /* a in units of 1/256 rounded down */
4512         /* q1 = (int)(a * 256.0); */
4513         q = float64_mul(float64_256, a, s);
4514         int64_t q_int = float64_to_int64_round_to_zero(q, s);
4515
4516         /* reciprocal root r */
4517         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4518         q = int64_to_float64(q_int, s);
4519         q = float64_add(q, float64_half, s);
4520         q = float64_div(q, float64_256, s);
4521         q = float64_sqrt(q, s);
4522         q = float64_div(float64_one, q, s);
4523     }
4524     /* r in units of 1/256 rounded to nearest */
4525     /* s = (int)(256.0 * r + 0.5); */
4526
4527     q = float64_mul(q, float64_256,s );
4528     q = float64_add(q, float64_half, s);
4529     q_int = float64_to_int64_round_to_zero(q, s);
4530
4531     /* return (double)s / 256.0;*/
4532     return float64_div(int64_to_float64(q_int, s), float64_256, s);
4533 }
4534
4535 float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4536 {
4537     float_status *s = &env->vfp.standard_fp_status;
4538     int result_exp;
4539     float64 f64;
4540     uint32_t val;
4541     uint64_t val64;
4542
4543     val = float32_val(a);
4544
4545     if (float32_is_any_nan(a)) {
4546         if (float32_is_signaling_nan(a)) {
4547             float_raise(float_flag_invalid, s);
4548         }
4549         return float32_default_nan;
4550     } else if (float32_is_zero_or_denormal(a)) {
4551         if (!float32_is_zero(a)) {
4552             float_raise(float_flag_input_denormal, s);
4553         }
4554         float_raise(float_flag_divbyzero, s);
4555         return float32_set_sign(float32_infinity, float32_is_neg(a));
4556     } else if (float32_is_neg(a)) {
4557         float_raise(float_flag_invalid, s);
4558         return float32_default_nan;
4559     } else if (float32_is_infinity(a)) {
4560         return float32_zero;
4561     }
4562
4563     /* Normalize to a double-precision value between 0.25 and 1.0,
4564      * preserving the parity of the exponent.  */
4565     if ((val & 0x800000) == 0) {
4566         f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4567                            | (0x3feULL << 52)
4568                            | ((uint64_t)(val & 0x7fffff) << 29));
4569     } else {
4570         f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4571                            | (0x3fdULL << 52)
4572                            | ((uint64_t)(val & 0x7fffff) << 29));
4573     }
4574
4575     result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
4576
4577     f64 = recip_sqrt_estimate(f64, env);
4578
4579     val64 = float64_val(f64);
4580
4581     val = ((result_exp & 0xff) << 23)
4582         | ((val64 >> 29)  & 0x7fffff);
4583     return make_float32(val);
4584 }
4585
4586 uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4587 {
4588     float64 f64;
4589
4590     if ((a & 0x80000000) == 0) {
4591         return 0xffffffff;
4592     }
4593
4594     f64 = make_float64((0x3feULL << 52)
4595                        | ((int64_t)(a & 0x7fffffff) << 21));
4596
4597     f64 = recip_estimate (f64, env);
4598
4599     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4600 }
4601
4602 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4603 {
4604     float64 f64;
4605
4606     if ((a & 0xc0000000) == 0) {
4607         return 0xffffffff;
4608     }
4609
4610     if (a & 0x80000000) {
4611         f64 = make_float64((0x3feULL << 52)
4612                            | ((uint64_t)(a & 0x7fffffff) << 21));
4613     } else { /* bits 31-30 == '01' */
4614         f64 = make_float64((0x3fdULL << 52)
4615                            | ((uint64_t)(a & 0x3fffffff) << 22));
4616     }
4617
4618     f64 = recip_sqrt_estimate(f64, env);
4619
4620     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4621 }
4622
4623 /* VFPv4 fused multiply-accumulate */
4624 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4625 {
4626     float_status *fpst = fpstp;
4627     return float32_muladd(a, b, c, 0, fpst);
4628 }
4629
4630 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4631 {
4632     float_status *fpst = fpstp;
4633     return float64_muladd(a, b, c, 0, fpst);
4634 }
4635
4636 /* ARMv8 round to integral */
4637 float32 HELPER(rints_exact)(float32 x, void *fp_status)
4638 {
4639     return float32_round_to_int(x, fp_status);
4640 }
4641
4642 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
4643 {
4644     return float64_round_to_int(x, fp_status);
4645 }
4646
4647 float32 HELPER(rints)(float32 x, void *fp_status)
4648 {
4649     int old_flags = get_float_exception_flags(fp_status), new_flags;
4650     float32 ret;
4651
4652     ret = float32_round_to_int(x, fp_status);
4653
4654     /* Suppress any inexact exceptions the conversion produced */
4655     if (!(old_flags & float_flag_inexact)) {
4656         new_flags = get_float_exception_flags(fp_status);
4657         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4658     }
4659
4660     return ret;
4661 }
4662
4663 float64 HELPER(rintd)(float64 x, void *fp_status)
4664 {
4665     int old_flags = get_float_exception_flags(fp_status), new_flags;
4666     float64 ret;
4667
4668     ret = float64_round_to_int(x, fp_status);
4669
4670     new_flags = get_float_exception_flags(fp_status);
4671
4672     /* Suppress any inexact exceptions the conversion produced */
4673     if (!(old_flags & float_flag_inexact)) {
4674         new_flags = get_float_exception_flags(fp_status);
4675         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4676     }
4677
4678     return ret;
4679 }
4680
4681 /* Convert ARM rounding mode to softfloat */
4682 int arm_rmode_to_sf(int rmode)
4683 {
4684     switch (rmode) {
4685     case FPROUNDING_TIEAWAY:
4686         rmode = float_round_ties_away;
4687         break;
4688     case FPROUNDING_ODD:
4689         /* FIXME: add support for TIEAWAY and ODD */
4690         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
4691                       rmode);
4692     case FPROUNDING_TIEEVEN:
4693     default:
4694         rmode = float_round_nearest_even;
4695         break;
4696     case FPROUNDING_POSINF:
4697         rmode = float_round_up;
4698         break;
4699     case FPROUNDING_NEGINF:
4700         rmode = float_round_down;
4701         break;
4702     case FPROUNDING_ZERO:
4703         rmode = float_round_to_zero;
4704         break;
4705     }
4706     return rmode;
4707 }
4708
4709 static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
4710 {
4711     memset(buf, 0, 4);
4712
4713     if (bytes == 1) {
4714         buf[0] = val & 0xff;
4715     } else if (bytes == 2) {
4716         buf[0] = val & 0xff;
4717         buf[1] = (val >> 8) & 0xff;
4718     } else {
4719         buf[0] = val & 0xff;
4720         buf[1] = (val >> 8) & 0xff;
4721         buf[2] = (val >> 16) & 0xff;
4722         buf[3] = (val >> 24) & 0xff;
4723     }
4724 }
4725
4726 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
4727 {
4728     uint8_t buf[4];
4729
4730     crc_init_buffer(buf, val, bytes);
4731
4732     /* zlib crc32 converts the accumulator and output to one's complement.  */
4733     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
4734 }
4735
4736 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
4737 {
4738     uint8_t buf[4];
4739
4740     crc_init_buffer(buf, val, bytes);
4741
4742     /* Linux crc32c converts the output to one's complement.  */
4743     return crc32c(acc, buf, bytes) ^ 0xffffffff;
4744 }