target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <assert.h>
  23
  24 #include "config.h"
  25 #include "cpu.h"
  26 #include "exec-all.h"
  27 #include "host-utils.h"
  28
  29 int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
  30                                int mmu_idx, int is_softmmu)
  31 {
  32     int prot;
  33
  34     address &= TARGET_PAGE_MASK;
  35     prot = PAGE_BITS;
  36     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  37         tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
  38                 TARGET_PAGE_SIZE);
  39     } else {
  40         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  41     }
  42
  43     return 0;
  44 }
  45
  46 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
  47 {
  48     return addr & TARGET_PAGE_MASK;
  49 }
  50
  51 void do_interrupt(CPUState *env)
  52 {
  53     qemu_log_mask(CPU_LOG_INT,
  54             "exception at pc=%x type=%x\n", env->pc, env->exception_index);
  55
  56     switch (env->exception_index) {
  57     case EXCP_INSN_BUS_ERROR:
  58     case EXCP_DATA_BUS_ERROR:
  59     case EXCP_DIVIDE_BY_ZERO:
  60     case EXCP_IRQ:
  61     case EXCP_SYSTEMCALL:
  62         /* non-debug exceptions */
  63         env->regs[R_EA] = env->pc;
  64         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
  65         env->ie &= ~IE_IE;
  66         if (env->dc & DC_RE) {
  67             env->pc = env->deba + (env->exception_index * 32);
  68         } else {
  69             env->pc = env->eba + (env->exception_index * 32);
  70         }
  71         log_cpu_state_mask(CPU_LOG_INT, env, 0);
  72         break;
  73     case EXCP_BREAKPOINT:
  74     case EXCP_WATCHPOINT:
  75         /* debug exceptions */
  76         env->regs[R_BA] = env->pc;
  77         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
  78         env->ie &= ~IE_IE;
  79         env->pc = env->deba + (env->exception_index * 32);
  80         log_cpu_state_mask(CPU_LOG_INT, env, 0);
  81         break;
  82     default:
  83         cpu_abort(env, "unhandled exception type=%d\n",
  84                   env->exception_index);
  85         break;
  86     }
  87 }
  88
  89 typedef struct {
  90     const char *name;
  91     uint32_t revision;
  92     uint8_t num_interrupts;
  93     uint8_t num_breakpoints;
  94     uint8_t num_watchpoints;
  95     uint32_t features;
  96 } LM32Def;
  97
  98 static const LM32Def lm32_defs[] = {
  99     {
 100         .name = "lm32-basic",
 101         .revision = 3,
 102         .num_interrupts = 32,
 103         .num_breakpoints = 4,
 104         .num_watchpoints = 4,
 105         .features = (LM32_FEATURE_SHIFT
 106                      | LM32_FEATURE_SIGN_EXTEND
 107                      | LM32_FEATURE_CYCLE_COUNT),
 108     },
 109     {
 110         .name = "lm32-standard",
 111         .revision = 3,
 112         .num_interrupts = 32,
 113         .num_breakpoints = 4,
 114         .num_watchpoints = 4,
 115         .features = (LM32_FEATURE_MULTIPLY
 116                      | LM32_FEATURE_DIVIDE
 117                      | LM32_FEATURE_SHIFT
 118                      | LM32_FEATURE_SIGN_EXTEND
 119                      | LM32_FEATURE_I_CACHE
 120                      | LM32_FEATURE_CYCLE_COUNT),
 121     },
 122     {
 123         .name = "lm32-full",
 124         .revision = 3,
 125         .num_interrupts = 32,
 126         .num_breakpoints = 4,
 127         .num_watchpoints = 4,
 128         .features = (LM32_FEATURE_MULTIPLY
 129                      | LM32_FEATURE_DIVIDE
 130                      | LM32_FEATURE_SHIFT
 131                      | LM32_FEATURE_SIGN_EXTEND
 132                      | LM32_FEATURE_I_CACHE
 133                      | LM32_FEATURE_D_CACHE
 134                      | LM32_FEATURE_CYCLE_COUNT),
 135     }
 136 };
 137
 138 void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
 139 {
 140     int i;
 141
 142     cpu_fprintf(f, "Available CPUs:\n");
 143     for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
 144         cpu_fprintf(f, "  %s\n", lm32_defs[i].name);
 145     }
 146 }
 147
 148 static const LM32Def *cpu_lm32_find_by_name(const char *name)
 149 {
 150     int i;
 151
 152     for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
 153         if (strcasecmp(name, lm32_defs[i].name) == 0) {
 154             return &lm32_defs[i];
 155         }
 156     }
 157
 158     return NULL;
 159 }
 160
 161 static uint32_t cfg_by_def(const LM32Def *def)
 162 {
 163     uint32_t cfg = 0;
 164
 165     if (def->features & LM32_FEATURE_MULTIPLY) {
 166         cfg |= CFG_M;
 167     }
 168
 169     if (def->features & LM32_FEATURE_DIVIDE) {
 170         cfg |= CFG_D;
 171     }
 172
 173     if (def->features & LM32_FEATURE_SHIFT) {
 174         cfg |= CFG_S;
 175     }
 176
 177     if (def->features & LM32_FEATURE_SIGN_EXTEND) {
 178         cfg |= CFG_X;
 179     }
 180
 181     if (def->features & LM32_FEATURE_I_CACHE) {
 182         cfg |= CFG_IC;
 183     }
 184
 185     if (def->features & LM32_FEATURE_D_CACHE) {
 186         cfg |= CFG_DC;
 187     }
 188
 189     if (def->features & LM32_FEATURE_CYCLE_COUNT) {
 190         cfg |= CFG_CC;
 191     }
 192
 193     cfg |= (def->num_interrupts << CFG_INT_SHIFT);
 194     cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
 195     cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
 196     cfg |= (def->revision << CFG_REV_SHIFT);
 197
 198     return cfg;
 199 }
 200
 201 CPUState *cpu_lm32_init(const char *cpu_model)
 202 {
 203     CPUState *env;
 204     const LM32Def *def;
 205     static int tcg_initialized;
 206
 207     def = cpu_lm32_find_by_name(cpu_model);
 208     if (!def) {
 209         return NULL;
 210     }
 211
 212     env = qemu_mallocz(sizeof(CPUState));
 213
 214     env->features = def->features;
 215     env->num_bps = def->num_breakpoints;
 216     env->num_wps = def->num_watchpoints;
 217     env->cfg = cfg_by_def(def);
 218     env->flags = 0;
 219
 220     cpu_exec_init(env);
 221     cpu_reset(env);
 222
 223     if (!tcg_initialized) {
 224         tcg_initialized = 1;
 225         lm32_translate_init();
 226     }
 227
 228     return env;
 229 }
 230
 231 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 232  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 233  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 234 void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
 235 {
 236     if (value) {
 237         env->flags |= LM32_FLAG_IGNORE_MSB;
 238     } else {
 239         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 240     }
 241 }
 242
 243 void cpu_reset(CPUState *env)
 244 {
 245     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 246         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
 247         log_cpu_state(env, 0);
 248     }
 249
 250     tlb_flush(env, 1);
 251
 252     /* reset cpu state */
 253     memset(env, 0, offsetof(CPULM32State, breakpoints));
 254 }
 255