target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "internals.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #define SIGNBIT (uint32_t)0x80000000
  26 #define SIGNBIT64 ((uint64_t)1 << 63)
  27
  28 static void raise_exception(CPUARMState *env, uint32_t excp,
  29                             uint32_t syndrome, uint32_t target_el)
  30 {
  31     CPUState *cs = CPU(arm_env_get_cpu(env));
  32
  33     assert(!excp_is_internal(excp));
  34     cs->exception_index = excp;
  35     env->exception.syndrome = syndrome;
  36     env->exception.target_el = target_el;
  37     cpu_loop_exit(cs);
  38 }
  39
  40 static int exception_target_el(CPUARMState *env)
  41 {
  42     int target_el = MAX(1, arm_current_el(env));
  43
  44     /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
  45      * to EL3 in this case.
  46      */
  47     if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
  48         target_el = 3;
  49     }
  50
  51     return target_el;
  52 }
  53
  54 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  55                           uint32_t rn, uint32_t maxindex)
  56 {
  57     uint32_t val;
  58     uint32_t tmp;
  59     int index;
  60     int shift;
  61     uint64_t *table;
  62     table = (uint64_t *)&env->vfp.regs[rn];
  63     val = 0;
  64     for (shift = 0; shift < 32; shift += 8) {
  65         index = (ireg >> shift) & 0xff;
  66         if (index < maxindex) {
  67             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  68             val |= tmp << shift;
  69         } else {
  70             val |= def & (0xff << shift);
  71         }
  72     }
  73     return val;
  74 }
  75
  76 #if !defined(CONFIG_USER_ONLY)
  77
  78 /* try to fill the TLB and return an exception if error. If retaddr is
  79  * NULL, it means that the function was called in C code (i.e. not
  80  * from generated code or from helper.c)
  81  */
  82 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  83               uintptr_t retaddr)
  84 {
  85     bool ret;
  86     uint32_t fsr = 0;
  87     ARMMMUFaultInfo fi = {};
  88
  89     ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr, &fi);
  90     if (unlikely(ret)) {
  91         ARMCPU *cpu = ARM_CPU(cs);
  92         CPUARMState *env = &cpu->env;
  93         uint32_t syn, exc;
  94         unsigned int target_el;
  95         bool same_el;
  96
  97         if (retaddr) {
  98             /* now we have a real cpu fault */
  99             cpu_restore_state(cs, retaddr);
 100         }
 101
 102         target_el = exception_target_el(env);
 103         if (fi.stage2) {
 104             target_el = 2;
 105             env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
 106         }
 107         same_el = arm_current_el(env) == target_el;
 108         /* AArch64 syndrome does not have an LPAE bit */
 109         syn = fsr & ~(1 << 9);
 110
 111         /* For insn and data aborts we assume there is no instruction syndrome
 112          * information; this is always true for exceptions reported to EL1.
 113          */
 114         if (is_write == 2) {
 115             syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
 116             exc = EXCP_PREFETCH_ABORT;
 117         } else {
 118             syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn);
 119             if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
 120                 fsr |= (1 << 11);
 121             }
 122             exc = EXCP_DATA_ABORT;
 123         }
 124
 125         env->exception.vaddress = addr;
 126         env->exception.fsr = fsr;
 127         raise_exception(env, exc, syn, target_el);
 128     }
 129 }
 130
 131 /* Raise a data fault alignment exception for the specified virtual address */
 132 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
 133                                  int is_user, uintptr_t retaddr)
 134 {
 135     ARMCPU *cpu = ARM_CPU(cs);
 136     CPUARMState *env = &cpu->env;
 137     int target_el;
 138     bool same_el;
 139
 140     if (retaddr) {
 141         /* now we have a real cpu fault */
 142         cpu_restore_state(cs, retaddr);
 143     }
 144
 145     target_el = exception_target_el(env);
 146     same_el = (arm_current_el(env) == target_el);
 147
 148     env->exception.vaddress = vaddr;
 149
 150     /* the DFSR for an alignment fault depends on whether we're using
 151      * the LPAE long descriptor format, or the short descriptor format
 152      */
 153     if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
 154         env->exception.fsr = 0x21;
 155     } else {
 156         env->exception.fsr = 0x1;
 157     }
 158
 159     if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
 160         env->exception.fsr |= (1 << 11);
 161     }
 162
 163     raise_exception(env, EXCP_DATA_ABORT,
 164                     syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21),
 165                     target_el);
 166 }
 167
 168 #endif /* !defined(CONFIG_USER_ONLY) */
 169
 170 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
 171 {
 172     uint32_t res = a + b;
 173     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
 174         env->QF = 1;
 175     return res;
 176 }
 177
 178 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 179 {
 180     uint32_t res = a + b;
 181     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
 182         env->QF = 1;
 183         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 184     }
 185     return res;
 186 }
 187
 188 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 189 {
 190     uint32_t res = a - b;
 191     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 192         env->QF = 1;
 193         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 194     }
 195     return res;
 196 }
 197
 198 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 199 {
 200     uint32_t res;
 201     if (val >= 0x40000000) {
 202         res = ~SIGNBIT;
 203         env->QF = 1;
 204     } else if (val <= (int32_t)0xc0000000) {
 205         res = SIGNBIT;
 206         env->QF = 1;
 207     } else {
 208         res = val << 1;
 209     }
 210     return res;
 211 }
 212
 213 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 214 {
 215     uint32_t res = a + b;
 216     if (res < a) {
 217         env->QF = 1;
 218         res = ~0;
 219     }
 220     return res;
 221 }
 222
 223 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 224 {
 225     uint32_t res = a - b;
 226     if (res > a) {
 227         env->QF = 1;
 228         res = 0;
 229     }
 230     return res;
 231 }
 232
 233 /* Signed saturation.  */
 234 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 235 {
 236     int32_t top;
 237     uint32_t mask;
 238
 239     top = val >> shift;
 240     mask = (1u << shift) - 1;
 241     if (top > 0) {
 242         env->QF = 1;
 243         return mask;
 244     } else if (top < -1) {
 245         env->QF = 1;
 246         return ~mask;
 247     }
 248     return val;
 249 }
 250
 251 /* Unsigned saturation.  */
 252 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 253 {
 254     uint32_t max;
 255
 256     max = (1u << shift) - 1;
 257     if (val < 0) {
 258         env->QF = 1;
 259         return 0;
 260     } else if (val > max) {
 261         env->QF = 1;
 262         return max;
 263     }
 264     return val;
 265 }
 266
 267 /* Signed saturate.  */
 268 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 269 {
 270     return do_ssat(env, x, shift);
 271 }
 272
 273 /* Dual halfword signed saturate.  */
 274 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 275 {
 276     uint32_t res;
 277
 278     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 279     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 280     return res;
 281 }
 282
 283 /* Unsigned saturate.  */
 284 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 285 {
 286     return do_usat(env, x, shift);
 287 }
 288
 289 /* Dual halfword unsigned saturate.  */
 290 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 291 {
 292     uint32_t res;
 293
 294     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 295     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 296     return res;
 297 }
 298
 299 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
 300  * The function returns the target EL (1-3) if the instruction is to be trapped;
 301  * otherwise it returns 0 indicating it is not trapped.
 302  */
 303 static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
 304 {
 305     int cur_el = arm_current_el(env);
 306     uint64_t mask;
 307
 308     /* If we are currently in EL0 then we need to check if SCTLR is set up for
 309      * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
 310      */
 311     if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) {
 312         int target_el;
 313
 314         mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI;
 315         if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) {
 316             /* Secure EL0 and Secure PL1 is at EL3 */
 317             target_el = 3;
 318         } else {
 319             target_el = 1;
 320         }
 321
 322         if (!(env->cp15.sctlr_el[target_el] & mask)) {
 323             return target_el;
 324         }
 325     }
 326
 327     /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
 328      * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
 329      * bits will be zero indicating no trap.
 330      */
 331     if (cur_el < 2 && !arm_is_secure(env)) {
 332         mask = (is_wfe) ? HCR_TWE : HCR_TWI;
 333         if (env->cp15.hcr_el2 & mask) {
 334             return 2;
 335         }
 336     }
 337
 338     /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
 339     if (cur_el < 3) {
 340         mask = (is_wfe) ? SCR_TWE : SCR_TWI;
 341         if (env->cp15.scr_el3 & mask) {
 342             return 3;
 343         }
 344     }
 345
 346     return 0;
 347 }
 348
 349 void HELPER(wfi)(CPUARMState *env)
 350 {
 351     CPUState *cs = CPU(arm_env_get_cpu(env));
 352     int target_el = check_wfx_trap(env, false);
 353
 354     if (cpu_has_work(cs)) {
 355         /* Don't bother to go into our "low power state" if
 356          * we would just wake up immediately.
 357          */
 358         return;
 359     }
 360
 361     if (target_el) {
 362         env->pc -= 4;
 363         raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el);
 364     }
 365
 366     cs->exception_index = EXCP_HLT;
 367     cs->halted = 1;
 368     cpu_loop_exit(cs);
 369 }
 370
 371 void HELPER(wfe)(CPUARMState *env)
 372 {
 373     /* This is a hint instruction that is semantically different
 374      * from YIELD even though we currently implement it identically.
 375      * Don't actually halt the CPU, just yield back to top
 376      * level loop. This is not going into a "low power state"
 377      * (ie halting until some event occurs), so we never take
 378      * a configurable trap to a different exception level.
 379      */
 380     HELPER(yield)(env);
 381 }
 382
 383 void HELPER(yield)(CPUARMState *env)
 384 {
 385     ARMCPU *cpu = arm_env_get_cpu(env);
 386     CPUState *cs = CPU(cpu);
 387
 388     /* This is a non-trappable hint instruction that generally indicates
 389      * that the guest is currently busy-looping. Yield control back to the
 390      * top level loop so that a more deserving VCPU has a chance to run.
 391      */
 392     cs->exception_index = EXCP_YIELD;
 393     cpu_loop_exit(cs);
 394 }
 395
 396 /* Raise an internal-to-QEMU exception. This is limited to only
 397  * those EXCP values which are special cases for QEMU to interrupt
 398  * execution and not to be used for exceptions which are passed to
 399  * the guest (those must all have syndrome information and thus should
 400  * use exception_with_syndrome).
 401  */
 402 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 403 {
 404     CPUState *cs = CPU(arm_env_get_cpu(env));
 405
 406     assert(excp_is_internal(excp));
 407     cs->exception_index = excp;
 408     cpu_loop_exit(cs);
 409 }
 410
 411 /* Raise an exception with the specified syndrome register value */
 412 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
 413                                      uint32_t syndrome, uint32_t target_el)
 414 {
 415     raise_exception(env, excp, syndrome, target_el);
 416 }
 417
 418 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 419 {
 420     return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
 421 }
 422
 423 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 424 {
 425     cpsr_write(env, val, mask);
 426 }
 427
 428 /* Access to user mode registers from privileged modes.  */
 429 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 430 {
 431     uint32_t val;
 432
 433     if (regno == 13) {
 434         val = env->banked_r13[BANK_USRSYS];
 435     } else if (regno == 14) {
 436         val = env->banked_r14[BANK_USRSYS];
 437     } else if (regno >= 8
 438                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 439         val = env->usr_regs[regno - 8];
 440     } else {
 441         val = env->regs[regno];
 442     }
 443     return val;
 444 }
 445
 446 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 447 {
 448     if (regno == 13) {
 449         env->banked_r13[BANK_USRSYS] = val;
 450     } else if (regno == 14) {
 451         env->banked_r14[BANK_USRSYS] = val;
 452     } else if (regno >= 8
 453                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 454         env->usr_regs[regno - 8] = val;
 455     } else {
 456         env->regs[regno] = val;
 457     }
 458 }
 459
 460 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
 461 {
 462     if ((env->uncached_cpsr & CPSR_M) == mode) {
 463         env->regs[13] = val;
 464     } else {
 465         env->banked_r13[bank_number(mode)] = val;
 466     }
 467 }
 468
 469 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
 470 {
 471     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) {
 472         /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
 473          * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
 474          */
 475         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 476                         exception_target_el(env));
 477     }
 478
 479     if ((env->uncached_cpsr & CPSR_M) == mode) {
 480         return env->regs[13];
 481     } else {
 482         return env->banked_r13[bank_number(mode)];
 483     }
 484 }
 485
 486 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
 487                                  uint32_t isread)
 488 {
 489     const ARMCPRegInfo *ri = rip;
 490     int target_el;
 491
 492     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
 493         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
 494         raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
 495     }
 496
 497     if (!ri->accessfn) {
 498         return;
 499     }
 500
 501     switch (ri->accessfn(env, ri, isread)) {
 502     case CP_ACCESS_OK:
 503         return;
 504     case CP_ACCESS_TRAP:
 505         target_el = exception_target_el(env);
 506         break;
 507     case CP_ACCESS_TRAP_EL2:
 508         /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
 509          * a bug in the access function.
 510          */
 511         assert(!arm_is_secure(env) && arm_current_el(env) != 3);
 512         target_el = 2;
 513         break;
 514     case CP_ACCESS_TRAP_EL3:
 515         target_el = 3;
 516         break;
 517     case CP_ACCESS_TRAP_UNCATEGORIZED:
 518         target_el = exception_target_el(env);
 519         syndrome = syn_uncategorized();
 520         break;
 521     case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
 522         target_el = 2;
 523         syndrome = syn_uncategorized();
 524         break;
 525     case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
 526         target_el = 3;
 527         syndrome = syn_uncategorized();
 528         break;
 529     case CP_ACCESS_TRAP_FP_EL2:
 530         target_el = 2;
 531         /* Since we are an implementation that takes exceptions on a trapped
 532          * conditional insn only if the insn has passed its condition code
 533          * check, we take the IMPDEF choice to always report CV=1 COND=0xe
 534          * (which is also the required value for AArch64 traps).
 535          */
 536         syndrome = syn_fp_access_trap(1, 0xe, false);
 537         break;
 538     case CP_ACCESS_TRAP_FP_EL3:
 539         target_el = 3;
 540         syndrome = syn_fp_access_trap(1, 0xe, false);
 541         break;
 542     default:
 543         g_assert_not_reached();
 544     }
 545
 546     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 547 }
 548
 549 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 550 {
 551     const ARMCPRegInfo *ri = rip;
 552
 553     ri->writefn(env, ri, value);
 554 }
 555
 556 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 557 {
 558     const ARMCPRegInfo *ri = rip;
 559
 560     return ri->readfn(env, ri);
 561 }
 562
 563 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 564 {
 565     const ARMCPRegInfo *ri = rip;
 566
 567     ri->writefn(env, ri, value);
 568 }
 569
 570 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 571 {
 572     const ARMCPRegInfo *ri = rip;
 573
 574     return ri->readfn(env, ri);
 575 }
 576
 577 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 578 {
 579     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 580      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 581      * to catch that case at translate time.
 582      */
 583     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
 584         uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),
 585                                                 extract32(op, 3, 3), 4,
 586                                                 imm, 0x1f, 0);
 587         raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
 588     }
 589
 590     switch (op) {
 591     case 0x05: /* SPSel */
 592         update_spsel(env, imm);
 593         break;
 594     case 0x1e: /* DAIFSet */
 595         env->daif |= (imm << 6) & PSTATE_DAIF;
 596         break;
 597     case 0x1f: /* DAIFClear */
 598         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 599         break;
 600     default:
 601         g_assert_not_reached();
 602     }
 603 }
 604
 605 void HELPER(clear_pstate_ss)(CPUARMState *env)
 606 {
 607     env->pstate &= ~PSTATE_SS;
 608 }
 609
 610 void HELPER(pre_hvc)(CPUARMState *env)
 611 {
 612     ARMCPU *cpu = arm_env_get_cpu(env);
 613     int cur_el = arm_current_el(env);
 614     /* FIXME: Use actual secure state.  */
 615     bool secure = false;
 616     bool undef;
 617
 618     if (arm_is_psci_call(cpu, EXCP_HVC)) {
 619         /* If PSCI is enabled and this looks like a valid PSCI call then
 620          * that overrides the architecturally mandated HVC behaviour.
 621          */
 622         return;
 623     }
 624
 625     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 626         /* If EL2 doesn't exist, HVC always UNDEFs */
 627         undef = true;
 628     } else if (arm_feature(env, ARM_FEATURE_EL3)) {
 629         /* EL3.HCE has priority over EL2.HCD. */
 630         undef = !(env->cp15.scr_el3 & SCR_HCE);
 631     } else {
 632         undef = env->cp15.hcr_el2 & HCR_HCD;
 633     }
 634
 635     /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
 636      * For ARMv8/AArch64, HVC is allowed in EL3.
 637      * Note that we've already trapped HVC from EL0 at translation
 638      * time.
 639      */
 640     if (secure && (!is_a64(env) || cur_el == 1)) {
 641         undef = true;
 642     }
 643
 644     if (undef) {
 645         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 646                         exception_target_el(env));
 647     }
 648 }
 649
 650 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
 651 {
 652     ARMCPU *cpu = arm_env_get_cpu(env);
 653     int cur_el = arm_current_el(env);
 654     bool secure = arm_is_secure(env);
 655     bool smd = env->cp15.scr_el3 & SCR_SMD;
 656     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
 657      * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
 658      *  extensions, SMD only applies to NS state.
 659      * On ARMv7 without the Virtualization extensions, the SMD bit
 660      * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
 661      * so we need not special case this here.
 662      */
 663     bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
 664
 665     if (arm_is_psci_call(cpu, EXCP_SMC)) {
 666         /* If PSCI is enabled and this looks like a valid PSCI call then
 667          * that overrides the architecturally mandated SMC behaviour.
 668          */
 669         return;
 670     }
 671
 672     if (!arm_feature(env, ARM_FEATURE_EL3)) {
 673         /* If we have no EL3 then SMC always UNDEFs */
 674         undef = true;
 675     } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
 676         /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
 677         raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
 678     }
 679
 680     if (undef) {
 681         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 682                         exception_target_el(env));
 683     }
 684 }
 685
 686 static int el_from_spsr(uint32_t spsr)
 687 {
 688     /* Return the exception level that this SPSR is requesting a return to,
 689      * or -1 if it is invalid (an illegal return)
 690      */
 691     if (spsr & PSTATE_nRW) {
 692         switch (spsr & CPSR_M) {
 693         case ARM_CPU_MODE_USR:
 694             return 0;
 695         case ARM_CPU_MODE_HYP:
 696             return 2;
 697         case ARM_CPU_MODE_FIQ:
 698         case ARM_CPU_MODE_IRQ:
 699         case ARM_CPU_MODE_SVC:
 700         case ARM_CPU_MODE_ABT:
 701         case ARM_CPU_MODE_UND:
 702         case ARM_CPU_MODE_SYS:
 703             return 1;
 704         case ARM_CPU_MODE_MON:
 705             /* Returning to Mon from AArch64 is never possible,
 706              * so this is an illegal return.
 707              */
 708         default:
 709             return -1;
 710         }
 711     } else {
 712         if (extract32(spsr, 1, 1)) {
 713             /* Return with reserved M[1] bit set */
 714             return -1;
 715         }
 716         if (extract32(spsr, 0, 4) == 1) {
 717             /* return to EL0 with M[0] bit set */
 718             return -1;
 719         }
 720         return extract32(spsr, 2, 2);
 721     }
 722 }
 723
 724 void HELPER(exception_return)(CPUARMState *env)
 725 {
 726     int cur_el = arm_current_el(env);
 727     unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
 728     uint32_t spsr = env->banked_spsr[spsr_idx];
 729     int new_el;
 730     bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
 731
 732     aarch64_save_sp(env, cur_el);
 733
 734     env->exclusive_addr = -1;
 735
 736     /* We must squash the PSTATE.SS bit to zero unless both of the
 737      * following hold:
 738      *  1. debug exceptions are currently disabled
 739      *  2. singlestep will be active in the EL we return to
 740      * We check 1 here and 2 after we've done the pstate/cpsr write() to
 741      * transition to the EL we're going to.
 742      */
 743     if (arm_generate_debug_exceptions(env)) {
 744         spsr &= ~PSTATE_SS;
 745     }
 746
 747     new_el = el_from_spsr(spsr);
 748     if (new_el == -1) {
 749         goto illegal_return;
 750     }
 751     if (new_el > cur_el
 752         || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
 753         /* Disallow return to an EL which is unimplemented or higher
 754          * than the current one.
 755          */
 756         goto illegal_return;
 757     }
 758
 759     if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) {
 760         /* Return to an EL which is configured for a different register width */
 761         goto illegal_return;
 762     }
 763
 764     if (new_el == 2 && arm_is_secure_below_el3(env)) {
 765         /* Return to the non-existent secure-EL2 */
 766         goto illegal_return;
 767     }
 768
 769     if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE)
 770         && !arm_is_secure_below_el3(env)) {
 771         goto illegal_return;
 772     }
 773
 774     if (!return_to_aa64) {
 775         env->aarch64 = 0;
 776         env->uncached_cpsr = spsr & CPSR_M;
 777         cpsr_write(env, spsr, ~0);
 778         if (!arm_singlestep_active(env)) {
 779             env->uncached_cpsr &= ~PSTATE_SS;
 780         }
 781         aarch64_sync_64_to_32(env);
 782
 783         if (spsr & CPSR_T) {
 784             env->regs[15] = env->elr_el[cur_el] & ~0x1;
 785         } else {
 786             env->regs[15] = env->elr_el[cur_el] & ~0x3;
 787         }
 788     } else {
 789         env->aarch64 = 1;
 790         pstate_write(env, spsr);
 791         if (!arm_singlestep_active(env)) {
 792             env->pstate &= ~PSTATE_SS;
 793         }
 794         aarch64_restore_sp(env, new_el);
 795         env->pc = env->elr_el[cur_el];
 796     }
 797
 798     return;
 799
 800 illegal_return:
 801     /* Illegal return events of various kinds have architecturally
 802      * mandated behaviour:
 803      * restore NZCV and DAIF from SPSR_ELx
 804      * set PSTATE.IL
 805      * restore PC from ELR_ELx
 806      * no change to exception level, execution state or stack pointer
 807      */
 808     env->pstate |= PSTATE_IL;
 809     env->pc = env->elr_el[cur_el];
 810     spsr &= PSTATE_NZCV | PSTATE_DAIF;
 811     spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
 812     pstate_write(env, spsr);
 813     if (!arm_singlestep_active(env)) {
 814         env->pstate &= ~PSTATE_SS;
 815     }
 816 }
 817
 818 /* Return true if the linked breakpoint entry lbn passes its checks */
 819 static bool linked_bp_matches(ARMCPU *cpu, int lbn)
 820 {
 821     CPUARMState *env = &cpu->env;
 822     uint64_t bcr = env->cp15.dbgbcr[lbn];
 823     int brps = extract32(cpu->dbgdidr, 24, 4);
 824     int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
 825     int bt;
 826     uint32_t contextidr;
 827
 828     /* Links to unimplemented or non-context aware breakpoints are
 829      * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
 830      * as if linked to an UNKNOWN context-aware breakpoint (in which
 831      * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
 832      * We choose the former.
 833      */
 834     if (lbn > brps || lbn < (brps - ctx_cmps)) {
 835         return false;
 836     }
 837
 838     bcr = env->cp15.dbgbcr[lbn];
 839
 840     if (extract64(bcr, 0, 1) == 0) {
 841         /* Linked breakpoint disabled : generate no events */
 842         return false;
 843     }
 844
 845     bt = extract64(bcr, 20, 4);
 846
 847     /* We match the whole register even if this is AArch32 using the
 848      * short descriptor format (in which case it holds both PROCID and ASID),
 849      * since we don't implement the optional v7 context ID masking.
 850      */
 851     contextidr = extract64(env->cp15.contextidr_el[1], 0, 32);
 852
 853     switch (bt) {
 854     case 3: /* linked context ID match */
 855         if (arm_current_el(env) > 1) {
 856             /* Context matches never fire in EL2 or (AArch64) EL3 */
 857             return false;
 858         }
 859         return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
 860     case 5: /* linked address mismatch (reserved in AArch64) */
 861     case 9: /* linked VMID match (reserved if no EL2) */
 862     case 11: /* linked context ID and VMID match (reserved if no EL2) */
 863     default:
 864         /* Links to Unlinked context breakpoints must generate no
 865          * events; we choose to do the same for reserved values too.
 866          */
 867         return false;
 868     }
 869
 870     return false;
 871 }
 872
 873 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
 874 {
 875     CPUARMState *env = &cpu->env;
 876     uint64_t cr;
 877     int pac, hmc, ssc, wt, lbn;
 878     /* Note that for watchpoints the check is against the CPU security
 879      * state, not the S/NS attribute on the offending data access.
 880      */
 881     bool is_secure = arm_is_secure(env);
 882     int access_el = arm_current_el(env);
 883
 884     if (is_wp) {
 885         CPUWatchpoint *wp = env->cpu_watchpoint[n];
 886
 887         if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
 888             return false;
 889         }
 890         cr = env->cp15.dbgwcr[n];
 891         if (wp->hitattrs.user) {
 892             /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
 893              * match watchpoints as if they were accesses done at EL0, even if
 894              * the CPU is at EL1 or higher.
 895              */
 896             access_el = 0;
 897         }
 898     } else {
 899         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
 900
 901         if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
 902             return false;
 903         }
 904         cr = env->cp15.dbgbcr[n];
 905     }
 906     /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
 907      * enabled and that the address and access type match; for breakpoints
 908      * we know the address matched; check the remaining fields, including
 909      * linked breakpoints. We rely on WCR and BCR having the same layout
 910      * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
 911      * Note that some combinations of {PAC, HMC, SSC} are reserved and
 912      * must act either like some valid combination or as if the watchpoint
 913      * were disabled. We choose the former, and use this together with
 914      * the fact that EL3 must always be Secure and EL2 must always be
 915      * Non-Secure to simplify the code slightly compared to the full
 916      * table in the ARM ARM.
 917      */
 918     pac = extract64(cr, 1, 2);
 919     hmc = extract64(cr, 13, 1);
 920     ssc = extract64(cr, 14, 2);
 921
 922     switch (ssc) {
 923     case 0:
 924         break;
 925     case 1:
 926     case 3:
 927         if (is_secure) {
 928             return false;
 929         }
 930         break;
 931     case 2:
 932         if (!is_secure) {
 933             return false;
 934         }
 935         break;
 936     }
 937
 938     switch (access_el) {
 939     case 3:
 940     case 2:
 941         if (!hmc) {
 942             return false;
 943         }
 944         break;
 945     case 1:
 946         if (extract32(pac, 0, 1) == 0) {
 947             return false;
 948         }
 949         break;
 950     case 0:
 951         if (extract32(pac, 1, 1) == 0) {
 952             return false;
 953         }
 954         break;
 955     default:
 956         g_assert_not_reached();
 957     }
 958
 959     wt = extract64(cr, 20, 1);
 960     lbn = extract64(cr, 16, 4);
 961
 962     if (wt && !linked_bp_matches(cpu, lbn)) {
 963         return false;
 964     }
 965
 966     return true;
 967 }
 968
 969 static bool check_watchpoints(ARMCPU *cpu)
 970 {
 971     CPUARMState *env = &cpu->env;
 972     int n;
 973
 974     /* If watchpoints are disabled globally or we can't take debug
 975      * exceptions here then watchpoint firings are ignored.
 976      */
 977     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 978         || !arm_generate_debug_exceptions(env)) {
 979         return false;
 980     }
 981
 982     for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
 983         if (bp_wp_matches(cpu, n, true)) {
 984             return true;
 985         }
 986     }
 987     return false;
 988 }
 989
 990 static bool check_breakpoints(ARMCPU *cpu)
 991 {
 992     CPUARMState *env = &cpu->env;
 993     int n;
 994
 995     /* If breakpoints are disabled globally or we can't take debug
 996      * exceptions here then breakpoint firings are ignored.
 997      */
 998     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 999         || !arm_generate_debug_exceptions(env)) {
1000         return false;
1001     }
1002
1003     for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
1004         if (bp_wp_matches(cpu, n, false)) {
1005             return true;
1006         }
1007     }
1008     return false;
1009 }
1010
1011 void HELPER(check_breakpoints)(CPUARMState *env)
1012 {
1013     ARMCPU *cpu = arm_env_get_cpu(env);
1014
1015     if (check_breakpoints(cpu)) {
1016         HELPER(exception_internal(env, EXCP_DEBUG));
1017     }
1018 }
1019
1020 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
1021 {
1022     /* Called by core code when a CPU watchpoint fires; need to check if this
1023      * is also an architectural watchpoint match.
1024      */
1025     ARMCPU *cpu = ARM_CPU(cs);
1026
1027     return check_watchpoints(cpu);
1028 }
1029
1030 void arm_debug_excp_handler(CPUState *cs)
1031 {
1032     /* Called by core code when a watchpoint or breakpoint fires;
1033      * need to check which one and raise the appropriate exception.
1034      */
1035     ARMCPU *cpu = ARM_CPU(cs);
1036     CPUARMState *env = &cpu->env;
1037     CPUWatchpoint *wp_hit = cs->watchpoint_hit;
1038
1039     if (wp_hit) {
1040         if (wp_hit->flags & BP_CPU) {
1041             bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
1042             bool same_el = arm_debug_target_el(env) == arm_current_el(env);
1043
1044             cs->watchpoint_hit = NULL;
1045
1046             if (extended_addresses_enabled(env)) {
1047                 env->exception.fsr = (1 << 9) | 0x22;
1048             } else {
1049                 env->exception.fsr = 0x2;
1050             }
1051             env->exception.vaddress = wp_hit->hitaddr;
1052             raise_exception(env, EXCP_DATA_ABORT,
1053                     syn_watchpoint(same_el, 0, wnr),
1054                     arm_debug_target_el(env));
1055         }
1056     } else {
1057         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
1058         bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
1059
1060         /* (1) GDB breakpoints should be handled first.
1061          * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1062          * since singlestep is also done by generating a debug internal
1063          * exception.
1064          */
1065         if (cpu_breakpoint_test(cs, pc, BP_GDB)
1066             || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
1067             return;
1068         }
1069
1070         if (extended_addresses_enabled(env)) {
1071             env->exception.fsr = (1 << 9) | 0x22;
1072         } else {
1073             env->exception.fsr = 0x2;
1074         }
1075         /* FAR is UNKNOWN, so doesn't need setting */
1076         raise_exception(env, EXCP_PREFETCH_ABORT,
1077                         syn_breakpoint(same_el),
1078                         arm_debug_target_el(env));
1079     }
1080 }
1081
1082 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1083    The only way to do that in TCG is a conditional branch, which clobbers
1084    all our temporaries.  For now implement these as helper functions.  */
1085
1086 /* Similarly for variable shift instructions.  */
1087
1088 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1089 {
1090     int shift = i & 0xff;
1091     if (shift >= 32) {
1092         if (shift == 32)
1093             env->CF = x & 1;
1094         else
1095             env->CF = 0;
1096         return 0;
1097     } else if (shift != 0) {
1098         env->CF = (x >> (32 - shift)) & 1;
1099         return x << shift;
1100     }
1101     return x;
1102 }
1103
1104 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1105 {
1106     int shift = i & 0xff;
1107     if (shift >= 32) {
1108         if (shift == 32)
1109             env->CF = (x >> 31) & 1;
1110         else
1111             env->CF = 0;
1112         return 0;
1113     } else if (shift != 0) {
1114         env->CF = (x >> (shift - 1)) & 1;
1115         return x >> shift;
1116     }
1117     return x;
1118 }
1119
1120 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1121 {
1122     int shift = i & 0xff;
1123     if (shift >= 32) {
1124         env->CF = (x >> 31) & 1;
1125         return (int32_t)x >> 31;
1126     } else if (shift != 0) {
1127         env->CF = (x >> (shift - 1)) & 1;
1128         return (int32_t)x >> shift;
1129     }
1130     return x;
1131 }
1132
1133 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1134 {
1135     int shift1, shift;
1136     shift1 = i & 0xff;
1137     shift = shift1 & 0x1f;
1138     if (shift == 0) {
1139         if (shift1 != 0)
1140             env->CF = (x >> 31) & 1;
1141         return x;
1142     } else {
1143         env->CF = (x >> (shift - 1)) & 1;
1144         return ((uint32_t)x >> shift) | (x << (32 - shift));
1145     }
1146 }