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qapi: make query-cpu-definitions depend on specific targets
[qemu.git] / target / i386 / cpu.c
blobd3aa6a815b0968459aef90fe59f66c6597df21c7
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/hvf.h"
29 #include "sysemu/cpus.h"
30 #include "kvm_i386.h"
31 #include "sev_i386.h"
32
33 #include "qemu/error-report.h"
34 #include "qemu/option.h"
35 #include "qemu/config-file.h"
36 #include "qapi/error.h"
37 #include "qapi/qapi-visit-misc.h"
38 #include "qapi/qapi-visit-run-state.h"
39 #include "qapi/qmp/qdict.h"
40 #include "qapi/qmp/qerror.h"
41 #include "qapi/visitor.h"
42 #include "qom/qom-qobject.h"
43 #include "sysemu/arch_init.h"
44 #include "qapi/qapi-commands-target.h"
45
46 #include "standard-headers/asm-x86/kvm_para.h"
47
48 #include "sysemu/sysemu.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/i386/topology.h"
51 #ifndef CONFIG_USER_ONLY
52 #include "exec/address-spaces.h"
53 #include "hw/hw.h"
54 #include "hw/xen/xen.h"
55 #include "hw/i386/apic_internal.h"
56 #endif
57
58 #include "disas/capstone.h"
59
60 /* Helpers for building CPUID[2] descriptors: */
61
62 struct CPUID2CacheDescriptorInfo {
63 enum CacheType type;
64 int level;
65 int size;
66 int line_size;
67 int associativity;
68 };
69
70 /*
71 * Known CPUID 2 cache descriptors.
72 * From Intel SDM Volume 2A, CPUID instruction
73 */
74 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
75 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
76 .associativity = 4, .line_size = 32, },
77 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
78 .associativity = 4, .line_size = 32, },
79 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
80 .associativity = 4, .line_size = 64, },
81 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
82 .associativity = 2, .line_size = 32, },
83 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
84 .associativity = 4, .line_size = 32, },
85 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
86 .associativity = 4, .line_size = 64, },
87 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
88 .associativity = 6, .line_size = 64, },
89 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
90 .associativity = 2, .line_size = 64, },
91 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
92 .associativity = 8, .line_size = 64, },
93 /* lines per sector is not supported cpuid2_cache_descriptor(),
94 * so descriptors 0x22, 0x23 are not included
95 */
96 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
97 .associativity = 16, .line_size = 64, },
98 /* lines per sector is not supported cpuid2_cache_descriptor(),
99 * so descriptors 0x25, 0x20 are not included
100 */
101 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
102 .associativity = 8, .line_size = 64, },
103 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
104 .associativity = 8, .line_size = 64, },
105 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
106 .associativity = 4, .line_size = 32, },
107 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
108 .associativity = 4, .line_size = 32, },
109 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
112 .associativity = 4, .line_size = 32, },
113 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
114 .associativity = 4, .line_size = 32, },
115 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
116 .associativity = 4, .line_size = 64, },
117 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
118 .associativity = 8, .line_size = 64, },
119 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
120 .associativity = 12, .line_size = 64, },
121 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
122 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
123 .associativity = 12, .line_size = 64, },
124 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
125 .associativity = 16, .line_size = 64, },
126 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
131 .associativity = 24, .line_size = 64, },
132 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
133 .associativity = 8, .line_size = 64, },
134 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
135 .associativity = 4, .line_size = 64, },
136 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 4, .line_size = 64, },
138 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
141 .associativity = 4, .line_size = 64, },
142 /* lines per sector is not supported cpuid2_cache_descriptor(),
143 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
144 */
145 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
146 .associativity = 8, .line_size = 64, },
147 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
148 .associativity = 2, .line_size = 64, },
149 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
150 .associativity = 8, .line_size = 64, },
151 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
152 .associativity = 8, .line_size = 32, },
153 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 32, },
155 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
156 .associativity = 8, .line_size = 32, },
157 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
158 .associativity = 8, .line_size = 32, },
159 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
160 .associativity = 4, .line_size = 64, },
161 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
162 .associativity = 8, .line_size = 64, },
163 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 4, .line_size = 64, },
167 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 8, .line_size = 64, },
171 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 8, .line_size = 64, },
173 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
176 .associativity = 12, .line_size = 64, },
177 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
178 .associativity = 12, .line_size = 64, },
179 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
182 .associativity = 16, .line_size = 64, },
183 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
184 .associativity = 16, .line_size = 64, },
185 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
188 .associativity = 24, .line_size = 64, },
189 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
190 .associativity = 24, .line_size = 64, },
191 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
192 .associativity = 24, .line_size = 64, },
193 };
194
195 /*
196 * "CPUID leaf 2 does not report cache descriptor information,
197 * use CPUID leaf 4 to query cache parameters"
198 */
199 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
200
201 /*
202 * Return a CPUID 2 cache descriptor for a given cache.
203 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
204 */
205 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
206 {
207 int i;
208
209 assert(cache->size > 0);
210 assert(cache->level > 0);
211 assert(cache->line_size > 0);
212 assert(cache->associativity > 0);
213 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
214 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
215 if (d->level == cache->level && d->type == cache->type &&
216 d->size == cache->size && d->line_size == cache->line_size &&
217 d->associativity == cache->associativity) {
218 return i;
219 }
220 }
221
222 return CACHE_DESCRIPTOR_UNAVAILABLE;
223 }
224
225 /* CPUID Leaf 4 constants: */
226
227 /* EAX: */
228 #define CACHE_TYPE_D 1
229 #define CACHE_TYPE_I 2
230 #define CACHE_TYPE_UNIFIED 3
231
232 #define CACHE_LEVEL(l) (l << 5)
233
234 #define CACHE_SELF_INIT_LEVEL (1 << 8)
235
236 /* EDX: */
237 #define CACHE_NO_INVD_SHARING (1 << 0)
238 #define CACHE_INCLUSIVE (1 << 1)
239 #define CACHE_COMPLEX_IDX (1 << 2)
240
241 /* Encode CacheType for CPUID[4].EAX */
242 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
243 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
244 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
245 0 /* Invalid value */)
246
247
248 /* Encode cache info for CPUID[4] */
249 static void encode_cache_cpuid4(CPUCacheInfo *cache,
250 int num_apic_ids, int num_cores,
251 uint32_t *eax, uint32_t *ebx,
252 uint32_t *ecx, uint32_t *edx)
253 {
254 assert(cache->size == cache->line_size * cache->associativity *
255 cache->partitions * cache->sets);
256
257 assert(num_apic_ids > 0);
258 *eax = CACHE_TYPE(cache->type) |
259 CACHE_LEVEL(cache->level) |
260 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
261 ((num_cores - 1) << 26) |
262 ((num_apic_ids - 1) << 14);
263
264 assert(cache->line_size > 0);
265 assert(cache->partitions > 0);
266 assert(cache->associativity > 0);
267 /* We don't implement fully-associative caches */
268 assert(cache->associativity < cache->sets);
269 *ebx = (cache->line_size - 1) |
270 ((cache->partitions - 1) << 12) |
271 ((cache->associativity - 1) << 22);
272
273 assert(cache->sets > 0);
274 *ecx = cache->sets - 1;
275
276 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
277 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
278 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
279 }
280
281 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
282 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
283 {
284 assert(cache->size % 1024 == 0);
285 assert(cache->lines_per_tag > 0);
286 assert(cache->associativity > 0);
287 assert(cache->line_size > 0);
288 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
289 (cache->lines_per_tag << 8) | (cache->line_size);
290 }
291
292 #define ASSOC_FULL 0xFF
293
294 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
295 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
296 a == 2 ? 0x2 : \
297 a == 4 ? 0x4 : \
298 a == 8 ? 0x6 : \
299 a == 16 ? 0x8 : \
300 a == 32 ? 0xA : \
301 a == 48 ? 0xB : \
302 a == 64 ? 0xC : \
303 a == 96 ? 0xD : \
304 a == 128 ? 0xE : \
305 a == ASSOC_FULL ? 0xF : \
306 0 /* invalid value */)
307
308 /*
309 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
310 * @l3 can be NULL.
311 */
312 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
313 CPUCacheInfo *l3,
314 uint32_t *ecx, uint32_t *edx)
315 {
316 assert(l2->size % 1024 == 0);
317 assert(l2->associativity > 0);
318 assert(l2->lines_per_tag > 0);
319 assert(l2->line_size > 0);
320 *ecx = ((l2->size / 1024) << 16) |
321 (AMD_ENC_ASSOC(l2->associativity) << 12) |
322 (l2->lines_per_tag << 8) | (l2->line_size);
323
324 if (l3) {
325 assert(l3->size % (512 * 1024) == 0);
326 assert(l3->associativity > 0);
327 assert(l3->lines_per_tag > 0);
328 assert(l3->line_size > 0);
329 *edx = ((l3->size / (512 * 1024)) << 18) |
330 (AMD_ENC_ASSOC(l3->associativity) << 12) |
331 (l3->lines_per_tag << 8) | (l3->line_size);
332 } else {
333 *edx = 0;
334 }
335 }
336
337 /*
338 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
339 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
340 * Define the constants to build the cpu topology. Right now, TOPOEXT
341 * feature is enabled only on EPYC. So, these constants are based on
342 * EPYC supported configurations. We may need to handle the cases if
343 * these values change in future.
344 */
345 /* Maximum core complexes in a node */
346 #define MAX_CCX 2
347 /* Maximum cores in a core complex */
348 #define MAX_CORES_IN_CCX 4
349 /* Maximum cores in a node */
350 #define MAX_CORES_IN_NODE 8
351 /* Maximum nodes in a socket */
352 #define MAX_NODES_PER_SOCKET 4
353
354 /*
355 * Figure out the number of nodes required to build this config.
356 * Max cores in a node is 8
357 */
358 static int nodes_in_socket(int nr_cores)
359 {
360 int nodes;
361
362 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
363
364 /* Hardware does not support config with 3 nodes, return 4 in that case */
365 return (nodes == 3) ? 4 : nodes;
366 }
367
368 /*
369 * Decide the number of cores in a core complex with the given nr_cores using
370 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
371 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
372 * L3 cache is shared across all cores in a core complex. So, this will also
373 * tell us how many cores are sharing the L3 cache.
374 */
375 static int cores_in_core_complex(int nr_cores)
376 {
377 int nodes;
378
379 /* Check if we can fit all the cores in one core complex */
380 if (nr_cores <= MAX_CORES_IN_CCX) {
381 return nr_cores;
382 }
383 /* Get the number of nodes required to build this config */
384 nodes = nodes_in_socket(nr_cores);
385
386 /*
387 * Divide the cores accros all the core complexes
388 * Return rounded up value
389 */
390 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
391 }
392
393 /* Encode cache info for CPUID[8000001D] */
394 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
395 uint32_t *eax, uint32_t *ebx,
396 uint32_t *ecx, uint32_t *edx)
397 {
398 uint32_t l3_cores;
399 assert(cache->size == cache->line_size * cache->associativity *
400 cache->partitions * cache->sets);
401
402 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
403 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
404
405 /* L3 is shared among multiple cores */
406 if (cache->level == 3) {
407 l3_cores = cores_in_core_complex(cs->nr_cores);
408 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
409 } else {
410 *eax |= ((cs->nr_threads - 1) << 14);
411 }
412
413 assert(cache->line_size > 0);
414 assert(cache->partitions > 0);
415 assert(cache->associativity > 0);
416 /* We don't implement fully-associative caches */
417 assert(cache->associativity < cache->sets);
418 *ebx = (cache->line_size - 1) |
419 ((cache->partitions - 1) << 12) |
420 ((cache->associativity - 1) << 22);
421
422 assert(cache->sets > 0);
423 *ecx = cache->sets - 1;
424
425 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
426 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
427 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
428 }
429
430 /* Data structure to hold the configuration info for a given core index */
431 struct core_topology {
432 /* core complex id of the current core index */
433 int ccx_id;
434 /*
435 * Adjusted core index for this core in the topology
436 * This can be 0,1,2,3 with max 4 cores in a core complex
437 */
438 int core_id;
439 /* Node id for this core index */
440 int node_id;
441 /* Number of nodes in this config */
442 int num_nodes;
443 };
444
445 /*
446 * Build the configuration closely match the EPYC hardware. Using the EPYC
447 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
448 * right now. This could change in future.
449 * nr_cores : Total number of cores in the config
450 * core_id : Core index of the current CPU
451 * topo : Data structure to hold all the config info for this core index
452 */
453 static void build_core_topology(int nr_cores, int core_id,
454 struct core_topology *topo)
455 {
456 int nodes, cores_in_ccx;
457
458 /* First get the number of nodes required */
459 nodes = nodes_in_socket(nr_cores);
460
461 cores_in_ccx = cores_in_core_complex(nr_cores);
462
463 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
464 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
465 topo->core_id = core_id % cores_in_ccx;
466 topo->num_nodes = nodes;
467 }
468
469 /* Encode cache info for CPUID[8000001E] */
470 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
471 uint32_t *eax, uint32_t *ebx,
472 uint32_t *ecx, uint32_t *edx)
473 {
474 struct core_topology topo = {0};
475 unsigned long nodes;
476 int shift;
477
478 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
479 *eax = cpu->apic_id;
480 /*
481 * CPUID_Fn8000001E_EBX
482 * 31:16 Reserved
483 * 15:8 Threads per core (The number of threads per core is
484 * Threads per core + 1)
485 * 7:0 Core id (see bit decoding below)
486 * SMT:
487 * 4:3 node id
488 * 2 Core complex id
489 * 1:0 Core id
490 * Non SMT:
491 * 5:4 node id
492 * 3 Core complex id
493 * 1:0 Core id
494 */
495 if (cs->nr_threads - 1) {
496 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
497 (topo.ccx_id << 2) | topo.core_id;
498 } else {
499 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
500 }
501 /*
502 * CPUID_Fn8000001E_ECX
503 * 31:11 Reserved
504 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
505 * 7:0 Node id (see bit decoding below)
506 * 2 Socket id
507 * 1:0 Node id
508 */
509 if (topo.num_nodes <= 4) {
510 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
511 topo.node_id;
512 } else {
513 /*
514 * Node id fix up. Actual hardware supports up to 4 nodes. But with
515 * more than 32 cores, we may end up with more than 4 nodes.
516 * Node id is a combination of socket id and node id. Only requirement
517 * here is that this number should be unique accross the system.
518 * Shift the socket id to accommodate more nodes. We dont expect both
519 * socket id and node id to be big number at the same time. This is not
520 * an ideal config but we need to to support it. Max nodes we can have
521 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
522 * 5 bits for nodes. Find the left most set bit to represent the total
523 * number of nodes. find_last_bit returns last set bit(0 based). Left
524 * shift(+1) the socket id to represent all the nodes.
525 */
526 nodes = topo.num_nodes - 1;
527 shift = find_last_bit(&nodes, 8);
528 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
529 topo.node_id;
530 }
531 *edx = 0;
532 }
533
534 /*
535 * Definitions of the hardcoded cache entries we expose:
536 * These are legacy cache values. If there is a need to change any
537 * of these values please use builtin_x86_defs
538 */
539
540 /* L1 data cache: */
541 static CPUCacheInfo legacy_l1d_cache = {
542 .type = DATA_CACHE,
543 .level = 1,
544 .size = 32 * KiB,
545 .self_init = 1,
546 .line_size = 64,
547 .associativity = 8,
548 .sets = 64,
549 .partitions = 1,
550 .no_invd_sharing = true,
551 };
552
553 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
554 static CPUCacheInfo legacy_l1d_cache_amd = {
555 .type = DATA_CACHE,
556 .level = 1,
557 .size = 64 * KiB,
558 .self_init = 1,
559 .line_size = 64,
560 .associativity = 2,
561 .sets = 512,
562 .partitions = 1,
563 .lines_per_tag = 1,
564 .no_invd_sharing = true,
565 };
566
567 /* L1 instruction cache: */
568 static CPUCacheInfo legacy_l1i_cache = {
569 .type = INSTRUCTION_CACHE,
570 .level = 1,
571 .size = 32 * KiB,
572 .self_init = 1,
573 .line_size = 64,
574 .associativity = 8,
575 .sets = 64,
576 .partitions = 1,
577 .no_invd_sharing = true,
578 };
579
580 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
581 static CPUCacheInfo legacy_l1i_cache_amd = {
582 .type = INSTRUCTION_CACHE,
583 .level = 1,
584 .size = 64 * KiB,
585 .self_init = 1,
586 .line_size = 64,
587 .associativity = 2,
588 .sets = 512,
589 .partitions = 1,
590 .lines_per_tag = 1,
591 .no_invd_sharing = true,
592 };
593
594 /* Level 2 unified cache: */
595 static CPUCacheInfo legacy_l2_cache = {
596 .type = UNIFIED_CACHE,
597 .level = 2,
598 .size = 4 * MiB,
599 .self_init = 1,
600 .line_size = 64,
601 .associativity = 16,
602 .sets = 4096,
603 .partitions = 1,
604 .no_invd_sharing = true,
605 };
606
607 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
608 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
609 .type = UNIFIED_CACHE,
610 .level = 2,
611 .size = 2 * MiB,
612 .line_size = 64,
613 .associativity = 8,
614 };
615
616
617 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
618 static CPUCacheInfo legacy_l2_cache_amd = {
619 .type = UNIFIED_CACHE,
620 .level = 2,
621 .size = 512 * KiB,
622 .line_size = 64,
623 .lines_per_tag = 1,
624 .associativity = 16,
625 .sets = 512,
626 .partitions = 1,
627 };
628
629 /* Level 3 unified cache: */
630 static CPUCacheInfo legacy_l3_cache = {
631 .type = UNIFIED_CACHE,
632 .level = 3,
633 .size = 16 * MiB,
634 .line_size = 64,
635 .associativity = 16,
636 .sets = 16384,
637 .partitions = 1,
638 .lines_per_tag = 1,
639 .self_init = true,
640 .inclusive = true,
641 .complex_indexing = true,
642 };
643
644 /* TLB definitions: */
645
646 #define L1_DTLB_2M_ASSOC 1
647 #define L1_DTLB_2M_ENTRIES 255
648 #define L1_DTLB_4K_ASSOC 1
649 #define L1_DTLB_4K_ENTRIES 255
650
651 #define L1_ITLB_2M_ASSOC 1
652 #define L1_ITLB_2M_ENTRIES 255
653 #define L1_ITLB_4K_ASSOC 1
654 #define L1_ITLB_4K_ENTRIES 255
655
656 #define L2_DTLB_2M_ASSOC 0 /* disabled */
657 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
658 #define L2_DTLB_4K_ASSOC 4
659 #define L2_DTLB_4K_ENTRIES 512
660
661 #define L2_ITLB_2M_ASSOC 0 /* disabled */
662 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
663 #define L2_ITLB_4K_ASSOC 4
664 #define L2_ITLB_4K_ENTRIES 512
665
666 /* CPUID Leaf 0x14 constants: */
667 #define INTEL_PT_MAX_SUBLEAF 0x1
668 /*
669 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
670 * MSR can be accessed;
671 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
672 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
673 * of Intel PT MSRs across warm reset;
674 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
675 */
676 #define INTEL_PT_MINIMAL_EBX 0xf
677 /*
678 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
679 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
680 * accessed;
681 * bit[01]: ToPA tables can hold any number of output entries, up to the
682 * maximum allowed by the MaskOrTableOffset field of
683 * IA32_RTIT_OUTPUT_MASK_PTRS;
684 * bit[02]: Support Single-Range Output scheme;
685 */
686 #define INTEL_PT_MINIMAL_ECX 0x7
687 /* generated packets which contain IP payloads have LIP values */
688 #define INTEL_PT_IP_LIP (1 << 31)
689 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
690 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
691 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
692 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
693 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
694
695 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
696 uint32_t vendor2, uint32_t vendor3)
697 {
698 int i;
699 for (i = 0; i < 4; i++) {
700 dst[i] = vendor1 >> (8 * i);
701 dst[i + 4] = vendor2 >> (8 * i);
702 dst[i + 8] = vendor3 >> (8 * i);
703 }
704 dst[CPUID_VENDOR_SZ] = '\0';
705 }
706
707 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
708 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
709 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
710 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
711 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
712 CPUID_PSE36 | CPUID_FXSR)
713 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
714 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
715 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
716 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
717 CPUID_PAE | CPUID_SEP | CPUID_APIC)
718
719 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
720 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
721 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
722 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
723 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
724 /* partly implemented:
725 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
726 /* missing:
727 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
728 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
729 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
730 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
731 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
732 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
733 /* missing:
734 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
735 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
736 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
737 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
738 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
739
740 #ifdef TARGET_X86_64
741 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
742 #else
743 #define TCG_EXT2_X86_64_FEATURES 0
744 #endif
745
746 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
747 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
748 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
749 TCG_EXT2_X86_64_FEATURES)
750 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
751 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
752 #define TCG_EXT4_FEATURES 0
753 #define TCG_SVM_FEATURES CPUID_SVM_NPT
754 #define TCG_KVM_FEATURES 0
755 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
756 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
757 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
758 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
759 CPUID_7_0_EBX_ERMS)
760 /* missing:
761 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
762 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
763 CPUID_7_0_EBX_RDSEED */
764 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
765 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
766 CPUID_7_0_ECX_LA57)
767 #define TCG_7_0_EDX_FEATURES 0
768 #define TCG_APM_FEATURES 0
769 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
770 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
771 /* missing:
772 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
773
774 typedef enum FeatureWordType {
775 CPUID_FEATURE_WORD,
776 MSR_FEATURE_WORD,
777 } FeatureWordType;
778
779 typedef struct FeatureWordInfo {
780 FeatureWordType type;
781 /* feature flags names are taken from "Intel Processor Identification and
782 * the CPUID Instruction" and AMD's "CPUID Specification".
783 * In cases of disagreement between feature naming conventions,
784 * aliases may be added.
785 */
786 const char *feat_names[32];
787 union {
788 /* If type==CPUID_FEATURE_WORD */
789 struct {
790 uint32_t eax; /* Input EAX for CPUID */
791 bool needs_ecx; /* CPUID instruction uses ECX as input */
792 uint32_t ecx; /* Input ECX value for CPUID */
793 int reg; /* output register (R_* constant) */
794 } cpuid;
795 /* If type==MSR_FEATURE_WORD */
796 struct {
797 uint32_t index;
798 struct { /*CPUID that enumerate this MSR*/
799 FeatureWord cpuid_class;
800 uint32_t cpuid_flag;
801 } cpuid_dep;
802 } msr;
803 };
804 uint32_t tcg_features; /* Feature flags supported by TCG */
805 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
806 uint32_t migratable_flags; /* Feature flags known to be migratable */
807 /* Features that shouldn't be auto-enabled by "-cpu host" */
808 uint32_t no_autoenable_flags;
809 } FeatureWordInfo;
810
811 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
812 [FEAT_1_EDX] = {
813 .type = CPUID_FEATURE_WORD,
814 .feat_names = {
815 "fpu", "vme", "de", "pse",
816 "tsc", "msr", "pae", "mce",
817 "cx8", "apic", NULL, "sep",
818 "mtrr", "pge", "mca", "cmov",
819 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
820 NULL, "ds" /* Intel dts */, "acpi", "mmx",
821 "fxsr", "sse", "sse2", "ss",
822 "ht" /* Intel htt */, "tm", "ia64", "pbe",
823 },
824 .cpuid = {.eax = 1, .reg = R_EDX, },
825 .tcg_features = TCG_FEATURES,
826 },
827 [FEAT_1_ECX] = {
828 .type = CPUID_FEATURE_WORD,
829 .feat_names = {
830 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
831 "ds-cpl", "vmx", "smx", "est",
832 "tm2", "ssse3", "cid", NULL,
833 "fma", "cx16", "xtpr", "pdcm",
834 NULL, "pcid", "dca", "sse4.1",
835 "sse4.2", "x2apic", "movbe", "popcnt",
836 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
837 "avx", "f16c", "rdrand", "hypervisor",
838 },
839 .cpuid = { .eax = 1, .reg = R_ECX, },
840 .tcg_features = TCG_EXT_FEATURES,
841 },
842 /* Feature names that are already defined on feature_name[] but
843 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
844 * names on feat_names below. They are copied automatically
845 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
846 */
847 [FEAT_8000_0001_EDX] = {
848 .type = CPUID_FEATURE_WORD,
849 .feat_names = {
850 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
851 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
852 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
853 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
854 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
855 "nx", NULL, "mmxext", NULL /* mmx */,
856 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
857 NULL, "lm", "3dnowext", "3dnow",
858 },
859 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
860 .tcg_features = TCG_EXT2_FEATURES,
861 },
862 [FEAT_8000_0001_ECX] = {
863 .type = CPUID_FEATURE_WORD,
864 .feat_names = {
865 "lahf-lm", "cmp-legacy", "svm", "extapic",
866 "cr8legacy", "abm", "sse4a", "misalignsse",
867 "3dnowprefetch", "osvw", "ibs", "xop",
868 "skinit", "wdt", NULL, "lwp",
869 "fma4", "tce", NULL, "nodeid-msr",
870 NULL, "tbm", "topoext", "perfctr-core",
871 "perfctr-nb", NULL, NULL, NULL,
872 NULL, NULL, NULL, NULL,
873 },
874 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
875 .tcg_features = TCG_EXT3_FEATURES,
876 /*
877 * TOPOEXT is always allowed but can't be enabled blindly by
878 * "-cpu host", as it requires consistent cache topology info
879 * to be provided so it doesn't confuse guests.
880 */
881 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
882 },
883 [FEAT_C000_0001_EDX] = {
884 .type = CPUID_FEATURE_WORD,
885 .feat_names = {
886 NULL, NULL, "xstore", "xstore-en",
887 NULL, NULL, "xcrypt", "xcrypt-en",
888 "ace2", "ace2-en", "phe", "phe-en",
889 "pmm", "pmm-en", NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 },
895 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
896 .tcg_features = TCG_EXT4_FEATURES,
897 },
898 [FEAT_KVM] = {
899 .type = CPUID_FEATURE_WORD,
900 .feat_names = {
901 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
902 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
903 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 NULL, NULL, NULL, NULL,
907 "kvmclock-stable-bit", NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 },
910 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
911 .tcg_features = TCG_KVM_FEATURES,
912 },
913 [FEAT_KVM_HINTS] = {
914 .type = CPUID_FEATURE_WORD,
915 .feat_names = {
916 "kvm-hint-dedicated", NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 },
925 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
926 .tcg_features = TCG_KVM_FEATURES,
927 /*
928 * KVM hints aren't auto-enabled by -cpu host, they need to be
929 * explicitly enabled in the command-line.
930 */
931 .no_autoenable_flags = ~0U,
932 },
933 /*
934 * .feat_names are commented out for Hyper-V enlightenments because we
935 * don't want to have two different ways for enabling them on QEMU command
936 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
937 * enabling several feature bits simultaneously, exposing these bits
938 * individually may just confuse guests.
939 */
940 [FEAT_HYPERV_EAX] = {
941 .type = CPUID_FEATURE_WORD,
942 .feat_names = {
943 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
944 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
945 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
946 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
947 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
948 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
949 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
950 NULL, NULL,
951 NULL, NULL, NULL, NULL,
952 NULL, NULL, NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 },
956 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
957 },
958 [FEAT_HYPERV_EBX] = {
959 .type = CPUID_FEATURE_WORD,
960 .feat_names = {
961 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
962 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
963 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
964 NULL /* hv_create_port */, NULL /* hv_connect_port */,
965 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
966 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
967 NULL, NULL,
968 NULL, NULL, NULL, NULL,
969 NULL, NULL, NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 },
973 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
974 },
975 [FEAT_HYPERV_EDX] = {
976 .type = CPUID_FEATURE_WORD,
977 .feat_names = {
978 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
979 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
980 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
981 NULL, NULL,
982 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
983 NULL, NULL, NULL, NULL,
984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 },
989 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
990 },
991 [FEAT_HV_RECOMM_EAX] = {
992 .type = CPUID_FEATURE_WORD,
993 .feat_names = {
994 NULL /* hv_recommend_pv_as_switch */,
995 NULL /* hv_recommend_pv_tlbflush_local */,
996 NULL /* hv_recommend_pv_tlbflush_remote */,
997 NULL /* hv_recommend_msr_apic_access */,
998 NULL /* hv_recommend_msr_reset */,
999 NULL /* hv_recommend_relaxed_timing */,
1000 NULL /* hv_recommend_dma_remapping */,
1001 NULL /* hv_recommend_int_remapping */,
1002 NULL /* hv_recommend_x2apic_msrs */,
1003 NULL /* hv_recommend_autoeoi_deprecation */,
1004 NULL /* hv_recommend_pv_ipi */,
1005 NULL /* hv_recommend_ex_hypercalls */,
1006 NULL /* hv_hypervisor_is_nested */,
1007 NULL /* hv_recommend_int_mbec */,
1008 NULL /* hv_recommend_evmcs */,
1009 NULL,
1010 NULL, NULL, NULL, NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 },
1015 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1016 },
1017 [FEAT_HV_NESTED_EAX] = {
1018 .type = CPUID_FEATURE_WORD,
1019 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1020 },
1021 [FEAT_SVM] = {
1022 .type = CPUID_FEATURE_WORD,
1023 .feat_names = {
1024 "npt", "lbrv", "svm-lock", "nrip-save",
1025 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1026 NULL, NULL, "pause-filter", NULL,
1027 "pfthreshold", NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 },
1033 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1034 .tcg_features = TCG_SVM_FEATURES,
1035 },
1036 [FEAT_7_0_EBX] = {
1037 .type = CPUID_FEATURE_WORD,
1038 .feat_names = {
1039 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1040 "hle", "avx2", NULL, "smep",
1041 "bmi2", "erms", "invpcid", "rtm",
1042 NULL, NULL, "mpx", NULL,
1043 "avx512f", "avx512dq", "rdseed", "adx",
1044 "smap", "avx512ifma", "pcommit", "clflushopt",
1045 "clwb", "intel-pt", "avx512pf", "avx512er",
1046 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1047 },
1048 .cpuid = {
1049 .eax = 7,
1050 .needs_ecx = true, .ecx = 0,
1051 .reg = R_EBX,
1052 },
1053 .tcg_features = TCG_7_0_EBX_FEATURES,
1054 },
1055 [FEAT_7_0_ECX] = {
1056 .type = CPUID_FEATURE_WORD,
1057 .feat_names = {
1058 NULL, "avx512vbmi", "umip", "pku",
1059 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
1060 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1061 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1062 "la57", NULL, NULL, NULL,
1063 NULL, NULL, "rdpid", NULL,
1064 NULL, "cldemote", NULL, "movdiri",
1065 "movdir64b", NULL, NULL, NULL,
1066 },
1067 .cpuid = {
1068 .eax = 7,
1069 .needs_ecx = true, .ecx = 0,
1070 .reg = R_ECX,
1071 },
1072 .tcg_features = TCG_7_0_ECX_FEATURES,
1073 },
1074 [FEAT_7_0_EDX] = {
1075 .type = CPUID_FEATURE_WORD,
1076 .feat_names = {
1077 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1078 NULL, NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, "spec-ctrl", "stibp",
1084 NULL, "arch-capabilities", NULL, "ssbd",
1085 },
1086 .cpuid = {
1087 .eax = 7,
1088 .needs_ecx = true, .ecx = 0,
1089 .reg = R_EDX,
1090 },
1091 .tcg_features = TCG_7_0_EDX_FEATURES,
1092 .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
1093 },
1094 [FEAT_8000_0007_EDX] = {
1095 .type = CPUID_FEATURE_WORD,
1096 .feat_names = {
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 "invtsc", NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 },
1106 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1107 .tcg_features = TCG_APM_FEATURES,
1108 .unmigratable_flags = CPUID_APM_INVTSC,
1109 },
1110 [FEAT_8000_0008_EBX] = {
1111 .type = CPUID_FEATURE_WORD,
1112 .feat_names = {
1113 NULL, NULL, NULL, NULL,
1114 NULL, NULL, NULL, NULL,
1115 NULL, "wbnoinvd", NULL, NULL,
1116 "ibpb", NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1120 NULL, NULL, NULL, NULL,
1121 },
1122 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1123 .tcg_features = 0,
1124 .unmigratable_flags = 0,
1125 },
1126 [FEAT_XSAVE] = {
1127 .type = CPUID_FEATURE_WORD,
1128 .feat_names = {
1129 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1130 NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 },
1138 .cpuid = {
1139 .eax = 0xd,
1140 .needs_ecx = true, .ecx = 1,
1141 .reg = R_EAX,
1142 },
1143 .tcg_features = TCG_XSAVE_FEATURES,
1144 },
1145 [FEAT_6_EAX] = {
1146 .type = CPUID_FEATURE_WORD,
1147 .feat_names = {
1148 NULL, NULL, "arat", NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 },
1157 .cpuid = { .eax = 6, .reg = R_EAX, },
1158 .tcg_features = TCG_6_EAX_FEATURES,
1159 },
1160 [FEAT_XSAVE_COMP_LO] = {
1161 .type = CPUID_FEATURE_WORD,
1162 .cpuid = {
1163 .eax = 0xD,
1164 .needs_ecx = true, .ecx = 0,
1165 .reg = R_EAX,
1166 },
1167 .tcg_features = ~0U,
1168 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1169 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1170 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1171 XSTATE_PKRU_MASK,
1172 },
1173 [FEAT_XSAVE_COMP_HI] = {
1174 .type = CPUID_FEATURE_WORD,
1175 .cpuid = {
1176 .eax = 0xD,
1177 .needs_ecx = true, .ecx = 0,
1178 .reg = R_EDX,
1179 },
1180 .tcg_features = ~0U,
1181 },
1182 /*Below are MSR exposed features*/
1183 [FEAT_ARCH_CAPABILITIES] = {
1184 .type = MSR_FEATURE_WORD,
1185 .feat_names = {
1186 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1187 "ssb-no", NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 },
1195 .msr = {
1196 .index = MSR_IA32_ARCH_CAPABILITIES,
1197 .cpuid_dep = {
1198 FEAT_7_0_EDX,
1199 CPUID_7_0_EDX_ARCH_CAPABILITIES
1200 }
1201 },
1202 },
1203 };
1204
1205 typedef struct X86RegisterInfo32 {
1206 /* Name of register */
1207 const char *name;
1208 /* QAPI enum value register */
1209 X86CPURegister32 qapi_enum;
1210 } X86RegisterInfo32;
1211
1212 #define REGISTER(reg) \
1213 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1214 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1215 REGISTER(EAX),
1216 REGISTER(ECX),
1217 REGISTER(EDX),
1218 REGISTER(EBX),
1219 REGISTER(ESP),
1220 REGISTER(EBP),
1221 REGISTER(ESI),
1222 REGISTER(EDI),
1223 };
1224 #undef REGISTER
1225
1226 typedef struct ExtSaveArea {
1227 uint32_t feature, bits;
1228 uint32_t offset, size;
1229 } ExtSaveArea;
1230
1231 static const ExtSaveArea x86_ext_save_areas[] = {
1232 [XSTATE_FP_BIT] = {
1233 /* x87 FP state component is always enabled if XSAVE is supported */
1234 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1235 /* x87 state is in the legacy region of the XSAVE area */
1236 .offset = 0,
1237 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1238 },
1239 [XSTATE_SSE_BIT] = {
1240 /* SSE state component is always enabled if XSAVE is supported */
1241 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1242 /* SSE state is in the legacy region of the XSAVE area */
1243 .offset = 0,
1244 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1245 },
1246 [XSTATE_YMM_BIT] =
1247 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1248 .offset = offsetof(X86XSaveArea, avx_state),
1249 .size = sizeof(XSaveAVX) },
1250 [XSTATE_BNDREGS_BIT] =
1251 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1252 .offset = offsetof(X86XSaveArea, bndreg_state),
1253 .size = sizeof(XSaveBNDREG) },
1254 [XSTATE_BNDCSR_BIT] =
1255 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1256 .offset = offsetof(X86XSaveArea, bndcsr_state),
1257 .size = sizeof(XSaveBNDCSR) },
1258 [XSTATE_OPMASK_BIT] =
1259 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1260 .offset = offsetof(X86XSaveArea, opmask_state),
1261 .size = sizeof(XSaveOpmask) },
1262 [XSTATE_ZMM_Hi256_BIT] =
1263 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1264 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1265 .size = sizeof(XSaveZMM_Hi256) },
1266 [XSTATE_Hi16_ZMM_BIT] =
1267 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1268 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1269 .size = sizeof(XSaveHi16_ZMM) },
1270 [XSTATE_PKRU_BIT] =
1271 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1272 .offset = offsetof(X86XSaveArea, pkru_state),
1273 .size = sizeof(XSavePKRU) },
1274 };
1275
1276 static uint32_t xsave_area_size(uint64_t mask)
1277 {
1278 int i;
1279 uint64_t ret = 0;
1280
1281 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1282 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1283 if ((mask >> i) & 1) {
1284 ret = MAX(ret, esa->offset + esa->size);
1285 }
1286 }
1287 return ret;
1288 }
1289
1290 static inline bool accel_uses_host_cpuid(void)
1291 {
1292 return kvm_enabled() || hvf_enabled();
1293 }
1294
1295 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1296 {
1297 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1298 cpu->env.features[FEAT_XSAVE_COMP_LO];
1299 }
1300
1301 const char *get_register_name_32(unsigned int reg)
1302 {
1303 if (reg >= CPU_NB_REGS32) {
1304 return NULL;
1305 }
1306 return x86_reg_info_32[reg].name;
1307 }
1308
1309 /*
1310 * Returns the set of feature flags that are supported and migratable by
1311 * QEMU, for a given FeatureWord.
1312 */
1313 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1314 {
1315 FeatureWordInfo *wi = &feature_word_info[w];
1316 uint32_t r = 0;
1317 int i;
1318
1319 for (i = 0; i < 32; i++) {
1320 uint32_t f = 1U << i;
1321
1322 /* If the feature name is known, it is implicitly considered migratable,
1323 * unless it is explicitly set in unmigratable_flags */
1324 if ((wi->migratable_flags & f) ||
1325 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1326 r |= f;
1327 }
1328 }
1329 return r;
1330 }
1331
1332 void host_cpuid(uint32_t function, uint32_t count,
1333 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1334 {
1335 uint32_t vec[4];
1336
1337 #ifdef __x86_64__
1338 asm volatile("cpuid"
1339 : "=a"(vec[0]), "=b"(vec[1]),
1340 "=c"(vec[2]), "=d"(vec[3])
1341 : "0"(function), "c"(count) : "cc");
1342 #elif defined(__i386__)
1343 asm volatile("pusha \n\t"
1344 "cpuid \n\t"
1345 "mov %%eax, 0(%2) \n\t"
1346 "mov %%ebx, 4(%2) \n\t"
1347 "mov %%ecx, 8(%2) \n\t"
1348 "mov %%edx, 12(%2) \n\t"
1349 "popa"
1350 : : "a"(function), "c"(count), "S"(vec)
1351 : "memory", "cc");
1352 #else
1353 abort();
1354 #endif
1355
1356 if (eax)
1357 *eax = vec[0];
1358 if (ebx)
1359 *ebx = vec[1];
1360 if (ecx)
1361 *ecx = vec[2];
1362 if (edx)
1363 *edx = vec[3];
1364 }
1365
1366 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1367 {
1368 uint32_t eax, ebx, ecx, edx;
1369
1370 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1371 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1372
1373 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1374 if (family) {
1375 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1376 }
1377 if (model) {
1378 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1379 }
1380 if (stepping) {
1381 *stepping = eax & 0x0F;
1382 }
1383 }
1384
1385 /* CPU class name definitions: */
1386
1387 /* Return type name for a given CPU model name
1388 * Caller is responsible for freeing the returned string.
1389 */
1390 static char *x86_cpu_type_name(const char *model_name)
1391 {
1392 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1393 }
1394
1395 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1396 {
1397 ObjectClass *oc;
1398 char *typename = x86_cpu_type_name(cpu_model);
1399 oc = object_class_by_name(typename);
1400 g_free(typename);
1401 return oc;
1402 }
1403
1404 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1405 {
1406 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1407 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1408 return g_strndup(class_name,
1409 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1410 }
1411
1412 struct X86CPUDefinition {
1413 const char *name;
1414 uint32_t level;
1415 uint32_t xlevel;
1416 /* vendor is zero-terminated, 12 character ASCII string */
1417 char vendor[CPUID_VENDOR_SZ + 1];
1418 int family;
1419 int model;
1420 int stepping;
1421 FeatureWordArray features;
1422 const char *model_id;
1423 CPUCaches *cache_info;
1424 };
1425
1426 static CPUCaches epyc_cache_info = {
1427 .l1d_cache = &(CPUCacheInfo) {
1428 .type = DATA_CACHE,
1429 .level = 1,
1430 .size = 32 * KiB,
1431 .line_size = 64,
1432 .associativity = 8,
1433 .partitions = 1,
1434 .sets = 64,
1435 .lines_per_tag = 1,
1436 .self_init = 1,
1437 .no_invd_sharing = true,
1438 },
1439 .l1i_cache = &(CPUCacheInfo) {
1440 .type = INSTRUCTION_CACHE,
1441 .level = 1,
1442 .size = 64 * KiB,
1443 .line_size = 64,
1444 .associativity = 4,
1445 .partitions = 1,
1446 .sets = 256,
1447 .lines_per_tag = 1,
1448 .self_init = 1,
1449 .no_invd_sharing = true,
1450 },
1451 .l2_cache = &(CPUCacheInfo) {
1452 .type = UNIFIED_CACHE,
1453 .level = 2,
1454 .size = 512 * KiB,
1455 .line_size = 64,
1456 .associativity = 8,
1457 .partitions = 1,
1458 .sets = 1024,
1459 .lines_per_tag = 1,
1460 },
1461 .l3_cache = &(CPUCacheInfo) {
1462 .type = UNIFIED_CACHE,
1463 .level = 3,
1464 .size = 8 * MiB,
1465 .line_size = 64,
1466 .associativity = 16,
1467 .partitions = 1,
1468 .sets = 8192,
1469 .lines_per_tag = 1,
1470 .self_init = true,
1471 .inclusive = true,
1472 .complex_indexing = true,
1473 },
1474 };
1475
1476 static X86CPUDefinition builtin_x86_defs[] = {
1477 {
1478 .name = "qemu64",
1479 .level = 0xd,
1480 .vendor = CPUID_VENDOR_AMD,
1481 .family = 6,
1482 .model = 6,
1483 .stepping = 3,
1484 .features[FEAT_1_EDX] =
1485 PPRO_FEATURES |
1486 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1487 CPUID_PSE36,
1488 .features[FEAT_1_ECX] =
1489 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1490 .features[FEAT_8000_0001_EDX] =
1491 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1492 .features[FEAT_8000_0001_ECX] =
1493 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1494 .xlevel = 0x8000000A,
1495 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1496 },
1497 {
1498 .name = "phenom",
1499 .level = 5,
1500 .vendor = CPUID_VENDOR_AMD,
1501 .family = 16,
1502 .model = 2,
1503 .stepping = 3,
1504 /* Missing: CPUID_HT */
1505 .features[FEAT_1_EDX] =
1506 PPRO_FEATURES |
1507 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1508 CPUID_PSE36 | CPUID_VME,
1509 .features[FEAT_1_ECX] =
1510 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1511 CPUID_EXT_POPCNT,
1512 .features[FEAT_8000_0001_EDX] =
1513 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1514 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1515 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1516 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1517 CPUID_EXT3_CR8LEG,
1518 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1519 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1520 .features[FEAT_8000_0001_ECX] =
1521 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1522 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1523 /* Missing: CPUID_SVM_LBRV */
1524 .features[FEAT_SVM] =
1525 CPUID_SVM_NPT,
1526 .xlevel = 0x8000001A,
1527 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1528 },
1529 {
1530 .name = "core2duo",
1531 .level = 10,
1532 .vendor = CPUID_VENDOR_INTEL,
1533 .family = 6,
1534 .model = 15,
1535 .stepping = 11,
1536 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1537 .features[FEAT_1_EDX] =
1538 PPRO_FEATURES |
1539 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1540 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1541 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1542 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1543 .features[FEAT_1_ECX] =
1544 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1545 CPUID_EXT_CX16,
1546 .features[FEAT_8000_0001_EDX] =
1547 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1548 .features[FEAT_8000_0001_ECX] =
1549 CPUID_EXT3_LAHF_LM,
1550 .xlevel = 0x80000008,
1551 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1552 },
1553 {
1554 .name = "kvm64",
1555 .level = 0xd,
1556 .vendor = CPUID_VENDOR_INTEL,
1557 .family = 15,
1558 .model = 6,
1559 .stepping = 1,
1560 /* Missing: CPUID_HT */
1561 .features[FEAT_1_EDX] =
1562 PPRO_FEATURES | CPUID_VME |
1563 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1564 CPUID_PSE36,
1565 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1566 .features[FEAT_1_ECX] =
1567 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1568 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1569 .features[FEAT_8000_0001_EDX] =
1570 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1571 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1572 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1573 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1574 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1575 .features[FEAT_8000_0001_ECX] =
1576 0,
1577 .xlevel = 0x80000008,
1578 .model_id = "Common KVM processor"
1579 },
1580 {
1581 .name = "qemu32",
1582 .level = 4,
1583 .vendor = CPUID_VENDOR_INTEL,
1584 .family = 6,
1585 .model = 6,
1586 .stepping = 3,
1587 .features[FEAT_1_EDX] =
1588 PPRO_FEATURES,
1589 .features[FEAT_1_ECX] =
1590 CPUID_EXT_SSE3,
1591 .xlevel = 0x80000004,
1592 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1593 },
1594 {
1595 .name = "kvm32",
1596 .level = 5,
1597 .vendor = CPUID_VENDOR_INTEL,
1598 .family = 15,
1599 .model = 6,
1600 .stepping = 1,
1601 .features[FEAT_1_EDX] =
1602 PPRO_FEATURES | CPUID_VME |
1603 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1604 .features[FEAT_1_ECX] =
1605 CPUID_EXT_SSE3,
1606 .features[FEAT_8000_0001_ECX] =
1607 0,
1608 .xlevel = 0x80000008,
1609 .model_id = "Common 32-bit KVM processor"
1610 },
1611 {
1612 .name = "coreduo",
1613 .level = 10,
1614 .vendor = CPUID_VENDOR_INTEL,
1615 .family = 6,
1616 .model = 14,
1617 .stepping = 8,
1618 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1619 .features[FEAT_1_EDX] =
1620 PPRO_FEATURES | CPUID_VME |
1621 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1622 CPUID_SS,
1623 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1624 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1625 .features[FEAT_1_ECX] =
1626 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1627 .features[FEAT_8000_0001_EDX] =
1628 CPUID_EXT2_NX,
1629 .xlevel = 0x80000008,
1630 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1631 },
1632 {
1633 .name = "486",
1634 .level = 1,
1635 .vendor = CPUID_VENDOR_INTEL,
1636 .family = 4,
1637 .model = 8,
1638 .stepping = 0,
1639 .features[FEAT_1_EDX] =
1640 I486_FEATURES,
1641 .xlevel = 0,
1642 .model_id = "",
1643 },
1644 {
1645 .name = "pentium",
1646 .level = 1,
1647 .vendor = CPUID_VENDOR_INTEL,
1648 .family = 5,
1649 .model = 4,
1650 .stepping = 3,
1651 .features[FEAT_1_EDX] =
1652 PENTIUM_FEATURES,
1653 .xlevel = 0,
1654 .model_id = "",
1655 },
1656 {
1657 .name = "pentium2",
1658 .level = 2,
1659 .vendor = CPUID_VENDOR_INTEL,
1660 .family = 6,
1661 .model = 5,
1662 .stepping = 2,
1663 .features[FEAT_1_EDX] =
1664 PENTIUM2_FEATURES,
1665 .xlevel = 0,
1666 .model_id = "",
1667 },
1668 {
1669 .name = "pentium3",
1670 .level = 3,
1671 .vendor = CPUID_VENDOR_INTEL,
1672 .family = 6,
1673 .model = 7,
1674 .stepping = 3,
1675 .features[FEAT_1_EDX] =
1676 PENTIUM3_FEATURES,
1677 .xlevel = 0,
1678 .model_id = "",
1679 },
1680 {
1681 .name = "athlon",
1682 .level = 2,
1683 .vendor = CPUID_VENDOR_AMD,
1684 .family = 6,
1685 .model = 2,
1686 .stepping = 3,
1687 .features[FEAT_1_EDX] =
1688 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
1689 CPUID_MCA,
1690 .features[FEAT_8000_0001_EDX] =
1691 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
1692 .xlevel = 0x80000008,
1693 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1694 },
1695 {
1696 .name = "n270",
1697 .level = 10,
1698 .vendor = CPUID_VENDOR_INTEL,
1699 .family = 6,
1700 .model = 28,
1701 .stepping = 2,
1702 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1703 .features[FEAT_1_EDX] =
1704 PPRO_FEATURES |
1705 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1706 CPUID_ACPI | CPUID_SS,
1707 /* Some CPUs got no CPUID_SEP */
1708 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1709 * CPUID_EXT_XTPR */
1710 .features[FEAT_1_ECX] =
1711 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1712 CPUID_EXT_MOVBE,
1713 .features[FEAT_8000_0001_EDX] =
1714 CPUID_EXT2_NX,
1715 .features[FEAT_8000_0001_ECX] =
1716 CPUID_EXT3_LAHF_LM,
1717 .xlevel = 0x80000008,
1718 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1719 },
1720 {
1721 .name = "Conroe",
1722 .level = 10,
1723 .vendor = CPUID_VENDOR_INTEL,
1724 .family = 6,
1725 .model = 15,
1726 .stepping = 3,
1727 .features[FEAT_1_EDX] =
1728 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1729 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1730 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1731 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1732 CPUID_DE | CPUID_FP87,
1733 .features[FEAT_1_ECX] =
1734 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1735 .features[FEAT_8000_0001_EDX] =
1736 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1737 .features[FEAT_8000_0001_ECX] =
1738 CPUID_EXT3_LAHF_LM,
1739 .xlevel = 0x80000008,
1740 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1741 },
1742 {
1743 .name = "Penryn",
1744 .level = 10,
1745 .vendor = CPUID_VENDOR_INTEL,
1746 .family = 6,
1747 .model = 23,
1748 .stepping = 3,
1749 .features[FEAT_1_EDX] =
1750 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1751 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1752 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1753 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1754 CPUID_DE | CPUID_FP87,
1755 .features[FEAT_1_ECX] =
1756 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1757 CPUID_EXT_SSE3,
1758 .features[FEAT_8000_0001_EDX] =
1759 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1760 .features[FEAT_8000_0001_ECX] =
1761 CPUID_EXT3_LAHF_LM,
1762 .xlevel = 0x80000008,
1763 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1764 },
1765 {
1766 .name = "Nehalem",
1767 .level = 11,
1768 .vendor = CPUID_VENDOR_INTEL,
1769 .family = 6,
1770 .model = 26,
1771 .stepping = 3,
1772 .features[FEAT_1_EDX] =
1773 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1774 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1775 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1776 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1777 CPUID_DE | CPUID_FP87,
1778 .features[FEAT_1_ECX] =
1779 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1780 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1781 .features[FEAT_8000_0001_EDX] =
1782 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1783 .features[FEAT_8000_0001_ECX] =
1784 CPUID_EXT3_LAHF_LM,
1785 .xlevel = 0x80000008,
1786 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1787 },
1788 {
1789 .name = "Nehalem-IBRS",
1790 .level = 11,
1791 .vendor = CPUID_VENDOR_INTEL,
1792 .family = 6,
1793 .model = 26,
1794 .stepping = 3,
1795 .features[FEAT_1_EDX] =
1796 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1797 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1798 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1799 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1800 CPUID_DE | CPUID_FP87,
1801 .features[FEAT_1_ECX] =
1802 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1803 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1804 .features[FEAT_7_0_EDX] =
1805 CPUID_7_0_EDX_SPEC_CTRL,
1806 .features[FEAT_8000_0001_EDX] =
1807 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1808 .features[FEAT_8000_0001_ECX] =
1809 CPUID_EXT3_LAHF_LM,
1810 .xlevel = 0x80000008,
1811 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1812 },
1813 {
1814 .name = "Westmere",
1815 .level = 11,
1816 .vendor = CPUID_VENDOR_INTEL,
1817 .family = 6,
1818 .model = 44,
1819 .stepping = 1,
1820 .features[FEAT_1_EDX] =
1821 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1822 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1823 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1824 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1825 CPUID_DE | CPUID_FP87,
1826 .features[FEAT_1_ECX] =
1827 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1828 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1829 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1830 .features[FEAT_8000_0001_EDX] =
1831 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1832 .features[FEAT_8000_0001_ECX] =
1833 CPUID_EXT3_LAHF_LM,
1834 .features[FEAT_6_EAX] =
1835 CPUID_6_EAX_ARAT,
1836 .xlevel = 0x80000008,
1837 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1838 },
1839 {
1840 .name = "Westmere-IBRS",
1841 .level = 11,
1842 .vendor = CPUID_VENDOR_INTEL,
1843 .family = 6,
1844 .model = 44,
1845 .stepping = 1,
1846 .features[FEAT_1_EDX] =
1847 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1851 CPUID_DE | CPUID_FP87,
1852 .features[FEAT_1_ECX] =
1853 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1854 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1855 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1856 .features[FEAT_8000_0001_EDX] =
1857 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1858 .features[FEAT_8000_0001_ECX] =
1859 CPUID_EXT3_LAHF_LM,
1860 .features[FEAT_7_0_EDX] =
1861 CPUID_7_0_EDX_SPEC_CTRL,
1862 .features[FEAT_6_EAX] =
1863 CPUID_6_EAX_ARAT,
1864 .xlevel = 0x80000008,
1865 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1866 },
1867 {
1868 .name = "SandyBridge",
1869 .level = 0xd,
1870 .vendor = CPUID_VENDOR_INTEL,
1871 .family = 6,
1872 .model = 42,
1873 .stepping = 1,
1874 .features[FEAT_1_EDX] =
1875 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1876 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1877 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1878 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1879 CPUID_DE | CPUID_FP87,
1880 .features[FEAT_1_ECX] =
1881 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1882 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1883 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1884 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1885 CPUID_EXT_SSE3,
1886 .features[FEAT_8000_0001_EDX] =
1887 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1888 CPUID_EXT2_SYSCALL,
1889 .features[FEAT_8000_0001_ECX] =
1890 CPUID_EXT3_LAHF_LM,
1891 .features[FEAT_XSAVE] =
1892 CPUID_XSAVE_XSAVEOPT,
1893 .features[FEAT_6_EAX] =
1894 CPUID_6_EAX_ARAT,
1895 .xlevel = 0x80000008,
1896 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1897 },
1898 {
1899 .name = "SandyBridge-IBRS",
1900 .level = 0xd,
1901 .vendor = CPUID_VENDOR_INTEL,
1902 .family = 6,
1903 .model = 42,
1904 .stepping = 1,
1905 .features[FEAT_1_EDX] =
1906 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1907 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1908 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1909 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1910 CPUID_DE | CPUID_FP87,
1911 .features[FEAT_1_ECX] =
1912 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1913 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1914 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1915 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1916 CPUID_EXT_SSE3,
1917 .features[FEAT_8000_0001_EDX] =
1918 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1919 CPUID_EXT2_SYSCALL,
1920 .features[FEAT_8000_0001_ECX] =
1921 CPUID_EXT3_LAHF_LM,
1922 .features[FEAT_7_0_EDX] =
1923 CPUID_7_0_EDX_SPEC_CTRL,
1924 .features[FEAT_XSAVE] =
1925 CPUID_XSAVE_XSAVEOPT,
1926 .features[FEAT_6_EAX] =
1927 CPUID_6_EAX_ARAT,
1928 .xlevel = 0x80000008,
1929 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1930 },
1931 {
1932 .name = "IvyBridge",
1933 .level = 0xd,
1934 .vendor = CPUID_VENDOR_INTEL,
1935 .family = 6,
1936 .model = 58,
1937 .stepping = 9,
1938 .features[FEAT_1_EDX] =
1939 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1940 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1941 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1942 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1943 CPUID_DE | CPUID_FP87,
1944 .features[FEAT_1_ECX] =
1945 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1946 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1947 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1948 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1949 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1950 .features[FEAT_7_0_EBX] =
1951 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1952 CPUID_7_0_EBX_ERMS,
1953 .features[FEAT_8000_0001_EDX] =
1954 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1955 CPUID_EXT2_SYSCALL,
1956 .features[FEAT_8000_0001_ECX] =
1957 CPUID_EXT3_LAHF_LM,
1958 .features[FEAT_XSAVE] =
1959 CPUID_XSAVE_XSAVEOPT,
1960 .features[FEAT_6_EAX] =
1961 CPUID_6_EAX_ARAT,
1962 .xlevel = 0x80000008,
1963 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1964 },
1965 {
1966 .name = "IvyBridge-IBRS",
1967 .level = 0xd,
1968 .vendor = CPUID_VENDOR_INTEL,
1969 .family = 6,
1970 .model = 58,
1971 .stepping = 9,
1972 .features[FEAT_1_EDX] =
1973 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1977 CPUID_DE | CPUID_FP87,
1978 .features[FEAT_1_ECX] =
1979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1980 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1981 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1982 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1983 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1984 .features[FEAT_7_0_EBX] =
1985 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1986 CPUID_7_0_EBX_ERMS,
1987 .features[FEAT_8000_0001_EDX] =
1988 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1989 CPUID_EXT2_SYSCALL,
1990 .features[FEAT_8000_0001_ECX] =
1991 CPUID_EXT3_LAHF_LM,
1992 .features[FEAT_7_0_EDX] =
1993 CPUID_7_0_EDX_SPEC_CTRL,
1994 .features[FEAT_XSAVE] =
1995 CPUID_XSAVE_XSAVEOPT,
1996 .features[FEAT_6_EAX] =
1997 CPUID_6_EAX_ARAT,
1998 .xlevel = 0x80000008,
1999 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2000 },
2001 {
2002 .name = "Haswell-noTSX",
2003 .level = 0xd,
2004 .vendor = CPUID_VENDOR_INTEL,
2005 .family = 6,
2006 .model = 60,
2007 .stepping = 1,
2008 .features[FEAT_1_EDX] =
2009 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2013 CPUID_DE | CPUID_FP87,
2014 .features[FEAT_1_ECX] =
2015 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2016 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2017 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2018 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2019 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2020 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2021 .features[FEAT_8000_0001_EDX] =
2022 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2023 CPUID_EXT2_SYSCALL,
2024 .features[FEAT_8000_0001_ECX] =
2025 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2026 .features[FEAT_7_0_EBX] =
2027 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2028 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2029 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2030 .features[FEAT_XSAVE] =
2031 CPUID_XSAVE_XSAVEOPT,
2032 .features[FEAT_6_EAX] =
2033 CPUID_6_EAX_ARAT,
2034 .xlevel = 0x80000008,
2035 .model_id = "Intel Core Processor (Haswell, no TSX)",
2036 },
2037 {
2038 .name = "Haswell-noTSX-IBRS",
2039 .level = 0xd,
2040 .vendor = CPUID_VENDOR_INTEL,
2041 .family = 6,
2042 .model = 60,
2043 .stepping = 1,
2044 .features[FEAT_1_EDX] =
2045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2049 CPUID_DE | CPUID_FP87,
2050 .features[FEAT_1_ECX] =
2051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2052 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2053 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2054 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2055 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2056 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2057 .features[FEAT_8000_0001_EDX] =
2058 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2059 CPUID_EXT2_SYSCALL,
2060 .features[FEAT_8000_0001_ECX] =
2061 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2062 .features[FEAT_7_0_EDX] =
2063 CPUID_7_0_EDX_SPEC_CTRL,
2064 .features[FEAT_7_0_EBX] =
2065 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2066 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2067 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2068 .features[FEAT_XSAVE] =
2069 CPUID_XSAVE_XSAVEOPT,
2070 .features[FEAT_6_EAX] =
2071 CPUID_6_EAX_ARAT,
2072 .xlevel = 0x80000008,
2073 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2074 },
2075 {
2076 .name = "Haswell",
2077 .level = 0xd,
2078 .vendor = CPUID_VENDOR_INTEL,
2079 .family = 6,
2080 .model = 60,
2081 .stepping = 4,
2082 .features[FEAT_1_EDX] =
2083 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2084 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2085 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2086 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2087 CPUID_DE | CPUID_FP87,
2088 .features[FEAT_1_ECX] =
2089 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2090 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2091 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2092 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2093 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2094 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2095 .features[FEAT_8000_0001_EDX] =
2096 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2097 CPUID_EXT2_SYSCALL,
2098 .features[FEAT_8000_0001_ECX] =
2099 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2100 .features[FEAT_7_0_EBX] =
2101 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2102 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2103 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2104 CPUID_7_0_EBX_RTM,
2105 .features[FEAT_XSAVE] =
2106 CPUID_XSAVE_XSAVEOPT,
2107 .features[FEAT_6_EAX] =
2108 CPUID_6_EAX_ARAT,
2109 .xlevel = 0x80000008,
2110 .model_id = "Intel Core Processor (Haswell)",
2111 },
2112 {
2113 .name = "Haswell-IBRS",
2114 .level = 0xd,
2115 .vendor = CPUID_VENDOR_INTEL,
2116 .family = 6,
2117 .model = 60,
2118 .stepping = 4,
2119 .features[FEAT_1_EDX] =
2120 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2121 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2122 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2123 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2124 CPUID_DE | CPUID_FP87,
2125 .features[FEAT_1_ECX] =
2126 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2127 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2128 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2129 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2130 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2131 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2132 .features[FEAT_8000_0001_EDX] =
2133 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2134 CPUID_EXT2_SYSCALL,
2135 .features[FEAT_8000_0001_ECX] =
2136 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2137 .features[FEAT_7_0_EDX] =
2138 CPUID_7_0_EDX_SPEC_CTRL,
2139 .features[FEAT_7_0_EBX] =
2140 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2141 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2142 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2143 CPUID_7_0_EBX_RTM,
2144 .features[FEAT_XSAVE] =
2145 CPUID_XSAVE_XSAVEOPT,
2146 .features[FEAT_6_EAX] =
2147 CPUID_6_EAX_ARAT,
2148 .xlevel = 0x80000008,
2149 .model_id = "Intel Core Processor (Haswell, IBRS)",
2150 },
2151 {
2152 .name = "Broadwell-noTSX",
2153 .level = 0xd,
2154 .vendor = CPUID_VENDOR_INTEL,
2155 .family = 6,
2156 .model = 61,
2157 .stepping = 2,
2158 .features[FEAT_1_EDX] =
2159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2163 CPUID_DE | CPUID_FP87,
2164 .features[FEAT_1_ECX] =
2165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2171 .features[FEAT_8000_0001_EDX] =
2172 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2173 CPUID_EXT2_SYSCALL,
2174 .features[FEAT_8000_0001_ECX] =
2175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2176 .features[FEAT_7_0_EBX] =
2177 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2178 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2179 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2180 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2181 CPUID_7_0_EBX_SMAP,
2182 .features[FEAT_XSAVE] =
2183 CPUID_XSAVE_XSAVEOPT,
2184 .features[FEAT_6_EAX] =
2185 CPUID_6_EAX_ARAT,
2186 .xlevel = 0x80000008,
2187 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2188 },
2189 {
2190 .name = "Broadwell-noTSX-IBRS",
2191 .level = 0xd,
2192 .vendor = CPUID_VENDOR_INTEL,
2193 .family = 6,
2194 .model = 61,
2195 .stepping = 2,
2196 .features[FEAT_1_EDX] =
2197 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2198 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2199 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2200 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2201 CPUID_DE | CPUID_FP87,
2202 .features[FEAT_1_ECX] =
2203 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2204 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2205 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2206 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2207 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2208 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2209 .features[FEAT_8000_0001_EDX] =
2210 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2211 CPUID_EXT2_SYSCALL,
2212 .features[FEAT_8000_0001_ECX] =
2213 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2214 .features[FEAT_7_0_EDX] =
2215 CPUID_7_0_EDX_SPEC_CTRL,
2216 .features[FEAT_7_0_EBX] =
2217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2218 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2220 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2221 CPUID_7_0_EBX_SMAP,
2222 .features[FEAT_XSAVE] =
2223 CPUID_XSAVE_XSAVEOPT,
2224 .features[FEAT_6_EAX] =
2225 CPUID_6_EAX_ARAT,
2226 .xlevel = 0x80000008,
2227 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2228 },
2229 {
2230 .name = "Broadwell",
2231 .level = 0xd,
2232 .vendor = CPUID_VENDOR_INTEL,
2233 .family = 6,
2234 .model = 61,
2235 .stepping = 2,
2236 .features[FEAT_1_EDX] =
2237 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2238 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2239 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2240 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2241 CPUID_DE | CPUID_FP87,
2242 .features[FEAT_1_ECX] =
2243 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2244 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2245 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2246 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2247 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2248 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2249 .features[FEAT_8000_0001_EDX] =
2250 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2251 CPUID_EXT2_SYSCALL,
2252 .features[FEAT_8000_0001_ECX] =
2253 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2254 .features[FEAT_7_0_EBX] =
2255 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2256 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2257 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2258 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2259 CPUID_7_0_EBX_SMAP,
2260 .features[FEAT_XSAVE] =
2261 CPUID_XSAVE_XSAVEOPT,
2262 .features[FEAT_6_EAX] =
2263 CPUID_6_EAX_ARAT,
2264 .xlevel = 0x80000008,
2265 .model_id = "Intel Core Processor (Broadwell)",
2266 },
2267 {
2268 .name = "Broadwell-IBRS",
2269 .level = 0xd,
2270 .vendor = CPUID_VENDOR_INTEL,
2271 .family = 6,
2272 .model = 61,
2273 .stepping = 2,
2274 .features[FEAT_1_EDX] =
2275 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2276 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2277 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2278 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2279 CPUID_DE | CPUID_FP87,
2280 .features[FEAT_1_ECX] =
2281 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2282 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2283 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2284 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2285 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2286 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2287 .features[FEAT_8000_0001_EDX] =
2288 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2289 CPUID_EXT2_SYSCALL,
2290 .features[FEAT_8000_0001_ECX] =
2291 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2292 .features[FEAT_7_0_EDX] =
2293 CPUID_7_0_EDX_SPEC_CTRL,
2294 .features[FEAT_7_0_EBX] =
2295 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2296 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2297 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2298 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2299 CPUID_7_0_EBX_SMAP,
2300 .features[FEAT_XSAVE] =
2301 CPUID_XSAVE_XSAVEOPT,
2302 .features[FEAT_6_EAX] =
2303 CPUID_6_EAX_ARAT,
2304 .xlevel = 0x80000008,
2305 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2306 },
2307 {
2308 .name = "Skylake-Client",
2309 .level = 0xd,
2310 .vendor = CPUID_VENDOR_INTEL,
2311 .family = 6,
2312 .model = 94,
2313 .stepping = 3,
2314 .features[FEAT_1_EDX] =
2315 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2316 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2317 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2318 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2319 CPUID_DE | CPUID_FP87,
2320 .features[FEAT_1_ECX] =
2321 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2322 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2323 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2324 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2325 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2326 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2327 .features[FEAT_8000_0001_EDX] =
2328 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2329 CPUID_EXT2_SYSCALL,
2330 .features[FEAT_8000_0001_ECX] =
2331 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2332 .features[FEAT_7_0_EBX] =
2333 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2334 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2335 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2336 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2337 CPUID_7_0_EBX_SMAP,
2338 /* Missing: XSAVES (not supported by some Linux versions,
2339 * including v4.1 to v4.12).
2340 * KVM doesn't yet expose any XSAVES state save component,
2341 * and the only one defined in Skylake (processor tracing)
2342 * probably will block migration anyway.
2343 */
2344 .features[FEAT_XSAVE] =
2345 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2346 CPUID_XSAVE_XGETBV1,
2347 .features[FEAT_6_EAX] =
2348 CPUID_6_EAX_ARAT,
2349 .xlevel = 0x80000008,
2350 .model_id = "Intel Core Processor (Skylake)",
2351 },
2352 {
2353 .name = "Skylake-Client-IBRS",
2354 .level = 0xd,
2355 .vendor = CPUID_VENDOR_INTEL,
2356 .family = 6,
2357 .model = 94,
2358 .stepping = 3,
2359 .features[FEAT_1_EDX] =
2360 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2361 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2362 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2363 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2364 CPUID_DE | CPUID_FP87,
2365 .features[FEAT_1_ECX] =
2366 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2367 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2368 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2369 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2370 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2371 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2372 .features[FEAT_8000_0001_EDX] =
2373 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2374 CPUID_EXT2_SYSCALL,
2375 .features[FEAT_8000_0001_ECX] =
2376 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2377 .features[FEAT_7_0_EDX] =
2378 CPUID_7_0_EDX_SPEC_CTRL,
2379 .features[FEAT_7_0_EBX] =
2380 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2381 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2382 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2383 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2384 CPUID_7_0_EBX_SMAP,
2385 /* Missing: XSAVES (not supported by some Linux versions,
2386 * including v4.1 to v4.12).
2387 * KVM doesn't yet expose any XSAVES state save component,
2388 * and the only one defined in Skylake (processor tracing)
2389 * probably will block migration anyway.
2390 */
2391 .features[FEAT_XSAVE] =
2392 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2393 CPUID_XSAVE_XGETBV1,
2394 .features[FEAT_6_EAX] =
2395 CPUID_6_EAX_ARAT,
2396 .xlevel = 0x80000008,
2397 .model_id = "Intel Core Processor (Skylake, IBRS)",
2398 },
2399 {
2400 .name = "Skylake-Server",
2401 .level = 0xd,
2402 .vendor = CPUID_VENDOR_INTEL,
2403 .family = 6,
2404 .model = 85,
2405 .stepping = 4,
2406 .features[FEAT_1_EDX] =
2407 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2408 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2409 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2410 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2411 CPUID_DE | CPUID_FP87,
2412 .features[FEAT_1_ECX] =
2413 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2414 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2415 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2416 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2417 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2418 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2419 .features[FEAT_8000_0001_EDX] =
2420 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2421 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2422 .features[FEAT_8000_0001_ECX] =
2423 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2424 .features[FEAT_7_0_EBX] =
2425 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2426 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2427 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2428 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2429 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2430 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2431 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2432 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2433 .features[FEAT_7_0_ECX] =
2434 CPUID_7_0_ECX_PKU,
2435 /* Missing: XSAVES (not supported by some Linux versions,
2436 * including v4.1 to v4.12).
2437 * KVM doesn't yet expose any XSAVES state save component,
2438 * and the only one defined in Skylake (processor tracing)
2439 * probably will block migration anyway.
2440 */
2441 .features[FEAT_XSAVE] =
2442 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2443 CPUID_XSAVE_XGETBV1,
2444 .features[FEAT_6_EAX] =
2445 CPUID_6_EAX_ARAT,
2446 .xlevel = 0x80000008,
2447 .model_id = "Intel Xeon Processor (Skylake)",
2448 },
2449 {
2450 .name = "Skylake-Server-IBRS",
2451 .level = 0xd,
2452 .vendor = CPUID_VENDOR_INTEL,
2453 .family = 6,
2454 .model = 85,
2455 .stepping = 4,
2456 .features[FEAT_1_EDX] =
2457 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2458 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2459 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2460 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2461 CPUID_DE | CPUID_FP87,
2462 .features[FEAT_1_ECX] =
2463 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2464 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2465 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2466 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2467 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2468 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2469 .features[FEAT_8000_0001_EDX] =
2470 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2471 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2472 .features[FEAT_8000_0001_ECX] =
2473 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2474 .features[FEAT_7_0_EDX] =
2475 CPUID_7_0_EDX_SPEC_CTRL,
2476 .features[FEAT_7_0_EBX] =
2477 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2478 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2479 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2480 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2481 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2482 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2483 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2484 CPUID_7_0_EBX_AVX512VL,
2485 .features[FEAT_7_0_ECX] =
2486 CPUID_7_0_ECX_PKU,
2487 /* Missing: XSAVES (not supported by some Linux versions,
2488 * including v4.1 to v4.12).
2489 * KVM doesn't yet expose any XSAVES state save component,
2490 * and the only one defined in Skylake (processor tracing)
2491 * probably will block migration anyway.
2492 */
2493 .features[FEAT_XSAVE] =
2494 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2495 CPUID_XSAVE_XGETBV1,
2496 .features[FEAT_6_EAX] =
2497 CPUID_6_EAX_ARAT,
2498 .xlevel = 0x80000008,
2499 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2500 },
2501 {
2502 .name = "Cascadelake-Server",
2503 .level = 0xd,
2504 .vendor = CPUID_VENDOR_INTEL,
2505 .family = 6,
2506 .model = 85,
2507 .stepping = 6,
2508 .features[FEAT_1_EDX] =
2509 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2510 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2511 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2512 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2513 CPUID_DE | CPUID_FP87,
2514 .features[FEAT_1_ECX] =
2515 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2516 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2517 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2518 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2519 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2520 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2521 .features[FEAT_8000_0001_EDX] =
2522 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2523 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2524 .features[FEAT_8000_0001_ECX] =
2525 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2526 .features[FEAT_7_0_EBX] =
2527 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2528 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2529 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2530 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2531 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2532 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2533 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2534 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2535 .features[FEAT_7_0_ECX] =
2536 CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
2537 CPUID_7_0_ECX_AVX512VNNI,
2538 .features[FEAT_7_0_EDX] =
2539 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2540 /* Missing: XSAVES (not supported by some Linux versions,
2541 * including v4.1 to v4.12).
2542 * KVM doesn't yet expose any XSAVES state save component,
2543 * and the only one defined in Skylake (processor tracing)
2544 * probably will block migration anyway.
2545 */
2546 .features[FEAT_XSAVE] =
2547 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2548 CPUID_XSAVE_XGETBV1,
2549 .features[FEAT_6_EAX] =
2550 CPUID_6_EAX_ARAT,
2551 .xlevel = 0x80000008,
2552 .model_id = "Intel Xeon Processor (Cascadelake)",
2553 },
2554 {
2555 .name = "Icelake-Client",
2556 .level = 0xd,
2557 .vendor = CPUID_VENDOR_INTEL,
2558 .family = 6,
2559 .model = 126,
2560 .stepping = 0,
2561 .features[FEAT_1_EDX] =
2562 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2563 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2564 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2565 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2566 CPUID_DE | CPUID_FP87,
2567 .features[FEAT_1_ECX] =
2568 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2569 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2570 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2571 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2572 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2573 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2574 .features[FEAT_8000_0001_EDX] =
2575 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2576 CPUID_EXT2_SYSCALL,
2577 .features[FEAT_8000_0001_ECX] =
2578 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2579 .features[FEAT_8000_0008_EBX] =
2580 CPUID_8000_0008_EBX_WBNOINVD,
2581 .features[FEAT_7_0_EBX] =
2582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2586 CPUID_7_0_EBX_SMAP,
2587 .features[FEAT_7_0_ECX] =
2588 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2589 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2590 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2591 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2592 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2593 .features[FEAT_7_0_EDX] =
2594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2595 /* Missing: XSAVES (not supported by some Linux versions,
2596 * including v4.1 to v4.12).
2597 * KVM doesn't yet expose any XSAVES state save component,
2598 * and the only one defined in Skylake (processor tracing)
2599 * probably will block migration anyway.
2600 */
2601 .features[FEAT_XSAVE] =
2602 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2603 CPUID_XSAVE_XGETBV1,
2604 .features[FEAT_6_EAX] =
2605 CPUID_6_EAX_ARAT,
2606 .xlevel = 0x80000008,
2607 .model_id = "Intel Core Processor (Icelake)",
2608 },
2609 {
2610 .name = "Icelake-Server",
2611 .level = 0xd,
2612 .vendor = CPUID_VENDOR_INTEL,
2613 .family = 6,
2614 .model = 134,
2615 .stepping = 0,
2616 .features[FEAT_1_EDX] =
2617 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2621 CPUID_DE | CPUID_FP87,
2622 .features[FEAT_1_ECX] =
2623 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2624 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2625 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2626 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2627 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2628 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2629 .features[FEAT_8000_0001_EDX] =
2630 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2631 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2632 .features[FEAT_8000_0001_ECX] =
2633 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2634 .features[FEAT_8000_0008_EBX] =
2635 CPUID_8000_0008_EBX_WBNOINVD,
2636 .features[FEAT_7_0_EBX] =
2637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2638 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2640 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2641 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2642 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2643 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2644 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2645 .features[FEAT_7_0_ECX] =
2646 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2647 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2648 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2649 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2650 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2651 .features[FEAT_7_0_EDX] =
2652 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2653 /* Missing: XSAVES (not supported by some Linux versions,
2654 * including v4.1 to v4.12).
2655 * KVM doesn't yet expose any XSAVES state save component,
2656 * and the only one defined in Skylake (processor tracing)
2657 * probably will block migration anyway.
2658 */
2659 .features[FEAT_XSAVE] =
2660 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2661 CPUID_XSAVE_XGETBV1,
2662 .features[FEAT_6_EAX] =
2663 CPUID_6_EAX_ARAT,
2664 .xlevel = 0x80000008,
2665 .model_id = "Intel Xeon Processor (Icelake)",
2666 },
2667 {
2668 .name = "KnightsMill",
2669 .level = 0xd,
2670 .vendor = CPUID_VENDOR_INTEL,
2671 .family = 6,
2672 .model = 133,
2673 .stepping = 0,
2674 .features[FEAT_1_EDX] =
2675 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2676 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2677 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2678 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2679 CPUID_PSE | CPUID_DE | CPUID_FP87,
2680 .features[FEAT_1_ECX] =
2681 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2682 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2683 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2684 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2685 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2686 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2687 .features[FEAT_8000_0001_EDX] =
2688 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2689 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2690 .features[FEAT_8000_0001_ECX] =
2691 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2692 .features[FEAT_7_0_EBX] =
2693 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2694 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2695 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2696 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2697 CPUID_7_0_EBX_AVX512ER,
2698 .features[FEAT_7_0_ECX] =
2699 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2700 .features[FEAT_7_0_EDX] =
2701 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2702 .features[FEAT_XSAVE] =
2703 CPUID_XSAVE_XSAVEOPT,
2704 .features[FEAT_6_EAX] =
2705 CPUID_6_EAX_ARAT,
2706 .xlevel = 0x80000008,
2707 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2708 },
2709 {
2710 .name = "Opteron_G1",
2711 .level = 5,
2712 .vendor = CPUID_VENDOR_AMD,
2713 .family = 15,
2714 .model = 6,
2715 .stepping = 1,
2716 .features[FEAT_1_EDX] =
2717 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2718 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2719 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2720 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2721 CPUID_DE | CPUID_FP87,
2722 .features[FEAT_1_ECX] =
2723 CPUID_EXT_SSE3,
2724 .features[FEAT_8000_0001_EDX] =
2725 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2726 .xlevel = 0x80000008,
2727 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2728 },
2729 {
2730 .name = "Opteron_G2",
2731 .level = 5,
2732 .vendor = CPUID_VENDOR_AMD,
2733 .family = 15,
2734 .model = 6,
2735 .stepping = 1,
2736 .features[FEAT_1_EDX] =
2737 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2738 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2739 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2740 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2741 CPUID_DE | CPUID_FP87,
2742 .features[FEAT_1_ECX] =
2743 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
2744 .features[FEAT_8000_0001_EDX] =
2745 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2746 .features[FEAT_8000_0001_ECX] =
2747 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2748 .xlevel = 0x80000008,
2749 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2750 },
2751 {
2752 .name = "Opteron_G3",
2753 .level = 5,
2754 .vendor = CPUID_VENDOR_AMD,
2755 .family = 16,
2756 .model = 2,
2757 .stepping = 3,
2758 .features[FEAT_1_EDX] =
2759 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2760 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2761 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2762 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2763 CPUID_DE | CPUID_FP87,
2764 .features[FEAT_1_ECX] =
2765 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
2766 CPUID_EXT_SSE3,
2767 .features[FEAT_8000_0001_EDX] =
2768 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2769 CPUID_EXT2_RDTSCP,
2770 .features[FEAT_8000_0001_ECX] =
2771 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
2772 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2773 .xlevel = 0x80000008,
2774 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2775 },
2776 {
2777 .name = "Opteron_G4",
2778 .level = 0xd,
2779 .vendor = CPUID_VENDOR_AMD,
2780 .family = 21,
2781 .model = 1,
2782 .stepping = 2,
2783 .features[FEAT_1_EDX] =
2784 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2788 CPUID_DE | CPUID_FP87,
2789 .features[FEAT_1_ECX] =
2790 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2791 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2792 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2793 CPUID_EXT_SSE3,
2794 .features[FEAT_8000_0001_EDX] =
2795 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2796 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2797 .features[FEAT_8000_0001_ECX] =
2798 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2799 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2800 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2801 CPUID_EXT3_LAHF_LM,
2802 .features[FEAT_SVM] =
2803 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2804 /* no xsaveopt! */
2805 .xlevel = 0x8000001A,
2806 .model_id = "AMD Opteron 62xx class CPU",
2807 },
2808 {
2809 .name = "Opteron_G5",
2810 .level = 0xd,
2811 .vendor = CPUID_VENDOR_AMD,
2812 .family = 21,
2813 .model = 2,
2814 .stepping = 0,
2815 .features[FEAT_1_EDX] =
2816 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2820 CPUID_DE | CPUID_FP87,
2821 .features[FEAT_1_ECX] =
2822 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
2823 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2824 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2825 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2826 .features[FEAT_8000_0001_EDX] =
2827 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2828 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2829 .features[FEAT_8000_0001_ECX] =
2830 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2831 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2832 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2833 CPUID_EXT3_LAHF_LM,
2834 .features[FEAT_SVM] =
2835 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2836 /* no xsaveopt! */
2837 .xlevel = 0x8000001A,
2838 .model_id = "AMD Opteron 63xx class CPU",
2839 },
2840 {
2841 .name = "EPYC",
2842 .level = 0xd,
2843 .vendor = CPUID_VENDOR_AMD,
2844 .family = 23,
2845 .model = 1,
2846 .stepping = 2,
2847 .features[FEAT_1_EDX] =
2848 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2849 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2850 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2851 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2852 CPUID_VME | CPUID_FP87,
2853 .features[FEAT_1_ECX] =
2854 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2855 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2856 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2857 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2858 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2859 .features[FEAT_8000_0001_EDX] =
2860 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2861 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2862 CPUID_EXT2_SYSCALL,
2863 .features[FEAT_8000_0001_ECX] =
2864 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2865 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2866 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2867 CPUID_EXT3_TOPOEXT,
2868 .features[FEAT_7_0_EBX] =
2869 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2870 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2871 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2872 CPUID_7_0_EBX_SHA_NI,
2873 /* Missing: XSAVES (not supported by some Linux versions,
2874 * including v4.1 to v4.12).
2875 * KVM doesn't yet expose any XSAVES state save component.
2876 */
2877 .features[FEAT_XSAVE] =
2878 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2879 CPUID_XSAVE_XGETBV1,
2880 .features[FEAT_6_EAX] =
2881 CPUID_6_EAX_ARAT,
2882 .features[FEAT_SVM] =
2883 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2884 .xlevel = 0x8000001E,
2885 .model_id = "AMD EPYC Processor",
2886 .cache_info = &epyc_cache_info,
2887 },
2888 {
2889 .name = "EPYC-IBPB",
2890 .level = 0xd,
2891 .vendor = CPUID_VENDOR_AMD,
2892 .family = 23,
2893 .model = 1,
2894 .stepping = 2,
2895 .features[FEAT_1_EDX] =
2896 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2897 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2898 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2899 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2900 CPUID_VME | CPUID_FP87,
2901 .features[FEAT_1_ECX] =
2902 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2903 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2904 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2905 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2906 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2907 .features[FEAT_8000_0001_EDX] =
2908 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2909 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2910 CPUID_EXT2_SYSCALL,
2911 .features[FEAT_8000_0001_ECX] =
2912 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2913 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2914 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2915 CPUID_EXT3_TOPOEXT,
2916 .features[FEAT_8000_0008_EBX] =
2917 CPUID_8000_0008_EBX_IBPB,
2918 .features[FEAT_7_0_EBX] =
2919 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2920 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2921 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2922 CPUID_7_0_EBX_SHA_NI,
2923 /* Missing: XSAVES (not supported by some Linux versions,
2924 * including v4.1 to v4.12).
2925 * KVM doesn't yet expose any XSAVES state save component.
2926 */
2927 .features[FEAT_XSAVE] =
2928 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2929 CPUID_XSAVE_XGETBV1,
2930 .features[FEAT_6_EAX] =
2931 CPUID_6_EAX_ARAT,
2932 .features[FEAT_SVM] =
2933 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2934 .xlevel = 0x8000001E,
2935 .model_id = "AMD EPYC Processor (with IBPB)",
2936 .cache_info = &epyc_cache_info,
2937 },
2938 };
2939
2940 typedef struct PropValue {
2941 const char *prop, *value;
2942 } PropValue;
2943
2944 /* KVM-specific features that are automatically added/removed
2945 * from all CPU models when KVM is enabled.
2946 */
2947 static PropValue kvm_default_props[] = {
2948 { "kvmclock", "on" },
2949 { "kvm-nopiodelay", "on" },
2950 { "kvm-asyncpf", "on" },
2951 { "kvm-steal-time", "on" },
2952 { "kvm-pv-eoi", "on" },
2953 { "kvmclock-stable-bit", "on" },
2954 { "x2apic", "on" },
2955 { "acpi", "off" },
2956 { "monitor", "off" },
2957 { "svm", "off" },
2958 { NULL, NULL },
2959 };
2960
2961 /* TCG-specific defaults that override all CPU models when using TCG
2962 */
2963 static PropValue tcg_default_props[] = {
2964 { "vme", "off" },
2965 { NULL, NULL },
2966 };
2967
2968
2969 void x86_cpu_change_kvm_default(const char *prop, const char *value)
2970 {
2971 PropValue *pv;
2972 for (pv = kvm_default_props; pv->prop; pv++) {
2973 if (!strcmp(pv->prop, prop)) {
2974 pv->value = value;
2975 break;
2976 }
2977 }
2978
2979 /* It is valid to call this function only for properties that
2980 * are already present in the kvm_default_props table.
2981 */
2982 assert(pv->prop);
2983 }
2984
2985 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2986 bool migratable_only);
2987
2988 static bool lmce_supported(void)
2989 {
2990 uint64_t mce_cap = 0;
2991
2992 #ifdef CONFIG_KVM
2993 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2994 return false;
2995 }
2996 #endif
2997
2998 return !!(mce_cap & MCG_LMCE_P);
2999 }
3000
3001 #define CPUID_MODEL_ID_SZ 48
3002
3003 /**
3004 * cpu_x86_fill_model_id:
3005 * Get CPUID model ID string from host CPU.
3006 *
3007 * @str should have at least CPUID_MODEL_ID_SZ bytes
3008 *
3009 * The function does NOT add a null terminator to the string
3010 * automatically.
3011 */
3012 static int cpu_x86_fill_model_id(char *str)
3013 {
3014 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3015 int i;
3016
3017 for (i = 0; i < 3; i++) {
3018 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3019 memcpy(str + i * 16 + 0, &eax, 4);
3020 memcpy(str + i * 16 + 4, &ebx, 4);
3021 memcpy(str + i * 16 + 8, &ecx, 4);
3022 memcpy(str + i * 16 + 12, &edx, 4);
3023 }
3024 return 0;
3025 }
3026
3027 static Property max_x86_cpu_properties[] = {
3028 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
3029 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
3030 DEFINE_PROP_END_OF_LIST()
3031 };
3032
3033 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
3034 {
3035 DeviceClass *dc = DEVICE_CLASS(oc);
3036 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3037
3038 xcc->ordering = 9;
3039
3040 xcc->model_description =
3041 "Enables all features supported by the accelerator in the current host";
3042
3043 dc->props = max_x86_cpu_properties;
3044 }
3045
3046 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3047
3048 static void max_x86_cpu_initfn(Object *obj)
3049 {
3050 X86CPU *cpu = X86_CPU(obj);
3051 CPUX86State *env = &cpu->env;
3052 KVMState *s = kvm_state;
3053
3054 /* We can't fill the features array here because we don't know yet if
3055 * "migratable" is true or false.
3056 */
3057 cpu->max_features = true;
3058
3059 if (accel_uses_host_cpuid()) {
3060 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3061 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3062 int family, model, stepping;
3063 X86CPUDefinition host_cpudef = { };
3064 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3065
3066 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3067 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
3068
3069 host_vendor_fms(vendor, &family, &model, &stepping);
3070
3071 cpu_x86_fill_model_id(model_id);
3072
3073 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3074 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3075 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3076 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3077 &error_abort);
3078 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3079 &error_abort);
3080
3081 if (kvm_enabled()) {
3082 env->cpuid_min_level =
3083 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3084 env->cpuid_min_xlevel =
3085 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3086 env->cpuid_min_xlevel2 =
3087 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3088 } else {
3089 env->cpuid_min_level =
3090 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3091 env->cpuid_min_xlevel =
3092 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3093 env->cpuid_min_xlevel2 =
3094 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3095 }
3096
3097 if (lmce_supported()) {
3098 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3099 }
3100 } else {
3101 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3102 "vendor", &error_abort);
3103 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3104 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3105 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3106 object_property_set_str(OBJECT(cpu),
3107 "QEMU TCG CPU version " QEMU_HW_VERSION,
3108 "model-id", &error_abort);
3109 }
3110
3111 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
3112 }
3113
3114 static const TypeInfo max_x86_cpu_type_info = {
3115 .name = X86_CPU_TYPE_NAME("max"),
3116 .parent = TYPE_X86_CPU,
3117 .instance_init = max_x86_cpu_initfn,
3118 .class_init = max_x86_cpu_class_init,
3119 };
3120
3121 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3122 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3123 {
3124 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3125
3126 xcc->host_cpuid_required = true;
3127 xcc->ordering = 8;
3128
3129 #if defined(CONFIG_KVM)
3130 xcc->model_description =
3131 "KVM processor with all supported host features ";
3132 #elif defined(CONFIG_HVF)
3133 xcc->model_description =
3134 "HVF processor with all supported host features ";
3135 #endif
3136 }
3137
3138 static const TypeInfo host_x86_cpu_type_info = {
3139 .name = X86_CPU_TYPE_NAME("host"),
3140 .parent = X86_CPU_TYPE_NAME("max"),
3141 .class_init = host_x86_cpu_class_init,
3142 };
3143
3144 #endif
3145
3146 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3147 {
3148 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3149
3150 switch (f->type) {
3151 case CPUID_FEATURE_WORD:
3152 {
3153 const char *reg = get_register_name_32(f->cpuid.reg);
3154 assert(reg);
3155 return g_strdup_printf("CPUID.%02XH:%s",
3156 f->cpuid.eax, reg);
3157 }
3158 case MSR_FEATURE_WORD:
3159 return g_strdup_printf("MSR(%02XH)",
3160 f->msr.index);
3161 }
3162
3163 return NULL;
3164 }
3165
3166 static void report_unavailable_features(FeatureWord w, uint32_t mask)
3167 {
3168 FeatureWordInfo *f = &feature_word_info[w];
3169 int i;
3170 char *feat_word_str;
3171
3172 for (i = 0; i < 32; ++i) {
3173 if ((1UL << i) & mask) {
3174 feat_word_str = feature_word_description(f, i);
3175 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
3176 accel_uses_host_cpuid() ? "host" : "TCG",
3177 feat_word_str,
3178 f->feat_names[i] ? "." : "",
3179 f->feat_names[i] ? f->feat_names[i] : "", i);
3180 g_free(feat_word_str);
3181 }
3182 }
3183 }
3184
3185 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3186 const char *name, void *opaque,
3187 Error **errp)
3188 {
3189 X86CPU *cpu = X86_CPU(obj);
3190 CPUX86State *env = &cpu->env;
3191 int64_t value;
3192
3193 value = (env->cpuid_version >> 8) & 0xf;
3194 if (value == 0xf) {
3195 value += (env->cpuid_version >> 20) & 0xff;
3196 }
3197 visit_type_int(v, name, &value, errp);
3198 }
3199
3200 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3201 const char *name, void *opaque,
3202 Error **errp)
3203 {
3204 X86CPU *cpu = X86_CPU(obj);
3205 CPUX86State *env = &cpu->env;
3206 const int64_t min = 0;
3207 const int64_t max = 0xff + 0xf;
3208 Error *local_err = NULL;
3209 int64_t value;
3210
3211 visit_type_int(v, name, &value, &local_err);
3212 if (local_err) {
3213 error_propagate(errp, local_err);
3214 return;
3215 }
3216 if (value < min || value > max) {
3217 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3218 name ? name : "null", value, min, max);
3219 return;
3220 }
3221
3222 env->cpuid_version &= ~0xff00f00;
3223 if (value > 0x0f) {
3224 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
3225 } else {
3226 env->cpuid_version |= value << 8;
3227 }
3228 }
3229
3230 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3231 const char *name, void *opaque,
3232 Error **errp)
3233 {
3234 X86CPU *cpu = X86_CPU(obj);
3235 CPUX86State *env = &cpu->env;
3236 int64_t value;
3237
3238 value = (env->cpuid_version >> 4) & 0xf;
3239 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
3240 visit_type_int(v, name, &value, errp);
3241 }
3242
3243 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3244 const char *name, void *opaque,
3245 Error **errp)
3246 {
3247 X86CPU *cpu = X86_CPU(obj);
3248 CPUX86State *env = &cpu->env;
3249 const int64_t min = 0;
3250 const int64_t max = 0xff;
3251 Error *local_err = NULL;
3252 int64_t value;
3253
3254 visit_type_int(v, name, &value, &local_err);
3255 if (local_err) {
3256 error_propagate(errp, local_err);
3257 return;
3258 }
3259 if (value < min || value > max) {
3260 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3261 name ? name : "null", value, min, max);
3262 return;
3263 }
3264
3265 env->cpuid_version &= ~0xf00f0;
3266 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
3267 }
3268
3269 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
3270 const char *name, void *opaque,
3271 Error **errp)
3272 {
3273 X86CPU *cpu = X86_CPU(obj);
3274 CPUX86State *env = &cpu->env;
3275 int64_t value;
3276
3277 value = env->cpuid_version & 0xf;
3278 visit_type_int(v, name, &value, errp);
3279 }
3280
3281 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
3282 const char *name, void *opaque,
3283 Error **errp)
3284 {
3285 X86CPU *cpu = X86_CPU(obj);
3286 CPUX86State *env = &cpu->env;
3287 const int64_t min = 0;
3288 const int64_t max = 0xf;
3289 Error *local_err = NULL;
3290 int64_t value;
3291
3292 visit_type_int(v, name, &value, &local_err);
3293 if (local_err) {
3294 error_propagate(errp, local_err);
3295 return;
3296 }
3297 if (value < min || value > max) {
3298 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3299 name ? name : "null", value, min, max);
3300 return;
3301 }
3302
3303 env->cpuid_version &= ~0xf;
3304 env->cpuid_version |= value & 0xf;
3305 }
3306
3307 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3308 {
3309 X86CPU *cpu = X86_CPU(obj);
3310 CPUX86State *env = &cpu->env;
3311 char *value;
3312
3313 value = g_malloc(CPUID_VENDOR_SZ + 1);
3314 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3315 env->cpuid_vendor3);
3316 return value;
3317 }
3318
3319 static void x86_cpuid_set_vendor(Object *obj, const char *value,
3320 Error **errp)
3321 {
3322 X86CPU *cpu = X86_CPU(obj);
3323 CPUX86State *env = &cpu->env;
3324 int i;
3325
3326 if (strlen(value) != CPUID_VENDOR_SZ) {
3327 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
3328 return;
3329 }
3330
3331 env->cpuid_vendor1 = 0;
3332 env->cpuid_vendor2 = 0;
3333 env->cpuid_vendor3 = 0;
3334 for (i = 0; i < 4; i++) {
3335 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3336 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3337 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3338 }
3339 }
3340
3341 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3342 {
3343 X86CPU *cpu = X86_CPU(obj);
3344 CPUX86State *env = &cpu->env;
3345 char *value;
3346 int i;
3347
3348 value = g_malloc(48 + 1);
3349 for (i = 0; i < 48; i++) {
3350 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3351 }
3352 value[48] = '\0';
3353 return value;
3354 }
3355
3356 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3357 Error **errp)
3358 {
3359 X86CPU *cpu = X86_CPU(obj);
3360 CPUX86State *env = &cpu->env;
3361 int c, len, i;
3362
3363 if (model_id == NULL) {
3364 model_id = "";
3365 }
3366 len = strlen(model_id);
3367 memset(env->cpuid_model, 0, 48);
3368 for (i = 0; i < 48; i++) {
3369 if (i >= len) {
3370 c = '\0';
3371 } else {
3372 c = (uint8_t)model_id[i];
3373 }
3374 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3375 }
3376 }
3377
3378 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3379 void *opaque, Error **errp)
3380 {
3381 X86CPU *cpu = X86_CPU(obj);
3382 int64_t value;
3383
3384 value = cpu->env.tsc_khz * 1000;
3385 visit_type_int(v, name, &value, errp);
3386 }
3387
3388 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3389 void *opaque, Error **errp)
3390 {
3391 X86CPU *cpu = X86_CPU(obj);
3392 const int64_t min = 0;
3393 const int64_t max = INT64_MAX;
3394 Error *local_err = NULL;
3395 int64_t value;
3396
3397 visit_type_int(v, name, &value, &local_err);
3398 if (local_err) {
3399 error_propagate(errp, local_err);
3400 return;
3401 }
3402 if (value < min || value > max) {
3403 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3404 name ? name : "null", value, min, max);
3405 return;
3406 }
3407
3408 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
3409 }
3410
3411 /* Generic getter for "feature-words" and "filtered-features" properties */
3412 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3413 const char *name, void *opaque,
3414 Error **errp)
3415 {
3416 uint32_t *array = (uint32_t *)opaque;
3417 FeatureWord w;
3418 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3419 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3420 X86CPUFeatureWordInfoList *list = NULL;
3421
3422 for (w = 0; w < FEATURE_WORDS; w++) {
3423 FeatureWordInfo *wi = &feature_word_info[w];
3424 /*
3425 * We didn't have MSR features when "feature-words" was
3426 * introduced. Therefore skipped other type entries.
3427 */
3428 if (wi->type != CPUID_FEATURE_WORD) {
3429 continue;
3430 }
3431 X86CPUFeatureWordInfo *qwi = &word_infos[w];
3432 qwi->cpuid_input_eax = wi->cpuid.eax;
3433 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3434 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3435 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
3436 qwi->features = array[w];
3437
3438 /* List will be in reverse order, but order shouldn't matter */
3439 list_entries[w].next = list;
3440 list_entries[w].value = &word_infos[w];
3441 list = &list_entries[w];
3442 }
3443
3444 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
3445 }
3446
3447 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3448 void *opaque, Error **errp)
3449 {
3450 X86CPU *cpu = X86_CPU(obj);
3451 int64_t value = cpu->hyperv_spinlock_attempts;
3452
3453 visit_type_int(v, name, &value, errp);
3454 }
3455
3456 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3457 void *opaque, Error **errp)
3458 {
3459 const int64_t min = 0xFFF;
3460 const int64_t max = UINT_MAX;
3461 X86CPU *cpu = X86_CPU(obj);
3462 Error *err = NULL;
3463 int64_t value;
3464
3465 visit_type_int(v, name, &value, &err);
3466 if (err) {
3467 error_propagate(errp, err);
3468 return;
3469 }
3470
3471 if (value < min || value > max) {
3472 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
3473 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3474 object_get_typename(obj), name ? name : "null",
3475 value, min, max);
3476 return;
3477 }
3478 cpu->hyperv_spinlock_attempts = value;
3479 }
3480
3481 static const PropertyInfo qdev_prop_spinlocks = {
3482 .name = "int",
3483 .get = x86_get_hv_spinlocks,
3484 .set = x86_set_hv_spinlocks,
3485 };
3486
3487 /* Convert all '_' in a feature string option name to '-', to make feature
3488 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3489 */
3490 static inline void feat2prop(char *s)
3491 {
3492 while ((s = strchr(s, '_'))) {
3493 *s = '-';
3494 }
3495 }
3496
3497 /* Return the feature property name for a feature flag bit */
3498 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3499 {
3500 /* XSAVE components are automatically enabled by other features,
3501 * so return the original feature name instead
3502 */
3503 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3504 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3505
3506 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3507 x86_ext_save_areas[comp].bits) {
3508 w = x86_ext_save_areas[comp].feature;
3509 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3510 }
3511 }
3512
3513 assert(bitnr < 32);
3514 assert(w < FEATURE_WORDS);
3515 return feature_word_info[w].feat_names[bitnr];
3516 }
3517
3518 /* Compatibily hack to maintain legacy +-feat semantic,
3519 * where +-feat overwrites any feature set by
3520 * feat=on|feat even if the later is parsed after +-feat
3521 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3522 */
3523 static GList *plus_features, *minus_features;
3524
3525 static gint compare_string(gconstpointer a, gconstpointer b)
3526 {
3527 return g_strcmp0(a, b);
3528 }
3529
3530 /* Parse "+feature,-feature,feature=foo" CPU feature string
3531 */
3532 static void x86_cpu_parse_featurestr(const char *typename, char *features,
3533 Error **errp)
3534 {
3535 char *featurestr; /* Single 'key=value" string being parsed */
3536 static bool cpu_globals_initialized;
3537 bool ambiguous = false;
3538
3539 if (cpu_globals_initialized) {
3540 return;
3541 }
3542 cpu_globals_initialized = true;
3543
3544 if (!features) {
3545 return;
3546 }
3547
3548 for (featurestr = strtok(features, ",");
3549 featurestr;
3550 featurestr = strtok(NULL, ",")) {
3551 const char *name;
3552 const char *val = NULL;
3553 char *eq = NULL;
3554 char num[32];
3555 GlobalProperty *prop;
3556
3557 /* Compatibility syntax: */
3558 if (featurestr[0] == '+') {
3559 plus_features = g_list_append(plus_features,
3560 g_strdup(featurestr + 1));
3561 continue;
3562 } else if (featurestr[0] == '-') {
3563 minus_features = g_list_append(minus_features,
3564 g_strdup(featurestr + 1));
3565 continue;
3566 }
3567
3568 eq = strchr(featurestr, '=');
3569 if (eq) {
3570 *eq++ = 0;
3571 val = eq;
3572 } else {
3573 val = "on";
3574 }
3575
3576 feat2prop(featurestr);
3577 name = featurestr;
3578
3579 if (g_list_find_custom(plus_features, name, compare_string)) {
3580 warn_report("Ambiguous CPU model string. "
3581 "Don't mix both \"+%s\" and \"%s=%s\"",
3582 name, name, val);
3583 ambiguous = true;
3584 }
3585 if (g_list_find_custom(minus_features, name, compare_string)) {
3586 warn_report("Ambiguous CPU model string. "
3587 "Don't mix both \"-%s\" and \"%s=%s\"",
3588 name, name, val);
3589 ambiguous = true;
3590 }
3591
3592 /* Special case: */
3593 if (!strcmp(name, "tsc-freq")) {
3594 int ret;
3595 uint64_t tsc_freq;
3596
3597 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
3598 if (ret < 0 || tsc_freq > INT64_MAX) {
3599 error_setg(errp, "bad numerical value %s", val);
3600 return;
3601 }
3602 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3603 val = num;
3604 name = "tsc-frequency";
3605 }
3606
3607 prop = g_new0(typeof(*prop), 1);
3608 prop->driver = typename;
3609 prop->property = g_strdup(name);
3610 prop->value = g_strdup(val);
3611 qdev_prop_register_global(prop);
3612 }
3613
3614 if (ambiguous) {
3615 warn_report("Compatibility of ambiguous CPU model "
3616 "strings won't be kept on future QEMU versions");
3617 }
3618 }
3619
3620 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
3621 static int x86_cpu_filter_features(X86CPU *cpu);
3622
3623 /* Check for missing features that may prevent the CPU class from
3624 * running using the current machine and accelerator.
3625 */
3626 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3627 strList **missing_feats)
3628 {
3629 X86CPU *xc;
3630 FeatureWord w;
3631 Error *err = NULL;
3632 strList **next = missing_feats;
3633
3634 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
3635 strList *new = g_new0(strList, 1);
3636 new->value = g_strdup("kvm");
3637 *missing_feats = new;
3638 return;
3639 }
3640
3641 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3642
3643 x86_cpu_expand_features(xc, &err);
3644 if (err) {
3645 /* Errors at x86_cpu_expand_features should never happen,
3646 * but in case it does, just report the model as not
3647 * runnable at all using the "type" property.
3648 */
3649 strList *new = g_new0(strList, 1);
3650 new->value = g_strdup("type");
3651 *next = new;
3652 next = &new->next;
3653 }
3654
3655 x86_cpu_filter_features(xc);
3656
3657 for (w = 0; w < FEATURE_WORDS; w++) {
3658 uint32_t filtered = xc->filtered_features[w];
3659 int i;
3660 for (i = 0; i < 32; i++) {
3661 if (filtered & (1UL << i)) {
3662 strList *new = g_new0(strList, 1);
3663 new->value = g_strdup(x86_cpu_feature_name(w, i));
3664 *next = new;
3665 next = &new->next;
3666 }
3667 }
3668 }
3669
3670 object_unref(OBJECT(xc));
3671 }
3672
3673 /* Print all cpuid feature names in featureset
3674 */
3675 static void listflags(FILE *f, fprintf_function print, GList *features)
3676 {
3677 size_t len = 0;
3678 GList *tmp;
3679
3680 for (tmp = features; tmp; tmp = tmp->next) {
3681 const char *name = tmp->data;
3682 if ((len + strlen(name) + 1) >= 75) {
3683 print(f, "\n");
3684 len = 0;
3685 }
3686 print(f, "%s%s", len == 0 ? " " : " ", name);
3687 len += strlen(name) + 1;
3688 }
3689 print(f, "\n");
3690 }
3691
3692 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
3693 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3694 {
3695 ObjectClass *class_a = (ObjectClass *)a;
3696 ObjectClass *class_b = (ObjectClass *)b;
3697 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3698 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
3699 char *name_a, *name_b;
3700 int ret;
3701
3702 if (cc_a->ordering != cc_b->ordering) {
3703 ret = cc_a->ordering - cc_b->ordering;
3704 } else {
3705 name_a = x86_cpu_class_get_model_name(cc_a);
3706 name_b = x86_cpu_class_get_model_name(cc_b);
3707 ret = strcmp(name_a, name_b);
3708 g_free(name_a);
3709 g_free(name_b);
3710 }
3711 return ret;
3712 }
3713
3714 static GSList *get_sorted_cpu_model_list(void)
3715 {
3716 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3717 list = g_slist_sort(list, x86_cpu_list_compare);
3718 return list;
3719 }
3720
3721 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3722 {
3723 ObjectClass *oc = data;
3724 X86CPUClass *cc = X86_CPU_CLASS(oc);
3725 CPUListState *s = user_data;
3726 char *name = x86_cpu_class_get_model_name(cc);
3727 const char *desc = cc->model_description;
3728 if (!desc && cc->cpu_def) {
3729 desc = cc->cpu_def->model_id;
3730 }
3731
3732 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
3733 name, desc);
3734 g_free(name);
3735 }
3736
3737 /* list available CPU models and flags */
3738 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3739 {
3740 int i, j;
3741 CPUListState s = {
3742 .file = f,
3743 .cpu_fprintf = cpu_fprintf,
3744 };
3745 GSList *list;
3746 GList *names = NULL;
3747
3748 (*cpu_fprintf)(f, "Available CPUs:\n");
3749 list = get_sorted_cpu_model_list();
3750 g_slist_foreach(list, x86_cpu_list_entry, &s);
3751 g_slist_free(list);
3752
3753 names = NULL;
3754 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3755 FeatureWordInfo *fw = &feature_word_info[i];
3756 for (j = 0; j < 32; j++) {
3757 if (fw->feat_names[j]) {
3758 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3759 }
3760 }
3761 }
3762
3763 names = g_list_sort(names, (GCompareFunc)strcmp);
3764
3765 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3766 listflags(f, cpu_fprintf, names);
3767 (*cpu_fprintf)(f, "\n");
3768 g_list_free(names);
3769 }
3770
3771 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3772 {
3773 ObjectClass *oc = data;
3774 X86CPUClass *cc = X86_CPU_CLASS(oc);
3775 CpuDefinitionInfoList **cpu_list = user_data;
3776 CpuDefinitionInfoList *entry;
3777 CpuDefinitionInfo *info;
3778
3779 info = g_malloc0(sizeof(*info));
3780 info->name = x86_cpu_class_get_model_name(cc);
3781 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3782 info->has_unavailable_features = true;
3783 info->q_typename = g_strdup(object_class_get_name(oc));
3784 info->migration_safe = cc->migration_safe;
3785 info->has_migration_safe = true;
3786 info->q_static = cc->static_model;
3787
3788 entry = g_malloc0(sizeof(*entry));
3789 entry->value = info;
3790 entry->next = *cpu_list;
3791 *cpu_list = entry;
3792 }
3793
3794 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
3795 {
3796 CpuDefinitionInfoList *cpu_list = NULL;
3797 GSList *list = get_sorted_cpu_model_list();
3798 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3799 g_slist_free(list);
3800 return cpu_list;
3801 }
3802
3803 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3804 bool migratable_only)
3805 {
3806 FeatureWordInfo *wi = &feature_word_info[w];
3807 uint32_t r = 0;
3808
3809 if (kvm_enabled()) {
3810 switch (wi->type) {
3811 case CPUID_FEATURE_WORD:
3812 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3813 wi->cpuid.ecx,
3814 wi->cpuid.reg);
3815 break;
3816 case MSR_FEATURE_WORD:
3817 r = kvm_arch_get_supported_msr_feature(kvm_state,
3818 wi->msr.index);
3819 break;
3820 }
3821 } else if (hvf_enabled()) {
3822 if (wi->type != CPUID_FEATURE_WORD) {
3823 return 0;
3824 }
3825 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3826 wi->cpuid.ecx,
3827 wi->cpuid.reg);
3828 } else if (tcg_enabled()) {
3829 r = wi->tcg_features;
3830 } else {
3831 return ~0;
3832 }
3833 if (migratable_only) {
3834 r &= x86_cpu_get_migratable_flags(w);
3835 }
3836 return r;
3837 }
3838
3839 static void x86_cpu_report_filtered_features(X86CPU *cpu)
3840 {
3841 FeatureWord w;
3842
3843 for (w = 0; w < FEATURE_WORDS; w++) {
3844 report_unavailable_features(w, cpu->filtered_features[w]);
3845 }
3846 }
3847
3848 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3849 {
3850 PropValue *pv;
3851 for (pv = props; pv->prop; pv++) {
3852 if (!pv->value) {
3853 continue;
3854 }
3855 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3856 &error_abort);
3857 }
3858 }
3859
3860 /* Load data from X86CPUDefinition into a X86CPU object
3861 */
3862 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
3863 {
3864 CPUX86State *env = &cpu->env;
3865 const char *vendor;
3866 char host_vendor[CPUID_VENDOR_SZ + 1];
3867 FeatureWord w;
3868
3869 /*NOTE: any property set by this function should be returned by
3870 * x86_cpu_static_props(), so static expansion of
3871 * query-cpu-model-expansion is always complete.
3872 */
3873
3874 /* CPU models only set _minimum_ values for level/xlevel: */
3875 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3876 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
3877
3878 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3879 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3880 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
3881 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
3882 for (w = 0; w < FEATURE_WORDS; w++) {
3883 env->features[w] = def->features[w];
3884 }
3885
3886 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3887 cpu->legacy_cache = !def->cache_info;
3888
3889 /* Special cases not set in the X86CPUDefinition structs: */
3890 /* TODO: in-kernel irqchip for hvf */
3891 if (kvm_enabled()) {
3892 if (!kvm_irqchip_in_kernel()) {
3893 x86_cpu_change_kvm_default("x2apic", "off");
3894 }
3895
3896 x86_cpu_apply_props(cpu, kvm_default_props);
3897 } else if (tcg_enabled()) {
3898 x86_cpu_apply_props(cpu, tcg_default_props);
3899 }
3900
3901 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
3902
3903 /* sysenter isn't supported in compatibility mode on AMD,
3904 * syscall isn't supported in compatibility mode on Intel.
3905 * Normally we advertise the actual CPU vendor, but you can
3906 * override this using the 'vendor' property if you want to use
3907 * KVM's sysenter/syscall emulation in compatibility mode and
3908 * when doing cross vendor migration
3909 */
3910 vendor = def->vendor;
3911 if (accel_uses_host_cpuid()) {
3912 uint32_t ebx = 0, ecx = 0, edx = 0;
3913 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3914 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3915 vendor = host_vendor;
3916 }
3917
3918 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3919
3920 }
3921
3922 #ifndef CONFIG_USER_ONLY
3923 /* Return a QDict containing keys for all properties that can be included
3924 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3925 * must be included in the dictionary.
3926 */
3927 static QDict *x86_cpu_static_props(void)
3928 {
3929 FeatureWord w;
3930 int i;
3931 static const char *props[] = {
3932 "min-level",
3933 "min-xlevel",
3934 "family",
3935 "model",
3936 "stepping",
3937 "model-id",
3938 "vendor",
3939 "lmce",
3940 NULL,
3941 };
3942 static QDict *d;
3943
3944 if (d) {
3945 return d;
3946 }
3947
3948 d = qdict_new();
3949 for (i = 0; props[i]; i++) {
3950 qdict_put_null(d, props[i]);
3951 }
3952
3953 for (w = 0; w < FEATURE_WORDS; w++) {
3954 FeatureWordInfo *fi = &feature_word_info[w];
3955 int bit;
3956 for (bit = 0; bit < 32; bit++) {
3957 if (!fi->feat_names[bit]) {
3958 continue;
3959 }
3960 qdict_put_null(d, fi->feat_names[bit]);
3961 }
3962 }
3963
3964 return d;
3965 }
3966
3967 /* Add an entry to @props dict, with the value for property. */
3968 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3969 {
3970 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3971 &error_abort);
3972
3973 qdict_put_obj(props, prop, value);
3974 }
3975
3976 /* Convert CPU model data from X86CPU object to a property dictionary
3977 * that can recreate exactly the same CPU model.
3978 */
3979 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3980 {
3981 QDict *sprops = x86_cpu_static_props();
3982 const QDictEntry *e;
3983
3984 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3985 const char *prop = qdict_entry_key(e);
3986 x86_cpu_expand_prop(cpu, props, prop);
3987 }
3988 }
3989
3990 /* Convert CPU model data from X86CPU object to a property dictionary
3991 * that can recreate exactly the same CPU model, including every
3992 * writeable QOM property.
3993 */
3994 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3995 {
3996 ObjectPropertyIterator iter;
3997 ObjectProperty *prop;
3998
3999 object_property_iter_init(&iter, OBJECT(cpu));
4000 while ((prop = object_property_iter_next(&iter))) {
4001 /* skip read-only or write-only properties */
4002 if (!prop->get || !prop->set) {
4003 continue;
4004 }
4005
4006 /* "hotplugged" is the only property that is configurable
4007 * on the command-line but will be set differently on CPUs
4008 * created using "-cpu ... -smp ..." and by CPUs created
4009 * on the fly by x86_cpu_from_model() for querying. Skip it.
4010 */
4011 if (!strcmp(prop->name, "hotplugged")) {
4012 continue;
4013 }
4014 x86_cpu_expand_prop(cpu, props, prop->name);
4015 }
4016 }
4017
4018 static void object_apply_props(Object *obj, QDict *props, Error **errp)
4019 {
4020 const QDictEntry *prop;
4021 Error *err = NULL;
4022
4023 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4024 object_property_set_qobject(obj, qdict_entry_value(prop),
4025 qdict_entry_key(prop), &err);
4026 if (err) {
4027 break;
4028 }
4029 }
4030
4031 error_propagate(errp, err);
4032 }
4033
4034 /* Create X86CPU object according to model+props specification */
4035 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4036 {
4037 X86CPU *xc = NULL;
4038 X86CPUClass *xcc;
4039 Error *err = NULL;
4040
4041 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4042 if (xcc == NULL) {
4043 error_setg(&err, "CPU model '%s' not found", model);
4044 goto out;
4045 }
4046
4047 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4048 if (props) {
4049 object_apply_props(OBJECT(xc), props, &err);
4050 if (err) {
4051 goto out;
4052 }
4053 }
4054
4055 x86_cpu_expand_features(xc, &err);
4056 if (err) {
4057 goto out;
4058 }
4059
4060 out:
4061 if (err) {
4062 error_propagate(errp, err);
4063 object_unref(OBJECT(xc));
4064 xc = NULL;
4065 }
4066 return xc;
4067 }
4068
4069 CpuModelExpansionInfo *
4070 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
4071 CpuModelInfo *model,
4072 Error **errp)
4073 {
4074 X86CPU *xc = NULL;
4075 Error *err = NULL;
4076 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4077 QDict *props = NULL;
4078 const char *base_name;
4079
4080 xc = x86_cpu_from_model(model->name,
4081 model->has_props ?
4082 qobject_to(QDict, model->props) :
4083 NULL, &err);
4084 if (err) {
4085 goto out;
4086 }
4087
4088 props = qdict_new();
4089 ret->model = g_new0(CpuModelInfo, 1);
4090 ret->model->props = QOBJECT(props);
4091 ret->model->has_props = true;
4092
4093 switch (type) {
4094 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4095 /* Static expansion will be based on "base" only */
4096 base_name = "base";
4097 x86_cpu_to_dict(xc, props);
4098 break;
4099 case CPU_MODEL_EXPANSION_TYPE_FULL:
4100 /* As we don't return every single property, full expansion needs
4101 * to keep the original model name+props, and add extra
4102 * properties on top of that.
4103 */
4104 base_name = model->name;
4105 x86_cpu_to_dict_full(xc, props);
4106 break;
4107 default:
4108 error_setg(&err, "Unsupported expansion type");
4109 goto out;
4110 }
4111
4112 x86_cpu_to_dict(xc, props);
4113
4114 ret->model->name = g_strdup(base_name);
4115
4116 out:
4117 object_unref(OBJECT(xc));
4118 if (err) {
4119 error_propagate(errp, err);
4120 qapi_free_CpuModelExpansionInfo(ret);
4121 ret = NULL;
4122 }
4123 return ret;
4124 }
4125 #endif /* !CONFIG_USER_ONLY */
4126
4127 static gchar *x86_gdb_arch_name(CPUState *cs)
4128 {
4129 #ifdef TARGET_X86_64
4130 return g_strdup("i386:x86-64");
4131 #else
4132 return g_strdup("i386");
4133 #endif
4134 }
4135
4136 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4137 {
4138 X86CPUDefinition *cpudef = data;
4139 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4140
4141 xcc->cpu_def = cpudef;
4142 xcc->migration_safe = true;
4143 }
4144
4145 static void x86_register_cpudef_type(X86CPUDefinition *def)
4146 {
4147 char *typename = x86_cpu_type_name(def->name);
4148 TypeInfo ti = {
4149 .name = typename,
4150 .parent = TYPE_X86_CPU,
4151 .class_init = x86_cpu_cpudef_class_init,
4152 .class_data = def,
4153 };
4154
4155 /* AMD aliases are handled at runtime based on CPUID vendor, so
4156 * they shouldn't be set on the CPU model table.
4157 */
4158 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
4159 /* catch mistakes instead of silently truncating model_id when too long */
4160 assert(def->model_id && strlen(def->model_id) <= 48);
4161
4162
4163 type_register(&ti);
4164 g_free(typename);
4165 }
4166
4167 #if !defined(CONFIG_USER_ONLY)
4168
4169 void cpu_clear_apic_feature(CPUX86State *env)
4170 {
4171 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
4172 }
4173
4174 #endif /* !CONFIG_USER_ONLY */
4175
4176 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4177 uint32_t *eax, uint32_t *ebx,
4178 uint32_t *ecx, uint32_t *edx)
4179 {
4180 X86CPU *cpu = x86_env_get_cpu(env);
4181 CPUState *cs = CPU(cpu);
4182 uint32_t pkg_offset;
4183 uint32_t limit;
4184 uint32_t signature[3];
4185
4186 /* Calculate & apply limits for different index ranges */
4187 if (index >= 0xC0000000) {
4188 limit = env->cpuid_xlevel2;
4189 } else if (index >= 0x80000000) {
4190 limit = env->cpuid_xlevel;
4191 } else if (index >= 0x40000000) {
4192 limit = 0x40000001;
4193 } else {
4194 limit = env->cpuid_level;
4195 }
4196
4197 if (index > limit) {
4198 /* Intel documentation states that invalid EAX input will
4199 * return the same information as EAX=cpuid_level
4200 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4201 */
4202 index = env->cpuid_level;
4203 }
4204
4205 switch(index) {
4206 case 0:
4207 *eax = env->cpuid_level;
4208 *ebx = env->cpuid_vendor1;
4209 *edx = env->cpuid_vendor2;
4210 *ecx = env->cpuid_vendor3;
4211 break;
4212 case 1:
4213 *eax = env->cpuid_version;
4214 *ebx = (cpu->apic_id << 24) |
4215 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
4216 *ecx = env->features[FEAT_1_ECX];
4217 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4218 *ecx |= CPUID_EXT_OSXSAVE;
4219 }
4220 *edx = env->features[FEAT_1_EDX];
4221 if (cs->nr_cores * cs->nr_threads > 1) {
4222 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
4223 *edx |= CPUID_HT;
4224 }
4225 break;
4226 case 2:
4227 /* cache info: needed for Pentium Pro compatibility */
4228 if (cpu->cache_info_passthrough) {
4229 host_cpuid(index, 0, eax, ebx, ecx, edx);
4230 break;
4231 }
4232 *eax = 1; /* Number of CPUID[EAX=2] calls required */
4233 *ebx = 0;
4234 if (!cpu->enable_l3_cache) {
4235 *ecx = 0;
4236 } else {
4237 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
4238 }
4239 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4240 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4241 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
4242 break;
4243 case 4:
4244 /* cache info: needed for Core compatibility */
4245 if (cpu->cache_info_passthrough) {
4246 host_cpuid(index, count, eax, ebx, ecx, edx);
4247 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
4248 *eax &= ~0xFC000000;
4249 if ((*eax & 31) && cs->nr_cores > 1) {
4250 *eax |= (cs->nr_cores - 1) << 26;
4251 }
4252 } else {
4253 *eax = 0;
4254 switch (count) {
4255 case 0: /* L1 dcache info */
4256 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4257 1, cs->nr_cores,
4258 eax, ebx, ecx, edx);
4259 break;
4260 case 1: /* L1 icache info */
4261 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4262 1, cs->nr_cores,
4263 eax, ebx, ecx, edx);
4264 break;
4265 case 2: /* L2 cache info */
4266 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4267 cs->nr_threads, cs->nr_cores,
4268 eax, ebx, ecx, edx);
4269 break;
4270 case 3: /* L3 cache info */
4271 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4272 if (cpu->enable_l3_cache) {
4273 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4274 (1 << pkg_offset), cs->nr_cores,
4275 eax, ebx, ecx, edx);
4276 break;
4277 }
4278 /* fall through */
4279 default: /* end of info */
4280 *eax = *ebx = *ecx = *edx = 0;
4281 break;
4282 }
4283 }
4284 break;
4285 case 5:
4286 /* MONITOR/MWAIT Leaf */
4287 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4288 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4289 *ecx = cpu->mwait.ecx; /* flags */
4290 *edx = cpu->mwait.edx; /* mwait substates */
4291 break;
4292 case 6:
4293 /* Thermal and Power Leaf */
4294 *eax = env->features[FEAT_6_EAX];
4295 *ebx = 0;
4296 *ecx = 0;
4297 *edx = 0;
4298 break;
4299 case 7:
4300 /* Structured Extended Feature Flags Enumeration Leaf */
4301 if (count == 0) {
4302 *eax = 0; /* Maximum ECX value for sub-leaves */
4303 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
4304 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
4305 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4306 *ecx |= CPUID_7_0_ECX_OSPKE;
4307 }
4308 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
4309 } else {
4310 *eax = 0;
4311 *ebx = 0;
4312 *ecx = 0;
4313 *edx = 0;
4314 }
4315 break;
4316 case 9:
4317 /* Direct Cache Access Information Leaf */
4318 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4319 *ebx = 0;
4320 *ecx = 0;
4321 *edx = 0;
4322 break;
4323 case 0xA:
4324 /* Architectural Performance Monitoring Leaf */
4325 if (kvm_enabled() && cpu->enable_pmu) {
4326 KVMState *s = cs->kvm_state;
4327
4328 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4329 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4330 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4331 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
4332 } else if (hvf_enabled() && cpu->enable_pmu) {
4333 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4334 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4335 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4336 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
4337 } else {
4338 *eax = 0;
4339 *ebx = 0;
4340 *ecx = 0;
4341 *edx = 0;
4342 }
4343 break;
4344 case 0xB:
4345 /* Extended Topology Enumeration Leaf */
4346 if (!cpu->enable_cpuid_0xb) {
4347 *eax = *ebx = *ecx = *edx = 0;
4348 break;
4349 }
4350
4351 *ecx = count & 0xff;
4352 *edx = cpu->apic_id;
4353
4354 switch (count) {
4355 case 0:
4356 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4357 *ebx = cs->nr_threads;
4358 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4359 break;
4360 case 1:
4361 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4362 *ebx = cs->nr_cores * cs->nr_threads;
4363 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4364 break;
4365 default:
4366 *eax = 0;
4367 *ebx = 0;
4368 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4369 }
4370
4371 assert(!(*eax & ~0x1f));
4372 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4373 break;
4374 case 0xD: {
4375 /* Processor Extended State */
4376 *eax = 0;
4377 *ebx = 0;
4378 *ecx = 0;
4379 *edx = 0;
4380 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4381 break;
4382 }
4383
4384 if (count == 0) {
4385 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4386 *eax = env->features[FEAT_XSAVE_COMP_LO];
4387 *edx = env->features[FEAT_XSAVE_COMP_HI];
4388 *ebx = xsave_area_size(env->xcr0);
4389 } else if (count == 1) {
4390 *eax = env->features[FEAT_XSAVE];
4391 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
4392 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4393 const ExtSaveArea *esa = &x86_ext_save_areas[count];
4394 *eax = esa->size;
4395 *ebx = esa->offset;
4396 }
4397 }
4398 break;
4399 }
4400 case 0x14: {
4401 /* Intel Processor Trace Enumeration */
4402 *eax = 0;
4403 *ebx = 0;
4404 *ecx = 0;
4405 *edx = 0;
4406 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4407 !kvm_enabled()) {
4408 break;
4409 }
4410
4411 if (count == 0) {
4412 *eax = INTEL_PT_MAX_SUBLEAF;
4413 *ebx = INTEL_PT_MINIMAL_EBX;
4414 *ecx = INTEL_PT_MINIMAL_ECX;
4415 } else if (count == 1) {
4416 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4417 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4418 }
4419 break;
4420 }
4421 case 0x40000000:
4422 /*
4423 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4424 * set here, but we restrict to TCG none the less.
4425 */
4426 if (tcg_enabled() && cpu->expose_tcg) {
4427 memcpy(signature, "TCGTCGTCGTCG", 12);
4428 *eax = 0x40000001;
4429 *ebx = signature[0];
4430 *ecx = signature[1];
4431 *edx = signature[2];
4432 } else {
4433 *eax = 0;
4434 *ebx = 0;
4435 *ecx = 0;
4436 *edx = 0;
4437 }
4438 break;
4439 case 0x40000001:
4440 *eax = 0;
4441 *ebx = 0;
4442 *ecx = 0;
4443 *edx = 0;
4444 break;
4445 case 0x80000000:
4446 *eax = env->cpuid_xlevel;
4447 *ebx = env->cpuid_vendor1;
4448 *edx = env->cpuid_vendor2;
4449 *ecx = env->cpuid_vendor3;
4450 break;
4451 case 0x80000001:
4452 *eax = env->cpuid_version;
4453 *ebx = 0;
4454 *ecx = env->features[FEAT_8000_0001_ECX];
4455 *edx = env->features[FEAT_8000_0001_EDX];
4456
4457 /* The Linux kernel checks for the CMPLegacy bit and
4458 * discards multiple thread information if it is set.
4459 * So don't set it here for Intel to make Linux guests happy.
4460 */
4461 if (cs->nr_cores * cs->nr_threads > 1) {
4462 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4463 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4464 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
4465 *ecx |= 1 << 1; /* CmpLegacy bit */
4466 }
4467 }
4468 break;
4469 case 0x80000002:
4470 case 0x80000003:
4471 case 0x80000004:
4472 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4473 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4474 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4475 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4476 break;
4477 case 0x80000005:
4478 /* cache info (L1 cache) */
4479 if (cpu->cache_info_passthrough) {
4480 host_cpuid(index, 0, eax, ebx, ecx, edx);
4481 break;
4482 }
4483 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4484 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4485 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4486 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
4487 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4488 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
4489 break;
4490 case 0x80000006:
4491 /* cache info (L2 cache) */
4492 if (cpu->cache_info_passthrough) {
4493 host_cpuid(index, 0, eax, ebx, ecx, edx);
4494 break;
4495 }
4496 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4497 (L2_DTLB_2M_ENTRIES << 16) | \
4498 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4499 (L2_ITLB_2M_ENTRIES);
4500 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4501 (L2_DTLB_4K_ENTRIES << 16) | \
4502 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4503 (L2_ITLB_4K_ENTRIES);
4504 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4505 cpu->enable_l3_cache ?
4506 env->cache_info_amd.l3_cache : NULL,
4507 ecx, edx);
4508 break;
4509 case 0x80000007:
4510 *eax = 0;
4511 *ebx = 0;
4512 *ecx = 0;
4513 *edx = env->features[FEAT_8000_0007_EDX];
4514 break;
4515 case 0x80000008:
4516 /* virtual & phys address size in low 2 bytes. */
4517 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
4518 /* 64 bit processor */
4519 *eax = cpu->phys_bits; /* configurable physical bits */
4520 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4521 *eax |= 0x00003900; /* 57 bits virtual */
4522 } else {
4523 *eax |= 0x00003000; /* 48 bits virtual */
4524 }
4525 } else {
4526 *eax = cpu->phys_bits;
4527 }
4528 *ebx = env->features[FEAT_8000_0008_EBX];
4529 *ecx = 0;
4530 *edx = 0;
4531 if (cs->nr_cores * cs->nr_threads > 1) {
4532 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
4533 }
4534 break;
4535 case 0x8000000A:
4536 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4537 *eax = 0x00000001; /* SVM Revision */
4538 *ebx = 0x00000010; /* nr of ASIDs */
4539 *ecx = 0;
4540 *edx = env->features[FEAT_SVM]; /* optional features */
4541 } else {
4542 *eax = 0;
4543 *ebx = 0;
4544 *ecx = 0;
4545 *edx = 0;
4546 }
4547 break;
4548 case 0x8000001D:
4549 *eax = 0;
4550 switch (count) {
4551 case 0: /* L1 dcache info */
4552 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4553 eax, ebx, ecx, edx);
4554 break;
4555 case 1: /* L1 icache info */
4556 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4557 eax, ebx, ecx, edx);
4558 break;
4559 case 2: /* L2 cache info */
4560 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4561 eax, ebx, ecx, edx);
4562 break;
4563 case 3: /* L3 cache info */
4564 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4565 eax, ebx, ecx, edx);
4566 break;
4567 default: /* end of info */
4568 *eax = *ebx = *ecx = *edx = 0;
4569 break;
4570 }
4571 break;
4572 case 0x8000001E:
4573 assert(cpu->core_id <= 255);
4574 encode_topo_cpuid8000001e(cs, cpu,
4575 eax, ebx, ecx, edx);
4576 break;
4577 case 0xC0000000:
4578 *eax = env->cpuid_xlevel2;
4579 *ebx = 0;
4580 *ecx = 0;
4581 *edx = 0;
4582 break;
4583 case 0xC0000001:
4584 /* Support for VIA CPU's CPUID instruction */
4585 *eax = env->cpuid_version;
4586 *ebx = 0;
4587 *ecx = 0;
4588 *edx = env->features[FEAT_C000_0001_EDX];
4589 break;
4590 case 0xC0000002:
4591 case 0xC0000003:
4592 case 0xC0000004:
4593 /* Reserved for the future, and now filled with zero */
4594 *eax = 0;
4595 *ebx = 0;
4596 *ecx = 0;
4597 *edx = 0;
4598 break;
4599 case 0x8000001F:
4600 *eax = sev_enabled() ? 0x2 : 0;
4601 *ebx = sev_get_cbit_position();
4602 *ebx |= sev_get_reduced_phys_bits() << 6;
4603 *ecx = 0;
4604 *edx = 0;
4605 break;
4606 default:
4607 /* reserved values: zero */
4608 *eax = 0;
4609 *ebx = 0;
4610 *ecx = 0;
4611 *edx = 0;
4612 break;
4613 }
4614 }
4615
4616 /* CPUClass::reset() */
4617 static void x86_cpu_reset(CPUState *s)
4618 {
4619 X86CPU *cpu = X86_CPU(s);
4620 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4621 CPUX86State *env = &cpu->env;
4622 target_ulong cr4;
4623 uint64_t xcr0;
4624 int i;
4625
4626 xcc->parent_reset(s);
4627
4628 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
4629
4630 env->old_exception = -1;
4631
4632 /* init to reset state */
4633
4634 env->hflags2 |= HF2_GIF_MASK;
4635
4636 cpu_x86_update_cr0(env, 0x60000010);
4637 env->a20_mask = ~0x0;
4638 env->smbase = 0x30000;
4639 env->msr_smi_count = 0;
4640
4641 env->idt.limit = 0xffff;
4642 env->gdt.limit = 0xffff;
4643 env->ldt.limit = 0xffff;
4644 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4645 env->tr.limit = 0xffff;
4646 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4647
4648 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4649 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4650 DESC_R_MASK | DESC_A_MASK);
4651 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4652 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4653 DESC_A_MASK);
4654 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4655 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4656 DESC_A_MASK);
4657 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4658 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4659 DESC_A_MASK);
4660 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4661 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4662 DESC_A_MASK);
4663 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4664 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4665 DESC_A_MASK);
4666
4667 env->eip = 0xfff0;
4668 env->regs[R_EDX] = env->cpuid_version;
4669
4670 env->eflags = 0x2;
4671
4672 /* FPU init */
4673 for (i = 0; i < 8; i++) {
4674 env->fptags[i] = 1;
4675 }
4676 cpu_set_fpuc(env, 0x37f);
4677
4678 env->mxcsr = 0x1f80;
4679 /* All units are in INIT state. */
4680 env->xstate_bv = 0;
4681
4682 env->pat = 0x0007040600070406ULL;
4683 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4684
4685 memset(env->dr, 0, sizeof(env->dr));
4686 env->dr[6] = DR6_FIXED_1;
4687 env->dr[7] = DR7_FIXED_1;
4688 cpu_breakpoint_remove_all(s, BP_CPU);
4689 cpu_watchpoint_remove_all(s, BP_CPU);
4690
4691 cr4 = 0;
4692 xcr0 = XSTATE_FP_MASK;
4693
4694 #ifdef CONFIG_USER_ONLY
4695 /* Enable all the features for user-mode. */
4696 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4697 xcr0 |= XSTATE_SSE_MASK;
4698 }
4699 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4700 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4701 if (env->features[esa->feature] & esa->bits) {
4702 xcr0 |= 1ull << i;
4703 }
4704 }
4705
4706 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4707 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4708 }
4709 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4710 cr4 |= CR4_FSGSBASE_MASK;
4711 }
4712 #endif
4713
4714 env->xcr0 = xcr0;
4715 cpu_x86_update_cr4(env, cr4);
4716
4717 /*
4718 * SDM 11.11.5 requires:
4719 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4720 * - IA32_MTRR_PHYSMASKn.V = 0
4721 * All other bits are undefined. For simplification, zero it all.
4722 */
4723 env->mtrr_deftype = 0;
4724 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4725 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4726
4727 env->interrupt_injected = -1;
4728 env->exception_injected = -1;
4729 env->nmi_injected = false;
4730 #if !defined(CONFIG_USER_ONLY)
4731 /* We hard-wire the BSP to the first CPU. */
4732 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
4733
4734 s->halted = !cpu_is_bsp(cpu);
4735
4736 if (kvm_enabled()) {
4737 kvm_arch_reset_vcpu(cpu);
4738 }
4739 else if (hvf_enabled()) {
4740 hvf_reset_vcpu(s);
4741 }
4742 #endif
4743 }
4744
4745 #ifndef CONFIG_USER_ONLY
4746 bool cpu_is_bsp(X86CPU *cpu)
4747 {
4748 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
4749 }
4750
4751 /* TODO: remove me, when reset over QOM tree is implemented */
4752 static void x86_cpu_machine_reset_cb(void *opaque)
4753 {
4754 X86CPU *cpu = opaque;
4755 cpu_reset(CPU(cpu));
4756 }
4757 #endif
4758
4759 static void mce_init(X86CPU *cpu)
4760 {
4761 CPUX86State *cenv = &cpu->env;
4762 unsigned int bank;
4763
4764 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
4765 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
4766 (CPUID_MCE | CPUID_MCA)) {
4767 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4768 (cpu->enable_lmce ? MCG_LMCE_P : 0);
4769 cenv->mcg_ctl = ~(uint64_t)0;
4770 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4771 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4772 }
4773 }
4774 }
4775
4776 #ifndef CONFIG_USER_ONLY
4777 APICCommonClass *apic_get_class(void)
4778 {
4779 const char *apic_type = "apic";
4780
4781 /* TODO: in-kernel irqchip for hvf */
4782 if (kvm_apic_in_kernel()) {
4783 apic_type = "kvm-apic";
4784 } else if (xen_enabled()) {
4785 apic_type = "xen-apic";
4786 }
4787
4788 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4789 }
4790
4791 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4792 {
4793 APICCommonState *apic;
4794 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4795
4796 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
4797
4798 object_property_add_child(OBJECT(cpu), "lapic",
4799 OBJECT(cpu->apic_state), &error_abort);
4800 object_unref(OBJECT(cpu->apic_state));
4801
4802 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
4803 /* TODO: convert to link<> */
4804 apic = APIC_COMMON(cpu->apic_state);
4805 apic->cpu = cpu;
4806 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
4807 }
4808
4809 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4810 {
4811 APICCommonState *apic;
4812 static bool apic_mmio_map_once;
4813
4814 if (cpu->apic_state == NULL) {
4815 return;
4816 }
4817 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4818 errp);
4819
4820 /* Map APIC MMIO area */
4821 apic = APIC_COMMON(cpu->apic_state);
4822 if (!apic_mmio_map_once) {
4823 memory_region_add_subregion_overlap(get_system_memory(),
4824 apic->apicbase &
4825 MSR_IA32_APICBASE_BASE,
4826 &apic->io_memory,
4827 0x1000);
4828 apic_mmio_map_once = true;
4829 }
4830 }
4831
4832 static void x86_cpu_machine_done(Notifier *n, void *unused)
4833 {
4834 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4835 MemoryRegion *smram =
4836 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4837
4838 if (smram) {
4839 cpu->smram = g_new(MemoryRegion, 1);
4840 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4841 smram, 0, 1ull << 32);
4842 memory_region_set_enabled(cpu->smram, true);
4843 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4844 }
4845 }
4846 #else
4847 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4848 {
4849 }
4850 #endif
4851
4852 /* Note: Only safe for use on x86(-64) hosts */
4853 static uint32_t x86_host_phys_bits(void)
4854 {
4855 uint32_t eax;
4856 uint32_t host_phys_bits;
4857
4858 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4859 if (eax >= 0x80000008) {
4860 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4861 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4862 * at 23:16 that can specify a maximum physical address bits for
4863 * the guest that can override this value; but I've not seen
4864 * anything with that set.
4865 */
4866 host_phys_bits = eax & 0xff;
4867 } else {
4868 /* It's an odd 64 bit machine that doesn't have the leaf for
4869 * physical address bits; fall back to 36 that's most older
4870 * Intel.
4871 */
4872 host_phys_bits = 36;
4873 }
4874
4875 return host_phys_bits;
4876 }
4877
4878 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4879 {
4880 if (*min < value) {
4881 *min = value;
4882 }
4883 }
4884
4885 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4886 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4887 {
4888 CPUX86State *env = &cpu->env;
4889 FeatureWordInfo *fi = &feature_word_info[w];
4890 uint32_t eax = fi->cpuid.eax;
4891 uint32_t region = eax & 0xF0000000;
4892
4893 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
4894 if (!env->features[w]) {
4895 return;
4896 }
4897
4898 switch (region) {
4899 case 0x00000000:
4900 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4901 break;
4902 case 0x80000000:
4903 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4904 break;
4905 case 0xC0000000:
4906 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4907 break;
4908 }
4909 }
4910
4911 /* Calculate XSAVE components based on the configured CPU feature flags */
4912 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4913 {
4914 CPUX86State *env = &cpu->env;
4915 int i;
4916 uint64_t mask;
4917
4918 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4919 return;
4920 }
4921
4922 mask = 0;
4923 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4924 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4925 if (env->features[esa->feature] & esa->bits) {
4926 mask |= (1ULL << i);
4927 }
4928 }
4929
4930 env->features[FEAT_XSAVE_COMP_LO] = mask;
4931 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
4932 }
4933
4934 /***** Steps involved on loading and filtering CPUID data
4935 *
4936 * When initializing and realizing a CPU object, the steps
4937 * involved in setting up CPUID data are:
4938 *
4939 * 1) Loading CPU model definition (X86CPUDefinition). This is
4940 * implemented by x86_cpu_load_def() and should be completely
4941 * transparent, as it is done automatically by instance_init.
4942 * No code should need to look at X86CPUDefinition structs
4943 * outside instance_init.
4944 *
4945 * 2) CPU expansion. This is done by realize before CPUID
4946 * filtering, and will make sure host/accelerator data is
4947 * loaded for CPU models that depend on host capabilities
4948 * (e.g. "host"). Done by x86_cpu_expand_features().
4949 *
4950 * 3) CPUID filtering. This initializes extra data related to
4951 * CPUID, and checks if the host supports all capabilities
4952 * required by the CPU. Runnability of a CPU model is
4953 * determined at this step. Done by x86_cpu_filter_features().
4954 *
4955 * Some operations don't require all steps to be performed.
4956 * More precisely:
4957 *
4958 * - CPU instance creation (instance_init) will run only CPU
4959 * model loading. CPU expansion can't run at instance_init-time
4960 * because host/accelerator data may be not available yet.
4961 * - CPU realization will perform both CPU model expansion and CPUID
4962 * filtering, and return an error in case one of them fails.
4963 * - query-cpu-definitions needs to run all 3 steps. It needs
4964 * to run CPUID filtering, as the 'unavailable-features'
4965 * field is set based on the filtering results.
4966 * - The query-cpu-model-expansion QMP command only needs to run
4967 * CPU model loading and CPU expansion. It should not filter
4968 * any CPUID data based on host capabilities.
4969 */
4970
4971 /* Expand CPU configuration data, based on configured features
4972 * and host/accelerator capabilities when appropriate.
4973 */
4974 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
4975 {
4976 CPUX86State *env = &cpu->env;
4977 FeatureWord w;
4978 GList *l;
4979 Error *local_err = NULL;
4980
4981 /*TODO: Now cpu->max_features doesn't overwrite features
4982 * set using QOM properties, and we can convert
4983 * plus_features & minus_features to global properties
4984 * inside x86_cpu_parse_featurestr() too.
4985 */
4986 if (cpu->max_features) {
4987 for (w = 0; w < FEATURE_WORDS; w++) {
4988 /* Override only features that weren't set explicitly
4989 * by the user.
4990 */
4991 env->features[w] |=
4992 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
4993 ~env->user_features[w] & \
4994 ~feature_word_info[w].no_autoenable_flags;
4995 }
4996 }
4997
4998 for (l = plus_features; l; l = l->next) {
4999 const char *prop = l->data;
5000 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5001 if (local_err) {
5002 goto out;
5003 }
5004 }
5005
5006 for (l = minus_features; l; l = l->next) {
5007 const char *prop = l->data;
5008 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5009 if (local_err) {
5010 goto out;
5011 }
5012 }
5013
5014 if (!kvm_enabled() || !cpu->expose_kvm) {
5015 env->features[FEAT_KVM] = 0;
5016 }
5017
5018 x86_cpu_enable_xsave_components(cpu);
5019
5020 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5021 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5022 if (cpu->full_cpuid_auto_level) {
5023 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5024 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5025 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5026 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5027 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5028 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5029 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
5030 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
5031 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5032 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5033 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
5034 /* SVM requires CPUID[0x8000000A] */
5035 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5036 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5037 }
5038
5039 /* SEV requires CPUID[0x8000001F] */
5040 if (sev_enabled()) {
5041 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5042 }
5043 }
5044
5045 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5046 if (env->cpuid_level == UINT32_MAX) {
5047 env->cpuid_level = env->cpuid_min_level;
5048 }
5049 if (env->cpuid_xlevel == UINT32_MAX) {
5050 env->cpuid_xlevel = env->cpuid_min_xlevel;
5051 }
5052 if (env->cpuid_xlevel2 == UINT32_MAX) {
5053 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
5054 }
5055
5056 out:
5057 if (local_err != NULL) {
5058 error_propagate(errp, local_err);
5059 }
5060 }
5061
5062 /*
5063 * Finishes initialization of CPUID data, filters CPU feature
5064 * words based on host availability of each feature.
5065 *
5066 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5067 */
5068 static int x86_cpu_filter_features(X86CPU *cpu)
5069 {
5070 CPUX86State *env = &cpu->env;
5071 FeatureWord w;
5072 int rv = 0;
5073
5074 for (w = 0; w < FEATURE_WORDS; w++) {
5075 uint32_t host_feat =
5076 x86_cpu_get_supported_feature_word(w, false);
5077 uint32_t requested_features = env->features[w];
5078 env->features[w] &= host_feat;
5079 cpu->filtered_features[w] = requested_features & ~env->features[w];
5080 if (cpu->filtered_features[w]) {
5081 rv = 1;
5082 }
5083 }
5084
5085 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5086 kvm_enabled()) {
5087 KVMState *s = CPU(cpu)->kvm_state;
5088 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5089 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5090 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5091 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5092 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5093
5094 if (!eax_0 ||
5095 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5096 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5097 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5098 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5099 INTEL_PT_ADDR_RANGES_NUM) ||
5100 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
5101 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5102 (ecx_0 & INTEL_PT_IP_LIP)) {
5103 /*
5104 * Processor Trace capabilities aren't configurable, so if the
5105 * host can't emulate the capabilities we report on
5106 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5107 */
5108 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5109 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5110 rv = 1;
5111 }
5112 }
5113
5114 return rv;
5115 }
5116
5117 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5118 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5119 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5120 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5121 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5122 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5123 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5124 {
5125 CPUState *cs = CPU(dev);
5126 X86CPU *cpu = X86_CPU(dev);
5127 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5128 CPUX86State *env = &cpu->env;
5129 Error *local_err = NULL;
5130 static bool ht_warned;
5131
5132 if (xcc->host_cpuid_required) {
5133 if (!accel_uses_host_cpuid()) {
5134 char *name = x86_cpu_class_get_model_name(xcc);
5135 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5136 g_free(name);
5137 goto out;
5138 }
5139
5140 if (enable_cpu_pm) {
5141 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5142 &cpu->mwait.ecx, &cpu->mwait.edx);
5143 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5144 }
5145 }
5146
5147 /* mwait extended info: needed for Core compatibility */
5148 /* We always wake on interrupt even if host does not have the capability */
5149 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5150
5151 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5152 error_setg(errp, "apic-id property was not initialized properly");
5153 return;
5154 }
5155
5156 x86_cpu_expand_features(cpu, &local_err);
5157 if (local_err) {
5158 goto out;
5159 }
5160
5161 if (x86_cpu_filter_features(cpu) &&
5162 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5163 x86_cpu_report_filtered_features(cpu);
5164 if (cpu->enforce_cpuid) {
5165 error_setg(&local_err,
5166 accel_uses_host_cpuid() ?
5167 "Host doesn't support requested features" :
5168 "TCG doesn't support requested features");
5169 goto out;
5170 }
5171 }
5172
5173 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5174 * CPUID[1].EDX.
5175 */
5176 if (IS_AMD_CPU(env)) {
5177 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5178 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
5179 & CPUID_EXT2_AMD_ALIASES);
5180 }
5181
5182 /* For 64bit systems think about the number of physical bits to present.
5183 * ideally this should be the same as the host; anything other than matching
5184 * the host can cause incorrect guest behaviour.
5185 * QEMU used to pick the magic value of 40 bits that corresponds to
5186 * consumer AMD devices but nothing else.
5187 */
5188 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5189 if (accel_uses_host_cpuid()) {
5190 uint32_t host_phys_bits = x86_host_phys_bits();
5191 static bool warned;
5192
5193 if (cpu->host_phys_bits) {
5194 /* The user asked for us to use the host physical bits */
5195 cpu->phys_bits = host_phys_bits;
5196 if (cpu->host_phys_bits_limit &&
5197 cpu->phys_bits > cpu->host_phys_bits_limit) {
5198 cpu->phys_bits = cpu->host_phys_bits_limit;
5199 }
5200 }
5201
5202 /* Print a warning if the user set it to a value that's not the
5203 * host value.
5204 */
5205 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5206 !warned) {
5207 warn_report("Host physical bits (%u)"
5208 " does not match phys-bits property (%u)",
5209 host_phys_bits, cpu->phys_bits);
5210 warned = true;
5211 }
5212
5213 if (cpu->phys_bits &&
5214 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5215 cpu->phys_bits < 32)) {
5216 error_setg(errp, "phys-bits should be between 32 and %u "
5217 " (but is %u)",
5218 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5219 return;
5220 }
5221 } else {
5222 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
5223 error_setg(errp, "TCG only supports phys-bits=%u",
5224 TCG_PHYS_ADDR_BITS);
5225 return;
5226 }
5227 }
5228 /* 0 means it was not explicitly set by the user (or by machine
5229 * compat_props or by the host code above). In this case, the default
5230 * is the value used by TCG (40).
5231 */
5232 if (cpu->phys_bits == 0) {
5233 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5234 }
5235 } else {
5236 /* For 32 bit systems don't use the user set value, but keep
5237 * phys_bits consistent with what we tell the guest.
5238 */
5239 if (cpu->phys_bits != 0) {
5240 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5241 return;
5242 }
5243
5244 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5245 cpu->phys_bits = 36;
5246 } else {
5247 cpu->phys_bits = 32;
5248 }
5249 }
5250
5251 /* Cache information initialization */
5252 if (!cpu->legacy_cache) {
5253 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5254 char *name = x86_cpu_class_get_model_name(xcc);
5255 error_setg(errp,
5256 "CPU model '%s' doesn't support legacy-cache=off", name);
5257 g_free(name);
5258 return;
5259 }
5260 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5261 *xcc->cpu_def->cache_info;
5262 } else {
5263 /* Build legacy cache information */
5264 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5265 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5266 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5267 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5268
5269 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5270 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5271 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5272 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5273
5274 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5275 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5276 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5277 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5278 }
5279
5280
5281 cpu_exec_realizefn(cs, &local_err);
5282 if (local_err != NULL) {
5283 error_propagate(errp, local_err);
5284 return;
5285 }
5286
5287 #ifndef CONFIG_USER_ONLY
5288 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
5289
5290 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
5291 x86_cpu_apic_create(cpu, &local_err);
5292 if (local_err != NULL) {
5293 goto out;
5294 }
5295 }
5296 #endif
5297
5298 mce_init(cpu);
5299
5300 #ifndef CONFIG_USER_ONLY
5301 if (tcg_enabled()) {
5302 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
5303 cpu->cpu_as_root = g_new(MemoryRegion, 1);
5304
5305 /* Outer container... */
5306 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
5307 memory_region_set_enabled(cpu->cpu_as_root, true);
5308
5309 /* ... with two regions inside: normal system memory with low
5310 * priority, and...
5311 */
5312 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5313 get_system_memory(), 0, ~0ull);
5314 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5315 memory_region_set_enabled(cpu->cpu_as_mem, true);
5316
5317 cs->num_ases = 2;
5318 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5319 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
5320
5321 /* ... SMRAM with higher priority, linked from /machine/smram. */
5322 cpu->machine_done.notify = x86_cpu_machine_done;
5323 qemu_add_machine_init_done_notifier(&cpu->machine_done);
5324 }
5325 #endif
5326
5327 qemu_init_vcpu(cs);
5328
5329 /*
5330 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5331 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5332 * based on inputs (sockets,cores,threads), it is still better to give
5333 * users a warning.
5334 *
5335 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5336 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5337 */
5338 if (IS_AMD_CPU(env) &&
5339 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5340 cs->nr_threads > 1 && !ht_warned) {
5341 warn_report("This family of AMD CPU doesn't support "
5342 "hyperthreading(%d)",
5343 cs->nr_threads);
5344 error_printf("Please configure -smp options properly"
5345 " or try enabling topoext feature.\n");
5346 ht_warned = true;
5347 }
5348
5349 x86_cpu_apic_realize(cpu, &local_err);
5350 if (local_err != NULL) {
5351 goto out;
5352 }
5353 cpu_reset(cs);
5354
5355 xcc->parent_realize(dev, &local_err);
5356
5357 out:
5358 if (local_err != NULL) {
5359 error_propagate(errp, local_err);
5360 return;
5361 }
5362 }
5363
5364 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5365 {
5366 X86CPU *cpu = X86_CPU(dev);
5367 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5368 Error *local_err = NULL;
5369
5370 #ifndef CONFIG_USER_ONLY
5371 cpu_remove_sync(CPU(dev));
5372 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5373 #endif
5374
5375 if (cpu->apic_state) {
5376 object_unparent(OBJECT(cpu->apic_state));
5377 cpu->apic_state = NULL;
5378 }
5379
5380 xcc->parent_unrealize(dev, &local_err);
5381 if (local_err != NULL) {
5382 error_propagate(errp, local_err);
5383 return;
5384 }
5385 }
5386
5387 typedef struct BitProperty {
5388 FeatureWord w;
5389 uint32_t mask;
5390 } BitProperty;
5391
5392 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5393 void *opaque, Error **errp)
5394 {
5395 X86CPU *cpu = X86_CPU(obj);
5396 BitProperty *fp = opaque;
5397 uint32_t f = cpu->env.features[fp->w];
5398 bool value = (f & fp->mask) == fp->mask;
5399 visit_type_bool(v, name, &value, errp);
5400 }
5401
5402 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5403 void *opaque, Error **errp)
5404 {
5405 DeviceState *dev = DEVICE(obj);
5406 X86CPU *cpu = X86_CPU(obj);
5407 BitProperty *fp = opaque;
5408 Error *local_err = NULL;
5409 bool value;
5410
5411 if (dev->realized) {
5412 qdev_prop_set_after_realize(dev, name, errp);
5413 return;
5414 }
5415
5416 visit_type_bool(v, name, &value, &local_err);
5417 if (local_err) {
5418 error_propagate(errp, local_err);
5419 return;
5420 }
5421
5422 if (value) {
5423 cpu->env.features[fp->w] |= fp->mask;
5424 } else {
5425 cpu->env.features[fp->w] &= ~fp->mask;
5426 }
5427 cpu->env.user_features[fp->w] |= fp->mask;
5428 }
5429
5430 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5431 void *opaque)
5432 {
5433 BitProperty *prop = opaque;
5434 g_free(prop);
5435 }
5436
5437 /* Register a boolean property to get/set a single bit in a uint32_t field.
5438 *
5439 * The same property name can be registered multiple times to make it affect
5440 * multiple bits in the same FeatureWord. In that case, the getter will return
5441 * true only if all bits are set.
5442 */
5443 static void x86_cpu_register_bit_prop(X86CPU *cpu,
5444 const char *prop_name,
5445 FeatureWord w,
5446 int bitnr)
5447 {
5448 BitProperty *fp;
5449 ObjectProperty *op;
5450 uint32_t mask = (1UL << bitnr);
5451
5452 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5453 if (op) {
5454 fp = op->opaque;
5455 assert(fp->w == w);
5456 fp->mask |= mask;
5457 } else {
5458 fp = g_new0(BitProperty, 1);
5459 fp->w = w;
5460 fp->mask = mask;
5461 object_property_add(OBJECT(cpu), prop_name, "bool",
5462 x86_cpu_get_bit_prop,
5463 x86_cpu_set_bit_prop,
5464 x86_cpu_release_bit_prop, fp, &error_abort);
5465 }
5466 }
5467
5468 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5469 FeatureWord w,
5470 int bitnr)
5471 {
5472 FeatureWordInfo *fi = &feature_word_info[w];
5473 const char *name = fi->feat_names[bitnr];
5474
5475 if (!name) {
5476 return;
5477 }
5478
5479 /* Property names should use "-" instead of "_".
5480 * Old names containing underscores are registered as aliases
5481 * using object_property_add_alias()
5482 */
5483 assert(!strchr(name, '_'));
5484 /* aliases don't use "|" delimiters anymore, they are registered
5485 * manually using object_property_add_alias() */
5486 assert(!strchr(name, '|'));
5487 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
5488 }
5489
5490 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5491 {
5492 X86CPU *cpu = X86_CPU(cs);
5493 CPUX86State *env = &cpu->env;
5494 GuestPanicInformation *panic_info = NULL;
5495
5496 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
5497 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5498
5499 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
5500
5501 assert(HV_CRASH_PARAMS >= 5);
5502 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5503 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5504 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5505 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5506 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
5507 }
5508
5509 return panic_info;
5510 }
5511 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5512 const char *name, void *opaque,
5513 Error **errp)
5514 {
5515 CPUState *cs = CPU(obj);
5516 GuestPanicInformation *panic_info;
5517
5518 if (!cs->crash_occurred) {
5519 error_setg(errp, "No crash occured");
5520 return;
5521 }
5522
5523 panic_info = x86_cpu_get_crash_info(cs);
5524 if (panic_info == NULL) {
5525 error_setg(errp, "No crash information");
5526 return;
5527 }
5528
5529 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5530 errp);
5531 qapi_free_GuestPanicInformation(panic_info);
5532 }
5533
5534 static void x86_cpu_initfn(Object *obj)
5535 {
5536 CPUState *cs = CPU(obj);
5537 X86CPU *cpu = X86_CPU(obj);
5538 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
5539 CPUX86State *env = &cpu->env;
5540 FeatureWord w;
5541
5542 cs->env_ptr = env;
5543
5544 object_property_add(obj, "family", "int",
5545 x86_cpuid_version_get_family,
5546 x86_cpuid_version_set_family, NULL, NULL, NULL);
5547 object_property_add(obj, "model", "int",
5548 x86_cpuid_version_get_model,
5549 x86_cpuid_version_set_model, NULL, NULL, NULL);
5550 object_property_add(obj, "stepping", "int",
5551 x86_cpuid_version_get_stepping,
5552 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
5553 object_property_add_str(obj, "vendor",
5554 x86_cpuid_get_vendor,
5555 x86_cpuid_set_vendor, NULL);
5556 object_property_add_str(obj, "model-id",
5557 x86_cpuid_get_model_id,
5558 x86_cpuid_set_model_id, NULL);
5559 object_property_add(obj, "tsc-frequency", "int",
5560 x86_cpuid_get_tsc_freq,
5561 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
5562 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5563 x86_cpu_get_feature_words,
5564 NULL, NULL, (void *)env->features, NULL);
5565 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5566 x86_cpu_get_feature_words,
5567 NULL, NULL, (void *)cpu->filtered_features, NULL);
5568
5569 object_property_add(obj, "crash-information", "GuestPanicInformation",
5570 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5571
5572 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
5573
5574 for (w = 0; w < FEATURE_WORDS; w++) {
5575 int bitnr;
5576
5577 for (bitnr = 0; bitnr < 32; bitnr++) {
5578 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5579 }
5580 }
5581
5582 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5583 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5584 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5585 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5586 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5587 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5588 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5589
5590 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5591 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5592 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5593 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5594 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5595 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5596 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5597 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5598 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5599 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5600 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5601 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5602 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5603 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5604 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5605 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5606 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5607 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5608 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5609 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5610 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5611
5612 if (xcc->cpu_def) {
5613 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5614 }
5615 }
5616
5617 static int64_t x86_cpu_get_arch_id(CPUState *cs)
5618 {
5619 X86CPU *cpu = X86_CPU(cs);
5620
5621 return cpu->apic_id;
5622 }
5623
5624 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5625 {
5626 X86CPU *cpu = X86_CPU(cs);
5627
5628 return cpu->env.cr[0] & CR0_PG_MASK;
5629 }
5630
5631 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5632 {
5633 X86CPU *cpu = X86_CPU(cs);
5634
5635 cpu->env.eip = value;
5636 }
5637
5638 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5639 {
5640 X86CPU *cpu = X86_CPU(cs);
5641
5642 cpu->env.eip = tb->pc - tb->cs_base;
5643 }
5644
5645 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
5646 {
5647 X86CPU *cpu = X86_CPU(cs);
5648 CPUX86State *env = &cpu->env;
5649
5650 #if !defined(CONFIG_USER_ONLY)
5651 if (interrupt_request & CPU_INTERRUPT_POLL) {
5652 return CPU_INTERRUPT_POLL;
5653 }
5654 #endif
5655 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5656 return CPU_INTERRUPT_SIPI;
5657 }
5658
5659 if (env->hflags2 & HF2_GIF_MASK) {
5660 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5661 !(env->hflags & HF_SMM_MASK)) {
5662 return CPU_INTERRUPT_SMI;
5663 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5664 !(env->hflags2 & HF2_NMI_MASK)) {
5665 return CPU_INTERRUPT_NMI;
5666 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5667 return CPU_INTERRUPT_MCE;
5668 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5669 (((env->hflags2 & HF2_VINTR_MASK) &&
5670 (env->hflags2 & HF2_HIF_MASK)) ||
5671 (!(env->hflags2 & HF2_VINTR_MASK) &&
5672 (env->eflags & IF_MASK &&
5673 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5674 return CPU_INTERRUPT_HARD;
5675 #if !defined(CONFIG_USER_ONLY)
5676 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5677 (env->eflags & IF_MASK) &&
5678 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5679 return CPU_INTERRUPT_VIRQ;
5680 #endif
5681 }
5682 }
5683
5684 return 0;
5685 }
5686
5687 static bool x86_cpu_has_work(CPUState *cs)
5688 {
5689 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
5690 }
5691
5692 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5693 {
5694 X86CPU *cpu = X86_CPU(cs);
5695 CPUX86State *env = &cpu->env;
5696
5697 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5698 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5699 : bfd_mach_i386_i8086);
5700 info->print_insn = print_insn_i386;
5701
5702 info->cap_arch = CS_ARCH_X86;
5703 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5704 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5705 : CS_MODE_16);
5706 info->cap_insn_unit = 1;
5707 info->cap_insn_split = 8;
5708 }
5709
5710 void x86_update_hflags(CPUX86State *env)
5711 {
5712 uint32_t hflags;
5713 #define HFLAG_COPY_MASK \
5714 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5715 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5716 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5717 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5718
5719 hflags = env->hflags & HFLAG_COPY_MASK;
5720 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5721 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5722 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5723 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5724 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5725
5726 if (env->cr[4] & CR4_OSFXSR_MASK) {
5727 hflags |= HF_OSFXSR_MASK;
5728 }
5729
5730 if (env->efer & MSR_EFER_LMA) {
5731 hflags |= HF_LMA_MASK;
5732 }
5733
5734 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5735 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5736 } else {
5737 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5738 (DESC_B_SHIFT - HF_CS32_SHIFT);
5739 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5740 (DESC_B_SHIFT - HF_SS32_SHIFT);
5741 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5742 !(hflags & HF_CS32_MASK)) {
5743 hflags |= HF_ADDSEG_MASK;
5744 } else {
5745 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5746 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5747 }
5748 }
5749 env->hflags = hflags;
5750 }
5751
5752 static Property x86_cpu_properties[] = {
5753 #ifdef CONFIG_USER_ONLY
5754 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5755 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
5756 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5757 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5758 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
5759 #else
5760 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
5761 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5762 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5763 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
5764 #endif
5765 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
5766 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
5767 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
5768 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
5769 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
5770 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
5771 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
5772 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
5773 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
5774 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
5775 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
5776 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
5777 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
5778 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
5779 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
5780 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
5781 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
5782 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
5783 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
5784 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
5785 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
5786 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
5787 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
5788 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
5789 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5790 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5791 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5792 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5793 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5794 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5795 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
5796 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5797 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
5798 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
5799 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
5800 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5801 false),
5802 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
5803 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
5804 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5805 true),
5806 /*
5807 * lecacy_cache defaults to true unless the CPU model provides its
5808 * own cache information (see x86_cpu_load_def()).
5809 */
5810 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
5811
5812 /*
5813 * From "Requirements for Implementing the Microsoft
5814 * Hypervisor Interface":
5815 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5816 *
5817 * "Starting with Windows Server 2012 and Windows 8, if
5818 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5819 * the hypervisor imposes no specific limit to the number of VPs.
5820 * In this case, Windows Server 2012 guest VMs may use more than
5821 * 64 VPs, up to the maximum supported number of processors applicable
5822 * to the specific Windows version being used."
5823 */
5824 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
5825 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5826 false),
5827 DEFINE_PROP_END_OF_LIST()
5828 };
5829
5830 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5831 {
5832 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5833 CPUClass *cc = CPU_CLASS(oc);
5834 DeviceClass *dc = DEVICE_CLASS(oc);
5835
5836 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5837 &xcc->parent_realize);
5838 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5839 &xcc->parent_unrealize);
5840 dc->props = x86_cpu_properties;
5841
5842 xcc->parent_reset = cc->reset;
5843 cc->reset = x86_cpu_reset;
5844 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
5845
5846 cc->class_by_name = x86_cpu_class_by_name;
5847 cc->parse_features = x86_cpu_parse_featurestr;
5848 cc->has_work = x86_cpu_has_work;
5849 #ifdef CONFIG_TCG
5850 cc->do_interrupt = x86_cpu_do_interrupt;
5851 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
5852 #endif
5853 cc->dump_state = x86_cpu_dump_state;
5854 cc->get_crash_info = x86_cpu_get_crash_info;
5855 cc->set_pc = x86_cpu_set_pc;
5856 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5857 cc->gdb_read_register = x86_cpu_gdb_read_register;
5858 cc->gdb_write_register = x86_cpu_gdb_write_register;
5859 cc->get_arch_id = x86_cpu_get_arch_id;
5860 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5861 #ifdef CONFIG_USER_ONLY
5862 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5863 #else
5864 cc->asidx_from_attrs = x86_asidx_from_attrs;
5865 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
5866 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
5867 cc->write_elf64_note = x86_cpu_write_elf64_note;
5868 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5869 cc->write_elf32_note = x86_cpu_write_elf32_note;
5870 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
5871 cc->vmsd = &vmstate_x86_cpu;
5872 #endif
5873 cc->gdb_arch_name = x86_gdb_arch_name;
5874 #ifdef TARGET_X86_64
5875 cc->gdb_core_xml_file = "i386-64bit.xml";
5876 cc->gdb_num_core_regs = 66;
5877 #else
5878 cc->gdb_core_xml_file = "i386-32bit.xml";
5879 cc->gdb_num_core_regs = 50;
5880 #endif
5881 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
5882 cc->debug_excp_handler = breakpoint_handler;
5883 #endif
5884 cc->cpu_exec_enter = x86_cpu_exec_enter;
5885 cc->cpu_exec_exit = x86_cpu_exec_exit;
5886 #ifdef CONFIG_TCG
5887 cc->tcg_initialize = tcg_x86_init;
5888 #endif
5889 cc->disas_set_info = x86_disas_set_info;
5890
5891 dc->user_creatable = true;
5892 }
5893
5894 static const TypeInfo x86_cpu_type_info = {
5895 .name = TYPE_X86_CPU,
5896 .parent = TYPE_CPU,
5897 .instance_size = sizeof(X86CPU),
5898 .instance_init = x86_cpu_initfn,
5899 .abstract = true,
5900 .class_size = sizeof(X86CPUClass),
5901 .class_init = x86_cpu_common_class_init,
5902 };
5903
5904
5905 /* "base" CPU model, used by query-cpu-model-expansion */
5906 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5907 {
5908 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5909
5910 xcc->static_model = true;
5911 xcc->migration_safe = true;
5912 xcc->model_description = "base CPU model type with no features enabled";
5913 xcc->ordering = 8;
5914 }
5915
5916 static const TypeInfo x86_base_cpu_type_info = {
5917 .name = X86_CPU_TYPE_NAME("base"),
5918 .parent = TYPE_X86_CPU,
5919 .class_init = x86_cpu_base_class_init,
5920 };
5921
5922 static void x86_cpu_register_types(void)
5923 {
5924 int i;
5925
5926 type_register_static(&x86_cpu_type_info);
5927 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5928 x86_register_cpudef_type(&builtin_x86_defs[i]);
5929 }
5930 type_register_static(&max_x86_cpu_type_info);
5931 type_register_static(&x86_base_cpu_type_info);
5932 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
5933 type_register_static(&host_x86_cpu_type_info);
5934 #endif
5935 }
5936
5937 type_init(x86_cpu_register_types)
QEmu