hw/s390x/s390-pci-bus.c

   1 /*
   2  * s390 PCI BUS
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "s390-pci-bus.h"
  18 #include "s390-pci-inst.h"
  19 #include <hw/pci/pci_bus.h>
  20 #include <hw/pci/msi.h>
  21 #include <qemu/error-report.h>
  22
  23 /* #define DEBUG_S390PCI_BUS */
  24 #ifdef DEBUG_S390PCI_BUS
  25 #define DPRINTF(fmt, ...) \
  26     do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
  27 #else
  28 #define DPRINTF(fmt, ...) \
  29     do { } while (0)
  30 #endif
  31
  32 int chsc_sei_nt2_get_event(void *res)
  33 {
  34     ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
  35     PciCcdfAvail *accdf;
  36     PciCcdfErr *eccdf;
  37     int rc = 1;
  38     SeiContainer *sei_cont;
  39     S390pciState *s = S390_PCI_HOST_BRIDGE(
  40         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  41
  42     if (!s) {
  43         return rc;
  44     }
  45
  46     sei_cont = QTAILQ_FIRST(&s->pending_sei);
  47     if (sei_cont) {
  48         QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
  49         nt2_res->nt = 2;
  50         nt2_res->cc = sei_cont->cc;
  51         nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
  52         switch (sei_cont->cc) {
  53         case 1: /* error event */
  54             eccdf = (PciCcdfErr *)nt2_res->ccdf;
  55             eccdf->fid = cpu_to_be32(sei_cont->fid);
  56             eccdf->fh = cpu_to_be32(sei_cont->fh);
  57             eccdf->e = cpu_to_be32(sei_cont->e);
  58             eccdf->faddr = cpu_to_be64(sei_cont->faddr);
  59             eccdf->pec = cpu_to_be16(sei_cont->pec);
  60             break;
  61         case 2: /* availability event */
  62             accdf = (PciCcdfAvail *)nt2_res->ccdf;
  63             accdf->fid = cpu_to_be32(sei_cont->fid);
  64             accdf->fh = cpu_to_be32(sei_cont->fh);
  65             accdf->pec = cpu_to_be16(sei_cont->pec);
  66             break;
  67         default:
  68             abort();
  69         }
  70         g_free(sei_cont);
  71         rc = 0;
  72     }
  73
  74     return rc;
  75 }
  76
  77 int chsc_sei_nt2_have_event(void)
  78 {
  79     S390pciState *s = S390_PCI_HOST_BRIDGE(
  80         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  81
  82     if (!s) {
  83         return 0;
  84     }
  85
  86     return !QTAILQ_EMPTY(&s->pending_sei);
  87 }
  88
  89 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
  90 {
  91     S390PCIBusDevice *pbdev;
  92     int i;
  93     S390pciState *s = S390_PCI_HOST_BRIDGE(
  94         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  95
  96     if (!s) {
  97         return NULL;
  98     }
  99
 100     for (i = 0; i < PCI_SLOT_MAX; i++) {
 101         pbdev = &s->pbdev[i];
 102         if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
 103             return pbdev;
 104         }
 105     }
 106
 107     return NULL;
 108 }
 109
 110 void s390_pci_sclp_configure(SCCB *sccb)
 111 {
 112     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 113     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 114     uint16_t rc;
 115
 116     if (pbdev) {
 117         if (pbdev->configured) {
 118             rc = SCLP_RC_NO_ACTION_REQUIRED;
 119         } else {
 120             pbdev->configured = true;
 121             rc = SCLP_RC_NORMAL_COMPLETION;
 122         }
 123     } else {
 124         DPRINTF("sclp config no dev found\n");
 125         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 126     }
 127
 128     psccb->header.response_code = cpu_to_be16(rc);
 129 }
 130
 131 void s390_pci_sclp_deconfigure(SCCB *sccb)
 132 {
 133     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 134     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 135     uint16_t rc;
 136
 137     if (pbdev) {
 138         if (!pbdev->configured) {
 139             rc = SCLP_RC_NO_ACTION_REQUIRED;
 140         } else {
 141             if (pbdev->summary_ind) {
 142                 pci_dereg_irqs(pbdev);
 143             }
 144             if (pbdev->iommu_enabled) {
 145                 pci_dereg_ioat(pbdev);
 146             }
 147             pbdev->configured = false;
 148             rc = SCLP_RC_NORMAL_COMPLETION;
 149         }
 150     } else {
 151         DPRINTF("sclp deconfig no dev found\n");
 152         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 153     }
 154
 155     psccb->header.response_code = cpu_to_be16(rc);
 156 }
 157
 158 static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
 159 {
 160     return PCI_SLOT(pdev->devfn);
 161 }
 162
 163 static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
 164 {
 165     return PCI_SLOT(pdev->devfn) | FH_VIRT;
 166 }
 167
 168 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
 169 {
 170     S390PCIBusDevice *pbdev;
 171     int i;
 172     int j = 0;
 173     S390pciState *s = S390_PCI_HOST_BRIDGE(
 174         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 175
 176     if (!s) {
 177         return NULL;
 178     }
 179
 180     for (i = 0; i < PCI_SLOT_MAX; i++) {
 181         pbdev = &s->pbdev[i];
 182
 183         if (pbdev->fh == 0) {
 184             continue;
 185         }
 186
 187         if (j == idx) {
 188             return pbdev;
 189         }
 190         j++;
 191     }
 192
 193     return NULL;
 194 }
 195
 196 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
 197 {
 198     S390PCIBusDevice *pbdev;
 199     int i;
 200     S390pciState *s = S390_PCI_HOST_BRIDGE(
 201         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 202
 203     if (!s || !fh) {
 204         return NULL;
 205     }
 206
 207     for (i = 0; i < PCI_SLOT_MAX; i++) {
 208         pbdev = &s->pbdev[i];
 209         if (pbdev->fh == fh) {
 210             return pbdev;
 211         }
 212     }
 213
 214     return NULL;
 215 }
 216
 217 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
 218                                     uint32_t fid, uint64_t faddr, uint32_t e)
 219 {
 220     SeiContainer *sei_cont;
 221     S390pciState *s = S390_PCI_HOST_BRIDGE(
 222         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 223
 224     if (!s) {
 225         return;
 226     }
 227
 228     sei_cont = g_malloc0(sizeof(SeiContainer));
 229     sei_cont->fh = fh;
 230     sei_cont->fid = fid;
 231     sei_cont->cc = cc;
 232     sei_cont->pec = pec;
 233     sei_cont->faddr = faddr;
 234     sei_cont->e = e;
 235
 236     QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
 237     css_generate_css_crws(0);
 238 }
 239
 240 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
 241                                          uint32_t fid)
 242 {
 243     s390_pci_generate_event(2, pec, fh, fid, 0, 0);
 244 }
 245
 246 static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
 247                                           uint32_t fid, uint64_t faddr,
 248                                           uint32_t e)
 249 {
 250     s390_pci_generate_event(1, pec, fh, fid, faddr, e);
 251 }
 252
 253 static void s390_pci_set_irq(void *opaque, int irq, int level)
 254 {
 255     /* nothing to do */
 256 }
 257
 258 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 259 {
 260     /* nothing to do */
 261     return 0;
 262 }
 263
 264 static uint64_t s390_pci_get_table_origin(uint64_t iota)
 265 {
 266     return iota & ~ZPCI_IOTA_RTTO_FLAG;
 267 }
 268
 269 static unsigned int calc_rtx(dma_addr_t ptr)
 270 {
 271     return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
 272 }
 273
 274 static unsigned int calc_sx(dma_addr_t ptr)
 275 {
 276     return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
 277 }
 278
 279 static unsigned int calc_px(dma_addr_t ptr)
 280 {
 281     return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
 282 }
 283
 284 static uint64_t get_rt_sto(uint64_t entry)
 285 {
 286     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
 287                 ? (entry & ZPCI_RTE_ADDR_MASK)
 288                 : 0;
 289 }
 290
 291 static uint64_t get_st_pto(uint64_t entry)
 292 {
 293     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
 294             ? (entry & ZPCI_STE_ADDR_MASK)
 295             : 0;
 296 }
 297
 298 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
 299                                   uint64_t guest_dma_address)
 300 {
 301     uint64_t sto_a, pto_a, px_a;
 302     uint64_t sto, pto, pte;
 303     uint32_t rtx, sx, px;
 304
 305     rtx = calc_rtx(guest_dma_address);
 306     sx = calc_sx(guest_dma_address);
 307     px = calc_px(guest_dma_address);
 308
 309     sto_a = guest_iota + rtx * sizeof(uint64_t);
 310     sto = address_space_ldq(&address_space_memory, sto_a,
 311                             MEMTXATTRS_UNSPECIFIED, NULL);
 312     sto = get_rt_sto(sto);
 313     if (!sto) {
 314         pte = 0;
 315         goto out;
 316     }
 317
 318     pto_a = sto + sx * sizeof(uint64_t);
 319     pto = address_space_ldq(&address_space_memory, pto_a,
 320                             MEMTXATTRS_UNSPECIFIED, NULL);
 321     pto = get_st_pto(pto);
 322     if (!pto) {
 323         pte = 0;
 324         goto out;
 325     }
 326
 327     px_a = pto + px * sizeof(uint64_t);
 328     pte = address_space_ldq(&address_space_memory, px_a,
 329                             MEMTXATTRS_UNSPECIFIED, NULL);
 330
 331 out:
 332     return pte;
 333 }
 334
 335 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 336                                           bool is_write)
 337 {
 338     uint64_t pte;
 339     uint32_t flags;
 340     S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, iommu_mr);
 341     S390pciState *s;
 342     IOMMUTLBEntry ret = {
 343         .target_as = &address_space_memory,
 344         .iova = 0,
 345         .translated_addr = 0,
 346         .addr_mask = ~(hwaddr)0,
 347         .perm = IOMMU_NONE,
 348     };
 349
 350     if (!pbdev->configured || !pbdev->pdev ||
 351         !(pbdev->fh & FH_ENABLED) || !pbdev->iommu_enabled) {
 352         return ret;
 353     }
 354
 355     DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
 356
 357     s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)->qbus.parent);
 358     /* s390 does not have an APIC mapped to main storage so we use
 359      * a separate AddressSpace only for msix notifications
 360      */
 361     if (addr == ZPCI_MSI_ADDR) {
 362         ret.target_as = &s->msix_notify_as;
 363         ret.iova = addr;
 364         ret.translated_addr = addr;
 365         ret.addr_mask = 0xfff;
 366         ret.perm = IOMMU_RW;
 367         return ret;
 368     }
 369
 370     if (!pbdev->g_iota) {
 371         pbdev->error_state = true;
 372         pbdev->lgstg_blocked = true;
 373         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 374                                       addr, 0);
 375         return ret;
 376     }
 377
 378     if (addr < pbdev->pba || addr > pbdev->pal) {
 379         pbdev->error_state = true;
 380         pbdev->lgstg_blocked = true;
 381         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 382                                       addr, 0);
 383         return ret;
 384     }
 385
 386     pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
 387                                    addr);
 388
 389     if (!pte) {
 390         pbdev->error_state = true;
 391         pbdev->lgstg_blocked = true;
 392         s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 393                                       addr, ERR_EVENT_Q_BIT);
 394         return ret;
 395     }
 396
 397     flags = pte & ZPCI_PTE_FLAG_MASK;
 398     ret.iova = addr;
 399     ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
 400     ret.addr_mask = 0xfff;
 401
 402     if (flags & ZPCI_PTE_INVALID) {
 403         ret.perm = IOMMU_NONE;
 404     } else {
 405         ret.perm = IOMMU_RW;
 406     }
 407
 408     return ret;
 409 }
 410
 411 static const MemoryRegionIOMMUOps s390_iommu_ops = {
 412     .translate = s390_translate_iommu,
 413 };
 414
 415 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 416 {
 417     S390pciState *s = opaque;
 418
 419     return &s->pbdev[PCI_SLOT(devfn)].as;
 420 }
 421
 422 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
 423 {
 424     uint8_t ind_old, ind_new;
 425     hwaddr len = 1;
 426     uint8_t *ind_addr;
 427
 428     ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
 429     if (!ind_addr) {
 430         s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
 431         return -1;
 432     }
 433     do {
 434         ind_old = *ind_addr;
 435         ind_new = ind_old | to_be_set;
 436     } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
 437     cpu_physical_memory_unmap(ind_addr, len, 1, len);
 438
 439     return ind_old;
 440 }
 441
 442 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
 443                                 unsigned int size)
 444 {
 445     S390PCIBusDevice *pbdev;
 446     uint32_t io_int_word;
 447     uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
 448     uint32_t vec = data & ZPCI_MSI_VEC_MASK;
 449     uint64_t ind_bit;
 450     uint32_t sum_bit;
 451     uint32_t e = 0;
 452
 453     DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
 454
 455     pbdev = s390_pci_find_dev_by_fid(fid);
 456     if (!pbdev) {
 457         e |= (vec << ERR_EVENT_MVN_OFFSET);
 458         s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
 459         return;
 460     }
 461
 462     if (!(pbdev->fh & FH_ENABLED)) {
 463         return;
 464     }
 465
 466     ind_bit = pbdev->routes.adapter.ind_offset;
 467     sum_bit = pbdev->routes.adapter.summary_offset;
 468
 469     set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
 470                    0x80 >> ((ind_bit + vec) % 8));
 471     if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
 472                                        0x80 >> (sum_bit % 8))) {
 473         io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
 474         s390_io_interrupt(0, 0, 0, io_int_word);
 475     }
 476 }
 477
 478 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
 479 {
 480     return 0xffffffff;
 481 }
 482
 483 static const MemoryRegionOps s390_msi_ctrl_ops = {
 484     .write = s390_msi_ctrl_write,
 485     .read = s390_msi_ctrl_read,
 486     .endianness = DEVICE_LITTLE_ENDIAN,
 487 };
 488
 489 void s390_pci_iommu_enable(S390PCIBusDevice *pbdev)
 490 {
 491     uint64_t size = pbdev->pal - pbdev->pba + 1;
 492
 493     memory_region_init_iommu(&pbdev->iommu_mr, OBJECT(&pbdev->mr),
 494                              &s390_iommu_ops, "iommu-s390", size);
 495     memory_region_add_subregion(&pbdev->mr, pbdev->pba, &pbdev->iommu_mr);
 496     pbdev->iommu_enabled = true;
 497 }
 498
 499 void s390_pci_iommu_disable(S390PCIBusDevice *pbdev)
 500 {
 501     memory_region_del_subregion(&pbdev->mr, &pbdev->iommu_mr);
 502     object_unparent(OBJECT(&pbdev->iommu_mr));
 503     pbdev->iommu_enabled = false;
 504 }
 505
 506 static void s390_pcihost_init_as(S390pciState *s)
 507 {
 508     int i;
 509     S390PCIBusDevice *pbdev;
 510
 511     for (i = 0; i < PCI_SLOT_MAX; i++) {
 512         pbdev = &s->pbdev[i];
 513         memory_region_init(&pbdev->mr, OBJECT(s),
 514                            "iommu-root-s390", UINT64_MAX);
 515         address_space_init(&pbdev->as, &pbdev->mr, "iommu-pci");
 516     }
 517
 518     memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
 519                           &s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
 520     address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
 521 }
 522
 523 static int s390_pcihost_init(SysBusDevice *dev)
 524 {
 525     PCIBus *b;
 526     BusState *bus;
 527     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 528     S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
 529
 530     DPRINTF("host_init\n");
 531
 532     b = pci_register_bus(DEVICE(dev), NULL,
 533                          s390_pci_set_irq, s390_pci_map_irq, NULL,
 534                          get_system_memory(), get_system_io(), 0, 64,
 535                          TYPE_PCI_BUS);
 536     s390_pcihost_init_as(s);
 537     pci_setup_iommu(b, s390_pci_dma_iommu, s);
 538
 539     bus = BUS(b);
 540     qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
 541     phb->bus = b;
 542     QTAILQ_INIT(&s->pending_sei);
 543     return 0;
 544 }
 545
 546 static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
 547 {
 548     uint8_t pos;
 549     uint16_t ctrl;
 550     uint32_t table, pba;
 551
 552     pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
 553     if (!pos) {
 554         pbdev->msix.available = false;
 555         return 0;
 556     }
 557
 558     ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS,
 559              pci_config_size(pbdev->pdev), sizeof(ctrl));
 560     table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
 561              pci_config_size(pbdev->pdev), sizeof(table));
 562     pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
 563              pci_config_size(pbdev->pdev), sizeof(pba));
 564
 565     pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
 566     pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
 567     pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
 568     pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
 569     pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
 570     pbdev->msix.available = true;
 571     return 0;
 572 }
 573
 574 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
 575                                   DeviceState *dev, Error **errp)
 576 {
 577     PCIDevice *pci_dev = PCI_DEVICE(dev);
 578     S390PCIBusDevice *pbdev;
 579     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 580                                            ->qbus.parent);
 581
 582     pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 583
 584     pbdev->fid = s390_pci_get_pfid(pci_dev);
 585     pbdev->pdev = pci_dev;
 586     pbdev->configured = true;
 587     pbdev->fh = s390_pci_get_pfh(pci_dev);
 588
 589     s390_pcihost_setup_msix(pbdev);
 590
 591     if (dev->hotplugged) {
 592         s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
 593                                      pbdev->fh, pbdev->fid);
 594         s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
 595                                      pbdev->fh, pbdev->fid);
 596     }
 597 }
 598
 599 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
 600                                     DeviceState *dev, Error **errp)
 601 {
 602     PCIDevice *pci_dev = PCI_DEVICE(dev);
 603     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 604                                            ->qbus.parent);
 605     S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 606
 607     if (pbdev->configured) {
 608         pbdev->configured = false;
 609         s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
 610                                      pbdev->fh, pbdev->fid);
 611     }
 612
 613     s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
 614                                  pbdev->fh, pbdev->fid);
 615     pbdev->fh = 0;
 616     pbdev->fid = 0;
 617     pbdev->pdev = NULL;
 618     object_unparent(OBJECT(pci_dev));
 619 }
 620
 621 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
 622 {
 623     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 624     DeviceClass *dc = DEVICE_CLASS(klass);
 625     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 626
 627     dc->cannot_instantiate_with_device_add_yet = true;
 628     k->init = s390_pcihost_init;
 629     hc->plug = s390_pcihost_hot_plug;
 630     hc->unplug = s390_pcihost_hot_unplug;
 631     msi_nonbroken = true;
 632 }
 633
 634 static const TypeInfo s390_pcihost_info = {
 635     .name          = TYPE_S390_PCI_HOST_BRIDGE,
 636     .parent        = TYPE_PCI_HOST_BRIDGE,
 637     .instance_size = sizeof(S390pciState),
 638     .class_init    = s390_pcihost_class_init,
 639     .interfaces = (InterfaceInfo[]) {
 640         { TYPE_HOTPLUG_HANDLER },
 641         { }
 642     }
 643 };
 644
 645 static void s390_pci_register_types(void)
 646 {
 647     type_register_static(&s390_pcihost_info);
 648 }
 649
 650 type_init(s390_pci_register_types)