1 Tiny Code Generator - Fabrice Bellard.
5 TCG (Tiny Code Generator) began as a generic backend for a C
6 compiler. It was simplified to be used in QEMU. It also has its roots
7 in the QOP code generator written by Paul Brook.
11 The TCG "target" is the architecture for which we generate the
12 code. It is of course not the same as the "target" of QEMU which is
13 the emulated architecture. As TCG started as a generic C backend used
14 for cross compiling, it is assumed that the TCG target is different
15 from the host, although it is never the case for QEMU.
17 In this document, we use "guest" to specify what architecture we are
18 emulating; "target" always means the TCG target, the machine on which
21 A TCG "function" corresponds to a QEMU Translated Block (TB).
23 A TCG "temporary" is a variable only live in a basic
24 block. Temporaries are allocated explicitly in each function.
26 A TCG "local temporary" is a variable only live in a function. Local
27 temporaries are allocated explicitly in each function.
29 A TCG "global" is a variable which is live in all the functions
30 (equivalent of a C global variable). They are defined before the
31 functions defined. A TCG global can be a memory location (e.g. a QEMU
32 CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
33 or a memory location which is stored in a register outside QEMU TBs
34 (not implemented yet).
36 A TCG "basic block" corresponds to a list of instructions terminated
37 by a branch instruction.
39 An operation with "undefined behavior" may result in a crash.
41 An operation with "unspecified behavior" shall not crash. However,
42 the result may be one of several possibilities so may be considered
43 an "undefined result".
45 3) Intermediate representation
49 TCG instructions operate on variables which are temporaries, local
50 temporaries or globals. TCG instructions and variables are strongly
51 typed. Two types are supported: 32 bit integers and 64 bit
52 integers. Pointers are defined as an alias to 32 bit or 64 bit
53 integers depending on the TCG target word size.
55 Each instruction has a fixed number of output variable operands, input
56 variable operands and always constant operands.
58 The notable exception is the call instruction which has a variable
59 number of outputs and inputs.
61 In the textual form, output operands usually come first, followed by
62 input operands, followed by constant operands. The output type is
63 included in the instruction name. Constants are prefixed with a '$'.
65 add_i32 t0, t1, t2 (t0 <- t1 + t2)
71 - Basic blocks end after branches (e.g. brcond_i32 instruction),
72 goto_tb and exit_tb instructions.
73 - Basic blocks start after the end of a previous basic block, or at a
74 set_label instruction.
76 After the end of a basic block, the content of temporaries is
77 destroyed, but local temporaries and globals are preserved.
79 * Floating point types are not supported yet
81 * Pointers: depending on the TCG target, pointer size is 32 bit or 64
82 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
87 Using the tcg_gen_helper_x_y it is possible to call any function
88 taking i32, i64 or pointer types. By default, before calling a helper,
89 all globals are stored at their canonical location and it is assumed
90 that the function can modify them. By default, the helper is allowed to
91 modify the CPU state or raise an exception.
93 This can be overridden using the following function modifiers:
94 - TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,
95 either directly or via an exception. They will not be saved to their
96 canonical locations before calling the helper.
97 - TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
98 They will only be saved to their canonical location before calling helpers,
99 but they won't be reloaded afterwise.
100 - TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
101 the return value is not used.
103 Note that TCG_CALL_NO_READ_GLOBALS implies TCG_CALL_NO_WRITE_GLOBALS.
105 On some TCG targets (e.g. x86), several calling conventions are
110 Use the instruction 'br' to jump to a label.
112 3.3) Code Optimizations
114 When generating instructions, you can count on at least the following
117 - Single instructions are simplified, e.g.
119 and_i32 t0, t0, $0xffffffff
123 - A liveness analysis is done at the basic block level. The
124 information is used to suppress moves from a dead variable to
125 another one. It is also used to remove instructions which compute
126 dead results. The later is especially useful for condition code
127 optimization in QEMU.
129 In the following example:
135 only the last instruction is kept.
137 3.4) Instruction Reference
139 ********* Function call
141 * call <ret> <params> ptr
143 call function 'ptr' (pointer type)
145 <ret> optional 32 bit or 64 bit return value
146 <params> optional 32 bit or 64 bit parameters
148 ********* Jumps/Labels
152 Define label 'label' at the current program point.
158 * brcond_i32/i64 t0, t1, cond, label
160 Conditional jump if t0 cond t1 is true. cond can be:
163 TCG_COND_LT /* signed */
164 TCG_COND_GE /* signed */
165 TCG_COND_LE /* signed */
166 TCG_COND_GT /* signed */
167 TCG_COND_LTU /* unsigned */
168 TCG_COND_GEU /* unsigned */
169 TCG_COND_LEU /* unsigned */
170 TCG_COND_GTU /* unsigned */
174 * add_i32/i64 t0, t1, t2
178 * sub_i32/i64 t0, t1, t2
184 t0=-t1 (two's complement)
186 * mul_i32/i64 t0, t1, t2
190 * div_i32/i64 t0, t1, t2
192 t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
194 * divu_i32/i64 t0, t1, t2
196 t0=t1/t2 (unsigned). Undefined behavior if division by zero.
198 * rem_i32/i64 t0, t1, t2
200 t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
202 * remu_i32/i64 t0, t1, t2
204 t0=t1%t2 (unsigned). Undefined behavior if division by zero.
208 * and_i32/i64 t0, t1, t2
212 * or_i32/i64 t0, t1, t2
216 * xor_i32/i64 t0, t1, t2
224 * andc_i32/i64 t0, t1, t2
228 * eqv_i32/i64 t0, t1, t2
230 t0=~(t1^t2), or equivalently, t0=t1^~t2
232 * nand_i32/i64 t0, t1, t2
236 * nor_i32/i64 t0, t1, t2
240 * orc_i32/i64 t0, t1, t2
244 ********* Shifts/Rotates
246 * shl_i32/i64 t0, t1, t2
248 t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
250 * shr_i32/i64 t0, t1, t2
252 t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
254 * sar_i32/i64 t0, t1, t2
256 t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
258 * rotl_i32/i64 t0, t1, t2
260 Rotation of t2 bits to the left.
261 Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
263 * rotr_i32/i64 t0, t1, t2
265 Rotation of t2 bits to the right.
266 Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
274 Move t1 to t0 (both operands must have the same type).
276 * ext8s_i32/i64 t0, t1
278 ext16s_i32/i64 t0, t1
279 ext16u_i32/i64 t0, t1
283 8, 16 or 32 bit sign/zero extension (both operands must have the same type)
285 * bswap16_i32/i64 t0, t1
287 16 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
288 bytes are set to zero.
290 * bswap32_i32/i64 t0, t1
292 32 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
293 the four high order bytes are set to zero.
301 Indicate that the value of t0 won't be used later. It is useful to
302 force dead code elimination.
304 * deposit_i32/i64 dest, t1, t2, pos, len
306 Deposit T2 as a bitfield into T1, placing the result in DEST.
307 The bitfield is described by POS/LEN, which are immediate values:
309 LEN - the length of the bitfield
310 POS - the position of the first bit, counting from the LSB
312 For example, pos=8, len=4 indicates a 4-bit field at bit 8.
313 This operation would be equivalent to
315 dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
318 ********* Conditional moves
320 * setcond_i32/i64 dest, t1, t2, cond
324 Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
326 * movcond_i32/i64 dest, c1, c2, v1, v2, cond
328 dest = (c1 cond c2 ? v1 : v2)
330 Set DEST to V1 if (C1 cond C2) is true, otherwise set to V2.
332 ********* Type conversions
335 Convert t1 (32 bit) to t0 (64 bit) and does sign extension
337 * extu_i32_i64 t0, t1
338 Convert t1 (32 bit) to t0 (64 bit) and does zero extension
340 * trunc_i64_i32 t0, t1
341 Truncate t1 (64 bit) to t0 (32 bit)
343 * concat_i32_i64 t0, t1, t2
344 Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
347 * concat32_i64 t0, t1, t2
348 Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
353 * ld_i32/i64 t0, t1, offset
354 ld8s_i32/i64 t0, t1, offset
355 ld8u_i32/i64 t0, t1, offset
356 ld16s_i32/i64 t0, t1, offset
357 ld16u_i32/i64 t0, t1, offset
358 ld32s_i64 t0, t1, offset
359 ld32u_i64 t0, t1, offset
361 t0 = read(t1 + offset)
362 Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
363 offset must be a constant.
365 * st_i32/i64 t0, t1, offset
366 st8_i32/i64 t0, t1, offset
367 st16_i32/i64 t0, t1, offset
368 st32_i64 t0, t1, offset
370 write(t0, t1 + offset)
371 Write 8, 16, 32 or 64 bits to host memory.
373 All this opcodes assume that the pointed host memory doesn't correspond
374 to a global. In the latter case the behaviour is unpredictable.
376 ********* Multiword arithmetic support
378 * add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
379 * sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
381 Similar to add/sub, except that the double-word inputs T1 and T2 are
382 formed from two single-word arguments, and the double-word output T0
383 is returned in two single-word outputs.
385 * mulu2_i32/i64 t0_low, t0_high, t1, t2
387 Similar to mul, except two unsigned inputs T1 and T2 yielding the full
388 double-word product T0. The later is returned in two single-word outputs.
390 * muls2_i32/i64 t0_low, t0_high, t1, t2
392 Similar to mulu2, except the two inputs T1 and T2 are signed.
394 ********* 64-bit guest on 32-bit host support
396 The following opcodes are internal to TCG. Thus they are to be implemented by
397 32-bit host code generators, but are not to be emitted by guest translators.
398 They are emitted as needed by inline functions within "tcg-op.h".
400 * brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
402 Similar to brcond, except that the 64-bit values T0 and T1
403 are formed from two 32-bit arguments.
405 * setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
407 Similar to setcond, except that the 64-bit values T1 and T2 are
408 formed from two 32-bit arguments. The result is a 32-bit value.
410 ********* QEMU specific operations
414 Exit the current TB and return the value t0 (word type).
418 Exit the current TB and jump to the TB index 'index' (constant) if the
419 current TB was linked to this TB. Otherwise execute the next
420 instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
421 at most once with each slot index per TB.
423 * qemu_ld_i32/i64 t0, t1, flags, memidx
424 * qemu_st_i32/i64 t0, t1, flags, memidx
426 Load data at the guest address t1 into t0, or store data in t0 at guest
427 address t1. The _i32/_i64 size applies to the size of the input/output
428 register t0 only. The address t1 is always sized according to the guest,
429 and the width of the memory operation is controlled by flags.
431 Both t0 and t1 may be split into little-endian ordered pairs of registers
432 if dealing with 64-bit quantities on a 32-bit host.
434 The memidx selects the qemu tlb index to use (e.g. user or kernel access).
435 The flags are the TCGMemOp bits, selecting the sign, width, and endianness
436 of the memory access.
438 For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
439 64-bit memory access specified in flags.
443 Note 1: Some shortcuts are defined when the last operand is known to be
444 a constant (e.g. addi for add, movi for mov).
446 Note 2: When using TCG, the opcodes must never be generated directly
447 as some of them may not be available as "real" opcodes. Always use the
448 function tcg_gen_xxx(args).
452 tcg-target.h contains the target specific definitions. tcg-target.c
453 contains the target specific code.
457 The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
458 64 bit. It is expected that the pointer has the same size as the word.
460 On a 32 bit target, all 64 bit operations are converted to 32 bits. A
461 few specific operations must be implemented to allow it (see add2_i32,
462 sub2_i32, brcond2_i32).
464 Floating point operations are not supported in this version. A
465 previous incarnation of the code generator had full support of them,
466 but it is better to concentrate on integer operations first.
468 On a 64 bit target, no assumption is made in TCG about the storage of
469 the 32 bit values in 64 bit registers.
473 GCC like constraints are used to define the constraints of every
474 instruction. Memory constraints are not supported in this
475 version. Aliases are specified in the input operands as for GCC.
477 The same register may be used for both an input and an output, even when
478 they are not explicitly aliased. If an op expands to multiple target
479 instructions then care must be taken to avoid clobbering input values.
480 GCC style "early clobber" outputs are not currently supported.
482 A target can define specific register or constant constraints. If an
483 operation uses a constant input constraint which does not allow all
484 constants, it must also accept registers in order to have a fallback.
486 The movi_i32 and movi_i64 operations must accept any constants.
488 The mov_i32 and mov_i64 operations must accept any registers of the
491 The ld/st instructions must accept signed 32 bit constant offsets. It
492 can be implemented by reserving a specific register to compute the
493 address if the offset is too big.
495 The ld/st instructions must accept any destination (ld) or source (st)
498 4.3) Function call assumptions
500 - The only supported types for parameters and return value are: 32 and
501 64 bit integers and pointer.
502 - The stack grows downwards.
503 - The first N parameters are passed in registers.
504 - The next parameters are passed on the stack by storing them as words.
505 - Some registers are clobbered during the call.
506 - The function can return 0 or 1 value in registers. On a 32 bit
507 target, functions must be able to return 2 values in registers for
510 5) Recommended coding rules for best performance
512 - Use globals to represent the parts of the QEMU CPU state which are
513 often modified, e.g. the integer registers and the condition
514 codes. TCG will be able to use host registers to store them.
516 - Avoid globals stored in fixed registers. They must be used only to
517 store the pointer to the CPU state and possibly to store a pointer
518 to a register window.
520 - Use temporaries. Use local temporaries only when really needed,
521 e.g. when you need to use a value after a jump. Local temporaries
522 introduce a performance hit in the current TCG implementation: their
523 content is saved to memory at end of each basic block.
525 - Free temporaries and local temporaries when they are no longer used
526 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you
527 should free it after it is used. Freeing temporaries does not yield
528 a better generated code, but it reduces the memory usage of TCG and
529 the speed of the translation.
531 - Don't hesitate to use helpers for complicated or seldom used guest
532 instructions. There is little performance advantage in using TCG to
533 implement guest instructions taking more than about twenty TCG
534 instructions. Note that this rule of thumb is more applicable to
535 helpers doing complex logic or arithmetic, where the C compiler has
536 scope to do a good job of optimisation; it is less relevant where
537 the instruction is mostly doing loads and stores, and in those cases
538 inline TCG may still be faster for longer sequences.
540 - The hard limit on the number of TCG instructions you can generate
541 per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h --
542 you cannot exceed this without risking a buffer overrun.
544 - Use the 'discard' instruction if you know that TCG won't be able to
545 prove that a given global is "dead" at a given program point. The
546 x86 guest uses it to improve the condition codes optimisation.