hw/sd/milkymist-memcard.c

   1 /*
   2  *  QEMU model of the Milkymist SD Card Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/memcard.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "qemu/module.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "trace.h"
  30 #include "qapi/error.h"
  31 #include "sysemu/block-backend.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/qdev-properties.h"
  34 #include "hw/sd/sd.h"
  35
  36 enum {
  37     ENABLE_CMD_TX   = (1<<0),
  38     ENABLE_CMD_RX   = (1<<1),
  39     ENABLE_DAT_TX   = (1<<2),
  40     ENABLE_DAT_RX   = (1<<3),
  41 };
  42
  43 enum {
  44     PENDING_CMD_TX   = (1<<0),
  45     PENDING_CMD_RX   = (1<<1),
  46     PENDING_DAT_TX   = (1<<2),
  47     PENDING_DAT_RX   = (1<<3),
  48 };
  49
  50 enum {
  51     START_CMD_TX    = (1<<0),
  52     START_DAT_RX    = (1<<1),
  53 };
  54
  55 enum {
  56     R_CLK2XDIV = 0,
  57     R_ENABLE,
  58     R_PENDING,
  59     R_START,
  60     R_CMD,
  61     R_DAT,
  62     R_MAX
  63 };
  64
  65 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
  66 #define MILKYMIST_MEMCARD(obj) \
  67     OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
  68
  69 #define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
  70
  71 struct MilkymistMemcardState {
  72     SysBusDevice parent_obj;
  73
  74     MemoryRegion regs_region;
  75     SDBus sdbus;
  76
  77     int command_write_ptr;
  78     int response_read_ptr;
  79     int response_len;
  80     int ignore_next_cmd;
  81     int enabled;
  82     uint8_t command[6];
  83     uint8_t response[17];
  84     uint32_t regs[R_MAX];
  85 };
  86 typedef struct MilkymistMemcardState MilkymistMemcardState;
  87
  88 static void update_pending_bits(MilkymistMemcardState *s)
  89 {
  90     /* transmits are instantaneous, thus tx pending bits are never set */
  91     s->regs[R_PENDING] = 0;
  92     /* if rx is enabled the corresponding pending bits are always set */
  93     if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
  94         s->regs[R_PENDING] |= PENDING_CMD_RX;
  95     }
  96     if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
  97         s->regs[R_PENDING] |= PENDING_DAT_RX;
  98     }
  99 }
 100
 101 static void memcard_sd_command(MilkymistMemcardState *s)
 102 {
 103     SDRequest req;
 104
 105     req.cmd = s->command[0] & 0x3f;
 106     req.arg = ldl_be_p(s->command + 1);
 107     req.crc = s->command[5];
 108
 109     s->response[0] = req.cmd;
 110     s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
 111     s->response_read_ptr = 0;
 112
 113     if (s->response_len == 16) {
 114         /* R2 response */
 115         s->response[0] = 0x3f;
 116         s->response_len += 1;
 117     } else if (s->response_len == 4) {
 118         /* no crc calculation, insert dummy byte */
 119         s->response[5] = 0;
 120         s->response_len += 2;
 121     }
 122
 123     if (req.cmd == 0) {
 124         /* next write is a dummy byte to clock the initialization of the sd
 125          * card */
 126         s->ignore_next_cmd = 1;
 127     }
 128 }
 129
 130 static uint64_t memcard_read(void *opaque, hwaddr addr,
 131                              unsigned size)
 132 {
 133     MilkymistMemcardState *s = opaque;
 134     uint32_t r = 0;
 135
 136     addr >>= 2;
 137     switch (addr) {
 138     case R_CMD:
 139         if (!s->enabled) {
 140             r = 0xff;
 141         } else {
 142             r = s->response[s->response_read_ptr++];
 143             if (s->response_read_ptr > s->response_len) {
 144                 qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
 145                               "read more cmd bytes than available: clipping\n");
 146                 s->response_read_ptr = 0;
 147             }
 148         }
 149         break;
 150     case R_DAT:
 151         if (!s->enabled) {
 152             r = 0xffffffff;
 153         } else {
 154             sdbus_read_data(&s->sdbus, &r, sizeof(r));
 155             be32_to_cpus(&r);
 156         }
 157         break;
 158     case R_CLK2XDIV:
 159     case R_ENABLE:
 160     case R_PENDING:
 161     case R_START:
 162         r = s->regs[addr];
 163         break;
 164
 165     default:
 166         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 167                       "read access to unknown register 0x%" HWADDR_PRIx "\n",
 168                       addr << 2);
 169         break;
 170     }
 171
 172     trace_milkymist_memcard_memory_read(addr << 2, r);
 173
 174     return r;
 175 }
 176
 177 static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
 178                           unsigned size)
 179 {
 180     MilkymistMemcardState *s = opaque;
 181     uint32_t val32;
 182
 183     trace_milkymist_memcard_memory_write(addr, value);
 184
 185     addr >>= 2;
 186     switch (addr) {
 187     case R_PENDING:
 188         /* clear rx pending bits */
 189         s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
 190         update_pending_bits(s);
 191         break;
 192     case R_CMD:
 193         if (!s->enabled) {
 194             break;
 195         }
 196         if (s->ignore_next_cmd) {
 197             s->ignore_next_cmd = 0;
 198             break;
 199         }
 200         s->command[s->command_write_ptr] = value & 0xff;
 201         s->command_write_ptr = (s->command_write_ptr + 1) % 6;
 202         if (s->command_write_ptr == 0) {
 203             memcard_sd_command(s);
 204         }
 205         break;
 206     case R_DAT:
 207         if (!s->enabled) {
 208             break;
 209         }
 210         val32 = cpu_to_be32(value);
 211         sdbus_write_data(&s->sdbus, &val32, sizeof(val32));
 212         break;
 213     case R_ENABLE:
 214         s->regs[addr] = value;
 215         update_pending_bits(s);
 216         break;
 217     case R_CLK2XDIV:
 218     case R_START:
 219         s->regs[addr] = value;
 220         break;
 221
 222     default:
 223         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 224                       "write access to unknown register 0x%" HWADDR_PRIx " "
 225                       "(value 0x%" PRIx64 ")\n", addr << 2, value);
 226         break;
 227     }
 228 }
 229
 230 static const MemoryRegionOps memcard_mmio_ops = {
 231     .read = memcard_read,
 232     .write = memcard_write,
 233     .valid = {
 234         .min_access_size = 4,
 235         .max_access_size = 4,
 236     },
 237     .endianness = DEVICE_NATIVE_ENDIAN,
 238 };
 239
 240 static void milkymist_memcard_reset(DeviceState *d)
 241 {
 242     MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
 243     int i;
 244
 245     s->command_write_ptr = 0;
 246     s->response_read_ptr = 0;
 247     s->response_len = 0;
 248
 249     for (i = 0; i < R_MAX; i++) {
 250         s->regs[i] = 0;
 251     }
 252 }
 253
 254 static void milkymist_memcard_set_readonly(DeviceState *dev, bool level)
 255 {
 256     qemu_log_mask(LOG_UNIMP,
 257                   "milkymist_memcard: read-only mode not supported\n");
 258 }
 259
 260 static void milkymist_memcard_set_inserted(DeviceState *dev, bool level)
 261 {
 262     MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
 263
 264     s->enabled = !!level;
 265 }
 266
 267 static void milkymist_memcard_init(Object *obj)
 268 {
 269     MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
 270     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 271
 272     memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
 273             "milkymist-memcard", R_MAX * 4);
 274     sysbus_init_mmio(dev, &s->regs_region);
 275
 276     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
 277                         DEVICE(obj), "sd-bus");
 278 }
 279
 280 static const VMStateDescription vmstate_milkymist_memcard = {
 281     .name = "milkymist-memcard",
 282     .version_id = 1,
 283     .minimum_version_id = 1,
 284     .fields = (VMStateField[]) {
 285         VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
 286         VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
 287         VMSTATE_INT32(response_len, MilkymistMemcardState),
 288         VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
 289         VMSTATE_INT32(enabled, MilkymistMemcardState),
 290         VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
 291         VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
 292         VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
 293         VMSTATE_END_OF_LIST()
 294     }
 295 };
 296
 297 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
 298 {
 299     DeviceClass *dc = DEVICE_CLASS(klass);
 300
 301     dc->reset = milkymist_memcard_reset;
 302     dc->vmsd = &vmstate_milkymist_memcard;
 303     /* Reason: output IRQs should be wired up */
 304     dc->user_creatable = false;
 305 }
 306
 307 static const TypeInfo milkymist_memcard_info = {
 308     .name          = TYPE_MILKYMIST_MEMCARD,
 309     .parent        = TYPE_SYS_BUS_DEVICE,
 310     .instance_size = sizeof(MilkymistMemcardState),
 311     .instance_init = milkymist_memcard_init,
 312     .class_init    = milkymist_memcard_class_init,
 313 };
 314
 315 static void milkymist_sdbus_class_init(ObjectClass *klass, void *data)
 316 {
 317     SDBusClass *sbc = SD_BUS_CLASS(klass);
 318
 319     sbc->set_inserted = milkymist_memcard_set_inserted;
 320     sbc->set_readonly = milkymist_memcard_set_readonly;
 321 }
 322
 323 static const TypeInfo milkymist_sdbus_info = {
 324     .name = TYPE_MILKYMIST_SDBUS,
 325     .parent = TYPE_SD_BUS,
 326     .instance_size = sizeof(SDBus),
 327     .class_init = milkymist_sdbus_class_init,
 328 };
 329
 330 static void milkymist_memcard_register_types(void)
 331 {
 332     type_register_static(&milkymist_memcard_info);
 333     type_register_static(&milkymist_sdbus_info);
 334 }
 335
 336 type_init(milkymist_memcard_register_types)