?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
scsi: esp: check TI buffer index before read/write
[qemu.git] / linux-user / main.c
blob5f3ec9747acd7ead4eef98cfde14bde363ccdc5a
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu.h"
25 #include "qemu/path.h"
26 #include "qemu/cutils.h"
27 #include "qemu/help_option.h"
28 #include "cpu.h"
29 #include "tcg.h"
30 #include "qemu/timer.h"
31 #include "qemu/envlist.h"
32 #include "elf.h"
33 #include "exec/log.h"
34
35 char *exec_path;
36
37 int singlestep;
38 static const char *filename;
39 static const char *argv0;
40 static int gdbstub_port;
41 static envlist_t *envlist;
42 static const char *cpu_model;
43 unsigned long mmap_min_addr;
44 unsigned long guest_base;
45 int have_guest_base;
46
47 #define EXCP_DUMP(env, fmt, ...) \
48 do { \
49 CPUState *cs = ENV_GET_CPU(env); \
50 fprintf(stderr, fmt , ## __VA_ARGS__); \
51 cpu_dump_state(cs, stderr, fprintf, 0); \
52 if (qemu_log_separate()) { \
53 qemu_log(fmt, ## __VA_ARGS__); \
54 log_cpu_state(cs, 0); \
55 } \
56 } while (0)
57
58 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
59 /*
60 * When running 32-on-64 we should make sure we can fit all of the possible
61 * guest address space into a contiguous chunk of virtual host memory.
62 *
63 * This way we will never overlap with our own libraries or binaries or stack
64 * or anything else that QEMU maps.
65 */
66 # ifdef TARGET_MIPS
67 /* MIPS only supports 31 bits of virtual address space for user space */
68 unsigned long reserved_va = 0x77000000;
69 # else
70 unsigned long reserved_va = 0xf7000000;
71 # endif
72 #else
73 unsigned long reserved_va;
74 #endif
75
76 static void usage(int exitcode);
77
78 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
79 const char *qemu_uname_release;
80
81 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
82 we allocate a bigger stack. Need a better solution, for example
83 by remapping the process stack directly at the right place */
84 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
85
86 void gemu_log(const char *fmt, ...)
87 {
88 va_list ap;
89
90 va_start(ap, fmt);
91 vfprintf(stderr, fmt, ap);
92 va_end(ap);
93 }
94
95 #if defined(TARGET_I386)
96 int cpu_get_pic_interrupt(CPUX86State *env)
97 {
98 return -1;
99 }
100 #endif
101
102 /***********************************************************/
103 /* Helper routines for implementing atomic operations. */
104
105 /* To implement exclusive operations we force all cpus to syncronise.
106 We don't require a full sync, only that no cpus are executing guest code.
107 The alternative is to map target atomic ops onto host equivalents,
108 which requires quite a lot of per host/target work. */
109 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
110 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
111 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
112 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
113 static int pending_cpus;
114
115 /* Make sure everything is in a consistent state for calling fork(). */
116 void fork_start(void)
117 {
118 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
119 pthread_mutex_lock(&exclusive_lock);
120 mmap_fork_start();
121 }
122
123 void fork_end(int child)
124 {
125 mmap_fork_end(child);
126 if (child) {
127 CPUState *cpu, *next_cpu;
128 /* Child processes created by fork() only have a single thread.
129 Discard information about the parent threads. */
130 CPU_FOREACH_SAFE(cpu, next_cpu) {
131 if (cpu != thread_cpu) {
132 QTAILQ_REMOVE(&cpus, thread_cpu, node);
133 }
134 }
135 pending_cpus = 0;
136 pthread_mutex_init(&exclusive_lock, NULL);
137 pthread_mutex_init(&cpu_list_mutex, NULL);
138 pthread_cond_init(&exclusive_cond, NULL);
139 pthread_cond_init(&exclusive_resume, NULL);
140 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
141 gdbserver_fork(thread_cpu);
142 } else {
143 pthread_mutex_unlock(&exclusive_lock);
144 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
145 }
146 }
147
148 /* Wait for pending exclusive operations to complete. The exclusive lock
149 must be held. */
150 static inline void exclusive_idle(void)
151 {
152 while (pending_cpus) {
153 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
154 }
155 }
156
157 /* Start an exclusive operation.
158 Must only be called from outside cpu_arm_exec. */
159 static inline void start_exclusive(void)
160 {
161 CPUState *other_cpu;
162
163 pthread_mutex_lock(&exclusive_lock);
164 exclusive_idle();
165
166 pending_cpus = 1;
167 /* Make all other cpus stop executing. */
168 CPU_FOREACH(other_cpu) {
169 if (other_cpu->running) {
170 pending_cpus++;
171 cpu_exit(other_cpu);
172 }
173 }
174 if (pending_cpus > 1) {
175 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
176 }
177 }
178
179 /* Finish an exclusive operation. */
180 static inline void __attribute__((unused)) end_exclusive(void)
181 {
182 pending_cpus = 0;
183 pthread_cond_broadcast(&exclusive_resume);
184 pthread_mutex_unlock(&exclusive_lock);
185 }
186
187 /* Wait for exclusive ops to finish, and begin cpu execution. */
188 static inline void cpu_exec_start(CPUState *cpu)
189 {
190 pthread_mutex_lock(&exclusive_lock);
191 exclusive_idle();
192 cpu->running = true;
193 pthread_mutex_unlock(&exclusive_lock);
194 }
195
196 /* Mark cpu as not executing, and release pending exclusive ops. */
197 static inline void cpu_exec_end(CPUState *cpu)
198 {
199 pthread_mutex_lock(&exclusive_lock);
200 cpu->running = false;
201 if (pending_cpus > 1) {
202 pending_cpus--;
203 if (pending_cpus == 1) {
204 pthread_cond_signal(&exclusive_cond);
205 }
206 }
207 exclusive_idle();
208 pthread_mutex_unlock(&exclusive_lock);
209 }
210
211 void cpu_list_lock(void)
212 {
213 pthread_mutex_lock(&cpu_list_mutex);
214 }
215
216 void cpu_list_unlock(void)
217 {
218 pthread_mutex_unlock(&cpu_list_mutex);
219 }
220
221
222 #ifdef TARGET_I386
223 /***********************************************************/
224 /* CPUX86 core interface */
225
226 uint64_t cpu_get_tsc(CPUX86State *env)
227 {
228 return cpu_get_host_ticks();
229 }
230
231 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
232 int flags)
233 {
234 unsigned int e1, e2;
235 uint32_t *p;
236 e1 = (addr << 16) | (limit & 0xffff);
237 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
238 e2 |= flags;
239 p = ptr;
240 p[0] = tswap32(e1);
241 p[1] = tswap32(e2);
242 }
243
244 static uint64_t *idt_table;
245 #ifdef TARGET_X86_64
246 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
247 uint64_t addr, unsigned int sel)
248 {
249 uint32_t *p, e1, e2;
250 e1 = (addr & 0xffff) | (sel << 16);
251 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
252 p = ptr;
253 p[0] = tswap32(e1);
254 p[1] = tswap32(e2);
255 p[2] = tswap32(addr >> 32);
256 p[3] = 0;
257 }
258 /* only dpl matters as we do only user space emulation */
259 static void set_idt(int n, unsigned int dpl)
260 {
261 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
262 }
263 #else
264 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
265 uint32_t addr, unsigned int sel)
266 {
267 uint32_t *p, e1, e2;
268 e1 = (addr & 0xffff) | (sel << 16);
269 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
270 p = ptr;
271 p[0] = tswap32(e1);
272 p[1] = tswap32(e2);
273 }
274
275 /* only dpl matters as we do only user space emulation */
276 static void set_idt(int n, unsigned int dpl)
277 {
278 set_gate(idt_table + n, 0, dpl, 0, 0);
279 }
280 #endif
281
282 void cpu_loop(CPUX86State *env)
283 {
284 CPUState *cs = CPU(x86_env_get_cpu(env));
285 int trapnr;
286 abi_ulong pc;
287 target_siginfo_t info;
288
289 for(;;) {
290 cpu_exec_start(cs);
291 trapnr = cpu_x86_exec(cs);
292 cpu_exec_end(cs);
293 switch(trapnr) {
294 case 0x80:
295 /* linux syscall from int $0x80 */
296 env->regs[R_EAX] = do_syscall(env,
297 env->regs[R_EAX],
298 env->regs[R_EBX],
299 env->regs[R_ECX],
300 env->regs[R_EDX],
301 env->regs[R_ESI],
302 env->regs[R_EDI],
303 env->regs[R_EBP],
304 0, 0);
305 break;
306 #ifndef TARGET_ABI32
307 case EXCP_SYSCALL:
308 /* linux syscall from syscall instruction */
309 env->regs[R_EAX] = do_syscall(env,
310 env->regs[R_EAX],
311 env->regs[R_EDI],
312 env->regs[R_ESI],
313 env->regs[R_EDX],
314 env->regs[10],
315 env->regs[8],
316 env->regs[9],
317 0, 0);
318 break;
319 #endif
320 case EXCP0B_NOSEG:
321 case EXCP0C_STACK:
322 info.si_signo = TARGET_SIGBUS;
323 info.si_errno = 0;
324 info.si_code = TARGET_SI_KERNEL;
325 info._sifields._sigfault._addr = 0;
326 queue_signal(env, info.si_signo, &info);
327 break;
328 case EXCP0D_GPF:
329 /* XXX: potential problem if ABI32 */
330 #ifndef TARGET_X86_64
331 if (env->eflags & VM_MASK) {
332 handle_vm86_fault(env);
333 } else
334 #endif
335 {
336 info.si_signo = TARGET_SIGSEGV;
337 info.si_errno = 0;
338 info.si_code = TARGET_SI_KERNEL;
339 info._sifields._sigfault._addr = 0;
340 queue_signal(env, info.si_signo, &info);
341 }
342 break;
343 case EXCP0E_PAGE:
344 info.si_signo = TARGET_SIGSEGV;
345 info.si_errno = 0;
346 if (!(env->error_code & 1))
347 info.si_code = TARGET_SEGV_MAPERR;
348 else
349 info.si_code = TARGET_SEGV_ACCERR;
350 info._sifields._sigfault._addr = env->cr[2];
351 queue_signal(env, info.si_signo, &info);
352 break;
353 case EXCP00_DIVZ:
354 #ifndef TARGET_X86_64
355 if (env->eflags & VM_MASK) {
356 handle_vm86_trap(env, trapnr);
357 } else
358 #endif
359 {
360 /* division by zero */
361 info.si_signo = TARGET_SIGFPE;
362 info.si_errno = 0;
363 info.si_code = TARGET_FPE_INTDIV;
364 info._sifields._sigfault._addr = env->eip;
365 queue_signal(env, info.si_signo, &info);
366 }
367 break;
368 case EXCP01_DB:
369 case EXCP03_INT3:
370 #ifndef TARGET_X86_64
371 if (env->eflags & VM_MASK) {
372 handle_vm86_trap(env, trapnr);
373 } else
374 #endif
375 {
376 info.si_signo = TARGET_SIGTRAP;
377 info.si_errno = 0;
378 if (trapnr == EXCP01_DB) {
379 info.si_code = TARGET_TRAP_BRKPT;
380 info._sifields._sigfault._addr = env->eip;
381 } else {
382 info.si_code = TARGET_SI_KERNEL;
383 info._sifields._sigfault._addr = 0;
384 }
385 queue_signal(env, info.si_signo, &info);
386 }
387 break;
388 case EXCP04_INTO:
389 case EXCP05_BOUND:
390 #ifndef TARGET_X86_64
391 if (env->eflags & VM_MASK) {
392 handle_vm86_trap(env, trapnr);
393 } else
394 #endif
395 {
396 info.si_signo = TARGET_SIGSEGV;
397 info.si_errno = 0;
398 info.si_code = TARGET_SI_KERNEL;
399 info._sifields._sigfault._addr = 0;
400 queue_signal(env, info.si_signo, &info);
401 }
402 break;
403 case EXCP06_ILLOP:
404 info.si_signo = TARGET_SIGILL;
405 info.si_errno = 0;
406 info.si_code = TARGET_ILL_ILLOPN;
407 info._sifields._sigfault._addr = env->eip;
408 queue_signal(env, info.si_signo, &info);
409 break;
410 case EXCP_INTERRUPT:
411 /* just indicate that signals should be handled asap */
412 break;
413 case EXCP_DEBUG:
414 {
415 int sig;
416
417 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
418 if (sig)
419 {
420 info.si_signo = sig;
421 info.si_errno = 0;
422 info.si_code = TARGET_TRAP_BRKPT;
423 queue_signal(env, info.si_signo, &info);
424 }
425 }
426 break;
427 default:
428 pc = env->segs[R_CS].base + env->eip;
429 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
430 (long)pc, trapnr);
431 abort();
432 }
433 process_pending_signals(env);
434 }
435 }
436 #endif
437
438 #ifdef TARGET_ARM
439
440 #define get_user_code_u32(x, gaddr, env) \
441 ({ abi_long __r = get_user_u32((x), (gaddr)); \
442 if (!__r && bswap_code(arm_sctlr_b(env))) { \
443 (x) = bswap32(x); \
444 } \
445 __r; \
446 })
447
448 #define get_user_code_u16(x, gaddr, env) \
449 ({ abi_long __r = get_user_u16((x), (gaddr)); \
450 if (!__r && bswap_code(arm_sctlr_b(env))) { \
451 (x) = bswap16(x); \
452 } \
453 __r; \
454 })
455
456 #define get_user_data_u32(x, gaddr, env) \
457 ({ abi_long __r = get_user_u32((x), (gaddr)); \
458 if (!__r && arm_cpu_bswap_data(env)) { \
459 (x) = bswap32(x); \
460 } \
461 __r; \
462 })
463
464 #define get_user_data_u16(x, gaddr, env) \
465 ({ abi_long __r = get_user_u16((x), (gaddr)); \
466 if (!__r && arm_cpu_bswap_data(env)) { \
467 (x) = bswap16(x); \
468 } \
469 __r; \
470 })
471
472 #define put_user_data_u32(x, gaddr, env) \
473 ({ typeof(x) __x = (x); \
474 if (arm_cpu_bswap_data(env)) { \
475 __x = bswap32(__x); \
476 } \
477 put_user_u32(__x, (gaddr)); \
478 })
479
480 #define put_user_data_u16(x, gaddr, env) \
481 ({ typeof(x) __x = (x); \
482 if (arm_cpu_bswap_data(env)) { \
483 __x = bswap16(__x); \
484 } \
485 put_user_u16(__x, (gaddr)); \
486 })
487
488 #ifdef TARGET_ABI32
489 /* Commpage handling -- there is no commpage for AArch64 */
490
491 /*
492 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
493 * Input:
494 * r0 = pointer to oldval
495 * r1 = pointer to newval
496 * r2 = pointer to target value
497 *
498 * Output:
499 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
500 * C set if *ptr was changed, clear if no exchange happened
501 *
502 * Note segv's in kernel helpers are a bit tricky, we can set the
503 * data address sensibly but the PC address is just the entry point.
504 */
505 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
506 {
507 uint64_t oldval, newval, val;
508 uint32_t addr, cpsr;
509 target_siginfo_t info;
510
511 /* Based on the 32 bit code in do_kernel_trap */
512
513 /* XXX: This only works between threads, not between processes.
514 It's probably possible to implement this with native host
515 operations. However things like ldrex/strex are much harder so
516 there's not much point trying. */
517 start_exclusive();
518 cpsr = cpsr_read(env);
519 addr = env->regs[2];
520
521 if (get_user_u64(oldval, env->regs[0])) {
522 env->exception.vaddress = env->regs[0];
523 goto segv;
524 };
525
526 if (get_user_u64(newval, env->regs[1])) {
527 env->exception.vaddress = env->regs[1];
528 goto segv;
529 };
530
531 if (get_user_u64(val, addr)) {
532 env->exception.vaddress = addr;
533 goto segv;
534 }
535
536 if (val == oldval) {
537 val = newval;
538
539 if (put_user_u64(val, addr)) {
540 env->exception.vaddress = addr;
541 goto segv;
542 };
543
544 env->regs[0] = 0;
545 cpsr |= CPSR_C;
546 } else {
547 env->regs[0] = -1;
548 cpsr &= ~CPSR_C;
549 }
550 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
551 end_exclusive();
552 return;
553
554 segv:
555 end_exclusive();
556 /* We get the PC of the entry address - which is as good as anything,
557 on a real kernel what you get depends on which mode it uses. */
558 info.si_signo = TARGET_SIGSEGV;
559 info.si_errno = 0;
560 /* XXX: check env->error_code */
561 info.si_code = TARGET_SEGV_MAPERR;
562 info._sifields._sigfault._addr = env->exception.vaddress;
563 queue_signal(env, info.si_signo, &info);
564 }
565
566 /* Handle a jump to the kernel code page. */
567 static int
568 do_kernel_trap(CPUARMState *env)
569 {
570 uint32_t addr;
571 uint32_t cpsr;
572 uint32_t val;
573
574 switch (env->regs[15]) {
575 case 0xffff0fa0: /* __kernel_memory_barrier */
576 /* ??? No-op. Will need to do better for SMP. */
577 break;
578 case 0xffff0fc0: /* __kernel_cmpxchg */
579 /* XXX: This only works between threads, not between processes.
580 It's probably possible to implement this with native host
581 operations. However things like ldrex/strex are much harder so
582 there's not much point trying. */
583 start_exclusive();
584 cpsr = cpsr_read(env);
585 addr = env->regs[2];
586 /* FIXME: This should SEGV if the access fails. */
587 if (get_user_u32(val, addr))
588 val = ~env->regs[0];
589 if (val == env->regs[0]) {
590 val = env->regs[1];
591 /* FIXME: Check for segfaults. */
592 put_user_u32(val, addr);
593 env->regs[0] = 0;
594 cpsr |= CPSR_C;
595 } else {
596 env->regs[0] = -1;
597 cpsr &= ~CPSR_C;
598 }
599 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
600 end_exclusive();
601 break;
602 case 0xffff0fe0: /* __kernel_get_tls */
603 env->regs[0] = cpu_get_tls(env);
604 break;
605 case 0xffff0f60: /* __kernel_cmpxchg64 */
606 arm_kernel_cmpxchg64_helper(env);
607 break;
608
609 default:
610 return 1;
611 }
612 /* Jump back to the caller. */
613 addr = env->regs[14];
614 if (addr & 1) {
615 env->thumb = 1;
616 addr &= ~1;
617 }
618 env->regs[15] = addr;
619
620 return 0;
621 }
622
623 /* Store exclusive handling for AArch32 */
624 static int do_strex(CPUARMState *env)
625 {
626 uint64_t val;
627 int size;
628 int rc = 1;
629 int segv = 0;
630 uint32_t addr;
631 start_exclusive();
632 if (env->exclusive_addr != env->exclusive_test) {
633 goto fail;
634 }
635 /* We know we're always AArch32 so the address is in uint32_t range
636 * unless it was the -1 exclusive-monitor-lost value (which won't
637 * match exclusive_test above).
638 */
639 assert(extract64(env->exclusive_addr, 32, 32) == 0);
640 addr = env->exclusive_addr;
641 size = env->exclusive_info & 0xf;
642 switch (size) {
643 case 0:
644 segv = get_user_u8(val, addr);
645 break;
646 case 1:
647 segv = get_user_data_u16(val, addr, env);
648 break;
649 case 2:
650 case 3:
651 segv = get_user_data_u32(val, addr, env);
652 break;
653 default:
654 abort();
655 }
656 if (segv) {
657 env->exception.vaddress = addr;
658 goto done;
659 }
660 if (size == 3) {
661 uint32_t valhi;
662 segv = get_user_data_u32(valhi, addr + 4, env);
663 if (segv) {
664 env->exception.vaddress = addr + 4;
665 goto done;
666 }
667 if (arm_cpu_bswap_data(env)) {
668 val = deposit64((uint64_t)valhi, 32, 32, val);
669 } else {
670 val = deposit64(val, 32, 32, valhi);
671 }
672 }
673 if (val != env->exclusive_val) {
674 goto fail;
675 }
676
677 val = env->regs[(env->exclusive_info >> 8) & 0xf];
678 switch (size) {
679 case 0:
680 segv = put_user_u8(val, addr);
681 break;
682 case 1:
683 segv = put_user_data_u16(val, addr, env);
684 break;
685 case 2:
686 case 3:
687 segv = put_user_data_u32(val, addr, env);
688 break;
689 }
690 if (segv) {
691 env->exception.vaddress = addr;
692 goto done;
693 }
694 if (size == 3) {
695 val = env->regs[(env->exclusive_info >> 12) & 0xf];
696 segv = put_user_data_u32(val, addr + 4, env);
697 if (segv) {
698 env->exception.vaddress = addr + 4;
699 goto done;
700 }
701 }
702 rc = 0;
703 fail:
704 env->regs[15] += 4;
705 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
706 done:
707 end_exclusive();
708 return segv;
709 }
710
711 void cpu_loop(CPUARMState *env)
712 {
713 CPUState *cs = CPU(arm_env_get_cpu(env));
714 int trapnr;
715 unsigned int n, insn;
716 target_siginfo_t info;
717 uint32_t addr;
718
719 for(;;) {
720 cpu_exec_start(cs);
721 trapnr = cpu_arm_exec(cs);
722 cpu_exec_end(cs);
723 switch(trapnr) {
724 case EXCP_UDEF:
725 {
726 TaskState *ts = cs->opaque;
727 uint32_t opcode;
728 int rc;
729
730 /* we handle the FPU emulation here, as Linux */
731 /* we get the opcode */
732 /* FIXME - what to do if get_user() fails? */
733 get_user_code_u32(opcode, env->regs[15], env);
734
735 rc = EmulateAll(opcode, &ts->fpa, env);
736 if (rc == 0) { /* illegal instruction */
737 info.si_signo = TARGET_SIGILL;
738 info.si_errno = 0;
739 info.si_code = TARGET_ILL_ILLOPN;
740 info._sifields._sigfault._addr = env->regs[15];
741 queue_signal(env, info.si_signo, &info);
742 } else if (rc < 0) { /* FP exception */
743 int arm_fpe=0;
744
745 /* translate softfloat flags to FPSR flags */
746 if (-rc & float_flag_invalid)
747 arm_fpe |= BIT_IOC;
748 if (-rc & float_flag_divbyzero)
749 arm_fpe |= BIT_DZC;
750 if (-rc & float_flag_overflow)
751 arm_fpe |= BIT_OFC;
752 if (-rc & float_flag_underflow)
753 arm_fpe |= BIT_UFC;
754 if (-rc & float_flag_inexact)
755 arm_fpe |= BIT_IXC;
756
757 FPSR fpsr = ts->fpa.fpsr;
758 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
759
760 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
761 info.si_signo = TARGET_SIGFPE;
762 info.si_errno = 0;
763
764 /* ordered by priority, least first */
765 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
766 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
767 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
768 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
769 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
770
771 info._sifields._sigfault._addr = env->regs[15];
772 queue_signal(env, info.si_signo, &info);
773 } else {
774 env->regs[15] += 4;
775 }
776
777 /* accumulate unenabled exceptions */
778 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
779 fpsr |= BIT_IXC;
780 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
781 fpsr |= BIT_UFC;
782 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
783 fpsr |= BIT_OFC;
784 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
785 fpsr |= BIT_DZC;
786 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
787 fpsr |= BIT_IOC;
788 ts->fpa.fpsr=fpsr;
789 } else { /* everything OK */
790 /* increment PC */
791 env->regs[15] += 4;
792 }
793 }
794 break;
795 case EXCP_SWI:
796 case EXCP_BKPT:
797 {
798 env->eabi = 1;
799 /* system call */
800 if (trapnr == EXCP_BKPT) {
801 if (env->thumb) {
802 /* FIXME - what to do if get_user() fails? */
803 get_user_code_u16(insn, env->regs[15], env);
804 n = insn & 0xff;
805 env->regs[15] += 2;
806 } else {
807 /* FIXME - what to do if get_user() fails? */
808 get_user_code_u32(insn, env->regs[15], env);
809 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
810 env->regs[15] += 4;
811 }
812 } else {
813 if (env->thumb) {
814 /* FIXME - what to do if get_user() fails? */
815 get_user_code_u16(insn, env->regs[15] - 2, env);
816 n = insn & 0xff;
817 } else {
818 /* FIXME - what to do if get_user() fails? */
819 get_user_code_u32(insn, env->regs[15] - 4, env);
820 n = insn & 0xffffff;
821 }
822 }
823
824 if (n == ARM_NR_cacheflush) {
825 /* nop */
826 } else if (n == ARM_NR_semihosting
827 || n == ARM_NR_thumb_semihosting) {
828 env->regs[0] = do_arm_semihosting (env);
829 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
830 /* linux syscall */
831 if (env->thumb || n == 0) {
832 n = env->regs[7];
833 } else {
834 n -= ARM_SYSCALL_BASE;
835 env->eabi = 0;
836 }
837 if ( n > ARM_NR_BASE) {
838 switch (n) {
839 case ARM_NR_cacheflush:
840 /* nop */
841 break;
842 case ARM_NR_set_tls:
843 cpu_set_tls(env, env->regs[0]);
844 env->regs[0] = 0;
845 break;
846 case ARM_NR_breakpoint:
847 env->regs[15] -= env->thumb ? 2 : 4;
848 goto excp_debug;
849 default:
850 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
851 n);
852 env->regs[0] = -TARGET_ENOSYS;
853 break;
854 }
855 } else {
856 env->regs[0] = do_syscall(env,
857 n,
858 env->regs[0],
859 env->regs[1],
860 env->regs[2],
861 env->regs[3],
862 env->regs[4],
863 env->regs[5],
864 0, 0);
865 }
866 } else {
867 goto error;
868 }
869 }
870 break;
871 case EXCP_INTERRUPT:
872 /* just indicate that signals should be handled asap */
873 break;
874 case EXCP_STREX:
875 if (!do_strex(env)) {
876 break;
877 }
878 /* fall through for segv */
879 case EXCP_PREFETCH_ABORT:
880 case EXCP_DATA_ABORT:
881 addr = env->exception.vaddress;
882 {
883 info.si_signo = TARGET_SIGSEGV;
884 info.si_errno = 0;
885 /* XXX: check env->error_code */
886 info.si_code = TARGET_SEGV_MAPERR;
887 info._sifields._sigfault._addr = addr;
888 queue_signal(env, info.si_signo, &info);
889 }
890 break;
891 case EXCP_DEBUG:
892 excp_debug:
893 {
894 int sig;
895
896 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
897 if (sig)
898 {
899 info.si_signo = sig;
900 info.si_errno = 0;
901 info.si_code = TARGET_TRAP_BRKPT;
902 queue_signal(env, info.si_signo, &info);
903 }
904 }
905 break;
906 case EXCP_KERNEL_TRAP:
907 if (do_kernel_trap(env))
908 goto error;
909 break;
910 case EXCP_YIELD:
911 /* nothing to do here for user-mode, just resume guest code */
912 break;
913 default:
914 error:
915 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
916 abort();
917 }
918 process_pending_signals(env);
919 }
920 }
921
922 #else
923
924 /*
925 * Handle AArch64 store-release exclusive
926 *
927 * rs = gets the status result of store exclusive
928 * rt = is the register that is stored
929 * rt2 = is the second register store (in STP)
930 *
931 */
932 static int do_strex_a64(CPUARMState *env)
933 {
934 uint64_t val;
935 int size;
936 bool is_pair;
937 int rc = 1;
938 int segv = 0;
939 uint64_t addr;
940 int rs, rt, rt2;
941
942 start_exclusive();
943 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
944 size = extract32(env->exclusive_info, 0, 2);
945 is_pair = extract32(env->exclusive_info, 2, 1);
946 rs = extract32(env->exclusive_info, 4, 5);
947 rt = extract32(env->exclusive_info, 9, 5);
948 rt2 = extract32(env->exclusive_info, 14, 5);
949
950 addr = env->exclusive_addr;
951
952 if (addr != env->exclusive_test) {
953 goto finish;
954 }
955
956 switch (size) {
957 case 0:
958 segv = get_user_u8(val, addr);
959 break;
960 case 1:
961 segv = get_user_u16(val, addr);
962 break;
963 case 2:
964 segv = get_user_u32(val, addr);
965 break;
966 case 3:
967 segv = get_user_u64(val, addr);
968 break;
969 default:
970 abort();
971 }
972 if (segv) {
973 env->exception.vaddress = addr;
974 goto error;
975 }
976 if (val != env->exclusive_val) {
977 goto finish;
978 }
979 if (is_pair) {
980 if (size == 2) {
981 segv = get_user_u32(val, addr + 4);
982 } else {
983 segv = get_user_u64(val, addr + 8);
984 }
985 if (segv) {
986 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
987 goto error;
988 }
989 if (val != env->exclusive_high) {
990 goto finish;
991 }
992 }
993 /* handle the zero register */
994 val = rt == 31 ? 0 : env->xregs[rt];
995 switch (size) {
996 case 0:
997 segv = put_user_u8(val, addr);
998 break;
999 case 1:
1000 segv = put_user_u16(val, addr);
1001 break;
1002 case 2:
1003 segv = put_user_u32(val, addr);
1004 break;
1005 case 3:
1006 segv = put_user_u64(val, addr);
1007 break;
1008 }
1009 if (segv) {
1010 goto error;
1011 }
1012 if (is_pair) {
1013 /* handle the zero register */
1014 val = rt2 == 31 ? 0 : env->xregs[rt2];
1015 if (size == 2) {
1016 segv = put_user_u32(val, addr + 4);
1017 } else {
1018 segv = put_user_u64(val, addr + 8);
1019 }
1020 if (segv) {
1021 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1022 goto error;
1023 }
1024 }
1025 rc = 0;
1026 finish:
1027 env->pc += 4;
1028 /* rs == 31 encodes a write to the ZR, thus throwing away
1029 * the status return. This is rather silly but valid.
1030 */
1031 if (rs < 31) {
1032 env->xregs[rs] = rc;
1033 }
1034 error:
1035 /* instruction faulted, PC does not advance */
1036 /* either way a strex releases any exclusive lock we have */
1037 env->exclusive_addr = -1;
1038 end_exclusive();
1039 return segv;
1040 }
1041
1042 /* AArch64 main loop */
1043 void cpu_loop(CPUARMState *env)
1044 {
1045 CPUState *cs = CPU(arm_env_get_cpu(env));
1046 int trapnr, sig;
1047 target_siginfo_t info;
1048
1049 for (;;) {
1050 cpu_exec_start(cs);
1051 trapnr = cpu_arm_exec(cs);
1052 cpu_exec_end(cs);
1053
1054 switch (trapnr) {
1055 case EXCP_SWI:
1056 env->xregs[0] = do_syscall(env,
1057 env->xregs[8],
1058 env->xregs[0],
1059 env->xregs[1],
1060 env->xregs[2],
1061 env->xregs[3],
1062 env->xregs[4],
1063 env->xregs[5],
1064 0, 0);
1065 break;
1066 case EXCP_INTERRUPT:
1067 /* just indicate that signals should be handled asap */
1068 break;
1069 case EXCP_UDEF:
1070 info.si_signo = TARGET_SIGILL;
1071 info.si_errno = 0;
1072 info.si_code = TARGET_ILL_ILLOPN;
1073 info._sifields._sigfault._addr = env->pc;
1074 queue_signal(env, info.si_signo, &info);
1075 break;
1076 case EXCP_STREX:
1077 if (!do_strex_a64(env)) {
1078 break;
1079 }
1080 /* fall through for segv */
1081 case EXCP_PREFETCH_ABORT:
1082 case EXCP_DATA_ABORT:
1083 info.si_signo = TARGET_SIGSEGV;
1084 info.si_errno = 0;
1085 /* XXX: check env->error_code */
1086 info.si_code = TARGET_SEGV_MAPERR;
1087 info._sifields._sigfault._addr = env->exception.vaddress;
1088 queue_signal(env, info.si_signo, &info);
1089 break;
1090 case EXCP_DEBUG:
1091 case EXCP_BKPT:
1092 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1093 if (sig) {
1094 info.si_signo = sig;
1095 info.si_errno = 0;
1096 info.si_code = TARGET_TRAP_BRKPT;
1097 queue_signal(env, info.si_signo, &info);
1098 }
1099 break;
1100 case EXCP_SEMIHOST:
1101 env->xregs[0] = do_arm_semihosting(env);
1102 break;
1103 case EXCP_YIELD:
1104 /* nothing to do here for user-mode, just resume guest code */
1105 break;
1106 default:
1107 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1108 abort();
1109 }
1110 process_pending_signals(env);
1111 /* Exception return on AArch64 always clears the exclusive monitor,
1112 * so any return to running guest code implies this.
1113 * A strex (successful or otherwise) also clears the monitor, so
1114 * we don't need to specialcase EXCP_STREX.
1115 */
1116 env->exclusive_addr = -1;
1117 }
1118 }
1119 #endif /* ndef TARGET_ABI32 */
1120
1121 #endif
1122
1123 #ifdef TARGET_UNICORE32
1124
1125 void cpu_loop(CPUUniCore32State *env)
1126 {
1127 CPUState *cs = CPU(uc32_env_get_cpu(env));
1128 int trapnr;
1129 unsigned int n, insn;
1130 target_siginfo_t info;
1131
1132 for (;;) {
1133 cpu_exec_start(cs);
1134 trapnr = uc32_cpu_exec(cs);
1135 cpu_exec_end(cs);
1136 switch (trapnr) {
1137 case UC32_EXCP_PRIV:
1138 {
1139 /* system call */
1140 get_user_u32(insn, env->regs[31] - 4);
1141 n = insn & 0xffffff;
1142
1143 if (n >= UC32_SYSCALL_BASE) {
1144 /* linux syscall */
1145 n -= UC32_SYSCALL_BASE;
1146 if (n == UC32_SYSCALL_NR_set_tls) {
1147 cpu_set_tls(env, env->regs[0]);
1148 env->regs[0] = 0;
1149 } else {
1150 env->regs[0] = do_syscall(env,
1151 n,
1152 env->regs[0],
1153 env->regs[1],
1154 env->regs[2],
1155 env->regs[3],
1156 env->regs[4],
1157 env->regs[5],
1158 0, 0);
1159 }
1160 } else {
1161 goto error;
1162 }
1163 }
1164 break;
1165 case UC32_EXCP_DTRAP:
1166 case UC32_EXCP_ITRAP:
1167 info.si_signo = TARGET_SIGSEGV;
1168 info.si_errno = 0;
1169 /* XXX: check env->error_code */
1170 info.si_code = TARGET_SEGV_MAPERR;
1171 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1172 queue_signal(env, info.si_signo, &info);
1173 break;
1174 case EXCP_INTERRUPT:
1175 /* just indicate that signals should be handled asap */
1176 break;
1177 case EXCP_DEBUG:
1178 {
1179 int sig;
1180
1181 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1182 if (sig) {
1183 info.si_signo = sig;
1184 info.si_errno = 0;
1185 info.si_code = TARGET_TRAP_BRKPT;
1186 queue_signal(env, info.si_signo, &info);
1187 }
1188 }
1189 break;
1190 default:
1191 goto error;
1192 }
1193 process_pending_signals(env);
1194 }
1195
1196 error:
1197 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1198 abort();
1199 }
1200 #endif
1201
1202 #ifdef TARGET_SPARC
1203 #define SPARC64_STACK_BIAS 2047
1204
1205 //#define DEBUG_WIN
1206
1207 /* WARNING: dealing with register windows _is_ complicated. More info
1208 can be found at http://www.sics.se/~psm/sparcstack.html */
1209 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1210 {
1211 index = (index + cwp * 16) % (16 * env->nwindows);
1212 /* wrap handling : if cwp is on the last window, then we use the
1213 registers 'after' the end */
1214 if (index < 8 && env->cwp == env->nwindows - 1)
1215 index += 16 * env->nwindows;
1216 return index;
1217 }
1218
1219 /* save the register window 'cwp1' */
1220 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1221 {
1222 unsigned int i;
1223 abi_ulong sp_ptr;
1224
1225 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1226 #ifdef TARGET_SPARC64
1227 if (sp_ptr & 3)
1228 sp_ptr += SPARC64_STACK_BIAS;
1229 #endif
1230 #if defined(DEBUG_WIN)
1231 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1232 sp_ptr, cwp1);
1233 #endif
1234 for(i = 0; i < 16; i++) {
1235 /* FIXME - what to do if put_user() fails? */
1236 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1237 sp_ptr += sizeof(abi_ulong);
1238 }
1239 }
1240
1241 static void save_window(CPUSPARCState *env)
1242 {
1243 #ifndef TARGET_SPARC64
1244 unsigned int new_wim;
1245 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1246 ((1LL << env->nwindows) - 1);
1247 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1248 env->wim = new_wim;
1249 #else
1250 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1251 env->cansave++;
1252 env->canrestore--;
1253 #endif
1254 }
1255
1256 static void restore_window(CPUSPARCState *env)
1257 {
1258 #ifndef TARGET_SPARC64
1259 unsigned int new_wim;
1260 #endif
1261 unsigned int i, cwp1;
1262 abi_ulong sp_ptr;
1263
1264 #ifndef TARGET_SPARC64
1265 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1266 ((1LL << env->nwindows) - 1);
1267 #endif
1268
1269 /* restore the invalid window */
1270 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1271 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1272 #ifdef TARGET_SPARC64
1273 if (sp_ptr & 3)
1274 sp_ptr += SPARC64_STACK_BIAS;
1275 #endif
1276 #if defined(DEBUG_WIN)
1277 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1278 sp_ptr, cwp1);
1279 #endif
1280 for(i = 0; i < 16; i++) {
1281 /* FIXME - what to do if get_user() fails? */
1282 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1283 sp_ptr += sizeof(abi_ulong);
1284 }
1285 #ifdef TARGET_SPARC64
1286 env->canrestore++;
1287 if (env->cleanwin < env->nwindows - 1)
1288 env->cleanwin++;
1289 env->cansave--;
1290 #else
1291 env->wim = new_wim;
1292 #endif
1293 }
1294
1295 static void flush_windows(CPUSPARCState *env)
1296 {
1297 int offset, cwp1;
1298
1299 offset = 1;
1300 for(;;) {
1301 /* if restore would invoke restore_window(), then we can stop */
1302 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1303 #ifndef TARGET_SPARC64
1304 if (env->wim & (1 << cwp1))
1305 break;
1306 #else
1307 if (env->canrestore == 0)
1308 break;
1309 env->cansave++;
1310 env->canrestore--;
1311 #endif
1312 save_window_offset(env, cwp1);
1313 offset++;
1314 }
1315 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1316 #ifndef TARGET_SPARC64
1317 /* set wim so that restore will reload the registers */
1318 env->wim = 1 << cwp1;
1319 #endif
1320 #if defined(DEBUG_WIN)
1321 printf("flush_windows: nb=%d\n", offset - 1);
1322 #endif
1323 }
1324
1325 void cpu_loop (CPUSPARCState *env)
1326 {
1327 CPUState *cs = CPU(sparc_env_get_cpu(env));
1328 int trapnr;
1329 abi_long ret;
1330 target_siginfo_t info;
1331
1332 while (1) {
1333 cpu_exec_start(cs);
1334 trapnr = cpu_sparc_exec(cs);
1335 cpu_exec_end(cs);
1336
1337 /* Compute PSR before exposing state. */
1338 if (env->cc_op != CC_OP_FLAGS) {
1339 cpu_get_psr(env);
1340 }
1341
1342 switch (trapnr) {
1343 #ifndef TARGET_SPARC64
1344 case 0x88:
1345 case 0x90:
1346 #else
1347 case 0x110:
1348 case 0x16d:
1349 #endif
1350 ret = do_syscall (env, env->gregs[1],
1351 env->regwptr[0], env->regwptr[1],
1352 env->regwptr[2], env->regwptr[3],
1353 env->regwptr[4], env->regwptr[5],
1354 0, 0);
1355 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1356 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1357 env->xcc |= PSR_CARRY;
1358 #else
1359 env->psr |= PSR_CARRY;
1360 #endif
1361 ret = -ret;
1362 } else {
1363 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1364 env->xcc &= ~PSR_CARRY;
1365 #else
1366 env->psr &= ~PSR_CARRY;
1367 #endif
1368 }
1369 env->regwptr[0] = ret;
1370 /* next instruction */
1371 env->pc = env->npc;
1372 env->npc = env->npc + 4;
1373 break;
1374 case 0x83: /* flush windows */
1375 #ifdef TARGET_ABI32
1376 case 0x103:
1377 #endif
1378 flush_windows(env);
1379 /* next instruction */
1380 env->pc = env->npc;
1381 env->npc = env->npc + 4;
1382 break;
1383 #ifndef TARGET_SPARC64
1384 case TT_WIN_OVF: /* window overflow */
1385 save_window(env);
1386 break;
1387 case TT_WIN_UNF: /* window underflow */
1388 restore_window(env);
1389 break;
1390 case TT_TFAULT:
1391 case TT_DFAULT:
1392 {
1393 info.si_signo = TARGET_SIGSEGV;
1394 info.si_errno = 0;
1395 /* XXX: check env->error_code */
1396 info.si_code = TARGET_SEGV_MAPERR;
1397 info._sifields._sigfault._addr = env->mmuregs[4];
1398 queue_signal(env, info.si_signo, &info);
1399 }
1400 break;
1401 #else
1402 case TT_SPILL: /* window overflow */
1403 save_window(env);
1404 break;
1405 case TT_FILL: /* window underflow */
1406 restore_window(env);
1407 break;
1408 case TT_TFAULT:
1409 case TT_DFAULT:
1410 {
1411 info.si_signo = TARGET_SIGSEGV;
1412 info.si_errno = 0;
1413 /* XXX: check env->error_code */
1414 info.si_code = TARGET_SEGV_MAPERR;
1415 if (trapnr == TT_DFAULT)
1416 info._sifields._sigfault._addr = env->dmmuregs[4];
1417 else
1418 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1419 queue_signal(env, info.si_signo, &info);
1420 }
1421 break;
1422 #ifndef TARGET_ABI32
1423 case 0x16e:
1424 flush_windows(env);
1425 sparc64_get_context(env);
1426 break;
1427 case 0x16f:
1428 flush_windows(env);
1429 sparc64_set_context(env);
1430 break;
1431 #endif
1432 #endif
1433 case EXCP_INTERRUPT:
1434 /* just indicate that signals should be handled asap */
1435 break;
1436 case TT_ILL_INSN:
1437 {
1438 info.si_signo = TARGET_SIGILL;
1439 info.si_errno = 0;
1440 info.si_code = TARGET_ILL_ILLOPC;
1441 info._sifields._sigfault._addr = env->pc;
1442 queue_signal(env, info.si_signo, &info);
1443 }
1444 break;
1445 case EXCP_DEBUG:
1446 {
1447 int sig;
1448
1449 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1450 if (sig)
1451 {
1452 info.si_signo = sig;
1453 info.si_errno = 0;
1454 info.si_code = TARGET_TRAP_BRKPT;
1455 queue_signal(env, info.si_signo, &info);
1456 }
1457 }
1458 break;
1459 default:
1460 printf ("Unhandled trap: 0x%x\n", trapnr);
1461 cpu_dump_state(cs, stderr, fprintf, 0);
1462 exit(EXIT_FAILURE);
1463 }
1464 process_pending_signals (env);
1465 }
1466 }
1467
1468 #endif
1469
1470 #ifdef TARGET_PPC
1471 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1472 {
1473 return cpu_get_host_ticks();
1474 }
1475
1476 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1477 {
1478 return cpu_ppc_get_tb(env);
1479 }
1480
1481 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1482 {
1483 return cpu_ppc_get_tb(env) >> 32;
1484 }
1485
1486 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1487 {
1488 return cpu_ppc_get_tb(env);
1489 }
1490
1491 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1492 {
1493 return cpu_ppc_get_tb(env) >> 32;
1494 }
1495
1496 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1497 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1498
1499 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1500 {
1501 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1502 }
1503
1504 /* XXX: to be fixed */
1505 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1506 {
1507 return -1;
1508 }
1509
1510 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1511 {
1512 return -1;
1513 }
1514
1515 static int do_store_exclusive(CPUPPCState *env)
1516 {
1517 target_ulong addr;
1518 target_ulong page_addr;
1519 target_ulong val, val2 __attribute__((unused)) = 0;
1520 int flags;
1521 int segv = 0;
1522
1523 addr = env->reserve_ea;
1524 page_addr = addr & TARGET_PAGE_MASK;
1525 start_exclusive();
1526 mmap_lock();
1527 flags = page_get_flags(page_addr);
1528 if ((flags & PAGE_READ) == 0) {
1529 segv = 1;
1530 } else {
1531 int reg = env->reserve_info & 0x1f;
1532 int size = env->reserve_info >> 5;
1533 int stored = 0;
1534
1535 if (addr == env->reserve_addr) {
1536 switch (size) {
1537 case 1: segv = get_user_u8(val, addr); break;
1538 case 2: segv = get_user_u16(val, addr); break;
1539 case 4: segv = get_user_u32(val, addr); break;
1540 #if defined(TARGET_PPC64)
1541 case 8: segv = get_user_u64(val, addr); break;
1542 case 16: {
1543 segv = get_user_u64(val, addr);
1544 if (!segv) {
1545 segv = get_user_u64(val2, addr + 8);
1546 }
1547 break;
1548 }
1549 #endif
1550 default: abort();
1551 }
1552 if (!segv && val == env->reserve_val) {
1553 val = env->gpr[reg];
1554 switch (size) {
1555 case 1: segv = put_user_u8(val, addr); break;
1556 case 2: segv = put_user_u16(val, addr); break;
1557 case 4: segv = put_user_u32(val, addr); break;
1558 #if defined(TARGET_PPC64)
1559 case 8: segv = put_user_u64(val, addr); break;
1560 case 16: {
1561 if (val2 == env->reserve_val2) {
1562 if (msr_le) {
1563 val2 = val;
1564 val = env->gpr[reg+1];
1565 } else {
1566 val2 = env->gpr[reg+1];
1567 }
1568 segv = put_user_u64(val, addr);
1569 if (!segv) {
1570 segv = put_user_u64(val2, addr + 8);
1571 }
1572 }
1573 break;
1574 }
1575 #endif
1576 default: abort();
1577 }
1578 if (!segv) {
1579 stored = 1;
1580 }
1581 }
1582 }
1583 env->crf[0] = (stored << 1) | xer_so;
1584 env->reserve_addr = (target_ulong)-1;
1585 }
1586 if (!segv) {
1587 env->nip += 4;
1588 }
1589 mmap_unlock();
1590 end_exclusive();
1591 return segv;
1592 }
1593
1594 void cpu_loop(CPUPPCState *env)
1595 {
1596 CPUState *cs = CPU(ppc_env_get_cpu(env));
1597 target_siginfo_t info;
1598 int trapnr;
1599 target_ulong ret;
1600
1601 for(;;) {
1602 cpu_exec_start(cs);
1603 trapnr = cpu_ppc_exec(cs);
1604 cpu_exec_end(cs);
1605 switch(trapnr) {
1606 case POWERPC_EXCP_NONE:
1607 /* Just go on */
1608 break;
1609 case POWERPC_EXCP_CRITICAL: /* Critical input */
1610 cpu_abort(cs, "Critical interrupt while in user mode. "
1611 "Aborting\n");
1612 break;
1613 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1614 cpu_abort(cs, "Machine check exception while in user mode. "
1615 "Aborting\n");
1616 break;
1617 case POWERPC_EXCP_DSI: /* Data storage exception */
1618 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1619 env->spr[SPR_DAR]);
1620 /* XXX: check this. Seems bugged */
1621 switch (env->error_code & 0xFF000000) {
1622 case 0x40000000:
1623 info.si_signo = TARGET_SIGSEGV;
1624 info.si_errno = 0;
1625 info.si_code = TARGET_SEGV_MAPERR;
1626 break;
1627 case 0x04000000:
1628 info.si_signo = TARGET_SIGILL;
1629 info.si_errno = 0;
1630 info.si_code = TARGET_ILL_ILLADR;
1631 break;
1632 case 0x08000000:
1633 info.si_signo = TARGET_SIGSEGV;
1634 info.si_errno = 0;
1635 info.si_code = TARGET_SEGV_ACCERR;
1636 break;
1637 default:
1638 /* Let's send a regular segfault... */
1639 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1640 env->error_code);
1641 info.si_signo = TARGET_SIGSEGV;
1642 info.si_errno = 0;
1643 info.si_code = TARGET_SEGV_MAPERR;
1644 break;
1645 }
1646 info._sifields._sigfault._addr = env->nip;
1647 queue_signal(env, info.si_signo, &info);
1648 break;
1649 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1650 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1651 "\n", env->spr[SPR_SRR0]);
1652 /* XXX: check this */
1653 switch (env->error_code & 0xFF000000) {
1654 case 0x40000000:
1655 info.si_signo = TARGET_SIGSEGV;
1656 info.si_errno = 0;
1657 info.si_code = TARGET_SEGV_MAPERR;
1658 break;
1659 case 0x10000000:
1660 case 0x08000000:
1661 info.si_signo = TARGET_SIGSEGV;
1662 info.si_errno = 0;
1663 info.si_code = TARGET_SEGV_ACCERR;
1664 break;
1665 default:
1666 /* Let's send a regular segfault... */
1667 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1668 env->error_code);
1669 info.si_signo = TARGET_SIGSEGV;
1670 info.si_errno = 0;
1671 info.si_code = TARGET_SEGV_MAPERR;
1672 break;
1673 }
1674 info._sifields._sigfault._addr = env->nip - 4;
1675 queue_signal(env, info.si_signo, &info);
1676 break;
1677 case POWERPC_EXCP_EXTERNAL: /* External input */
1678 cpu_abort(cs, "External interrupt while in user mode. "
1679 "Aborting\n");
1680 break;
1681 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1682 EXCP_DUMP(env, "Unaligned memory access\n");
1683 /* XXX: check this */
1684 info.si_signo = TARGET_SIGBUS;
1685 info.si_errno = 0;
1686 info.si_code = TARGET_BUS_ADRALN;
1687 info._sifields._sigfault._addr = env->nip;
1688 queue_signal(env, info.si_signo, &info);
1689 break;
1690 case POWERPC_EXCP_PROGRAM: /* Program exception */
1691 /* XXX: check this */
1692 switch (env->error_code & ~0xF) {
1693 case POWERPC_EXCP_FP:
1694 EXCP_DUMP(env, "Floating point program exception\n");
1695 info.si_signo = TARGET_SIGFPE;
1696 info.si_errno = 0;
1697 switch (env->error_code & 0xF) {
1698 case POWERPC_EXCP_FP_OX:
1699 info.si_code = TARGET_FPE_FLTOVF;
1700 break;
1701 case POWERPC_EXCP_FP_UX:
1702 info.si_code = TARGET_FPE_FLTUND;
1703 break;
1704 case POWERPC_EXCP_FP_ZX:
1705 case POWERPC_EXCP_FP_VXZDZ:
1706 info.si_code = TARGET_FPE_FLTDIV;
1707 break;
1708 case POWERPC_EXCP_FP_XX:
1709 info.si_code = TARGET_FPE_FLTRES;
1710 break;
1711 case POWERPC_EXCP_FP_VXSOFT:
1712 info.si_code = TARGET_FPE_FLTINV;
1713 break;
1714 case POWERPC_EXCP_FP_VXSNAN:
1715 case POWERPC_EXCP_FP_VXISI:
1716 case POWERPC_EXCP_FP_VXIDI:
1717 case POWERPC_EXCP_FP_VXIMZ:
1718 case POWERPC_EXCP_FP_VXVC:
1719 case POWERPC_EXCP_FP_VXSQRT:
1720 case POWERPC_EXCP_FP_VXCVI:
1721 info.si_code = TARGET_FPE_FLTSUB;
1722 break;
1723 default:
1724 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1725 env->error_code);
1726 break;
1727 }
1728 break;
1729 case POWERPC_EXCP_INVAL:
1730 EXCP_DUMP(env, "Invalid instruction\n");
1731 info.si_signo = TARGET_SIGILL;
1732 info.si_errno = 0;
1733 switch (env->error_code & 0xF) {
1734 case POWERPC_EXCP_INVAL_INVAL:
1735 info.si_code = TARGET_ILL_ILLOPC;
1736 break;
1737 case POWERPC_EXCP_INVAL_LSWX:
1738 info.si_code = TARGET_ILL_ILLOPN;
1739 break;
1740 case POWERPC_EXCP_INVAL_SPR:
1741 info.si_code = TARGET_ILL_PRVREG;
1742 break;
1743 case POWERPC_EXCP_INVAL_FP:
1744 info.si_code = TARGET_ILL_COPROC;
1745 break;
1746 default:
1747 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1748 env->error_code & 0xF);
1749 info.si_code = TARGET_ILL_ILLADR;
1750 break;
1751 }
1752 break;
1753 case POWERPC_EXCP_PRIV:
1754 EXCP_DUMP(env, "Privilege violation\n");
1755 info.si_signo = TARGET_SIGILL;
1756 info.si_errno = 0;
1757 switch (env->error_code & 0xF) {
1758 case POWERPC_EXCP_PRIV_OPC:
1759 info.si_code = TARGET_ILL_PRVOPC;
1760 break;
1761 case POWERPC_EXCP_PRIV_REG:
1762 info.si_code = TARGET_ILL_PRVREG;
1763 break;
1764 default:
1765 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1766 env->error_code & 0xF);
1767 info.si_code = TARGET_ILL_PRVOPC;
1768 break;
1769 }
1770 break;
1771 case POWERPC_EXCP_TRAP:
1772 cpu_abort(cs, "Tried to call a TRAP\n");
1773 break;
1774 default:
1775 /* Should not happen ! */
1776 cpu_abort(cs, "Unknown program exception (%02x)\n",
1777 env->error_code);
1778 break;
1779 }
1780 info._sifields._sigfault._addr = env->nip - 4;
1781 queue_signal(env, info.si_signo, &info);
1782 break;
1783 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1784 EXCP_DUMP(env, "No floating point allowed\n");
1785 info.si_signo = TARGET_SIGILL;
1786 info.si_errno = 0;
1787 info.si_code = TARGET_ILL_COPROC;
1788 info._sifields._sigfault._addr = env->nip - 4;
1789 queue_signal(env, info.si_signo, &info);
1790 break;
1791 case POWERPC_EXCP_SYSCALL: /* System call exception */
1792 cpu_abort(cs, "Syscall exception while in user mode. "
1793 "Aborting\n");
1794 break;
1795 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1796 EXCP_DUMP(env, "No APU instruction allowed\n");
1797 info.si_signo = TARGET_SIGILL;
1798 info.si_errno = 0;
1799 info.si_code = TARGET_ILL_COPROC;
1800 info._sifields._sigfault._addr = env->nip - 4;
1801 queue_signal(env, info.si_signo, &info);
1802 break;
1803 case POWERPC_EXCP_DECR: /* Decrementer exception */
1804 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1805 "Aborting\n");
1806 break;
1807 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1808 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1809 "Aborting\n");
1810 break;
1811 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1812 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1813 "Aborting\n");
1814 break;
1815 case POWERPC_EXCP_DTLB: /* Data TLB error */
1816 cpu_abort(cs, "Data TLB exception while in user mode. "
1817 "Aborting\n");
1818 break;
1819 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1820 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1821 "Aborting\n");
1822 break;
1823 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1824 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1825 info.si_signo = TARGET_SIGILL;
1826 info.si_errno = 0;
1827 info.si_code = TARGET_ILL_COPROC;
1828 info._sifields._sigfault._addr = env->nip - 4;
1829 queue_signal(env, info.si_signo, &info);
1830 break;
1831 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1832 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1833 break;
1834 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1835 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1836 break;
1837 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1838 cpu_abort(cs, "Performance monitor exception not handled\n");
1839 break;
1840 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1841 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1842 "Aborting\n");
1843 break;
1844 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1845 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1846 "Aborting\n");
1847 break;
1848 case POWERPC_EXCP_RESET: /* System reset exception */
1849 cpu_abort(cs, "Reset interrupt while in user mode. "
1850 "Aborting\n");
1851 break;
1852 case POWERPC_EXCP_DSEG: /* Data segment exception */
1853 cpu_abort(cs, "Data segment exception while in user mode. "
1854 "Aborting\n");
1855 break;
1856 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1857 cpu_abort(cs, "Instruction segment exception "
1858 "while in user mode. Aborting\n");
1859 break;
1860 /* PowerPC 64 with hypervisor mode support */
1861 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1862 cpu_abort(cs, "Hypervisor decrementer interrupt "
1863 "while in user mode. Aborting\n");
1864 break;
1865 case POWERPC_EXCP_TRACE: /* Trace exception */
1866 /* Nothing to do:
1867 * we use this exception to emulate step-by-step execution mode.
1868 */
1869 break;
1870 /* PowerPC 64 with hypervisor mode support */
1871 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1872 cpu_abort(cs, "Hypervisor data storage exception "
1873 "while in user mode. Aborting\n");
1874 break;
1875 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1876 cpu_abort(cs, "Hypervisor instruction storage exception "
1877 "while in user mode. Aborting\n");
1878 break;
1879 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1880 cpu_abort(cs, "Hypervisor data segment exception "
1881 "while in user mode. Aborting\n");
1882 break;
1883 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1884 cpu_abort(cs, "Hypervisor instruction segment exception "
1885 "while in user mode. Aborting\n");
1886 break;
1887 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1888 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1889 info.si_signo = TARGET_SIGILL;
1890 info.si_errno = 0;
1891 info.si_code = TARGET_ILL_COPROC;
1892 info._sifields._sigfault._addr = env->nip - 4;
1893 queue_signal(env, info.si_signo, &info);
1894 break;
1895 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1896 cpu_abort(cs, "Programmable interval timer interrupt "
1897 "while in user mode. Aborting\n");
1898 break;
1899 case POWERPC_EXCP_IO: /* IO error exception */
1900 cpu_abort(cs, "IO error exception while in user mode. "
1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_RUNM: /* Run mode exception */
1904 cpu_abort(cs, "Run mode exception while in user mode. "
1905 "Aborting\n");
1906 break;
1907 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1908 cpu_abort(cs, "Emulation trap exception not handled\n");
1909 break;
1910 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1911 cpu_abort(cs, "Instruction fetch TLB exception "
1912 "while in user-mode. Aborting");
1913 break;
1914 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1915 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1916 "Aborting");
1917 break;
1918 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1919 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1920 "Aborting");
1921 break;
1922 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1923 cpu_abort(cs, "Floating-point assist exception not handled\n");
1924 break;
1925 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1926 cpu_abort(cs, "Instruction address breakpoint exception "
1927 "not handled\n");
1928 break;
1929 case POWERPC_EXCP_SMI: /* System management interrupt */
1930 cpu_abort(cs, "System management interrupt while in user mode. "
1931 "Aborting\n");
1932 break;
1933 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1934 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1935 "Aborting\n");
1936 break;
1937 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1938 cpu_abort(cs, "Performance monitor exception not handled\n");
1939 break;
1940 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1941 cpu_abort(cs, "Vector assist exception not handled\n");
1942 break;
1943 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1944 cpu_abort(cs, "Soft patch exception not handled\n");
1945 break;
1946 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1947 cpu_abort(cs, "Maintenance exception while in user mode. "
1948 "Aborting\n");
1949 break;
1950 case POWERPC_EXCP_STOP: /* stop translation */
1951 /* We did invalidate the instruction cache. Go on */
1952 break;
1953 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1954 /* We just stopped because of a branch. Go on */
1955 break;
1956 case POWERPC_EXCP_SYSCALL_USER:
1957 /* system call in user-mode emulation */
1958 /* WARNING:
1959 * PPC ABI uses overflow flag in cr0 to signal an error
1960 * in syscalls.
1961 */
1962 env->crf[0] &= ~0x1;
1963 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1964 env->gpr[5], env->gpr[6], env->gpr[7],
1965 env->gpr[8], 0, 0);
1966 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1967 /* Returning from a successful sigreturn syscall.
1968 Avoid corrupting register state. */
1969 break;
1970 }
1971 if (ret > (target_ulong)(-515)) {
1972 env->crf[0] |= 0x1;
1973 ret = -ret;
1974 }
1975 env->gpr[3] = ret;
1976 break;
1977 case POWERPC_EXCP_STCX:
1978 if (do_store_exclusive(env)) {
1979 info.si_signo = TARGET_SIGSEGV;
1980 info.si_errno = 0;
1981 info.si_code = TARGET_SEGV_MAPERR;
1982 info._sifields._sigfault._addr = env->nip;
1983 queue_signal(env, info.si_signo, &info);
1984 }
1985 break;
1986 case EXCP_DEBUG:
1987 {
1988 int sig;
1989
1990 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1991 if (sig) {
1992 info.si_signo = sig;
1993 info.si_errno = 0;
1994 info.si_code = TARGET_TRAP_BRKPT;
1995 queue_signal(env, info.si_signo, &info);
1996 }
1997 }
1998 break;
1999 case EXCP_INTERRUPT:
2000 /* just indicate that signals should be handled asap */
2001 break;
2002 default:
2003 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2004 break;
2005 }
2006 process_pending_signals(env);
2007 }
2008 }
2009 #endif
2010
2011 #ifdef TARGET_MIPS
2012
2013 # ifdef TARGET_ABI_MIPSO32
2014 # define MIPS_SYS(name, args) args,
2015 static const uint8_t mips_syscall_args[] = {
2016 MIPS_SYS(sys_syscall , 8) /* 4000 */
2017 MIPS_SYS(sys_exit , 1)
2018 MIPS_SYS(sys_fork , 0)
2019 MIPS_SYS(sys_read , 3)
2020 MIPS_SYS(sys_write , 3)
2021 MIPS_SYS(sys_open , 3) /* 4005 */
2022 MIPS_SYS(sys_close , 1)
2023 MIPS_SYS(sys_waitpid , 3)
2024 MIPS_SYS(sys_creat , 2)
2025 MIPS_SYS(sys_link , 2)
2026 MIPS_SYS(sys_unlink , 1) /* 4010 */
2027 MIPS_SYS(sys_execve , 0)
2028 MIPS_SYS(sys_chdir , 1)
2029 MIPS_SYS(sys_time , 1)
2030 MIPS_SYS(sys_mknod , 3)
2031 MIPS_SYS(sys_chmod , 2) /* 4015 */
2032 MIPS_SYS(sys_lchown , 3)
2033 MIPS_SYS(sys_ni_syscall , 0)
2034 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2035 MIPS_SYS(sys_lseek , 3)
2036 MIPS_SYS(sys_getpid , 0) /* 4020 */
2037 MIPS_SYS(sys_mount , 5)
2038 MIPS_SYS(sys_umount , 1)
2039 MIPS_SYS(sys_setuid , 1)
2040 MIPS_SYS(sys_getuid , 0)
2041 MIPS_SYS(sys_stime , 1) /* 4025 */
2042 MIPS_SYS(sys_ptrace , 4)
2043 MIPS_SYS(sys_alarm , 1)
2044 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2045 MIPS_SYS(sys_pause , 0)
2046 MIPS_SYS(sys_utime , 2) /* 4030 */
2047 MIPS_SYS(sys_ni_syscall , 0)
2048 MIPS_SYS(sys_ni_syscall , 0)
2049 MIPS_SYS(sys_access , 2)
2050 MIPS_SYS(sys_nice , 1)
2051 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2052 MIPS_SYS(sys_sync , 0)
2053 MIPS_SYS(sys_kill , 2)
2054 MIPS_SYS(sys_rename , 2)
2055 MIPS_SYS(sys_mkdir , 2)
2056 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2057 MIPS_SYS(sys_dup , 1)
2058 MIPS_SYS(sys_pipe , 0)
2059 MIPS_SYS(sys_times , 1)
2060 MIPS_SYS(sys_ni_syscall , 0)
2061 MIPS_SYS(sys_brk , 1) /* 4045 */
2062 MIPS_SYS(sys_setgid , 1)
2063 MIPS_SYS(sys_getgid , 0)
2064 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2065 MIPS_SYS(sys_geteuid , 0)
2066 MIPS_SYS(sys_getegid , 0) /* 4050 */
2067 MIPS_SYS(sys_acct , 0)
2068 MIPS_SYS(sys_umount2 , 2)
2069 MIPS_SYS(sys_ni_syscall , 0)
2070 MIPS_SYS(sys_ioctl , 3)
2071 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2072 MIPS_SYS(sys_ni_syscall , 2)
2073 MIPS_SYS(sys_setpgid , 2)
2074 MIPS_SYS(sys_ni_syscall , 0)
2075 MIPS_SYS(sys_olduname , 1)
2076 MIPS_SYS(sys_umask , 1) /* 4060 */
2077 MIPS_SYS(sys_chroot , 1)
2078 MIPS_SYS(sys_ustat , 2)
2079 MIPS_SYS(sys_dup2 , 2)
2080 MIPS_SYS(sys_getppid , 0)
2081 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2082 MIPS_SYS(sys_setsid , 0)
2083 MIPS_SYS(sys_sigaction , 3)
2084 MIPS_SYS(sys_sgetmask , 0)
2085 MIPS_SYS(sys_ssetmask , 1)
2086 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2087 MIPS_SYS(sys_setregid , 2)
2088 MIPS_SYS(sys_sigsuspend , 0)
2089 MIPS_SYS(sys_sigpending , 1)
2090 MIPS_SYS(sys_sethostname , 2)
2091 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2092 MIPS_SYS(sys_getrlimit , 2)
2093 MIPS_SYS(sys_getrusage , 2)
2094 MIPS_SYS(sys_gettimeofday, 2)
2095 MIPS_SYS(sys_settimeofday, 2)
2096 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2097 MIPS_SYS(sys_setgroups , 2)
2098 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2099 MIPS_SYS(sys_symlink , 2)
2100 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2101 MIPS_SYS(sys_readlink , 3) /* 4085 */
2102 MIPS_SYS(sys_uselib , 1)
2103 MIPS_SYS(sys_swapon , 2)
2104 MIPS_SYS(sys_reboot , 3)
2105 MIPS_SYS(old_readdir , 3)
2106 MIPS_SYS(old_mmap , 6) /* 4090 */
2107 MIPS_SYS(sys_munmap , 2)
2108 MIPS_SYS(sys_truncate , 2)
2109 MIPS_SYS(sys_ftruncate , 2)
2110 MIPS_SYS(sys_fchmod , 2)
2111 MIPS_SYS(sys_fchown , 3) /* 4095 */
2112 MIPS_SYS(sys_getpriority , 2)
2113 MIPS_SYS(sys_setpriority , 3)
2114 MIPS_SYS(sys_ni_syscall , 0)
2115 MIPS_SYS(sys_statfs , 2)
2116 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2117 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2118 MIPS_SYS(sys_socketcall , 2)
2119 MIPS_SYS(sys_syslog , 3)
2120 MIPS_SYS(sys_setitimer , 3)
2121 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2122 MIPS_SYS(sys_newstat , 2)
2123 MIPS_SYS(sys_newlstat , 2)
2124 MIPS_SYS(sys_newfstat , 2)
2125 MIPS_SYS(sys_uname , 1)
2126 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2127 MIPS_SYS(sys_vhangup , 0)
2128 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2129 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2130 MIPS_SYS(sys_wait4 , 4)
2131 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2132 MIPS_SYS(sys_sysinfo , 1)
2133 MIPS_SYS(sys_ipc , 6)
2134 MIPS_SYS(sys_fsync , 1)
2135 MIPS_SYS(sys_sigreturn , 0)
2136 MIPS_SYS(sys_clone , 6) /* 4120 */
2137 MIPS_SYS(sys_setdomainname, 2)
2138 MIPS_SYS(sys_newuname , 1)
2139 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2140 MIPS_SYS(sys_adjtimex , 1)
2141 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2142 MIPS_SYS(sys_sigprocmask , 3)
2143 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2144 MIPS_SYS(sys_init_module , 5)
2145 MIPS_SYS(sys_delete_module, 1)
2146 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2147 MIPS_SYS(sys_quotactl , 0)
2148 MIPS_SYS(sys_getpgid , 1)
2149 MIPS_SYS(sys_fchdir , 1)
2150 MIPS_SYS(sys_bdflush , 2)
2151 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2152 MIPS_SYS(sys_personality , 1)
2153 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2154 MIPS_SYS(sys_setfsuid , 1)
2155 MIPS_SYS(sys_setfsgid , 1)
2156 MIPS_SYS(sys_llseek , 5) /* 4140 */
2157 MIPS_SYS(sys_getdents , 3)
2158 MIPS_SYS(sys_select , 5)
2159 MIPS_SYS(sys_flock , 2)
2160 MIPS_SYS(sys_msync , 3)
2161 MIPS_SYS(sys_readv , 3) /* 4145 */
2162 MIPS_SYS(sys_writev , 3)
2163 MIPS_SYS(sys_cacheflush , 3)
2164 MIPS_SYS(sys_cachectl , 3)
2165 MIPS_SYS(sys_sysmips , 4)
2166 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2167 MIPS_SYS(sys_getsid , 1)
2168 MIPS_SYS(sys_fdatasync , 0)
2169 MIPS_SYS(sys_sysctl , 1)
2170 MIPS_SYS(sys_mlock , 2)
2171 MIPS_SYS(sys_munlock , 2) /* 4155 */
2172 MIPS_SYS(sys_mlockall , 1)
2173 MIPS_SYS(sys_munlockall , 0)
2174 MIPS_SYS(sys_sched_setparam, 2)
2175 MIPS_SYS(sys_sched_getparam, 2)
2176 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2177 MIPS_SYS(sys_sched_getscheduler, 1)
2178 MIPS_SYS(sys_sched_yield , 0)
2179 MIPS_SYS(sys_sched_get_priority_max, 1)
2180 MIPS_SYS(sys_sched_get_priority_min, 1)
2181 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2182 MIPS_SYS(sys_nanosleep, 2)
2183 MIPS_SYS(sys_mremap , 5)
2184 MIPS_SYS(sys_accept , 3)
2185 MIPS_SYS(sys_bind , 3)
2186 MIPS_SYS(sys_connect , 3) /* 4170 */
2187 MIPS_SYS(sys_getpeername , 3)
2188 MIPS_SYS(sys_getsockname , 3)
2189 MIPS_SYS(sys_getsockopt , 5)
2190 MIPS_SYS(sys_listen , 2)
2191 MIPS_SYS(sys_recv , 4) /* 4175 */
2192 MIPS_SYS(sys_recvfrom , 6)
2193 MIPS_SYS(sys_recvmsg , 3)
2194 MIPS_SYS(sys_send , 4)
2195 MIPS_SYS(sys_sendmsg , 3)
2196 MIPS_SYS(sys_sendto , 6) /* 4180 */
2197 MIPS_SYS(sys_setsockopt , 5)
2198 MIPS_SYS(sys_shutdown , 2)
2199 MIPS_SYS(sys_socket , 3)
2200 MIPS_SYS(sys_socketpair , 4)
2201 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2202 MIPS_SYS(sys_getresuid , 3)
2203 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2204 MIPS_SYS(sys_poll , 3)
2205 MIPS_SYS(sys_nfsservctl , 3)
2206 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2207 MIPS_SYS(sys_getresgid , 3)
2208 MIPS_SYS(sys_prctl , 5)
2209 MIPS_SYS(sys_rt_sigreturn, 0)
2210 MIPS_SYS(sys_rt_sigaction, 4)
2211 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2212 MIPS_SYS(sys_rt_sigpending, 2)
2213 MIPS_SYS(sys_rt_sigtimedwait, 4)
2214 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2215 MIPS_SYS(sys_rt_sigsuspend, 0)
2216 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2217 MIPS_SYS(sys_pwrite64 , 6)
2218 MIPS_SYS(sys_chown , 3)
2219 MIPS_SYS(sys_getcwd , 2)
2220 MIPS_SYS(sys_capget , 2)
2221 MIPS_SYS(sys_capset , 2) /* 4205 */
2222 MIPS_SYS(sys_sigaltstack , 2)
2223 MIPS_SYS(sys_sendfile , 4)
2224 MIPS_SYS(sys_ni_syscall , 0)
2225 MIPS_SYS(sys_ni_syscall , 0)
2226 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2227 MIPS_SYS(sys_truncate64 , 4)
2228 MIPS_SYS(sys_ftruncate64 , 4)
2229 MIPS_SYS(sys_stat64 , 2)
2230 MIPS_SYS(sys_lstat64 , 2)
2231 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2232 MIPS_SYS(sys_pivot_root , 2)
2233 MIPS_SYS(sys_mincore , 3)
2234 MIPS_SYS(sys_madvise , 3)
2235 MIPS_SYS(sys_getdents64 , 3)
2236 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2237 MIPS_SYS(sys_ni_syscall , 0)
2238 MIPS_SYS(sys_gettid , 0)
2239 MIPS_SYS(sys_readahead , 5)
2240 MIPS_SYS(sys_setxattr , 5)
2241 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2242 MIPS_SYS(sys_fsetxattr , 5)
2243 MIPS_SYS(sys_getxattr , 4)
2244 MIPS_SYS(sys_lgetxattr , 4)
2245 MIPS_SYS(sys_fgetxattr , 4)
2246 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2247 MIPS_SYS(sys_llistxattr , 3)
2248 MIPS_SYS(sys_flistxattr , 3)
2249 MIPS_SYS(sys_removexattr , 2)
2250 MIPS_SYS(sys_lremovexattr, 2)
2251 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2252 MIPS_SYS(sys_tkill , 2)
2253 MIPS_SYS(sys_sendfile64 , 5)
2254 MIPS_SYS(sys_futex , 6)
2255 MIPS_SYS(sys_sched_setaffinity, 3)
2256 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2257 MIPS_SYS(sys_io_setup , 2)
2258 MIPS_SYS(sys_io_destroy , 1)
2259 MIPS_SYS(sys_io_getevents, 5)
2260 MIPS_SYS(sys_io_submit , 3)
2261 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2262 MIPS_SYS(sys_exit_group , 1)
2263 MIPS_SYS(sys_lookup_dcookie, 3)
2264 MIPS_SYS(sys_epoll_create, 1)
2265 MIPS_SYS(sys_epoll_ctl , 4)
2266 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2267 MIPS_SYS(sys_remap_file_pages, 5)
2268 MIPS_SYS(sys_set_tid_address, 1)
2269 MIPS_SYS(sys_restart_syscall, 0)
2270 MIPS_SYS(sys_fadvise64_64, 7)
2271 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2272 MIPS_SYS(sys_fstatfs64 , 2)
2273 MIPS_SYS(sys_timer_create, 3)
2274 MIPS_SYS(sys_timer_settime, 4)
2275 MIPS_SYS(sys_timer_gettime, 2)
2276 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2277 MIPS_SYS(sys_timer_delete, 1)
2278 MIPS_SYS(sys_clock_settime, 2)
2279 MIPS_SYS(sys_clock_gettime, 2)
2280 MIPS_SYS(sys_clock_getres, 2)
2281 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2282 MIPS_SYS(sys_tgkill , 3)
2283 MIPS_SYS(sys_utimes , 2)
2284 MIPS_SYS(sys_mbind , 4)
2285 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2286 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2287 MIPS_SYS(sys_mq_open , 4)
2288 MIPS_SYS(sys_mq_unlink , 1)
2289 MIPS_SYS(sys_mq_timedsend, 5)
2290 MIPS_SYS(sys_mq_timedreceive, 5)
2291 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2292 MIPS_SYS(sys_mq_getsetattr, 3)
2293 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2294 MIPS_SYS(sys_waitid , 4)
2295 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2296 MIPS_SYS(sys_add_key , 5)
2297 MIPS_SYS(sys_request_key, 4)
2298 MIPS_SYS(sys_keyctl , 5)
2299 MIPS_SYS(sys_set_thread_area, 1)
2300 MIPS_SYS(sys_inotify_init, 0)
2301 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2302 MIPS_SYS(sys_inotify_rm_watch, 2)
2303 MIPS_SYS(sys_migrate_pages, 4)
2304 MIPS_SYS(sys_openat, 4)
2305 MIPS_SYS(sys_mkdirat, 3)
2306 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2307 MIPS_SYS(sys_fchownat, 5)
2308 MIPS_SYS(sys_futimesat, 3)
2309 MIPS_SYS(sys_fstatat64, 4)
2310 MIPS_SYS(sys_unlinkat, 3)
2311 MIPS_SYS(sys_renameat, 4) /* 4295 */
2312 MIPS_SYS(sys_linkat, 5)
2313 MIPS_SYS(sys_symlinkat, 3)
2314 MIPS_SYS(sys_readlinkat, 4)
2315 MIPS_SYS(sys_fchmodat, 3)
2316 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2317 MIPS_SYS(sys_pselect6, 6)
2318 MIPS_SYS(sys_ppoll, 5)
2319 MIPS_SYS(sys_unshare, 1)
2320 MIPS_SYS(sys_splice, 6)
2321 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2322 MIPS_SYS(sys_tee, 4)
2323 MIPS_SYS(sys_vmsplice, 4)
2324 MIPS_SYS(sys_move_pages, 6)
2325 MIPS_SYS(sys_set_robust_list, 2)
2326 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2327 MIPS_SYS(sys_kexec_load, 4)
2328 MIPS_SYS(sys_getcpu, 3)
2329 MIPS_SYS(sys_epoll_pwait, 6)
2330 MIPS_SYS(sys_ioprio_set, 3)
2331 MIPS_SYS(sys_ioprio_get, 2)
2332 MIPS_SYS(sys_utimensat, 4)
2333 MIPS_SYS(sys_signalfd, 3)
2334 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2335 MIPS_SYS(sys_eventfd, 1)
2336 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2337 MIPS_SYS(sys_timerfd_create, 2)
2338 MIPS_SYS(sys_timerfd_gettime, 2)
2339 MIPS_SYS(sys_timerfd_settime, 4)
2340 MIPS_SYS(sys_signalfd4, 4)
2341 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2342 MIPS_SYS(sys_epoll_create1, 1)
2343 MIPS_SYS(sys_dup3, 3)
2344 MIPS_SYS(sys_pipe2, 2)
2345 MIPS_SYS(sys_inotify_init1, 1)
2346 MIPS_SYS(sys_preadv, 6) /* 4330 */
2347 MIPS_SYS(sys_pwritev, 6)
2348 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2349 MIPS_SYS(sys_perf_event_open, 5)
2350 MIPS_SYS(sys_accept4, 4)
2351 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2352 MIPS_SYS(sys_fanotify_init, 2)
2353 MIPS_SYS(sys_fanotify_mark, 6)
2354 MIPS_SYS(sys_prlimit64, 4)
2355 MIPS_SYS(sys_name_to_handle_at, 5)
2356 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2357 MIPS_SYS(sys_clock_adjtime, 2)
2358 MIPS_SYS(sys_syncfs, 1)
2359 };
2360 # undef MIPS_SYS
2361 # endif /* O32 */
2362
2363 static int do_store_exclusive(CPUMIPSState *env)
2364 {
2365 target_ulong addr;
2366 target_ulong page_addr;
2367 target_ulong val;
2368 int flags;
2369 int segv = 0;
2370 int reg;
2371 int d;
2372
2373 addr = env->lladdr;
2374 page_addr = addr & TARGET_PAGE_MASK;
2375 start_exclusive();
2376 mmap_lock();
2377 flags = page_get_flags(page_addr);
2378 if ((flags & PAGE_READ) == 0) {
2379 segv = 1;
2380 } else {
2381 reg = env->llreg & 0x1f;
2382 d = (env->llreg & 0x20) != 0;
2383 if (d) {
2384 segv = get_user_s64(val, addr);
2385 } else {
2386 segv = get_user_s32(val, addr);
2387 }
2388 if (!segv) {
2389 if (val != env->llval) {
2390 env->active_tc.gpr[reg] = 0;
2391 } else {
2392 if (d) {
2393 segv = put_user_u64(env->llnewval, addr);
2394 } else {
2395 segv = put_user_u32(env->llnewval, addr);
2396 }
2397 if (!segv) {
2398 env->active_tc.gpr[reg] = 1;
2399 }
2400 }
2401 }
2402 }
2403 env->lladdr = -1;
2404 if (!segv) {
2405 env->active_tc.PC += 4;
2406 }
2407 mmap_unlock();
2408 end_exclusive();
2409 return segv;
2410 }
2411
2412 /* Break codes */
2413 enum {
2414 BRK_OVERFLOW = 6,
2415 BRK_DIVZERO = 7
2416 };
2417
2418 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2419 unsigned int code)
2420 {
2421 int ret = -1;
2422
2423 switch (code) {
2424 case BRK_OVERFLOW:
2425 case BRK_DIVZERO:
2426 info->si_signo = TARGET_SIGFPE;
2427 info->si_errno = 0;
2428 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2429 queue_signal(env, info->si_signo, &*info);
2430 ret = 0;
2431 break;
2432 default:
2433 info->si_signo = TARGET_SIGTRAP;
2434 info->si_errno = 0;
2435 queue_signal(env, info->si_signo, &*info);
2436 ret = 0;
2437 break;
2438 }
2439
2440 return ret;
2441 }
2442
2443 void cpu_loop(CPUMIPSState *env)
2444 {
2445 CPUState *cs = CPU(mips_env_get_cpu(env));
2446 target_siginfo_t info;
2447 int trapnr;
2448 abi_long ret;
2449 # ifdef TARGET_ABI_MIPSO32
2450 unsigned int syscall_num;
2451 # endif
2452
2453 for(;;) {
2454 cpu_exec_start(cs);
2455 trapnr = cpu_mips_exec(cs);
2456 cpu_exec_end(cs);
2457 switch(trapnr) {
2458 case EXCP_SYSCALL:
2459 env->active_tc.PC += 4;
2460 # ifdef TARGET_ABI_MIPSO32
2461 syscall_num = env->active_tc.gpr[2] - 4000;
2462 if (syscall_num >= sizeof(mips_syscall_args)) {
2463 ret = -TARGET_ENOSYS;
2464 } else {
2465 int nb_args;
2466 abi_ulong sp_reg;
2467 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2468
2469 nb_args = mips_syscall_args[syscall_num];
2470 sp_reg = env->active_tc.gpr[29];
2471 switch (nb_args) {
2472 /* these arguments are taken from the stack */
2473 case 8:
2474 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2475 goto done_syscall;
2476 }
2477 case 7:
2478 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2479 goto done_syscall;
2480 }
2481 case 6:
2482 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2483 goto done_syscall;
2484 }
2485 case 5:
2486 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2487 goto done_syscall;
2488 }
2489 default:
2490 break;
2491 }
2492 ret = do_syscall(env, env->active_tc.gpr[2],
2493 env->active_tc.gpr[4],
2494 env->active_tc.gpr[5],
2495 env->active_tc.gpr[6],
2496 env->active_tc.gpr[7],
2497 arg5, arg6, arg7, arg8);
2498 }
2499 done_syscall:
2500 # else
2501 ret = do_syscall(env, env->active_tc.gpr[2],
2502 env->active_tc.gpr[4], env->active_tc.gpr[5],
2503 env->active_tc.gpr[6], env->active_tc.gpr[7],
2504 env->active_tc.gpr[8], env->active_tc.gpr[9],
2505 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2506 # endif /* O32 */
2507 if (ret == -TARGET_QEMU_ESIGRETURN) {
2508 /* Returning from a successful sigreturn syscall.
2509 Avoid clobbering register state. */
2510 break;
2511 }
2512 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2513 env->active_tc.gpr[7] = 1; /* error flag */
2514 ret = -ret;
2515 } else {
2516 env->active_tc.gpr[7] = 0; /* error flag */
2517 }
2518 env->active_tc.gpr[2] = ret;
2519 break;
2520 case EXCP_TLBL:
2521 case EXCP_TLBS:
2522 case EXCP_AdEL:
2523 case EXCP_AdES:
2524 info.si_signo = TARGET_SIGSEGV;
2525 info.si_errno = 0;
2526 /* XXX: check env->error_code */
2527 info.si_code = TARGET_SEGV_MAPERR;
2528 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2529 queue_signal(env, info.si_signo, &info);
2530 break;
2531 case EXCP_CpU:
2532 case EXCP_RI:
2533 info.si_signo = TARGET_SIGILL;
2534 info.si_errno = 0;
2535 info.si_code = 0;
2536 queue_signal(env, info.si_signo, &info);
2537 break;
2538 case EXCP_INTERRUPT:
2539 /* just indicate that signals should be handled asap */
2540 break;
2541 case EXCP_DEBUG:
2542 {
2543 int sig;
2544
2545 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2546 if (sig)
2547 {
2548 info.si_signo = sig;
2549 info.si_errno = 0;
2550 info.si_code = TARGET_TRAP_BRKPT;
2551 queue_signal(env, info.si_signo, &info);
2552 }
2553 }
2554 break;
2555 case EXCP_SC:
2556 if (do_store_exclusive(env)) {
2557 info.si_signo = TARGET_SIGSEGV;
2558 info.si_errno = 0;
2559 info.si_code = TARGET_SEGV_MAPERR;
2560 info._sifields._sigfault._addr = env->active_tc.PC;
2561 queue_signal(env, info.si_signo, &info);
2562 }
2563 break;
2564 case EXCP_DSPDIS:
2565 info.si_signo = TARGET_SIGILL;
2566 info.si_errno = 0;
2567 info.si_code = TARGET_ILL_ILLOPC;
2568 queue_signal(env, info.si_signo, &info);
2569 break;
2570 /* The code below was inspired by the MIPS Linux kernel trap
2571 * handling code in arch/mips/kernel/traps.c.
2572 */
2573 case EXCP_BREAK:
2574 {
2575 abi_ulong trap_instr;
2576 unsigned int code;
2577
2578 if (env->hflags & MIPS_HFLAG_M16) {
2579 if (env->insn_flags & ASE_MICROMIPS) {
2580 /* microMIPS mode */
2581 ret = get_user_u16(trap_instr, env->active_tc.PC);
2582 if (ret != 0) {
2583 goto error;
2584 }
2585
2586 if ((trap_instr >> 10) == 0x11) {
2587 /* 16-bit instruction */
2588 code = trap_instr & 0xf;
2589 } else {
2590 /* 32-bit instruction */
2591 abi_ulong instr_lo;
2592
2593 ret = get_user_u16(instr_lo,
2594 env->active_tc.PC + 2);
2595 if (ret != 0) {
2596 goto error;
2597 }
2598 trap_instr = (trap_instr << 16) | instr_lo;
2599 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2600 /* Unfortunately, microMIPS also suffers from
2601 the old assembler bug... */
2602 if (code >= (1 << 10)) {
2603 code >>= 10;
2604 }
2605 }
2606 } else {
2607 /* MIPS16e mode */
2608 ret = get_user_u16(trap_instr, env->active_tc.PC);
2609 if (ret != 0) {
2610 goto error;
2611 }
2612 code = (trap_instr >> 6) & 0x3f;
2613 }
2614 } else {
2615 ret = get_user_u32(trap_instr, env->active_tc.PC);
2616 if (ret != 0) {
2617 goto error;
2618 }
2619
2620 /* As described in the original Linux kernel code, the
2621 * below checks on 'code' are to work around an old
2622 * assembly bug.
2623 */
2624 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2625 if (code >= (1 << 10)) {
2626 code >>= 10;
2627 }
2628 }
2629
2630 if (do_break(env, &info, code) != 0) {
2631 goto error;
2632 }
2633 }
2634 break;
2635 case EXCP_TRAP:
2636 {
2637 abi_ulong trap_instr;
2638 unsigned int code = 0;
2639
2640 if (env->hflags & MIPS_HFLAG_M16) {
2641 /* microMIPS mode */
2642 abi_ulong instr[2];
2643
2644 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2645 get_user_u16(instr[1], env->active_tc.PC + 2);
2646
2647 trap_instr = (instr[0] << 16) | instr[1];
2648 } else {
2649 ret = get_user_u32(trap_instr, env->active_tc.PC);
2650 }
2651
2652 if (ret != 0) {
2653 goto error;
2654 }
2655
2656 /* The immediate versions don't provide a code. */
2657 if (!(trap_instr & 0xFC000000)) {
2658 if (env->hflags & MIPS_HFLAG_M16) {
2659 /* microMIPS mode */
2660 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2661 } else {
2662 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2663 }
2664 }
2665
2666 if (do_break(env, &info, code) != 0) {
2667 goto error;
2668 }
2669 }
2670 break;
2671 default:
2672 error:
2673 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2674 abort();
2675 }
2676 process_pending_signals(env);
2677 }
2678 }
2679 #endif
2680
2681 #ifdef TARGET_OPENRISC
2682
2683 void cpu_loop(CPUOpenRISCState *env)
2684 {
2685 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2686 int trapnr, gdbsig;
2687
2688 for (;;) {
2689 cpu_exec_start(cs);
2690 trapnr = cpu_openrisc_exec(cs);
2691 cpu_exec_end(cs);
2692 gdbsig = 0;
2693
2694 switch (trapnr) {
2695 case EXCP_RESET:
2696 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2697 exit(EXIT_FAILURE);
2698 break;
2699 case EXCP_BUSERR:
2700 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2701 gdbsig = TARGET_SIGBUS;
2702 break;
2703 case EXCP_DPF:
2704 case EXCP_IPF:
2705 cpu_dump_state(cs, stderr, fprintf, 0);
2706 gdbsig = TARGET_SIGSEGV;
2707 break;
2708 case EXCP_TICK:
2709 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2710 break;
2711 case EXCP_ALIGN:
2712 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2713 gdbsig = TARGET_SIGBUS;
2714 break;
2715 case EXCP_ILLEGAL:
2716 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2717 gdbsig = TARGET_SIGILL;
2718 break;
2719 case EXCP_INT:
2720 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2721 break;
2722 case EXCP_DTLBMISS:
2723 case EXCP_ITLBMISS:
2724 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2725 break;
2726 case EXCP_RANGE:
2727 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2728 gdbsig = TARGET_SIGSEGV;
2729 break;
2730 case EXCP_SYSCALL:
2731 env->pc += 4; /* 0xc00; */
2732 env->gpr[11] = do_syscall(env,
2733 env->gpr[11], /* return value */
2734 env->gpr[3], /* r3 - r7 are params */
2735 env->gpr[4],
2736 env->gpr[5],
2737 env->gpr[6],
2738 env->gpr[7],
2739 env->gpr[8], 0, 0);
2740 break;
2741 case EXCP_FPE:
2742 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2743 break;
2744 case EXCP_TRAP:
2745 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2746 gdbsig = TARGET_SIGTRAP;
2747 break;
2748 case EXCP_NR:
2749 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2750 break;
2751 default:
2752 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2753 trapnr);
2754 gdbsig = TARGET_SIGILL;
2755 break;
2756 }
2757 if (gdbsig) {
2758 gdb_handlesig(cs, gdbsig);
2759 if (gdbsig != TARGET_SIGTRAP) {
2760 exit(EXIT_FAILURE);
2761 }
2762 }
2763
2764 process_pending_signals(env);
2765 }
2766 }
2767
2768 #endif /* TARGET_OPENRISC */
2769
2770 #ifdef TARGET_SH4
2771 void cpu_loop(CPUSH4State *env)
2772 {
2773 CPUState *cs = CPU(sh_env_get_cpu(env));
2774 int trapnr, ret;
2775 target_siginfo_t info;
2776
2777 while (1) {
2778 cpu_exec_start(cs);
2779 trapnr = cpu_sh4_exec(cs);
2780 cpu_exec_end(cs);
2781
2782 switch (trapnr) {
2783 case 0x160:
2784 env->pc += 2;
2785 ret = do_syscall(env,
2786 env->gregs[3],
2787 env->gregs[4],
2788 env->gregs[5],
2789 env->gregs[6],
2790 env->gregs[7],
2791 env->gregs[0],
2792 env->gregs[1],
2793 0, 0);
2794 env->gregs[0] = ret;
2795 break;
2796 case EXCP_INTERRUPT:
2797 /* just indicate that signals should be handled asap */
2798 break;
2799 case EXCP_DEBUG:
2800 {
2801 int sig;
2802
2803 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2804 if (sig)
2805 {
2806 info.si_signo = sig;
2807 info.si_errno = 0;
2808 info.si_code = TARGET_TRAP_BRKPT;
2809 queue_signal(env, info.si_signo, &info);
2810 }
2811 }
2812 break;
2813 case 0xa0:
2814 case 0xc0:
2815 info.si_signo = TARGET_SIGSEGV;
2816 info.si_errno = 0;
2817 info.si_code = TARGET_SEGV_MAPERR;
2818 info._sifields._sigfault._addr = env->tea;
2819 queue_signal(env, info.si_signo, &info);
2820 break;
2821
2822 default:
2823 printf ("Unhandled trap: 0x%x\n", trapnr);
2824 cpu_dump_state(cs, stderr, fprintf, 0);
2825 exit(EXIT_FAILURE);
2826 }
2827 process_pending_signals (env);
2828 }
2829 }
2830 #endif
2831
2832 #ifdef TARGET_CRIS
2833 void cpu_loop(CPUCRISState *env)
2834 {
2835 CPUState *cs = CPU(cris_env_get_cpu(env));
2836 int trapnr, ret;
2837 target_siginfo_t info;
2838
2839 while (1) {
2840 cpu_exec_start(cs);
2841 trapnr = cpu_cris_exec(cs);
2842 cpu_exec_end(cs);
2843 switch (trapnr) {
2844 case 0xaa:
2845 {
2846 info.si_signo = TARGET_SIGSEGV;
2847 info.si_errno = 0;
2848 /* XXX: check env->error_code */
2849 info.si_code = TARGET_SEGV_MAPERR;
2850 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2851 queue_signal(env, info.si_signo, &info);
2852 }
2853 break;
2854 case EXCP_INTERRUPT:
2855 /* just indicate that signals should be handled asap */
2856 break;
2857 case EXCP_BREAK:
2858 ret = do_syscall(env,
2859 env->regs[9],
2860 env->regs[10],
2861 env->regs[11],
2862 env->regs[12],
2863 env->regs[13],
2864 env->pregs[7],
2865 env->pregs[11],
2866 0, 0);
2867 env->regs[10] = ret;
2868 break;
2869 case EXCP_DEBUG:
2870 {
2871 int sig;
2872
2873 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2874 if (sig)
2875 {
2876 info.si_signo = sig;
2877 info.si_errno = 0;
2878 info.si_code = TARGET_TRAP_BRKPT;
2879 queue_signal(env, info.si_signo, &info);
2880 }
2881 }
2882 break;
2883 default:
2884 printf ("Unhandled trap: 0x%x\n", trapnr);
2885 cpu_dump_state(cs, stderr, fprintf, 0);
2886 exit(EXIT_FAILURE);
2887 }
2888 process_pending_signals (env);
2889 }
2890 }
2891 #endif
2892
2893 #ifdef TARGET_MICROBLAZE
2894 void cpu_loop(CPUMBState *env)
2895 {
2896 CPUState *cs = CPU(mb_env_get_cpu(env));
2897 int trapnr, ret;
2898 target_siginfo_t info;
2899
2900 while (1) {
2901 cpu_exec_start(cs);
2902 trapnr = cpu_mb_exec(cs);
2903 cpu_exec_end(cs);
2904 switch (trapnr) {
2905 case 0xaa:
2906 {
2907 info.si_signo = TARGET_SIGSEGV;
2908 info.si_errno = 0;
2909 /* XXX: check env->error_code */
2910 info.si_code = TARGET_SEGV_MAPERR;
2911 info._sifields._sigfault._addr = 0;
2912 queue_signal(env, info.si_signo, &info);
2913 }
2914 break;
2915 case EXCP_INTERRUPT:
2916 /* just indicate that signals should be handled asap */
2917 break;
2918 case EXCP_BREAK:
2919 /* Return address is 4 bytes after the call. */
2920 env->regs[14] += 4;
2921 env->sregs[SR_PC] = env->regs[14];
2922 ret = do_syscall(env,
2923 env->regs[12],
2924 env->regs[5],
2925 env->regs[6],
2926 env->regs[7],
2927 env->regs[8],
2928 env->regs[9],
2929 env->regs[10],
2930 0, 0);
2931 env->regs[3] = ret;
2932 break;
2933 case EXCP_HW_EXCP:
2934 env->regs[17] = env->sregs[SR_PC] + 4;
2935 if (env->iflags & D_FLAG) {
2936 env->sregs[SR_ESR] |= 1 << 12;
2937 env->sregs[SR_PC] -= 4;
2938 /* FIXME: if branch was immed, replay the imm as well. */
2939 }
2940
2941 env->iflags &= ~(IMM_FLAG | D_FLAG);
2942
2943 switch (env->sregs[SR_ESR] & 31) {
2944 case ESR_EC_DIVZERO:
2945 info.si_signo = TARGET_SIGFPE;
2946 info.si_errno = 0;
2947 info.si_code = TARGET_FPE_FLTDIV;
2948 info._sifields._sigfault._addr = 0;
2949 queue_signal(env, info.si_signo, &info);
2950 break;
2951 case ESR_EC_FPU:
2952 info.si_signo = TARGET_SIGFPE;
2953 info.si_errno = 0;
2954 if (env->sregs[SR_FSR] & FSR_IO) {
2955 info.si_code = TARGET_FPE_FLTINV;
2956 }
2957 if (env->sregs[SR_FSR] & FSR_DZ) {
2958 info.si_code = TARGET_FPE_FLTDIV;
2959 }
2960 info._sifields._sigfault._addr = 0;
2961 queue_signal(env, info.si_signo, &info);
2962 break;
2963 default:
2964 printf ("Unhandled hw-exception: 0x%x\n",
2965 env->sregs[SR_ESR] & ESR_EC_MASK);
2966 cpu_dump_state(cs, stderr, fprintf, 0);
2967 exit(EXIT_FAILURE);
2968 break;
2969 }
2970 break;
2971 case EXCP_DEBUG:
2972 {
2973 int sig;
2974
2975 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2976 if (sig)
2977 {
2978 info.si_signo = sig;
2979 info.si_errno = 0;
2980 info.si_code = TARGET_TRAP_BRKPT;
2981 queue_signal(env, info.si_signo, &info);
2982 }
2983 }
2984 break;
2985 default:
2986 printf ("Unhandled trap: 0x%x\n", trapnr);
2987 cpu_dump_state(cs, stderr, fprintf, 0);
2988 exit(EXIT_FAILURE);
2989 }
2990 process_pending_signals (env);
2991 }
2992 }
2993 #endif
2994
2995 #ifdef TARGET_M68K
2996
2997 void cpu_loop(CPUM68KState *env)
2998 {
2999 CPUState *cs = CPU(m68k_env_get_cpu(env));
3000 int trapnr;
3001 unsigned int n;
3002 target_siginfo_t info;
3003 TaskState *ts = cs->opaque;
3004
3005 for(;;) {
3006 cpu_exec_start(cs);
3007 trapnr = cpu_m68k_exec(cs);
3008 cpu_exec_end(cs);
3009 switch(trapnr) {
3010 case EXCP_ILLEGAL:
3011 {
3012 if (ts->sim_syscalls) {
3013 uint16_t nr;
3014 get_user_u16(nr, env->pc + 2);
3015 env->pc += 4;
3016 do_m68k_simcall(env, nr);
3017 } else {
3018 goto do_sigill;
3019 }
3020 }
3021 break;
3022 case EXCP_HALT_INSN:
3023 /* Semihosing syscall. */
3024 env->pc += 4;
3025 do_m68k_semihosting(env, env->dregs[0]);
3026 break;
3027 case EXCP_LINEA:
3028 case EXCP_LINEF:
3029 case EXCP_UNSUPPORTED:
3030 do_sigill:
3031 info.si_signo = TARGET_SIGILL;
3032 info.si_errno = 0;
3033 info.si_code = TARGET_ILL_ILLOPN;
3034 info._sifields._sigfault._addr = env->pc;
3035 queue_signal(env, info.si_signo, &info);
3036 break;
3037 case EXCP_TRAP0:
3038 {
3039 ts->sim_syscalls = 0;
3040 n = env->dregs[0];
3041 env->pc += 2;
3042 env->dregs[0] = do_syscall(env,
3043 n,
3044 env->dregs[1],
3045 env->dregs[2],
3046 env->dregs[3],
3047 env->dregs[4],
3048 env->dregs[5],
3049 env->aregs[0],
3050 0, 0);
3051 }
3052 break;
3053 case EXCP_INTERRUPT:
3054 /* just indicate that signals should be handled asap */
3055 break;
3056 case EXCP_ACCESS:
3057 {
3058 info.si_signo = TARGET_SIGSEGV;
3059 info.si_errno = 0;
3060 /* XXX: check env->error_code */
3061 info.si_code = TARGET_SEGV_MAPERR;
3062 info._sifields._sigfault._addr = env->mmu.ar;
3063 queue_signal(env, info.si_signo, &info);
3064 }
3065 break;
3066 case EXCP_DEBUG:
3067 {
3068 int sig;
3069
3070 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3071 if (sig)
3072 {
3073 info.si_signo = sig;
3074 info.si_errno = 0;
3075 info.si_code = TARGET_TRAP_BRKPT;
3076 queue_signal(env, info.si_signo, &info);
3077 }
3078 }
3079 break;
3080 default:
3081 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3082 abort();
3083 }
3084 process_pending_signals(env);
3085 }
3086 }
3087 #endif /* TARGET_M68K */
3088
3089 #ifdef TARGET_ALPHA
3090 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3091 {
3092 target_ulong addr, val, tmp;
3093 target_siginfo_t info;
3094 int ret = 0;
3095
3096 addr = env->lock_addr;
3097 tmp = env->lock_st_addr;
3098 env->lock_addr = -1;
3099 env->lock_st_addr = 0;
3100
3101 start_exclusive();
3102 mmap_lock();
3103
3104 if (addr == tmp) {
3105 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3106 goto do_sigsegv;
3107 }
3108
3109 if (val == env->lock_value) {
3110 tmp = env->ir[reg];
3111 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3112 goto do_sigsegv;
3113 }
3114 ret = 1;
3115 }
3116 }
3117 env->ir[reg] = ret;
3118 env->pc += 4;
3119
3120 mmap_unlock();
3121 end_exclusive();
3122 return;
3123
3124 do_sigsegv:
3125 mmap_unlock();
3126 end_exclusive();
3127
3128 info.si_signo = TARGET_SIGSEGV;
3129 info.si_errno = 0;
3130 info.si_code = TARGET_SEGV_MAPERR;
3131 info._sifields._sigfault._addr = addr;
3132 queue_signal(env, TARGET_SIGSEGV, &info);
3133 }
3134
3135 void cpu_loop(CPUAlphaState *env)
3136 {
3137 CPUState *cs = CPU(alpha_env_get_cpu(env));
3138 int trapnr;
3139 target_siginfo_t info;
3140 abi_long sysret;
3141
3142 while (1) {
3143 cpu_exec_start(cs);
3144 trapnr = cpu_alpha_exec(cs);
3145 cpu_exec_end(cs);
3146
3147 /* All of the traps imply a transition through PALcode, which
3148 implies an REI instruction has been executed. Which means
3149 that the intr_flag should be cleared. */
3150 env->intr_flag = 0;
3151
3152 switch (trapnr) {
3153 case EXCP_RESET:
3154 fprintf(stderr, "Reset requested. Exit\n");
3155 exit(EXIT_FAILURE);
3156 break;
3157 case EXCP_MCHK:
3158 fprintf(stderr, "Machine check exception. Exit\n");
3159 exit(EXIT_FAILURE);
3160 break;
3161 case EXCP_SMP_INTERRUPT:
3162 case EXCP_CLK_INTERRUPT:
3163 case EXCP_DEV_INTERRUPT:
3164 fprintf(stderr, "External interrupt. Exit\n");
3165 exit(EXIT_FAILURE);
3166 break;
3167 case EXCP_MMFAULT:
3168 env->lock_addr = -1;
3169 info.si_signo = TARGET_SIGSEGV;
3170 info.si_errno = 0;
3171 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3172 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3173 info._sifields._sigfault._addr = env->trap_arg0;
3174 queue_signal(env, info.si_signo, &info);
3175 break;
3176 case EXCP_UNALIGN:
3177 env->lock_addr = -1;
3178 info.si_signo = TARGET_SIGBUS;
3179 info.si_errno = 0;
3180 info.si_code = TARGET_BUS_ADRALN;
3181 info._sifields._sigfault._addr = env->trap_arg0;
3182 queue_signal(env, info.si_signo, &info);
3183 break;
3184 case EXCP_OPCDEC:
3185 do_sigill:
3186 env->lock_addr = -1;
3187 info.si_signo = TARGET_SIGILL;
3188 info.si_errno = 0;
3189 info.si_code = TARGET_ILL_ILLOPC;
3190 info._sifields._sigfault._addr = env->pc;
3191 queue_signal(env, info.si_signo, &info);
3192 break;
3193 case EXCP_ARITH:
3194 env->lock_addr = -1;
3195 info.si_signo = TARGET_SIGFPE;
3196 info.si_errno = 0;
3197 info.si_code = TARGET_FPE_FLTINV;
3198 info._sifields._sigfault._addr = env->pc;
3199 queue_signal(env, info.si_signo, &info);
3200 break;
3201 case EXCP_FEN:
3202 /* No-op. Linux simply re-enables the FPU. */
3203 break;
3204 case EXCP_CALL_PAL:
3205 env->lock_addr = -1;
3206 switch (env->error_code) {
3207 case 0x80:
3208 /* BPT */
3209 info.si_signo = TARGET_SIGTRAP;
3210 info.si_errno = 0;
3211 info.si_code = TARGET_TRAP_BRKPT;
3212 info._sifields._sigfault._addr = env->pc;
3213 queue_signal(env, info.si_signo, &info);
3214 break;
3215 case 0x81:
3216 /* BUGCHK */
3217 info.si_signo = TARGET_SIGTRAP;
3218 info.si_errno = 0;
3219 info.si_code = 0;
3220 info._sifields._sigfault._addr = env->pc;
3221 queue_signal(env, info.si_signo, &info);
3222 break;
3223 case 0x83:
3224 /* CALLSYS */
3225 trapnr = env->ir[IR_V0];
3226 sysret = do_syscall(env, trapnr,
3227 env->ir[IR_A0], env->ir[IR_A1],
3228 env->ir[IR_A2], env->ir[IR_A3],
3229 env->ir[IR_A4], env->ir[IR_A5],
3230 0, 0);
3231 if (trapnr == TARGET_NR_sigreturn
3232 || trapnr == TARGET_NR_rt_sigreturn) {
3233 break;
3234 }
3235 /* Syscall writes 0 to V0 to bypass error check, similar
3236 to how this is handled internal to Linux kernel.
3237 (Ab)use trapnr temporarily as boolean indicating error. */
3238 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3239 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3240 env->ir[IR_A3] = trapnr;
3241 break;
3242 case 0x86:
3243 /* IMB */
3244 /* ??? We can probably elide the code using page_unprotect
3245 that is checking for self-modifying code. Instead we
3246 could simply call tb_flush here. Until we work out the
3247 changes required to turn off the extra write protection,
3248 this can be a no-op. */
3249 break;
3250 case 0x9E:
3251 /* RDUNIQUE */
3252 /* Handled in the translator for usermode. */
3253 abort();
3254 case 0x9F:
3255 /* WRUNIQUE */
3256 /* Handled in the translator for usermode. */
3257 abort();
3258 case 0xAA:
3259 /* GENTRAP */
3260 info.si_signo = TARGET_SIGFPE;
3261 switch (env->ir[IR_A0]) {
3262 case TARGET_GEN_INTOVF:
3263 info.si_code = TARGET_FPE_INTOVF;
3264 break;
3265 case TARGET_GEN_INTDIV:
3266 info.si_code = TARGET_FPE_INTDIV;
3267 break;
3268 case TARGET_GEN_FLTOVF:
3269 info.si_code = TARGET_FPE_FLTOVF;
3270 break;
3271 case TARGET_GEN_FLTUND:
3272 info.si_code = TARGET_FPE_FLTUND;
3273 break;
3274 case TARGET_GEN_FLTINV:
3275 info.si_code = TARGET_FPE_FLTINV;
3276 break;
3277 case TARGET_GEN_FLTINE:
3278 info.si_code = TARGET_FPE_FLTRES;
3279 break;
3280 case TARGET_GEN_ROPRAND:
3281 info.si_code = 0;
3282 break;
3283 default:
3284 info.si_signo = TARGET_SIGTRAP;
3285 info.si_code = 0;
3286 break;
3287 }
3288 info.si_errno = 0;
3289 info._sifields._sigfault._addr = env->pc;
3290 queue_signal(env, info.si_signo, &info);
3291 break;
3292 default:
3293 goto do_sigill;
3294 }
3295 break;
3296 case EXCP_DEBUG:
3297 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3298 if (info.si_signo) {
3299 env->lock_addr = -1;
3300 info.si_errno = 0;
3301 info.si_code = TARGET_TRAP_BRKPT;
3302 queue_signal(env, info.si_signo, &info);
3303 }
3304 break;
3305 case EXCP_STL_C:
3306 case EXCP_STQ_C:
3307 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3308 break;
3309 case EXCP_INTERRUPT:
3310 /* Just indicate that signals should be handled asap. */
3311 break;
3312 default:
3313 printf ("Unhandled trap: 0x%x\n", trapnr);
3314 cpu_dump_state(cs, stderr, fprintf, 0);
3315 exit(EXIT_FAILURE);
3316 }
3317 process_pending_signals (env);
3318 }
3319 }
3320 #endif /* TARGET_ALPHA */
3321
3322 #ifdef TARGET_S390X
3323 void cpu_loop(CPUS390XState *env)
3324 {
3325 CPUState *cs = CPU(s390_env_get_cpu(env));
3326 int trapnr, n, sig;
3327 target_siginfo_t info;
3328 target_ulong addr;
3329
3330 while (1) {
3331 cpu_exec_start(cs);
3332 trapnr = cpu_s390x_exec(cs);
3333 cpu_exec_end(cs);
3334 switch (trapnr) {
3335 case EXCP_INTERRUPT:
3336 /* Just indicate that signals should be handled asap. */
3337 break;
3338
3339 case EXCP_SVC:
3340 n = env->int_svc_code;
3341 if (!n) {
3342 /* syscalls > 255 */
3343 n = env->regs[1];
3344 }
3345 env->psw.addr += env->int_svc_ilen;
3346 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3347 env->regs[4], env->regs[5],
3348 env->regs[6], env->regs[7], 0, 0);
3349 break;
3350
3351 case EXCP_DEBUG:
3352 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3353 if (sig) {
3354 n = TARGET_TRAP_BRKPT;
3355 goto do_signal_pc;
3356 }
3357 break;
3358 case EXCP_PGM:
3359 n = env->int_pgm_code;
3360 switch (n) {
3361 case PGM_OPERATION:
3362 case PGM_PRIVILEGED:
3363 sig = TARGET_SIGILL;
3364 n = TARGET_ILL_ILLOPC;
3365 goto do_signal_pc;
3366 case PGM_PROTECTION:
3367 case PGM_ADDRESSING:
3368 sig = TARGET_SIGSEGV;
3369 /* XXX: check env->error_code */
3370 n = TARGET_SEGV_MAPERR;
3371 addr = env->__excp_addr;
3372 goto do_signal;
3373 case PGM_EXECUTE:
3374 case PGM_SPECIFICATION:
3375 case PGM_SPECIAL_OP:
3376 case PGM_OPERAND:
3377 do_sigill_opn:
3378 sig = TARGET_SIGILL;
3379 n = TARGET_ILL_ILLOPN;
3380 goto do_signal_pc;
3381
3382 case PGM_FIXPT_OVERFLOW:
3383 sig = TARGET_SIGFPE;
3384 n = TARGET_FPE_INTOVF;
3385 goto do_signal_pc;
3386 case PGM_FIXPT_DIVIDE:
3387 sig = TARGET_SIGFPE;
3388 n = TARGET_FPE_INTDIV;
3389 goto do_signal_pc;
3390
3391 case PGM_DATA:
3392 n = (env->fpc >> 8) & 0xff;
3393 if (n == 0xff) {
3394 /* compare-and-trap */
3395 goto do_sigill_opn;
3396 } else {
3397 /* An IEEE exception, simulated or otherwise. */
3398 if (n & 0x80) {
3399 n = TARGET_FPE_FLTINV;
3400 } else if (n & 0x40) {
3401 n = TARGET_FPE_FLTDIV;
3402 } else if (n & 0x20) {
3403 n = TARGET_FPE_FLTOVF;
3404 } else if (n & 0x10) {
3405 n = TARGET_FPE_FLTUND;
3406 } else if (n & 0x08) {
3407 n = TARGET_FPE_FLTRES;
3408 } else {
3409 /* ??? Quantum exception; BFP, DFP error. */
3410 goto do_sigill_opn;
3411 }
3412 sig = TARGET_SIGFPE;
3413 goto do_signal_pc;
3414 }
3415
3416 default:
3417 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3418 cpu_dump_state(cs, stderr, fprintf, 0);
3419 exit(EXIT_FAILURE);
3420 }
3421 break;
3422
3423 do_signal_pc:
3424 addr = env->psw.addr;
3425 do_signal:
3426 info.si_signo = sig;
3427 info.si_errno = 0;
3428 info.si_code = n;
3429 info._sifields._sigfault._addr = addr;
3430 queue_signal(env, info.si_signo, &info);
3431 break;
3432
3433 default:
3434 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3435 cpu_dump_state(cs, stderr, fprintf, 0);
3436 exit(EXIT_FAILURE);
3437 }
3438 process_pending_signals (env);
3439 }
3440 }
3441
3442 #endif /* TARGET_S390X */
3443
3444 #ifdef TARGET_TILEGX
3445
3446 static void gen_sigill_reg(CPUTLGState *env)
3447 {
3448 target_siginfo_t info;
3449
3450 info.si_signo = TARGET_SIGILL;
3451 info.si_errno = 0;
3452 info.si_code = TARGET_ILL_PRVREG;
3453 info._sifields._sigfault._addr = env->pc;
3454 queue_signal(env, info.si_signo, &info);
3455 }
3456
3457 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3458 {
3459 target_siginfo_t info;
3460
3461 info.si_signo = signo;
3462 info.si_errno = 0;
3463 info._sifields._sigfault._addr = env->pc;
3464
3465 if (signo == TARGET_SIGSEGV) {
3466 /* The passed in sigcode is a dummy; check for a page mapping
3467 and pass either MAPERR or ACCERR. */
3468 target_ulong addr = env->excaddr;
3469 info._sifields._sigfault._addr = addr;
3470 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3471 sigcode = TARGET_SEGV_MAPERR;
3472 } else {
3473 sigcode = TARGET_SEGV_ACCERR;
3474 }
3475 }
3476 info.si_code = sigcode;
3477
3478 queue_signal(env, info.si_signo, &info);
3479 }
3480
3481 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3482 {
3483 env->excaddr = addr;
3484 do_signal(env, TARGET_SIGSEGV, 0);
3485 }
3486
3487 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3488 {
3489 if (unlikely(reg >= TILEGX_R_COUNT)) {
3490 switch (reg) {
3491 case TILEGX_R_SN:
3492 case TILEGX_R_ZERO:
3493 return;
3494 case TILEGX_R_IDN0:
3495 case TILEGX_R_IDN1:
3496 case TILEGX_R_UDN0:
3497 case TILEGX_R_UDN1:
3498 case TILEGX_R_UDN2:
3499 case TILEGX_R_UDN3:
3500 gen_sigill_reg(env);
3501 return;
3502 default:
3503 g_assert_not_reached();
3504 }
3505 }
3506 env->regs[reg] = val;
3507 }
3508
3509 /*
3510 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3511 * memory at the address held in the first source register. If the values are
3512 * not equal, then no memory operation is performed. If the values are equal,
3513 * the 8-byte quantity from the second source register is written into memory
3514 * at the address held in the first source register. In either case, the result
3515 * of the instruction is the value read from memory. The compare and write to
3516 * memory are atomic and thus can be used for synchronization purposes. This
3517 * instruction only operates for addresses aligned to a 8-byte boundary.
3518 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3519 *
3520 * Functional Description (64-bit)
3521 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3522 * rf[Dest] = memVal;
3523 * if (memVal == SPR[CmpValueSPR])
3524 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3525 *
3526 * Functional Description (32-bit)
3527 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3528 * rf[Dest] = memVal;
3529 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3530 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3531 *
3532 *
3533 * This function also processes exch and exch4 which need not process SPR.
3534 */
3535 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3536 {
3537 target_ulong addr;
3538 target_long val, sprval;
3539
3540 start_exclusive();
3541
3542 addr = env->atomic_srca;
3543 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3544 goto sigsegv_maperr;
3545 }
3546
3547 if (cmp) {
3548 if (quad) {
3549 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3550 } else {
3551 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3552 }
3553 }
3554
3555 if (!cmp || val == sprval) {
3556 target_long valb = env->atomic_srcb;
3557 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3558 goto sigsegv_maperr;
3559 }
3560 }
3561
3562 set_regval(env, env->atomic_dstr, val);
3563 end_exclusive();
3564 return;
3565
3566 sigsegv_maperr:
3567 end_exclusive();
3568 gen_sigsegv_maperr(env, addr);
3569 }
3570
3571 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3572 {
3573 int8_t write = 1;
3574 target_ulong addr;
3575 target_long val, valb;
3576
3577 start_exclusive();
3578
3579 addr = env->atomic_srca;
3580 valb = env->atomic_srcb;
3581 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3582 goto sigsegv_maperr;
3583 }
3584
3585 switch (trapnr) {
3586 case TILEGX_EXCP_OPCODE_FETCHADD:
3587 case TILEGX_EXCP_OPCODE_FETCHADD4:
3588 valb += val;
3589 break;
3590 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3591 valb += val;
3592 if (valb < 0) {
3593 write = 0;
3594 }
3595 break;
3596 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3597 valb += val;
3598 if ((int32_t)valb < 0) {
3599 write = 0;
3600 }
3601 break;
3602 case TILEGX_EXCP_OPCODE_FETCHAND:
3603 case TILEGX_EXCP_OPCODE_FETCHAND4:
3604 valb &= val;
3605 break;
3606 case TILEGX_EXCP_OPCODE_FETCHOR:
3607 case TILEGX_EXCP_OPCODE_FETCHOR4:
3608 valb |= val;
3609 break;
3610 default:
3611 g_assert_not_reached();
3612 }
3613
3614 if (write) {
3615 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3616 goto sigsegv_maperr;
3617 }
3618 }
3619
3620 set_regval(env, env->atomic_dstr, val);
3621 end_exclusive();
3622 return;
3623
3624 sigsegv_maperr:
3625 end_exclusive();
3626 gen_sigsegv_maperr(env, addr);
3627 }
3628
3629 void cpu_loop(CPUTLGState *env)
3630 {
3631 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3632 int trapnr;
3633
3634 while (1) {
3635 cpu_exec_start(cs);
3636 trapnr = cpu_tilegx_exec(cs);
3637 cpu_exec_end(cs);
3638 switch (trapnr) {
3639 case TILEGX_EXCP_SYSCALL:
3640 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
3641 env->regs[0], env->regs[1],
3642 env->regs[2], env->regs[3],
3643 env->regs[4], env->regs[5],
3644 env->regs[6], env->regs[7]);
3645 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
3646 ? - env->regs[TILEGX_R_RE]
3647 : 0;
3648 break;
3649 case TILEGX_EXCP_OPCODE_EXCH:
3650 do_exch(env, true, false);
3651 break;
3652 case TILEGX_EXCP_OPCODE_EXCH4:
3653 do_exch(env, false, false);
3654 break;
3655 case TILEGX_EXCP_OPCODE_CMPEXCH:
3656 do_exch(env, true, true);
3657 break;
3658 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3659 do_exch(env, false, true);
3660 break;
3661 case TILEGX_EXCP_OPCODE_FETCHADD:
3662 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3663 case TILEGX_EXCP_OPCODE_FETCHAND:
3664 case TILEGX_EXCP_OPCODE_FETCHOR:
3665 do_fetch(env, trapnr, true);
3666 break;
3667 case TILEGX_EXCP_OPCODE_FETCHADD4:
3668 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3669 case TILEGX_EXCP_OPCODE_FETCHAND4:
3670 case TILEGX_EXCP_OPCODE_FETCHOR4:
3671 do_fetch(env, trapnr, false);
3672 break;
3673 case TILEGX_EXCP_SIGNAL:
3674 do_signal(env, env->signo, env->sigcode);
3675 break;
3676 case TILEGX_EXCP_REG_IDN_ACCESS:
3677 case TILEGX_EXCP_REG_UDN_ACCESS:
3678 gen_sigill_reg(env);
3679 break;
3680 default:
3681 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3682 g_assert_not_reached();
3683 }
3684 process_pending_signals(env);
3685 }
3686 }
3687
3688 #endif
3689
3690 THREAD CPUState *thread_cpu;
3691
3692 void task_settid(TaskState *ts)
3693 {
3694 if (ts->ts_tid == 0) {
3695 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3696 }
3697 }
3698
3699 void stop_all_tasks(void)
3700 {
3701 /*
3702 * We trust that when using NPTL, start_exclusive()
3703 * handles thread stopping correctly.
3704 */
3705 start_exclusive();
3706 }
3707
3708 /* Assumes contents are already zeroed. */
3709 void init_task_state(TaskState *ts)
3710 {
3711 int i;
3712
3713 ts->used = 1;
3714 ts->first_free = ts->sigqueue_table;
3715 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3716 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3717 }
3718 ts->sigqueue_table[i].next = NULL;
3719 }
3720
3721 CPUArchState *cpu_copy(CPUArchState *env)
3722 {
3723 CPUState *cpu = ENV_GET_CPU(env);
3724 CPUState *new_cpu = cpu_init(cpu_model);
3725 CPUArchState *new_env = new_cpu->env_ptr;
3726 CPUBreakpoint *bp;
3727 CPUWatchpoint *wp;
3728
3729 /* Reset non arch specific state */
3730 cpu_reset(new_cpu);
3731
3732 memcpy(new_env, env, sizeof(CPUArchState));
3733
3734 /* Clone all break/watchpoints.
3735 Note: Once we support ptrace with hw-debug register access, make sure
3736 BP_CPU break/watchpoints are handled correctly on clone. */
3737 QTAILQ_INIT(&new_cpu->breakpoints);
3738 QTAILQ_INIT(&new_cpu->watchpoints);
3739 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3740 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3741 }
3742 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3743 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3744 }
3745
3746 return new_env;
3747 }
3748
3749 static void handle_arg_help(const char *arg)
3750 {
3751 usage(EXIT_SUCCESS);
3752 }
3753
3754 static void handle_arg_log(const char *arg)
3755 {
3756 int mask;
3757
3758 mask = qemu_str_to_log_mask(arg);
3759 if (!mask) {
3760 qemu_print_log_usage(stdout);
3761 exit(EXIT_FAILURE);
3762 }
3763 qemu_set_log(mask);
3764 }
3765
3766 static void handle_arg_log_filename(const char *arg)
3767 {
3768 qemu_set_log_filename(arg);
3769 }
3770
3771 static void handle_arg_set_env(const char *arg)
3772 {
3773 char *r, *p, *token;
3774 r = p = strdup(arg);
3775 while ((token = strsep(&p, ",")) != NULL) {
3776 if (envlist_setenv(envlist, token) != 0) {
3777 usage(EXIT_FAILURE);
3778 }
3779 }
3780 free(r);
3781 }
3782
3783 static void handle_arg_unset_env(const char *arg)
3784 {
3785 char *r, *p, *token;
3786 r = p = strdup(arg);
3787 while ((token = strsep(&p, ",")) != NULL) {
3788 if (envlist_unsetenv(envlist, token) != 0) {
3789 usage(EXIT_FAILURE);
3790 }
3791 }
3792 free(r);
3793 }
3794
3795 static void handle_arg_argv0(const char *arg)
3796 {
3797 argv0 = strdup(arg);
3798 }
3799
3800 static void handle_arg_stack_size(const char *arg)
3801 {
3802 char *p;
3803 guest_stack_size = strtoul(arg, &p, 0);
3804 if (guest_stack_size == 0) {
3805 usage(EXIT_FAILURE);
3806 }
3807
3808 if (*p == 'M') {
3809 guest_stack_size *= 1024 * 1024;
3810 } else if (*p == 'k' || *p == 'K') {
3811 guest_stack_size *= 1024;
3812 }
3813 }
3814
3815 static void handle_arg_ld_prefix(const char *arg)
3816 {
3817 interp_prefix = strdup(arg);
3818 }
3819
3820 static void handle_arg_pagesize(const char *arg)
3821 {
3822 qemu_host_page_size = atoi(arg);
3823 if (qemu_host_page_size == 0 ||
3824 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3825 fprintf(stderr, "page size must be a power of two\n");
3826 exit(EXIT_FAILURE);
3827 }
3828 }
3829
3830 static void handle_arg_randseed(const char *arg)
3831 {
3832 unsigned long long seed;
3833
3834 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3835 fprintf(stderr, "Invalid seed number: %s\n", arg);
3836 exit(EXIT_FAILURE);
3837 }
3838 srand(seed);
3839 }
3840
3841 static void handle_arg_gdb(const char *arg)
3842 {
3843 gdbstub_port = atoi(arg);
3844 }
3845
3846 static void handle_arg_uname(const char *arg)
3847 {
3848 qemu_uname_release = strdup(arg);
3849 }
3850
3851 static void handle_arg_cpu(const char *arg)
3852 {
3853 cpu_model = strdup(arg);
3854 if (cpu_model == NULL || is_help_option(cpu_model)) {
3855 /* XXX: implement xxx_cpu_list for targets that still miss it */
3856 #if defined(cpu_list)
3857 cpu_list(stdout, &fprintf);
3858 #endif
3859 exit(EXIT_FAILURE);
3860 }
3861 }
3862
3863 static void handle_arg_guest_base(const char *arg)
3864 {
3865 guest_base = strtol(arg, NULL, 0);
3866 have_guest_base = 1;
3867 }
3868
3869 static void handle_arg_reserved_va(const char *arg)
3870 {
3871 char *p;
3872 int shift = 0;
3873 reserved_va = strtoul(arg, &p, 0);
3874 switch (*p) {
3875 case 'k':
3876 case 'K':
3877 shift = 10;
3878 break;
3879 case 'M':
3880 shift = 20;
3881 break;
3882 case 'G':
3883 shift = 30;
3884 break;
3885 }
3886 if (shift) {
3887 unsigned long unshifted = reserved_va;
3888 p++;
3889 reserved_va <<= shift;
3890 if (((reserved_va >> shift) != unshifted)
3891 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3892 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3893 #endif
3894 ) {
3895 fprintf(stderr, "Reserved virtual address too big\n");
3896 exit(EXIT_FAILURE);
3897 }
3898 }
3899 if (*p) {
3900 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3901 exit(EXIT_FAILURE);
3902 }
3903 }
3904
3905 static void handle_arg_singlestep(const char *arg)
3906 {
3907 singlestep = 1;
3908 }
3909
3910 static void handle_arg_strace(const char *arg)
3911 {
3912 do_strace = 1;
3913 }
3914
3915 static void handle_arg_version(const char *arg)
3916 {
3917 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3918 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3919 exit(EXIT_SUCCESS);
3920 }
3921
3922 struct qemu_argument {
3923 const char *argv;
3924 const char *env;
3925 bool has_arg;
3926 void (*handle_opt)(const char *arg);
3927 const char *example;
3928 const char *help;
3929 };
3930
3931 static const struct qemu_argument arg_table[] = {
3932 {"h", "", false, handle_arg_help,
3933 "", "print this help"},
3934 {"help", "", false, handle_arg_help,
3935 "", ""},
3936 {"g", "QEMU_GDB", true, handle_arg_gdb,
3937 "port", "wait gdb connection to 'port'"},
3938 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3939 "path", "set the elf interpreter prefix to 'path'"},
3940 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3941 "size", "set the stack size to 'size' bytes"},
3942 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3943 "model", "select CPU (-cpu help for list)"},
3944 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3945 "var=value", "sets targets environment variable (see below)"},
3946 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3947 "var", "unsets targets environment variable (see below)"},
3948 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3949 "argv0", "forces target process argv[0] to be 'argv0'"},
3950 {"r", "QEMU_UNAME", true, handle_arg_uname,
3951 "uname", "set qemu uname release string to 'uname'"},
3952 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3953 "address", "set guest_base address to 'address'"},
3954 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3955 "size", "reserve 'size' bytes for guest virtual address space"},
3956 {"d", "QEMU_LOG", true, handle_arg_log,
3957 "item[,...]", "enable logging of specified items "
3958 "(use '-d help' for a list of items)"},
3959 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3960 "logfile", "write logs to 'logfile' (default stderr)"},
3961 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3962 "pagesize", "set the host page size to 'pagesize'"},
3963 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3964 "", "run in singlestep mode"},
3965 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3966 "", "log system calls"},
3967 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3968 "", "Seed for pseudo-random number generator"},
3969 {"version", "QEMU_VERSION", false, handle_arg_version,
3970 "", "display version information and exit"},
3971 {NULL, NULL, false, NULL, NULL, NULL}
3972 };
3973
3974 static void usage(int exitcode)
3975 {
3976 const struct qemu_argument *arginfo;
3977 int maxarglen;
3978 int maxenvlen;
3979
3980 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3981 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3982 "\n"
3983 "Options and associated environment variables:\n"
3984 "\n");
3985
3986 /* Calculate column widths. We must always have at least enough space
3987 * for the column header.
3988 */
3989 maxarglen = strlen("Argument");
3990 maxenvlen = strlen("Env-variable");
3991
3992 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3993 int arglen = strlen(arginfo->argv);
3994 if (arginfo->has_arg) {
3995 arglen += strlen(arginfo->example) + 1;
3996 }
3997 if (strlen(arginfo->env) > maxenvlen) {
3998 maxenvlen = strlen(arginfo->env);
3999 }
4000 if (arglen > maxarglen) {
4001 maxarglen = arglen;
4002 }
4003 }
4004
4005 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4006 maxenvlen, "Env-variable");
4007
4008 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4009 if (arginfo->has_arg) {
4010 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4011 (int)(maxarglen - strlen(arginfo->argv) - 1),
4012 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4013 } else {
4014 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4015 maxenvlen, arginfo->env,
4016 arginfo->help);
4017 }
4018 }
4019
4020 printf("\n"
4021 "Defaults:\n"
4022 "QEMU_LD_PREFIX = %s\n"
4023 "QEMU_STACK_SIZE = %ld byte\n",
4024 interp_prefix,
4025 guest_stack_size);
4026
4027 printf("\n"
4028 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4029 "QEMU_UNSET_ENV environment variables to set and unset\n"
4030 "environment variables for the target process.\n"
4031 "It is possible to provide several variables by separating them\n"
4032 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4033 "provide the -E and -U options multiple times.\n"
4034 "The following lines are equivalent:\n"
4035 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4036 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4037 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4038 "Note that if you provide several changes to a single variable\n"
4039 "the last change will stay in effect.\n");
4040
4041 exit(exitcode);
4042 }
4043
4044 static int parse_args(int argc, char **argv)
4045 {
4046 const char *r;
4047 int optind;
4048 const struct qemu_argument *arginfo;
4049
4050 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4051 if (arginfo->env == NULL) {
4052 continue;
4053 }
4054
4055 r = getenv(arginfo->env);
4056 if (r != NULL) {
4057 arginfo->handle_opt(r);
4058 }
4059 }
4060
4061 optind = 1;
4062 for (;;) {
4063 if (optind >= argc) {
4064 break;
4065 }
4066 r = argv[optind];
4067 if (r[0] != '-') {
4068 break;
4069 }
4070 optind++;
4071 r++;
4072 if (!strcmp(r, "-")) {
4073 break;
4074 }
4075 /* Treat --foo the same as -foo. */
4076 if (r[0] == '-') {
4077 r++;
4078 }
4079
4080 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4081 if (!strcmp(r, arginfo->argv)) {
4082 if (arginfo->has_arg) {
4083 if (optind >= argc) {
4084 (void) fprintf(stderr,
4085 "qemu: missing argument for option '%s'\n", r);
4086 exit(EXIT_FAILURE);
4087 }
4088 arginfo->handle_opt(argv[optind]);
4089 optind++;
4090 } else {
4091 arginfo->handle_opt(NULL);
4092 }
4093 break;
4094 }
4095 }
4096
4097 /* no option matched the current argv */
4098 if (arginfo->handle_opt == NULL) {
4099 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4100 exit(EXIT_FAILURE);
4101 }
4102 }
4103
4104 if (optind >= argc) {
4105 (void) fprintf(stderr, "qemu: no user program specified\n");
4106 exit(EXIT_FAILURE);
4107 }
4108
4109 filename = argv[optind];
4110 exec_path = argv[optind];
4111
4112 return optind;
4113 }
4114
4115 int main(int argc, char **argv, char **envp)
4116 {
4117 struct target_pt_regs regs1, *regs = &regs1;
4118 struct image_info info1, *info = &info1;
4119 struct linux_binprm bprm;
4120 TaskState *ts;
4121 CPUArchState *env;
4122 CPUState *cpu;
4123 int optind;
4124 char **target_environ, **wrk;
4125 char **target_argv;
4126 int target_argc;
4127 int i;
4128 int ret;
4129 int execfd;
4130
4131 module_call_init(MODULE_INIT_QOM);
4132
4133 if ((envlist = envlist_create()) == NULL) {
4134 (void) fprintf(stderr, "Unable to allocate envlist\n");
4135 exit(EXIT_FAILURE);
4136 }
4137
4138 /* add current environment into the list */
4139 for (wrk = environ; *wrk != NULL; wrk++) {
4140 (void) envlist_setenv(envlist, *wrk);
4141 }
4142
4143 /* Read the stack limit from the kernel. If it's "unlimited",
4144 then we can do little else besides use the default. */
4145 {
4146 struct rlimit lim;
4147 if (getrlimit(RLIMIT_STACK, &lim) == 0
4148 && lim.rlim_cur != RLIM_INFINITY
4149 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4150 guest_stack_size = lim.rlim_cur;
4151 }
4152 }
4153
4154 cpu_model = NULL;
4155 #if defined(cpudef_setup)
4156 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
4157 #endif
4158
4159 srand(time(NULL));
4160
4161 optind = parse_args(argc, argv);
4162
4163 /* Zero out regs */
4164 memset(regs, 0, sizeof(struct target_pt_regs));
4165
4166 /* Zero out image_info */
4167 memset(info, 0, sizeof(struct image_info));
4168
4169 memset(&bprm, 0, sizeof (bprm));
4170
4171 /* Scan interp_prefix dir for replacement files. */
4172 init_paths(interp_prefix);
4173
4174 init_qemu_uname_release();
4175
4176 if (cpu_model == NULL) {
4177 #if defined(TARGET_I386)
4178 #ifdef TARGET_X86_64
4179 cpu_model = "qemu64";
4180 #else
4181 cpu_model = "qemu32";
4182 #endif
4183 #elif defined(TARGET_ARM)
4184 cpu_model = "any";
4185 #elif defined(TARGET_UNICORE32)
4186 cpu_model = "any";
4187 #elif defined(TARGET_M68K)
4188 cpu_model = "any";
4189 #elif defined(TARGET_SPARC)
4190 #ifdef TARGET_SPARC64
4191 cpu_model = "TI UltraSparc II";
4192 #else
4193 cpu_model = "Fujitsu MB86904";
4194 #endif
4195 #elif defined(TARGET_MIPS)
4196 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4197 cpu_model = "5KEf";
4198 #else
4199 cpu_model = "24Kf";
4200 #endif
4201 #elif defined TARGET_OPENRISC
4202 cpu_model = "or1200";
4203 #elif defined(TARGET_PPC)
4204 # ifdef TARGET_PPC64
4205 cpu_model = "POWER8";
4206 # else
4207 cpu_model = "750";
4208 # endif
4209 #elif defined TARGET_SH4
4210 cpu_model = TYPE_SH7785_CPU;
4211 #else
4212 cpu_model = "any";
4213 #endif
4214 }
4215 tcg_exec_init(0);
4216 /* NOTE: we need to init the CPU at this stage to get
4217 qemu_host_page_size */
4218 cpu = cpu_init(cpu_model);
4219 if (!cpu) {
4220 fprintf(stderr, "Unable to find CPU definition\n");
4221 exit(EXIT_FAILURE);
4222 }
4223 env = cpu->env_ptr;
4224 cpu_reset(cpu);
4225
4226 thread_cpu = cpu;
4227
4228 if (getenv("QEMU_STRACE")) {
4229 do_strace = 1;
4230 }
4231
4232 if (getenv("QEMU_RAND_SEED")) {
4233 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4234 }
4235
4236 target_environ = envlist_to_environ(envlist, NULL);
4237 envlist_free(envlist);
4238
4239 /*
4240 * Now that page sizes are configured in cpu_init() we can do
4241 * proper page alignment for guest_base.
4242 */
4243 guest_base = HOST_PAGE_ALIGN(guest_base);
4244
4245 if (reserved_va || have_guest_base) {
4246 guest_base = init_guest_space(guest_base, reserved_va, 0,
4247 have_guest_base);
4248 if (guest_base == (unsigned long)-1) {
4249 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4250 "space for use as guest address space (check your virtual "
4251 "memory ulimit setting or reserve less using -R option)\n",
4252 reserved_va);
4253 exit(EXIT_FAILURE);
4254 }
4255
4256 if (reserved_va) {
4257 mmap_next_start = reserved_va;
4258 }
4259 }
4260
4261 /*
4262 * Read in mmap_min_addr kernel parameter. This value is used
4263 * When loading the ELF image to determine whether guest_base
4264 * is needed. It is also used in mmap_find_vma.
4265 */
4266 {
4267 FILE *fp;
4268
4269 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4270 unsigned long tmp;
4271 if (fscanf(fp, "%lu", &tmp) == 1) {
4272 mmap_min_addr = tmp;
4273 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4274 }
4275 fclose(fp);
4276 }
4277 }
4278
4279 /*
4280 * Prepare copy of argv vector for target.
4281 */
4282 target_argc = argc - optind;
4283 target_argv = calloc(target_argc + 1, sizeof (char *));
4284 if (target_argv == NULL) {
4285 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4286 exit(EXIT_FAILURE);
4287 }
4288
4289 /*
4290 * If argv0 is specified (using '-0' switch) we replace
4291 * argv[0] pointer with the given one.
4292 */
4293 i = 0;
4294 if (argv0 != NULL) {
4295 target_argv[i++] = strdup(argv0);
4296 }
4297 for (; i < target_argc; i++) {
4298 target_argv[i] = strdup(argv[optind + i]);
4299 }
4300 target_argv[target_argc] = NULL;
4301
4302 ts = g_new0(TaskState, 1);
4303 init_task_state(ts);
4304 /* build Task State */
4305 ts->info = info;
4306 ts->bprm = &bprm;
4307 cpu->opaque = ts;
4308 task_settid(ts);
4309
4310 execfd = qemu_getauxval(AT_EXECFD);
4311 if (execfd == 0) {
4312 execfd = open(filename, O_RDONLY);
4313 if (execfd < 0) {
4314 printf("Error while loading %s: %s\n", filename, strerror(errno));
4315 _exit(EXIT_FAILURE);
4316 }
4317 }
4318
4319 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4320 info, &bprm);
4321 if (ret != 0) {
4322 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4323 _exit(EXIT_FAILURE);
4324 }
4325
4326 for (wrk = target_environ; *wrk; wrk++) {
4327 free(*wrk);
4328 }
4329
4330 free(target_environ);
4331
4332 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4333 qemu_log("guest_base 0x%lx\n", guest_base);
4334 log_page_dump();
4335
4336 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4337 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4338 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4339 info->start_code);
4340 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4341 info->start_data);
4342 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4343 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4344 info->start_stack);
4345 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4346 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4347 }
4348
4349 target_set_brk(info->brk);
4350 syscall_init();
4351 signal_init();
4352
4353 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4354 generating the prologue until now so that the prologue can take
4355 the real value of GUEST_BASE into account. */
4356 tcg_prologue_init(&tcg_ctx);
4357
4358 #if defined(TARGET_I386)
4359 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4360 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4361 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4362 env->cr[4] |= CR4_OSFXSR_MASK;
4363 env->hflags |= HF_OSFXSR_MASK;
4364 }
4365 #ifndef TARGET_ABI32
4366 /* enable 64 bit mode if possible */
4367 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4368 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4369 exit(EXIT_FAILURE);
4370 }
4371 env->cr[4] |= CR4_PAE_MASK;
4372 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4373 env->hflags |= HF_LMA_MASK;
4374 #endif
4375
4376 /* flags setup : we activate the IRQs by default as in user mode */
4377 env->eflags |= IF_MASK;
4378
4379 /* linux register setup */
4380 #ifndef TARGET_ABI32
4381 env->regs[R_EAX] = regs->rax;
4382 env->regs[R_EBX] = regs->rbx;
4383 env->regs[R_ECX] = regs->rcx;
4384 env->regs[R_EDX] = regs->rdx;
4385 env->regs[R_ESI] = regs->rsi;
4386 env->regs[R_EDI] = regs->rdi;
4387 env->regs[R_EBP] = regs->rbp;
4388 env->regs[R_ESP] = regs->rsp;
4389 env->eip = regs->rip;
4390 #else
4391 env->regs[R_EAX] = regs->eax;
4392 env->regs[R_EBX] = regs->ebx;
4393 env->regs[R_ECX] = regs->ecx;
4394 env->regs[R_EDX] = regs->edx;
4395 env->regs[R_ESI] = regs->esi;
4396 env->regs[R_EDI] = regs->edi;
4397 env->regs[R_EBP] = regs->ebp;
4398 env->regs[R_ESP] = regs->esp;
4399 env->eip = regs->eip;
4400 #endif
4401
4402 /* linux interrupt setup */
4403 #ifndef TARGET_ABI32
4404 env->idt.limit = 511;
4405 #else
4406 env->idt.limit = 255;
4407 #endif
4408 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4409 PROT_READ|PROT_WRITE,
4410 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4411 idt_table = g2h(env->idt.base);
4412 set_idt(0, 0);
4413 set_idt(1, 0);
4414 set_idt(2, 0);
4415 set_idt(3, 3);
4416 set_idt(4, 3);
4417 set_idt(5, 0);
4418 set_idt(6, 0);
4419 set_idt(7, 0);
4420 set_idt(8, 0);
4421 set_idt(9, 0);
4422 set_idt(10, 0);
4423 set_idt(11, 0);
4424 set_idt(12, 0);
4425 set_idt(13, 0);
4426 set_idt(14, 0);
4427 set_idt(15, 0);
4428 set_idt(16, 0);
4429 set_idt(17, 0);
4430 set_idt(18, 0);
4431 set_idt(19, 0);
4432 set_idt(0x80, 3);
4433
4434 /* linux segment setup */
4435 {
4436 uint64_t *gdt_table;
4437 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4438 PROT_READ|PROT_WRITE,
4439 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4440 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4441 gdt_table = g2h(env->gdt.base);
4442 #ifdef TARGET_ABI32
4443 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4444 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4445 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4446 #else
4447 /* 64 bit code segment */
4448 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4449 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4450 DESC_L_MASK |
4451 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4452 #endif
4453 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4454 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4455 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4456 }
4457 cpu_x86_load_seg(env, R_CS, __USER_CS);
4458 cpu_x86_load_seg(env, R_SS, __USER_DS);
4459 #ifdef TARGET_ABI32
4460 cpu_x86_load_seg(env, R_DS, __USER_DS);
4461 cpu_x86_load_seg(env, R_ES, __USER_DS);
4462 cpu_x86_load_seg(env, R_FS, __USER_DS);
4463 cpu_x86_load_seg(env, R_GS, __USER_DS);
4464 /* This hack makes Wine work... */
4465 env->segs[R_FS].selector = 0;
4466 #else
4467 cpu_x86_load_seg(env, R_DS, 0);
4468 cpu_x86_load_seg(env, R_ES, 0);
4469 cpu_x86_load_seg(env, R_FS, 0);
4470 cpu_x86_load_seg(env, R_GS, 0);
4471 #endif
4472 #elif defined(TARGET_AARCH64)
4473 {
4474 int i;
4475
4476 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4477 fprintf(stderr,
4478 "The selected ARM CPU does not support 64 bit mode\n");
4479 exit(EXIT_FAILURE);
4480 }
4481
4482 for (i = 0; i < 31; i++) {
4483 env->xregs[i] = regs->regs[i];
4484 }
4485 env->pc = regs->pc;
4486 env->xregs[31] = regs->sp;
4487 }
4488 #elif defined(TARGET_ARM)
4489 {
4490 int i;
4491 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4492 CPSRWriteByInstr);
4493 for(i = 0; i < 16; i++) {
4494 env->regs[i] = regs->uregs[i];
4495 }
4496 #ifdef TARGET_WORDS_BIGENDIAN
4497 /* Enable BE8. */
4498 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4499 && (info->elf_flags & EF_ARM_BE8)) {
4500 env->uncached_cpsr |= CPSR_E;
4501 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4502 } else {
4503 env->cp15.sctlr_el[1] |= SCTLR_B;
4504 }
4505 #endif
4506 }
4507 #elif defined(TARGET_UNICORE32)
4508 {
4509 int i;
4510 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4511 for (i = 0; i < 32; i++) {
4512 env->regs[i] = regs->uregs[i];
4513 }
4514 }
4515 #elif defined(TARGET_SPARC)
4516 {
4517 int i;
4518 env->pc = regs->pc;
4519 env->npc = regs->npc;
4520 env->y = regs->y;
4521 for(i = 0; i < 8; i++)
4522 env->gregs[i] = regs->u_regs[i];
4523 for(i = 0; i < 8; i++)
4524 env->regwptr[i] = regs->u_regs[i + 8];
4525 }
4526 #elif defined(TARGET_PPC)
4527 {
4528 int i;
4529
4530 #if defined(TARGET_PPC64)
4531 #if defined(TARGET_ABI32)
4532 env->msr &= ~((target_ulong)1 << MSR_SF);
4533 #else
4534 env->msr |= (target_ulong)1 << MSR_SF;
4535 #endif
4536 #endif
4537 env->nip = regs->nip;
4538 for(i = 0; i < 32; i++) {
4539 env->gpr[i] = regs->gpr[i];
4540 }
4541 }
4542 #elif defined(TARGET_M68K)
4543 {
4544 env->pc = regs->pc;
4545 env->dregs[0] = regs->d0;
4546 env->dregs[1] = regs->d1;
4547 env->dregs[2] = regs->d2;
4548 env->dregs[3] = regs->d3;
4549 env->dregs[4] = regs->d4;
4550 env->dregs[5] = regs->d5;
4551 env->dregs[6] = regs->d6;
4552 env->dregs[7] = regs->d7;
4553 env->aregs[0] = regs->a0;
4554 env->aregs[1] = regs->a1;
4555 env->aregs[2] = regs->a2;
4556 env->aregs[3] = regs->a3;
4557 env->aregs[4] = regs->a4;
4558 env->aregs[5] = regs->a5;
4559 env->aregs[6] = regs->a6;
4560 env->aregs[7] = regs->usp;
4561 env->sr = regs->sr;
4562 ts->sim_syscalls = 1;
4563 }
4564 #elif defined(TARGET_MICROBLAZE)
4565 {
4566 env->regs[0] = regs->r0;
4567 env->regs[1] = regs->r1;
4568 env->regs[2] = regs->r2;
4569 env->regs[3] = regs->r3;
4570 env->regs[4] = regs->r4;
4571 env->regs[5] = regs->r5;
4572 env->regs[6] = regs->r6;
4573 env->regs[7] = regs->r7;
4574 env->regs[8] = regs->r8;
4575 env->regs[9] = regs->r9;
4576 env->regs[10] = regs->r10;
4577 env->regs[11] = regs->r11;
4578 env->regs[12] = regs->r12;
4579 env->regs[13] = regs->r13;
4580 env->regs[14] = regs->r14;
4581 env->regs[15] = regs->r15;
4582 env->regs[16] = regs->r16;
4583 env->regs[17] = regs->r17;
4584 env->regs[18] = regs->r18;
4585 env->regs[19] = regs->r19;
4586 env->regs[20] = regs->r20;
4587 env->regs[21] = regs->r21;
4588 env->regs[22] = regs->r22;
4589 env->regs[23] = regs->r23;
4590 env->regs[24] = regs->r24;
4591 env->regs[25] = regs->r25;
4592 env->regs[26] = regs->r26;
4593 env->regs[27] = regs->r27;
4594 env->regs[28] = regs->r28;
4595 env->regs[29] = regs->r29;
4596 env->regs[30] = regs->r30;
4597 env->regs[31] = regs->r31;
4598 env->sregs[SR_PC] = regs->pc;
4599 }
4600 #elif defined(TARGET_MIPS)
4601 {
4602 int i;
4603
4604 for(i = 0; i < 32; i++) {
4605 env->active_tc.gpr[i] = regs->regs[i];
4606 }
4607 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4608 if (regs->cp0_epc & 1) {
4609 env->hflags |= MIPS_HFLAG_M16;
4610 }
4611 }
4612 #elif defined(TARGET_OPENRISC)
4613 {
4614 int i;
4615
4616 for (i = 0; i < 32; i++) {
4617 env->gpr[i] = regs->gpr[i];
4618 }
4619
4620 env->sr = regs->sr;
4621 env->pc = regs->pc;
4622 }
4623 #elif defined(TARGET_SH4)
4624 {
4625 int i;
4626
4627 for(i = 0; i < 16; i++) {
4628 env->gregs[i] = regs->regs[i];
4629 }
4630 env->pc = regs->pc;
4631 }
4632 #elif defined(TARGET_ALPHA)
4633 {
4634 int i;
4635
4636 for(i = 0; i < 28; i++) {
4637 env->ir[i] = ((abi_ulong *)regs)[i];
4638 }
4639 env->ir[IR_SP] = regs->usp;
4640 env->pc = regs->pc;
4641 }
4642 #elif defined(TARGET_CRIS)
4643 {
4644 env->regs[0] = regs->r0;
4645 env->regs[1] = regs->r1;
4646 env->regs[2] = regs->r2;
4647 env->regs[3] = regs->r3;
4648 env->regs[4] = regs->r4;
4649 env->regs[5] = regs->r5;
4650 env->regs[6] = regs->r6;
4651 env->regs[7] = regs->r7;
4652 env->regs[8] = regs->r8;
4653 env->regs[9] = regs->r9;
4654 env->regs[10] = regs->r10;
4655 env->regs[11] = regs->r11;
4656 env->regs[12] = regs->r12;
4657 env->regs[13] = regs->r13;
4658 env->regs[14] = info->start_stack;
4659 env->regs[15] = regs->acr;
4660 env->pc = regs->erp;
4661 }
4662 #elif defined(TARGET_S390X)
4663 {
4664 int i;
4665 for (i = 0; i < 16; i++) {
4666 env->regs[i] = regs->gprs[i];
4667 }
4668 env->psw.mask = regs->psw.mask;
4669 env->psw.addr = regs->psw.addr;
4670 }
4671 #elif defined(TARGET_TILEGX)
4672 {
4673 int i;
4674 for (i = 0; i < TILEGX_R_COUNT; i++) {
4675 env->regs[i] = regs->regs[i];
4676 }
4677 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4678 env->spregs[i] = 0;
4679 }
4680 env->pc = regs->pc;
4681 }
4682 #else
4683 #error unsupported target CPU
4684 #endif
4685
4686 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4687 ts->stack_base = info->start_stack;
4688 ts->heap_base = info->brk;
4689 /* This will be filled in on the first SYS_HEAPINFO call. */
4690 ts->heap_limit = 0;
4691 #endif
4692
4693 if (gdbstub_port) {
4694 if (gdbserver_start(gdbstub_port) < 0) {
4695 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4696 gdbstub_port);
4697 exit(EXIT_FAILURE);
4698 }
4699 gdb_handlesig(cpu, 0);
4700 }
4701 cpu_loop(env);
4702 /* never exits */
4703 return 0;
4704 }
QEmu