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pci: Free the space allocated for the option rom on removal
[qemu.git] / hw / pci.c
bloba7ff5668a717434108daba628a559a6d9b3327bc
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29 #include "loader.h"
30 #include "qemu-objects.h"
31
32 //#define DEBUG_PCI
33 #ifdef DEBUG_PCI
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
35 #else
36 # define PCI_DPRINTF(format, ...) do { } while (0)
37 #endif
38
39 struct PCIBus {
40 BusState qbus;
41 int devfn_min;
42 pci_set_irq_fn set_irq;
43 pci_map_irq_fn map_irq;
44 pci_hotplug_fn hotplug;
45 DeviceState *hotplug_qdev;
46 void *irq_opaque;
47 PCIDevice *devices[256];
48 PCIDevice *parent_dev;
49 target_phys_addr_t mem_base;
50
51 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
52 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
53
54 /* The bus IRQ state is the logical OR of the connected devices.
55 Keep a count of the number of devices with raised IRQs. */
56 int nirq;
57 int *irq_count;
58 };
59
60 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
61 static char *pcibus_get_dev_path(DeviceState *dev);
62
63 static struct BusInfo pci_bus_info = {
64 .name = "PCI",
65 .size = sizeof(PCIBus),
66 .print_dev = pcibus_dev_print,
67 .get_dev_path = pcibus_get_dev_path,
68 .props = (Property[]) {
69 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
70 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
71 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
72 DEFINE_PROP_END_OF_LIST()
73 }
74 };
75
76 static void pci_update_mappings(PCIDevice *d);
77 static void pci_set_irq(void *opaque, int irq_num, int level);
78 static int pci_add_option_rom(PCIDevice *pdev);
79 static void pci_del_option_rom(PCIDevice *pdev);
80
81 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
82 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
83
84 struct PCIHostBus {
85 int domain;
86 struct PCIBus *bus;
87 QLIST_ENTRY(PCIHostBus) next;
88 };
89 static QLIST_HEAD(, PCIHostBus) host_buses;
90
91 static const VMStateDescription vmstate_pcibus = {
92 .name = "PCIBUS",
93 .version_id = 1,
94 .minimum_version_id = 1,
95 .minimum_version_id_old = 1,
96 .fields = (VMStateField []) {
97 VMSTATE_INT32_EQUAL(nirq, PCIBus),
98 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
99 VMSTATE_END_OF_LIST()
100 }
101 };
102
103 static int pci_bar(PCIDevice *d, int reg)
104 {
105 uint8_t type;
106
107 if (reg != PCI_ROM_SLOT)
108 return PCI_BASE_ADDRESS_0 + reg * 4;
109
110 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
111 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
112 }
113
114 static inline int pci_irq_state(PCIDevice *d, int irq_num)
115 {
116 return (d->irq_state >> irq_num) & 0x1;
117 }
118
119 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
120 {
121 d->irq_state &= ~(0x1 << irq_num);
122 d->irq_state |= level << irq_num;
123 }
124
125 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
126 {
127 PCIBus *bus;
128 for (;;) {
129 bus = pci_dev->bus;
130 irq_num = bus->map_irq(pci_dev, irq_num);
131 if (bus->set_irq)
132 break;
133 pci_dev = bus->parent_dev;
134 }
135 bus->irq_count[irq_num] += change;
136 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
137 }
138
139 /* Update interrupt status bit in config space on interrupt
140 * state change. */
141 static void pci_update_irq_status(PCIDevice *dev)
142 {
143 if (dev->irq_state) {
144 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
145 } else {
146 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
147 }
148 }
149
150 static void pci_device_reset(PCIDevice *dev)
151 {
152 int r;
153
154 dev->irq_state = 0;
155 pci_update_irq_status(dev);
156 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
157 PCI_COMMAND_MASTER);
158 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
159 dev->config[PCI_INTERRUPT_LINE] = 0x0;
160 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
161 if (!dev->io_regions[r].size) {
162 continue;
163 }
164 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
165 }
166 pci_update_mappings(dev);
167 }
168
169 static void pci_bus_reset(void *opaque)
170 {
171 PCIBus *bus = opaque;
172 int i;
173
174 for (i = 0; i < bus->nirq; i++) {
175 bus->irq_count[i] = 0;
176 }
177 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
178 if (bus->devices[i]) {
179 pci_device_reset(bus->devices[i]);
180 }
181 }
182 }
183
184 static void pci_host_bus_register(int domain, PCIBus *bus)
185 {
186 struct PCIHostBus *host;
187 host = qemu_mallocz(sizeof(*host));
188 host->domain = domain;
189 host->bus = bus;
190 QLIST_INSERT_HEAD(&host_buses, host, next);
191 }
192
193 PCIBus *pci_find_root_bus(int domain)
194 {
195 struct PCIHostBus *host;
196
197 QLIST_FOREACH(host, &host_buses, next) {
198 if (host->domain == domain) {
199 return host->bus;
200 }
201 }
202
203 return NULL;
204 }
205
206 int pci_find_domain(const PCIBus *bus)
207 {
208 PCIDevice *d;
209 struct PCIHostBus *host;
210
211 /* obtain root bus */
212 while ((d = bus->parent_dev) != NULL) {
213 bus = d->bus;
214 }
215
216 QLIST_FOREACH(host, &host_buses, next) {
217 if (host->bus == bus) {
218 return host->domain;
219 }
220 }
221
222 abort(); /* should not be reached */
223 return -1;
224 }
225
226 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
227 const char *name, int devfn_min)
228 {
229 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
230 bus->devfn_min = devfn_min;
231
232 /* host bridge */
233 QLIST_INIT(&bus->child);
234 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
235
236 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
237 qemu_register_reset(pci_bus_reset, bus);
238 }
239
240 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
241 {
242 PCIBus *bus;
243
244 bus = qemu_mallocz(sizeof(*bus));
245 bus->qbus.qdev_allocated = 1;
246 pci_bus_new_inplace(bus, parent, name, devfn_min);
247 return bus;
248 }
249
250 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
251 void *irq_opaque, int nirq)
252 {
253 bus->set_irq = set_irq;
254 bus->map_irq = map_irq;
255 bus->irq_opaque = irq_opaque;
256 bus->nirq = nirq;
257 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
258 }
259
260 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
261 {
262 bus->qbus.allow_hotplug = 1;
263 bus->hotplug = hotplug;
264 bus->hotplug_qdev = qdev;
265 }
266
267 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
268 {
269 bus->mem_base = base;
270 }
271
272 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
273 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
274 void *irq_opaque, int devfn_min, int nirq)
275 {
276 PCIBus *bus;
277
278 bus = pci_bus_new(parent, name, devfn_min);
279 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
280 return bus;
281 }
282
283 static void pci_register_secondary_bus(PCIBus *parent,
284 PCIBus *bus,
285 PCIDevice *dev,
286 pci_map_irq_fn map_irq,
287 const char *name)
288 {
289 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
290 bus->map_irq = map_irq;
291 bus->parent_dev = dev;
292
293 QLIST_INIT(&bus->child);
294 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
295 }
296
297 static void pci_unregister_secondary_bus(PCIBus *bus)
298 {
299 assert(QLIST_EMPTY(&bus->child));
300 QLIST_REMOVE(bus, sibling);
301 }
302
303 int pci_bus_num(PCIBus *s)
304 {
305 if (!s->parent_dev)
306 return 0; /* pci host bridge */
307 return s->parent_dev->config[PCI_SECONDARY_BUS];
308 }
309
310 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
311 {
312 PCIDevice *s = container_of(pv, PCIDevice, config);
313 uint8_t *config;
314 int i;
315
316 assert(size == pci_config_size(s));
317 config = qemu_malloc(size);
318
319 qemu_get_buffer(f, config, size);
320 for (i = 0; i < size; ++i) {
321 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
322 qemu_free(config);
323 return -EINVAL;
324 }
325 }
326 memcpy(s->config, config, size);
327
328 pci_update_mappings(s);
329
330 qemu_free(config);
331 return 0;
332 }
333
334 /* just put buffer */
335 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
336 {
337 const uint8_t **v = pv;
338 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
339 qemu_put_buffer(f, *v, size);
340 }
341
342 static VMStateInfo vmstate_info_pci_config = {
343 .name = "pci config",
344 .get = get_pci_config_device,
345 .put = put_pci_config_device,
346 };
347
348 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
349 {
350 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
351 uint32_t irq_state[PCI_NUM_PINS];
352 int i;
353 for (i = 0; i < PCI_NUM_PINS; ++i) {
354 irq_state[i] = qemu_get_be32(f);
355 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
356 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
357 irq_state[i]);
358 return -EINVAL;
359 }
360 }
361
362 for (i = 0; i < PCI_NUM_PINS; ++i) {
363 pci_set_irq_state(s, i, irq_state[i]);
364 }
365
366 return 0;
367 }
368
369 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
370 {
371 int i;
372 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
373
374 for (i = 0; i < PCI_NUM_PINS; ++i) {
375 qemu_put_be32(f, pci_irq_state(s, i));
376 }
377 }
378
379 static VMStateInfo vmstate_info_pci_irq_state = {
380 .name = "pci irq state",
381 .get = get_pci_irq_state,
382 .put = put_pci_irq_state,
383 };
384
385 const VMStateDescription vmstate_pci_device = {
386 .name = "PCIDevice",
387 .version_id = 2,
388 .minimum_version_id = 1,
389 .minimum_version_id_old = 1,
390 .fields = (VMStateField []) {
391 VMSTATE_INT32_LE(version_id, PCIDevice),
392 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
393 vmstate_info_pci_config,
394 PCI_CONFIG_SPACE_SIZE),
395 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
396 vmstate_info_pci_irq_state,
397 PCI_NUM_PINS * sizeof(int32_t)),
398 VMSTATE_END_OF_LIST()
399 }
400 };
401
402 const VMStateDescription vmstate_pcie_device = {
403 .name = "PCIDevice",
404 .version_id = 2,
405 .minimum_version_id = 1,
406 .minimum_version_id_old = 1,
407 .fields = (VMStateField []) {
408 VMSTATE_INT32_LE(version_id, PCIDevice),
409 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
410 vmstate_info_pci_config,
411 PCIE_CONFIG_SPACE_SIZE),
412 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
413 vmstate_info_pci_irq_state,
414 PCI_NUM_PINS * sizeof(int32_t)),
415 VMSTATE_END_OF_LIST()
416 }
417 };
418
419 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
420 {
421 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
422 }
423
424 void pci_device_save(PCIDevice *s, QEMUFile *f)
425 {
426 /* Clear interrupt status bit: it is implicit
427 * in irq_state which we are saving.
428 * This makes us compatible with old devices
429 * which never set or clear this bit. */
430 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
431 vmstate_save_state(f, pci_get_vmstate(s), s);
432 /* Restore the interrupt status bit. */
433 pci_update_irq_status(s);
434 }
435
436 int pci_device_load(PCIDevice *s, QEMUFile *f)
437 {
438 int ret;
439 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
440 /* Restore the interrupt status bit. */
441 pci_update_irq_status(s);
442 return ret;
443 }
444
445 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
446 {
447 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
448 pci_default_sub_vendor_id);
449 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
450 pci_default_sub_device_id);
451 }
452
453 /*
454 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
455 */
456 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
457 {
458 const char *p;
459 char *e;
460 unsigned long val;
461 unsigned long dom = 0, bus = 0;
462 unsigned slot = 0;
463
464 p = addr;
465 val = strtoul(p, &e, 16);
466 if (e == p)
467 return -1;
468 if (*e == ':') {
469 bus = val;
470 p = e + 1;
471 val = strtoul(p, &e, 16);
472 if (e == p)
473 return -1;
474 if (*e == ':') {
475 dom = bus;
476 bus = val;
477 p = e + 1;
478 val = strtoul(p, &e, 16);
479 if (e == p)
480 return -1;
481 }
482 }
483
484 if (dom > 0xffff || bus > 0xff || val > 0x1f)
485 return -1;
486
487 slot = val;
488
489 if (*e)
490 return -1;
491
492 /* Note: QEMU doesn't implement domains other than 0 */
493 if (!pci_find_bus(pci_find_root_bus(dom), bus))
494 return -1;
495
496 *domp = dom;
497 *busp = bus;
498 *slotp = slot;
499 return 0;
500 }
501
502 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
503 unsigned *slotp)
504 {
505 /* strip legacy tag */
506 if (!strncmp(addr, "pci_addr=", 9)) {
507 addr += 9;
508 }
509 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
510 monitor_printf(mon, "Invalid pci address\n");
511 return -1;
512 }
513 return 0;
514 }
515
516 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
517 {
518 int dom, bus;
519 unsigned slot;
520
521 if (!devaddr) {
522 *devfnp = -1;
523 return pci_find_bus(pci_find_root_bus(0), 0);
524 }
525
526 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
527 return NULL;
528 }
529
530 *devfnp = slot << 3;
531 return pci_find_bus(pci_find_root_bus(dom), bus);
532 }
533
534 static void pci_init_cmask(PCIDevice *dev)
535 {
536 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
537 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
538 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
539 dev->cmask[PCI_REVISION_ID] = 0xff;
540 dev->cmask[PCI_CLASS_PROG] = 0xff;
541 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
542 dev->cmask[PCI_HEADER_TYPE] = 0xff;
543 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
544 }
545
546 static void pci_init_wmask(PCIDevice *dev)
547 {
548 int config_size = pci_config_size(dev);
549
550 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
551 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
552 pci_set_word(dev->wmask + PCI_COMMAND,
553 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
554 PCI_COMMAND_INTX_DISABLE);
555
556 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
557 config_size - PCI_CONFIG_HEADER_SIZE);
558 }
559
560 static void pci_init_wmask_bridge(PCIDevice *d)
561 {
562 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
563 PCI_SEC_LETENCY_TIMER */
564 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
565
566 /* base and limit */
567 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
568 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
569 pci_set_word(d->wmask + PCI_MEMORY_BASE,
570 PCI_MEMORY_RANGE_MASK & 0xffff);
571 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
572 PCI_MEMORY_RANGE_MASK & 0xffff);
573 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
574 PCI_PREF_RANGE_MASK & 0xffff);
575 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
576 PCI_PREF_RANGE_MASK & 0xffff);
577
578 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
579 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
580
581 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
582 }
583
584 static void pci_config_alloc(PCIDevice *pci_dev)
585 {
586 int config_size = pci_config_size(pci_dev);
587
588 pci_dev->config = qemu_mallocz(config_size);
589 pci_dev->cmask = qemu_mallocz(config_size);
590 pci_dev->wmask = qemu_mallocz(config_size);
591 pci_dev->used = qemu_mallocz(config_size);
592 }
593
594 static void pci_config_free(PCIDevice *pci_dev)
595 {
596 qemu_free(pci_dev->config);
597 qemu_free(pci_dev->cmask);
598 qemu_free(pci_dev->wmask);
599 qemu_free(pci_dev->used);
600 }
601
602 /* -1 for devfn means auto assign */
603 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
604 const char *name, int devfn,
605 PCIConfigReadFunc *config_read,
606 PCIConfigWriteFunc *config_write,
607 uint8_t header_type)
608 {
609 if (devfn < 0) {
610 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
611 devfn += 8) {
612 if (!bus->devices[devfn])
613 goto found;
614 }
615 error_report("PCI: no slot/function available for %s, all in use", name);
616 return NULL;
617 found: ;
618 } else if (bus->devices[devfn]) {
619 error_report("PCI: slot %d function %d not available for %s, in use by %s",
620 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
621 return NULL;
622 }
623 pci_dev->bus = bus;
624 pci_dev->devfn = devfn;
625 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
626 pci_dev->irq_state = 0;
627 pci_config_alloc(pci_dev);
628
629 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
630 if (header_type == PCI_HEADER_TYPE_NORMAL) {
631 pci_set_default_subsystem_id(pci_dev);
632 }
633 pci_init_cmask(pci_dev);
634 pci_init_wmask(pci_dev);
635 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
636 pci_init_wmask_bridge(pci_dev);
637 }
638
639 if (!config_read)
640 config_read = pci_default_read_config;
641 if (!config_write)
642 config_write = pci_default_write_config;
643 pci_dev->config_read = config_read;
644 pci_dev->config_write = config_write;
645 bus->devices[devfn] = pci_dev;
646 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
647 pci_dev->version_id = 2; /* Current pci device vmstate version */
648 return pci_dev;
649 }
650
651 static void do_pci_unregister_device(PCIDevice *pci_dev)
652 {
653 qemu_free_irqs(pci_dev->irq);
654 pci_dev->bus->devices[pci_dev->devfn] = NULL;
655 pci_config_free(pci_dev);
656 }
657
658 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
659 int instance_size, int devfn,
660 PCIConfigReadFunc *config_read,
661 PCIConfigWriteFunc *config_write)
662 {
663 PCIDevice *pci_dev;
664
665 pci_dev = qemu_mallocz(instance_size);
666 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
667 config_read, config_write,
668 PCI_HEADER_TYPE_NORMAL);
669 if (pci_dev == NULL) {
670 hw_error("PCI: can't register device\n");
671 }
672 return pci_dev;
673 }
674
675 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
676 target_phys_addr_t addr)
677 {
678 return addr + bus->mem_base;
679 }
680
681 static void pci_unregister_io_regions(PCIDevice *pci_dev)
682 {
683 PCIIORegion *r;
684 int i;
685
686 for(i = 0; i < PCI_NUM_REGIONS; i++) {
687 r = &pci_dev->io_regions[i];
688 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
689 continue;
690 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
691 isa_unassign_ioport(r->addr, r->filtered_size);
692 } else {
693 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
694 r->addr),
695 r->filtered_size,
696 IO_MEM_UNASSIGNED);
697 }
698 }
699 }
700
701 static int pci_unregister_device(DeviceState *dev)
702 {
703 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
704 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
705 int ret = 0;
706
707 if (info->exit)
708 ret = info->exit(pci_dev);
709 if (ret)
710 return ret;
711
712 pci_unregister_io_regions(pci_dev);
713 pci_del_option_rom(pci_dev);
714 do_pci_unregister_device(pci_dev);
715 return 0;
716 }
717
718 void pci_register_bar(PCIDevice *pci_dev, int region_num,
719 pcibus_t size, int type,
720 PCIMapIORegionFunc *map_func)
721 {
722 PCIIORegion *r;
723 uint32_t addr;
724 pcibus_t wmask;
725
726 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
727 return;
728
729 if (size & (size-1)) {
730 fprintf(stderr, "ERROR: PCI region size must be pow2 "
731 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
732 exit(1);
733 }
734
735 r = &pci_dev->io_regions[region_num];
736 r->addr = PCI_BAR_UNMAPPED;
737 r->size = size;
738 r->filtered_size = size;
739 r->type = type;
740 r->map_func = map_func;
741
742 wmask = ~(size - 1);
743 addr = pci_bar(pci_dev, region_num);
744 if (region_num == PCI_ROM_SLOT) {
745 /* ROM enable bit is writeable */
746 wmask |= PCI_ROM_ADDRESS_ENABLE;
747 }
748 pci_set_long(pci_dev->config + addr, type);
749 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
750 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
751 pci_set_quad(pci_dev->wmask + addr, wmask);
752 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
753 } else {
754 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
755 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
756 }
757 }
758
759 static uint32_t pci_config_get_io_base(PCIDevice *d,
760 uint32_t base, uint32_t base_upper16)
761 {
762 uint32_t val;
763
764 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
765 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
766 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
767 }
768 return val;
769 }
770
771 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
772 {
773 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
774 << 16;
775 }
776
777 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
778 uint32_t base, uint32_t upper)
779 {
780 pcibus_t tmp;
781 pcibus_t val;
782
783 tmp = (pcibus_t)pci_get_word(d->config + base);
784 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
785 if (tmp & PCI_PREF_RANGE_TYPE_64) {
786 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
787 }
788 return val;
789 }
790
791 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
792 {
793 pcibus_t base;
794 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
795 base = pci_config_get_io_base(bridge,
796 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
797 } else {
798 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
799 base = pci_config_get_pref_base(
800 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
801 } else {
802 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
803 }
804 }
805
806 return base;
807 }
808
809 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
810 {
811 pcibus_t limit;
812 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
813 limit = pci_config_get_io_base(bridge,
814 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
815 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
816 } else {
817 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
818 limit = pci_config_get_pref_base(
819 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
820 } else {
821 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
822 }
823 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
824 }
825 return limit;
826 }
827
828 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
829 uint8_t type)
830 {
831 pcibus_t base = *addr;
832 pcibus_t limit = *addr + *size - 1;
833 PCIDevice *br;
834
835 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
836 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
837
838 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
839 if (!(cmd & PCI_COMMAND_IO)) {
840 goto no_map;
841 }
842 } else {
843 if (!(cmd & PCI_COMMAND_MEMORY)) {
844 goto no_map;
845 }
846 }
847
848 base = MAX(base, pci_bridge_get_base(br, type));
849 limit = MIN(limit, pci_bridge_get_limit(br, type));
850 }
851
852 if (base > limit) {
853 goto no_map;
854 }
855 *addr = base;
856 *size = limit - base + 1;
857 return;
858 no_map:
859 *addr = PCI_BAR_UNMAPPED;
860 *size = 0;
861 }
862
863 static pcibus_t pci_bar_address(PCIDevice *d,
864 int reg, uint8_t type, pcibus_t size)
865 {
866 pcibus_t new_addr, last_addr;
867 int bar = pci_bar(d, reg);
868 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
869
870 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
871 if (!(cmd & PCI_COMMAND_IO)) {
872 return PCI_BAR_UNMAPPED;
873 }
874 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
875 last_addr = new_addr + size - 1;
876 /* NOTE: we have only 64K ioports on PC */
877 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
878 return PCI_BAR_UNMAPPED;
879 }
880 return new_addr;
881 }
882
883 if (!(cmd & PCI_COMMAND_MEMORY)) {
884 return PCI_BAR_UNMAPPED;
885 }
886 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
887 new_addr = pci_get_quad(d->config + bar);
888 } else {
889 new_addr = pci_get_long(d->config + bar);
890 }
891 /* the ROM slot has a specific enable bit */
892 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
893 return PCI_BAR_UNMAPPED;
894 }
895 new_addr &= ~(size - 1);
896 last_addr = new_addr + size - 1;
897 /* NOTE: we do not support wrapping */
898 /* XXX: as we cannot support really dynamic
899 mappings, we handle specific values as invalid
900 mappings. */
901 if (last_addr <= new_addr || new_addr == 0 ||
902 last_addr == PCI_BAR_UNMAPPED) {
903 return PCI_BAR_UNMAPPED;
904 }
905
906 /* Now pcibus_t is 64bit.
907 * Check if 32 bit BAR wraps around explicitly.
908 * Without this, PC ide doesn't work well.
909 * TODO: remove this work around.
910 */
911 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
912 return PCI_BAR_UNMAPPED;
913 }
914
915 /*
916 * OS is allowed to set BAR beyond its addressable
917 * bits. For example, 32 bit OS can set 64bit bar
918 * to >4G. Check it. TODO: we might need to support
919 * it in the future for e.g. PAE.
920 */
921 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
922 return PCI_BAR_UNMAPPED;
923 }
924
925 return new_addr;
926 }
927
928 static void pci_update_mappings(PCIDevice *d)
929 {
930 PCIIORegion *r;
931 int i;
932 pcibus_t new_addr, filtered_size;
933
934 for(i = 0; i < PCI_NUM_REGIONS; i++) {
935 r = &d->io_regions[i];
936
937 /* this region isn't registered */
938 if (!r->size)
939 continue;
940
941 new_addr = pci_bar_address(d, i, r->type, r->size);
942
943 /* bridge filtering */
944 filtered_size = r->size;
945 if (new_addr != PCI_BAR_UNMAPPED) {
946 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
947 }
948
949 /* This bar isn't changed */
950 if (new_addr == r->addr && filtered_size == r->filtered_size)
951 continue;
952
953 /* now do the real mapping */
954 if (r->addr != PCI_BAR_UNMAPPED) {
955 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
956 int class;
957 /* NOTE: specific hack for IDE in PC case:
958 only one byte must be mapped. */
959 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
960 if (class == 0x0101 && r->size == 4) {
961 isa_unassign_ioport(r->addr + 2, 1);
962 } else {
963 isa_unassign_ioport(r->addr, r->filtered_size);
964 }
965 } else {
966 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
967 r->filtered_size,
968 IO_MEM_UNASSIGNED);
969 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
970 }
971 }
972 r->addr = new_addr;
973 r->filtered_size = filtered_size;
974 if (r->addr != PCI_BAR_UNMAPPED) {
975 /*
976 * TODO: currently almost all the map funcions assumes
977 * filtered_size == size and addr & ~(size - 1) == addr.
978 * However with bridge filtering, they aren't always true.
979 * Teach them such cases, such that filtered_size < size and
980 * addr & (size - 1) != 0.
981 */
982 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
983 r->map_func(d, i, r->addr, r->filtered_size, r->type);
984 } else {
985 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
986 r->filtered_size, r->type);
987 }
988 }
989 }
990 }
991
992 static inline int pci_irq_disabled(PCIDevice *d)
993 {
994 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
995 }
996
997 /* Called after interrupt disabled field update in config space,
998 * assert/deassert interrupts if necessary.
999 * Gets original interrupt disable bit value (before update). */
1000 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1001 {
1002 int i, disabled = pci_irq_disabled(d);
1003 if (disabled == was_irq_disabled)
1004 return;
1005 for (i = 0; i < PCI_NUM_PINS; ++i) {
1006 int state = pci_irq_state(d, i);
1007 pci_change_irq_level(d, i, disabled ? -state : state);
1008 }
1009 }
1010
1011 uint32_t pci_default_read_config(PCIDevice *d,
1012 uint32_t address, int len)
1013 {
1014 uint32_t val = 0;
1015 assert(len == 1 || len == 2 || len == 4);
1016 len = MIN(len, pci_config_size(d) - address);
1017 memcpy(&val, d->config + address, len);
1018 return le32_to_cpu(val);
1019 }
1020
1021 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1022 {
1023 int i, was_irq_disabled = pci_irq_disabled(d);
1024 uint32_t config_size = pci_config_size(d);
1025
1026 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1027 uint8_t wmask = d->wmask[addr + i];
1028 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1029 }
1030 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1031 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1032 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1033 range_covers_byte(addr, l, PCI_COMMAND))
1034 pci_update_mappings(d);
1035
1036 if (range_covers_byte(addr, l, PCI_COMMAND))
1037 pci_update_irq_disabled(d, was_irq_disabled);
1038 }
1039
1040 /***********************************************************/
1041 /* generic PCI irq support */
1042
1043 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1044 static void pci_set_irq(void *opaque, int irq_num, int level)
1045 {
1046 PCIDevice *pci_dev = opaque;
1047 int change;
1048
1049 change = level - pci_irq_state(pci_dev, irq_num);
1050 if (!change)
1051 return;
1052
1053 pci_set_irq_state(pci_dev, irq_num, level);
1054 pci_update_irq_status(pci_dev);
1055 if (pci_irq_disabled(pci_dev))
1056 return;
1057 pci_change_irq_level(pci_dev, irq_num, change);
1058 }
1059
1060 /***********************************************************/
1061 /* monitor info on PCI */
1062
1063 typedef struct {
1064 uint16_t class;
1065 const char *desc;
1066 } pci_class_desc;
1067
1068 static const pci_class_desc pci_class_descriptions[] =
1069 {
1070 { 0x0100, "SCSI controller"},
1071 { 0x0101, "IDE controller"},
1072 { 0x0102, "Floppy controller"},
1073 { 0x0103, "IPI controller"},
1074 { 0x0104, "RAID controller"},
1075 { 0x0106, "SATA controller"},
1076 { 0x0107, "SAS controller"},
1077 { 0x0180, "Storage controller"},
1078 { 0x0200, "Ethernet controller"},
1079 { 0x0201, "Token Ring controller"},
1080 { 0x0202, "FDDI controller"},
1081 { 0x0203, "ATM controller"},
1082 { 0x0280, "Network controller"},
1083 { 0x0300, "VGA controller"},
1084 { 0x0301, "XGA controller"},
1085 { 0x0302, "3D controller"},
1086 { 0x0380, "Display controller"},
1087 { 0x0400, "Video controller"},
1088 { 0x0401, "Audio controller"},
1089 { 0x0402, "Phone"},
1090 { 0x0480, "Multimedia controller"},
1091 { 0x0500, "RAM controller"},
1092 { 0x0501, "Flash controller"},
1093 { 0x0580, "Memory controller"},
1094 { 0x0600, "Host bridge"},
1095 { 0x0601, "ISA bridge"},
1096 { 0x0602, "EISA bridge"},
1097 { 0x0603, "MC bridge"},
1098 { 0x0604, "PCI bridge"},
1099 { 0x0605, "PCMCIA bridge"},
1100 { 0x0606, "NUBUS bridge"},
1101 { 0x0607, "CARDBUS bridge"},
1102 { 0x0608, "RACEWAY bridge"},
1103 { 0x0680, "Bridge"},
1104 { 0x0c03, "USB controller"},
1105 { 0, NULL}
1106 };
1107
1108 static void pci_for_each_device_under_bus(PCIBus *bus,
1109 void (*fn)(PCIBus *b, PCIDevice *d))
1110 {
1111 PCIDevice *d;
1112 int devfn;
1113
1114 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1115 d = bus->devices[devfn];
1116 if (d) {
1117 fn(bus, d);
1118 }
1119 }
1120 }
1121
1122 void pci_for_each_device(PCIBus *bus, int bus_num,
1123 void (*fn)(PCIBus *b, PCIDevice *d))
1124 {
1125 bus = pci_find_bus(bus, bus_num);
1126
1127 if (bus) {
1128 pci_for_each_device_under_bus(bus, fn);
1129 }
1130 }
1131
1132 static void pci_device_print(Monitor *mon, QDict *device)
1133 {
1134 QDict *qdict;
1135 QListEntry *entry;
1136 uint64_t addr, size;
1137
1138 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1139 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1140 qdict_get_int(device, "slot"),
1141 qdict_get_int(device, "function"));
1142 monitor_printf(mon, " ");
1143
1144 qdict = qdict_get_qdict(device, "class_info");
1145 if (qdict_haskey(qdict, "desc")) {
1146 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1147 } else {
1148 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1149 }
1150
1151 qdict = qdict_get_qdict(device, "id");
1152 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1153 qdict_get_int(qdict, "device"),
1154 qdict_get_int(qdict, "vendor"));
1155
1156 if (qdict_haskey(device, "irq")) {
1157 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1158 qdict_get_int(device, "irq"));
1159 }
1160
1161 if (qdict_haskey(device, "pci_bridge")) {
1162 QDict *info;
1163
1164 qdict = qdict_get_qdict(device, "pci_bridge");
1165
1166 info = qdict_get_qdict(qdict, "bus");
1167 monitor_printf(mon, " BUS %" PRId64 ".\n",
1168 qdict_get_int(info, "number"));
1169 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1170 qdict_get_int(info, "secondary"));
1171 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1172 qdict_get_int(info, "subordinate"));
1173
1174 info = qdict_get_qdict(qdict, "io_range");
1175 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1176 qdict_get_int(info, "base"),
1177 qdict_get_int(info, "limit"));
1178
1179 info = qdict_get_qdict(qdict, "memory_range");
1180 monitor_printf(mon,
1181 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1182 qdict_get_int(info, "base"),
1183 qdict_get_int(info, "limit"));
1184
1185 info = qdict_get_qdict(qdict, "prefetchable_range");
1186 monitor_printf(mon, " prefetchable memory range "
1187 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1188 qdict_get_int(info, "base"),
1189 qdict_get_int(info, "limit"));
1190 }
1191
1192 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1193 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1194 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1195
1196 addr = qdict_get_int(qdict, "address");
1197 size = qdict_get_int(qdict, "size");
1198
1199 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1200 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1201 " [0x%04"FMT_PCIBUS"].\n",
1202 addr, addr + size - 1);
1203 } else {
1204 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1205 " [0x%08"FMT_PCIBUS"].\n",
1206 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1207 qdict_get_bool(qdict, "prefetch") ?
1208 " prefetchable" : "", addr, addr + size - 1);
1209 }
1210 }
1211
1212 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1213
1214 if (qdict_haskey(device, "pci_bridge")) {
1215 qdict = qdict_get_qdict(device, "pci_bridge");
1216 if (qdict_haskey(qdict, "devices")) {
1217 QListEntry *dev;
1218 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1219 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1220 }
1221 }
1222 }
1223 }
1224
1225 void do_pci_info_print(Monitor *mon, const QObject *data)
1226 {
1227 QListEntry *bus, *dev;
1228
1229 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1230 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1231 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1232 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1233 }
1234 }
1235 }
1236
1237 static QObject *pci_get_dev_class(const PCIDevice *dev)
1238 {
1239 int class;
1240 const pci_class_desc *desc;
1241
1242 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1243 desc = pci_class_descriptions;
1244 while (desc->desc && class != desc->class)
1245 desc++;
1246
1247 if (desc->desc) {
1248 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1249 desc->desc, class);
1250 } else {
1251 return qobject_from_jsonf("{ 'class': %d }", class);
1252 }
1253 }
1254
1255 static QObject *pci_get_dev_id(const PCIDevice *dev)
1256 {
1257 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1258 pci_get_word(dev->config + PCI_VENDOR_ID),
1259 pci_get_word(dev->config + PCI_DEVICE_ID));
1260 }
1261
1262 static QObject *pci_get_regions_list(const PCIDevice *dev)
1263 {
1264 int i;
1265 QList *regions_list;
1266
1267 regions_list = qlist_new();
1268
1269 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1270 QObject *obj;
1271 const PCIIORegion *r = &dev->io_regions[i];
1272
1273 if (!r->size) {
1274 continue;
1275 }
1276
1277 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1278 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1279 "'address': %" PRId64 ", "
1280 "'size': %" PRId64 " }",
1281 i, r->addr, r->size);
1282 } else {
1283 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1284
1285 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1286 "'mem_type_64': %i, 'prefetch': %i, "
1287 "'address': %" PRId64 ", "
1288 "'size': %" PRId64 " }",
1289 i, mem_type_64,
1290 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1291 r->addr, r->size);
1292 }
1293
1294 qlist_append_obj(regions_list, obj);
1295 }
1296
1297 return QOBJECT(regions_list);
1298 }
1299
1300 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1301
1302 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1303 {
1304 uint8_t type;
1305 QObject *obj;
1306
1307 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1308 " 'qdev_id': %s }",
1309 bus_num,
1310 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1311 pci_get_dev_class(dev), pci_get_dev_id(dev),
1312 pci_get_regions_list(dev),
1313 dev->qdev.id ? dev->qdev.id : "");
1314
1315 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1316 QDict *qdict = qobject_to_qdict(obj);
1317 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1318 }
1319
1320 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1321 if (type == PCI_HEADER_TYPE_BRIDGE) {
1322 QDict *qdict;
1323 QObject *pci_bridge;
1324
1325 pci_bridge = qobject_from_jsonf("{ 'bus': "
1326 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1327 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1328 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1329 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1330 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1331 dev->config[PCI_SUBORDINATE_BUS],
1332 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1333 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1334 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1335 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1336 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1337 PCI_BASE_ADDRESS_MEM_PREFETCH),
1338 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1339 PCI_BASE_ADDRESS_MEM_PREFETCH));
1340
1341 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1342 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1343
1344 if (child_bus) {
1345 qdict = qobject_to_qdict(pci_bridge);
1346 qdict_put_obj(qdict, "devices",
1347 pci_get_devices_list(child_bus,
1348 dev->config[PCI_SECONDARY_BUS]));
1349 }
1350 }
1351 qdict = qobject_to_qdict(obj);
1352 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1353 }
1354
1355 return obj;
1356 }
1357
1358 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1359 {
1360 int devfn;
1361 PCIDevice *dev;
1362 QList *dev_list;
1363
1364 dev_list = qlist_new();
1365
1366 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1367 dev = bus->devices[devfn];
1368 if (dev) {
1369 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1370 }
1371 }
1372
1373 return QOBJECT(dev_list);
1374 }
1375
1376 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1377 {
1378 bus = pci_find_bus(bus, bus_num);
1379 if (bus) {
1380 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1381 bus_num, pci_get_devices_list(bus, bus_num));
1382 }
1383
1384 return NULL;
1385 }
1386
1387 void do_pci_info(Monitor *mon, QObject **ret_data)
1388 {
1389 QList *bus_list;
1390 struct PCIHostBus *host;
1391
1392 bus_list = qlist_new();
1393
1394 QLIST_FOREACH(host, &host_buses, next) {
1395 QObject *obj = pci_get_bus_dict(host->bus, 0);
1396 if (obj) {
1397 qlist_append_obj(bus_list, obj);
1398 }
1399 }
1400
1401 *ret_data = QOBJECT(bus_list);
1402 }
1403
1404 static const char * const pci_nic_models[] = {
1405 "ne2k_pci",
1406 "i82551",
1407 "i82557b",
1408 "i82559er",
1409 "rtl8139",
1410 "e1000",
1411 "pcnet",
1412 "virtio",
1413 NULL
1414 };
1415
1416 static const char * const pci_nic_names[] = {
1417 "ne2k_pci",
1418 "i82551",
1419 "i82557b",
1420 "i82559er",
1421 "rtl8139",
1422 "e1000",
1423 "pcnet",
1424 "virtio-net-pci",
1425 NULL
1426 };
1427
1428 /* Initialize a PCI NIC. */
1429 /* FIXME callers should check for failure, but don't */
1430 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1431 const char *default_devaddr)
1432 {
1433 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1434 PCIBus *bus;
1435 int devfn;
1436 PCIDevice *pci_dev;
1437 DeviceState *dev;
1438 int i;
1439
1440 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1441 if (i < 0)
1442 return NULL;
1443
1444 bus = pci_get_bus_devfn(&devfn, devaddr);
1445 if (!bus) {
1446 error_report("Invalid PCI device address %s for device %s",
1447 devaddr, pci_nic_names[i]);
1448 return NULL;
1449 }
1450
1451 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1452 dev = &pci_dev->qdev;
1453 qdev_set_nic_properties(dev, nd);
1454 if (qdev_init(dev) < 0)
1455 return NULL;
1456 return pci_dev;
1457 }
1458
1459 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1460 const char *default_devaddr)
1461 {
1462 PCIDevice *res;
1463
1464 if (qemu_show_nic_models(nd->model, pci_nic_models))
1465 exit(0);
1466
1467 res = pci_nic_init(nd, default_model, default_devaddr);
1468 if (!res)
1469 exit(1);
1470 return res;
1471 }
1472
1473 typedef struct {
1474 PCIDevice dev;
1475 PCIBus bus;
1476 uint32_t vid;
1477 uint32_t did;
1478 } PCIBridge;
1479
1480
1481 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1482 {
1483 pci_update_mappings(d);
1484 }
1485
1486 static void pci_bridge_update_mappings(PCIBus *b)
1487 {
1488 PCIBus *child;
1489
1490 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1491
1492 QLIST_FOREACH(child, &b->child, sibling) {
1493 pci_bridge_update_mappings(child);
1494 }
1495 }
1496
1497 static void pci_bridge_write_config(PCIDevice *d,
1498 uint32_t address, uint32_t val, int len)
1499 {
1500 pci_default_write_config(d, address, val, len);
1501
1502 if (/* io base/limit */
1503 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1504
1505 /* memory base/limit, prefetchable base/limit and
1506 io base/limit upper 16 */
1507 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1508 pci_bridge_update_mappings(d->bus);
1509 }
1510 }
1511
1512 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1513 {
1514 PCIBus *sec;
1515
1516 if (!bus) {
1517 return NULL;
1518 }
1519
1520 if (pci_bus_num(bus) == bus_num) {
1521 return bus;
1522 }
1523
1524 /* try child bus */
1525 if (!bus->parent_dev /* host pci bridge */ ||
1526 (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1527 bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1528 for (; bus; bus = sec) {
1529 QLIST_FOREACH(sec, &bus->child, sibling) {
1530 assert(sec->parent_dev);
1531 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1532 return sec;
1533 }
1534 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1535 bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1536 break;
1537 }
1538 }
1539 }
1540 }
1541
1542 return NULL;
1543 }
1544
1545 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1546 {
1547 bus = pci_find_bus(bus, bus_num);
1548
1549 if (!bus)
1550 return NULL;
1551
1552 return bus->devices[PCI_DEVFN(slot, function)];
1553 }
1554
1555 static int pci_bridge_initfn(PCIDevice *dev)
1556 {
1557 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1558
1559 pci_config_set_vendor_id(s->dev.config, s->vid);
1560 pci_config_set_device_id(s->dev.config, s->did);
1561
1562 pci_set_word(dev->config + PCI_STATUS,
1563 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1564 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1565 dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1566 pci_set_word(dev->config + PCI_SEC_STATUS,
1567 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1568 return 0;
1569 }
1570
1571 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1572 {
1573 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1574 PCIBus *bus = &s->bus;
1575 pci_unregister_secondary_bus(bus);
1576 return 0;
1577 }
1578
1579 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1580 pci_map_irq_fn map_irq, const char *name)
1581 {
1582 PCIDevice *dev;
1583 PCIBridge *s;
1584
1585 dev = pci_create(bus, devfn, "pci-bridge");
1586 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1587 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1588 qdev_init_nofail(&dev->qdev);
1589
1590 s = DO_UPCAST(PCIBridge, dev, dev);
1591 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1592 return &s->bus;
1593 }
1594
1595 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1596 {
1597 return bus->parent_dev;
1598 }
1599
1600 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1601 {
1602 PCIDevice *pci_dev = (PCIDevice *)qdev;
1603 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1604 PCIBus *bus;
1605 int devfn, rc;
1606
1607 /* initialize cap_present for pci_is_express() and pci_config_size() */
1608 if (info->is_express) {
1609 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1610 }
1611
1612 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1613 devfn = pci_dev->devfn;
1614 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1615 info->config_read, info->config_write,
1616 info->header_type);
1617 if (pci_dev == NULL)
1618 return -1;
1619 rc = info->init(pci_dev);
1620 if (rc != 0) {
1621 do_pci_unregister_device(pci_dev);
1622 return rc;
1623 }
1624
1625 /* rom loading */
1626 if (pci_dev->romfile == NULL && info->romfile != NULL)
1627 pci_dev->romfile = qemu_strdup(info->romfile);
1628 pci_add_option_rom(pci_dev);
1629
1630 if (qdev->hotplugged)
1631 bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1632 return 0;
1633 }
1634
1635 static int pci_unplug_device(DeviceState *qdev)
1636 {
1637 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1638
1639 dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1640 return 0;
1641 }
1642
1643 void pci_qdev_register(PCIDeviceInfo *info)
1644 {
1645 info->qdev.init = pci_qdev_init;
1646 info->qdev.unplug = pci_unplug_device;
1647 info->qdev.exit = pci_unregister_device;
1648 info->qdev.bus_info = &pci_bus_info;
1649 qdev_register(&info->qdev);
1650 }
1651
1652 void pci_qdev_register_many(PCIDeviceInfo *info)
1653 {
1654 while (info->qdev.name) {
1655 pci_qdev_register(info);
1656 info++;
1657 }
1658 }
1659
1660 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1661 {
1662 DeviceState *dev;
1663
1664 dev = qdev_create(&bus->qbus, name);
1665 qdev_prop_set_uint32(dev, "addr", devfn);
1666 return DO_UPCAST(PCIDevice, qdev, dev);
1667 }
1668
1669 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1670 {
1671 PCIDevice *dev = pci_create(bus, devfn, name);
1672 qdev_init_nofail(&dev->qdev);
1673 return dev;
1674 }
1675
1676 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1677 {
1678 int config_size = pci_config_size(pdev);
1679 int offset = PCI_CONFIG_HEADER_SIZE;
1680 int i;
1681 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1682 if (pdev->used[i])
1683 offset = i + 1;
1684 else if (i - offset + 1 == size)
1685 return offset;
1686 return 0;
1687 }
1688
1689 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1690 uint8_t *prev_p)
1691 {
1692 uint8_t next, prev;
1693
1694 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1695 return 0;
1696
1697 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1698 prev = next + PCI_CAP_LIST_NEXT)
1699 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1700 break;
1701
1702 if (prev_p)
1703 *prev_p = prev;
1704 return next;
1705 }
1706
1707 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1708 {
1709 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1710 }
1711
1712 /* Add an option rom for the device */
1713 static int pci_add_option_rom(PCIDevice *pdev)
1714 {
1715 int size;
1716 char *path;
1717 void *ptr;
1718 char name[32];
1719
1720 if (!pdev->romfile)
1721 return 0;
1722 if (strlen(pdev->romfile) == 0)
1723 return 0;
1724
1725 if (!pdev->rom_bar) {
1726 /*
1727 * Load rom via fw_cfg instead of creating a rom bar,
1728 * for 0.11 compatibility.
1729 */
1730 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1731 if (class == 0x0300) {
1732 rom_add_vga(pdev->romfile);
1733 } else {
1734 rom_add_option(pdev->romfile);
1735 }
1736 return 0;
1737 }
1738
1739 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1740 if (path == NULL) {
1741 path = qemu_strdup(pdev->romfile);
1742 }
1743
1744 size = get_image_size(path);
1745 if (size < 0) {
1746 error_report("%s: failed to find romfile \"%s\"",
1747 __FUNCTION__, pdev->romfile);
1748 return -1;
1749 }
1750 if (size & (size - 1)) {
1751 size = 1 << qemu_fls(size);
1752 }
1753
1754 if (pdev->qdev.info->vmsd)
1755 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1756 else
1757 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1758 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1759
1760 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1761 load_image(path, ptr);
1762 qemu_free(path);
1763
1764 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1765 0, pci_map_option_rom);
1766
1767 return 0;
1768 }
1769
1770 static void pci_del_option_rom(PCIDevice *pdev)
1771 {
1772 if (!pdev->rom_offset)
1773 return;
1774
1775 qemu_ram_free(pdev->rom_offset);
1776 pdev->rom_offset = 0;
1777 }
1778
1779 /* Reserve space and add capability to the linked list in pci config space */
1780 int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
1781 uint8_t offset, uint8_t size)
1782 {
1783 uint8_t *config = pdev->config + offset;
1784 config[PCI_CAP_LIST_ID] = cap_id;
1785 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1786 pdev->config[PCI_CAPABILITY_LIST] = offset;
1787 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1788 memset(pdev->used + offset, 0xFF, size);
1789 /* Make capability read-only by default */
1790 memset(pdev->wmask + offset, 0, size);
1791 /* Check capability by default */
1792 memset(pdev->cmask + offset, 0xFF, size);
1793 return offset;
1794 }
1795
1796 /* Find and reserve space and add capability to the linked list
1797 * in pci config space */
1798 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1799 {
1800 uint8_t offset = pci_find_space(pdev, size);
1801 if (!offset) {
1802 return -ENOSPC;
1803 }
1804 return pci_add_capability_at_offset(pdev, cap_id, offset, size);
1805 }
1806
1807 /* Unlink capability from the pci config space. */
1808 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1809 {
1810 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1811 if (!offset)
1812 return;
1813 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1814 /* Make capability writeable again */
1815 memset(pdev->wmask + offset, 0xff, size);
1816 /* Clear cmask as device-specific registers can't be checked */
1817 memset(pdev->cmask + offset, 0, size);
1818 memset(pdev->used + offset, 0, size);
1819
1820 if (!pdev->config[PCI_CAPABILITY_LIST])
1821 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1822 }
1823
1824 /* Reserve space for capability at a known offset (to call after load). */
1825 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1826 {
1827 memset(pdev->used + offset, 0xff, size);
1828 }
1829
1830 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1831 {
1832 return pci_find_capability_list(pdev, cap_id, NULL);
1833 }
1834
1835 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1836 {
1837 PCIDevice *d = (PCIDevice *)dev;
1838 const pci_class_desc *desc;
1839 char ctxt[64];
1840 PCIIORegion *r;
1841 int i, class;
1842
1843 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1844 desc = pci_class_descriptions;
1845 while (desc->desc && class != desc->class)
1846 desc++;
1847 if (desc->desc) {
1848 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1849 } else {
1850 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1851 }
1852
1853 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1854 "pci id %04x:%04x (sub %04x:%04x)\n",
1855 indent, "", ctxt,
1856 d->config[PCI_SECONDARY_BUS],
1857 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1858 pci_get_word(d->config + PCI_VENDOR_ID),
1859 pci_get_word(d->config + PCI_DEVICE_ID),
1860 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1861 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1862 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1863 r = &d->io_regions[i];
1864 if (!r->size)
1865 continue;
1866 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1867 " [0x%"FMT_PCIBUS"]\n",
1868 indent, "",
1869 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1870 r->addr, r->addr + r->size - 1);
1871 }
1872 }
1873
1874 static char *pcibus_get_dev_path(DeviceState *dev)
1875 {
1876 PCIDevice *d = (PCIDevice *)dev;
1877 char path[16];
1878
1879 snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1880 pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1881 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1882
1883 return strdup(path);
1884 }
1885
1886 static PCIDeviceInfo bridge_info = {
1887 .qdev.name = "pci-bridge",
1888 .qdev.size = sizeof(PCIBridge),
1889 .init = pci_bridge_initfn,
1890 .exit = pci_bridge_exitfn,
1891 .config_write = pci_bridge_write_config,
1892 .header_type = PCI_HEADER_TYPE_BRIDGE,
1893 .qdev.props = (Property[]) {
1894 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1895 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1896 DEFINE_PROP_END_OF_LIST(),
1897 }
1898 };
1899
1900 static void pci_register_devices(void)
1901 {
1902 pci_qdev_register(&bridge_info);
1903 }
1904
1905 device_init(pci_register_devices)
QEmu