hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "net.h"
  27 #include "ne2000.h"
  28
  29 /* debug NE2000 card */
  30 //#define DEBUG_NE2000
  31
  32 #define MAX_ETH_FRAME_SIZE 1514
  33
  34 #define E8390_CMD       0x00  /* The command register (for all pages) */
  35 /* Page 0 register offsets. */
  36 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  37 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  38 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  39 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  40 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  41 #define EN0_TSR         0x04    /* Transmit status reg RD */
  42 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  43 #define EN0_NCR         0x05    /* Number of collision reg RD */
  44 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  45 #define EN0_FIFO        0x06    /* FIFO RD */
  46 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  47 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  48 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  49 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  50 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  51 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  52 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  53 #define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
  54 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  55 #define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
  56 #define EN0_RSR         0x0c    /* rx status reg RD */
  57 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  58 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  59 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  60 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  61 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  62 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  63 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  64
  65 #define EN1_PHYS        0x11
  66 #define EN1_CURPAG      0x17
  67 #define EN1_MULT        0x18
  68
  69 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  70 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  71
  72 #define EN3_CONFIG0     0x33
  73 #define EN3_CONFIG1     0x34
  74 #define EN3_CONFIG2     0x35
  75 #define EN3_CONFIG3     0x36
  76
  77 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  78 #define E8390_STOP      0x01    /* Stop and reset the chip */
  79 #define E8390_START     0x02    /* Start the chip, clear reset */
  80 #define E8390_TRANS     0x04    /* Transmit a frame */
  81 #define E8390_RREAD     0x08    /* Remote read */
  82 #define E8390_RWRITE    0x10    /* Remote write  */
  83 #define E8390_NODMA     0x20    /* Remote DMA */
  84 #define E8390_PAGE0     0x00    /* Select page chip registers */
  85 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  86 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  87
  88 /* Bits in EN0_ISR - Interrupt status register */
  89 #define ENISR_RX        0x01    /* Receiver, no error */
  90 #define ENISR_TX        0x02    /* Transmitter, no error */
  91 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  92 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  93 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  94 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  95 #define ENISR_RDC       0x40    /* remote dma complete */
  96 #define ENISR_RESET     0x80    /* Reset completed */
  97 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
  98
  99 /* Bits in received packet status byte and EN0_RSR*/
 100 #define ENRSR_RXOK      0x01    /* Received a good packet */
 101 #define ENRSR_CRC       0x02    /* CRC error */
 102 #define ENRSR_FAE       0x04    /* frame alignment error */
 103 #define ENRSR_FO        0x08    /* FIFO overrun */
 104 #define ENRSR_MPA       0x10    /* missed pkt */
 105 #define ENRSR_PHY       0x20    /* physical/multicast address */
 106 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 107 #define ENRSR_DEF       0x80    /* deferring */
 108
 109 /* Transmitted packet status, EN0_TSR. */
 110 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 111 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 112 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 113 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 114 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 115 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 116 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 117 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 118
 119 typedef struct PCINE2000State {
 120     PCIDevice dev;
 121     NE2000State ne2000;
 122 } PCINE2000State;
 123
 124 void ne2000_reset(NE2000State *s)
 125 {
 126     int i;
 127
 128     s->isr = ENISR_RESET;
 129     memcpy(s->mem, s->macaddr, 6);
 130     s->mem[14] = 0x57;
 131     s->mem[15] = 0x57;
 132
 133     /* duplicate prom data */
 134     for(i = 15;i >= 0; i--) {
 135         s->mem[2 * i] = s->mem[i];
 136         s->mem[2 * i + 1] = s->mem[i];
 137     }
 138 }
 139
 140 static void ne2000_update_irq(NE2000State *s)
 141 {
 142     int isr;
 143     isr = (s->isr & s->imr) & 0x7f;
 144 #if defined(DEBUG_NE2000)
 145     printf("NE2000: Set IRQ to %d (%02x %02x)\n",
 146            isr ? 1 : 0, s->isr, s->imr);
 147 #endif
 148     qemu_set_irq(s->irq, (isr != 0));
 149 }
 150
 151 #define POLYNOMIAL 0x04c11db6
 152
 153 /* From FreeBSD */
 154 /* XXX: optimize */
 155 static int compute_mcast_idx(const uint8_t *ep)
 156 {
 157     uint32_t crc;
 158     int carry, i, j;
 159     uint8_t b;
 160
 161     crc = 0xffffffff;
 162     for (i = 0; i < 6; i++) {
 163         b = *ep++;
 164         for (j = 0; j < 8; j++) {
 165             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 166             crc <<= 1;
 167             b >>= 1;
 168             if (carry)
 169                 crc = ((crc ^ POLYNOMIAL) | carry);
 170         }
 171     }
 172     return (crc >> 26);
 173 }
 174
 175 static int ne2000_buffer_full(NE2000State *s)
 176 {
 177     int avail, index, boundary;
 178
 179     index = s->curpag << 8;
 180     boundary = s->boundary << 8;
 181     if (index < boundary)
 182         avail = boundary - index;
 183     else
 184         avail = (s->stop - s->start) - (index - boundary);
 185     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 186         return 1;
 187     return 0;
 188 }
 189
 190 int ne2000_can_receive(VLANClientState *vc)
 191 {
 192     NE2000State *s = vc->opaque;
 193
 194     if (s->cmd & E8390_STOP)
 195         return 1;
 196     return !ne2000_buffer_full(s);
 197 }
 198
 199 #define MIN_BUF_SIZE 60
 200
 201 ssize_t ne2000_receive(VLANClientState *vc, const uint8_t *buf, size_t size_)
 202 {
 203     NE2000State *s = vc->opaque;
 204     int size = size_;
 205     uint8_t *p;
 206     unsigned int total_len, next, avail, len, index, mcast_idx;
 207     uint8_t buf1[60];
 208     static const uint8_t broadcast_macaddr[6] =
 209         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 210
 211 #if defined(DEBUG_NE2000)
 212     printf("NE2000: received len=%d\n", size);
 213 #endif
 214
 215     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
 216         return -1;
 217
 218     /* XXX: check this */
 219     if (s->rxcr & 0x10) {
 220         /* promiscuous: receive all */
 221     } else {
 222         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 223             /* broadcast address */
 224             if (!(s->rxcr & 0x04))
 225                 return size;
 226         } else if (buf[0] & 0x01) {
 227             /* multicast */
 228             if (!(s->rxcr & 0x08))
 229                 return size;
 230             mcast_idx = compute_mcast_idx(buf);
 231             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 232                 return size;
 233         } else if (s->mem[0] == buf[0] &&
 234                    s->mem[2] == buf[1] &&
 235                    s->mem[4] == buf[2] &&
 236                    s->mem[6] == buf[3] &&
 237                    s->mem[8] == buf[4] &&
 238                    s->mem[10] == buf[5]) {
 239             /* match */
 240         } else {
 241             return size;
 242         }
 243     }
 244
 245
 246     /* if too small buffer, then expand it */
 247     if (size < MIN_BUF_SIZE) {
 248         memcpy(buf1, buf, size);
 249         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 250         buf = buf1;
 251         size = MIN_BUF_SIZE;
 252     }
 253
 254     index = s->curpag << 8;
 255     /* 4 bytes for header */
 256     total_len = size + 4;
 257     /* address for next packet (4 bytes for CRC) */
 258     next = index + ((total_len + 4 + 255) & ~0xff);
 259     if (next >= s->stop)
 260         next -= (s->stop - s->start);
 261     /* prepare packet header */
 262     p = s->mem + index;
 263     s->rsr = ENRSR_RXOK; /* receive status */
 264     /* XXX: check this */
 265     if (buf[0] & 0x01)
 266         s->rsr |= ENRSR_PHY;
 267     p[0] = s->rsr;
 268     p[1] = next >> 8;
 269     p[2] = total_len;
 270     p[3] = total_len >> 8;
 271     index += 4;
 272
 273     /* write packet data */
 274     while (size > 0) {
 275         if (index <= s->stop)
 276             avail = s->stop - index;
 277         else
 278             avail = 0;
 279         len = size;
 280         if (len > avail)
 281             len = avail;
 282         memcpy(s->mem + index, buf, len);
 283         buf += len;
 284         index += len;
 285         if (index == s->stop)
 286             index = s->start;
 287         size -= len;
 288     }
 289     s->curpag = next >> 8;
 290
 291     /* now we can signal we have received something */
 292     s->isr |= ENISR_RX;
 293     ne2000_update_irq(s);
 294
 295     return size_;
 296 }
 297
 298 void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 299 {
 300     NE2000State *s = opaque;
 301     int offset, page, index;
 302
 303     addr &= 0xf;
 304 #ifdef DEBUG_NE2000
 305     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 306 #endif
 307     if (addr == E8390_CMD) {
 308         /* control register */
 309         s->cmd = val;
 310         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 311             s->isr &= ~ENISR_RESET;
 312             /* test specific case: zero length transfer */
 313             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 314                 s->rcnt == 0) {
 315                 s->isr |= ENISR_RDC;
 316                 ne2000_update_irq(s);
 317             }
 318             if (val & E8390_TRANS) {
 319                 index = (s->tpsr << 8);
 320                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 321                 if (index >= NE2000_PMEM_END)
 322                     index -= NE2000_PMEM_SIZE;
 323                 /* fail safe: check range on the transmitted length  */
 324                 if (index + s->tcnt <= NE2000_PMEM_END) {
 325                     qemu_send_packet(s->vc, s->mem + index, s->tcnt);
 326                 }
 327                 /* signal end of transfer */
 328                 s->tsr = ENTSR_PTX;
 329                 s->isr |= ENISR_TX;
 330                 s->cmd &= ~E8390_TRANS;
 331                 ne2000_update_irq(s);
 332             }
 333         }
 334     } else {
 335         page = s->cmd >> 6;
 336         offset = addr | (page << 4);
 337         switch(offset) {
 338         case EN0_STARTPG:
 339             s->start = val << 8;
 340             break;
 341         case EN0_STOPPG:
 342             s->stop = val << 8;
 343             break;
 344         case EN0_BOUNDARY:
 345             s->boundary = val;
 346             break;
 347         case EN0_IMR:
 348             s->imr = val;
 349             ne2000_update_irq(s);
 350             break;
 351         case EN0_TPSR:
 352             s->tpsr = val;
 353             break;
 354         case EN0_TCNTLO:
 355             s->tcnt = (s->tcnt & 0xff00) | val;
 356             break;
 357         case EN0_TCNTHI:
 358             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 359             break;
 360         case EN0_RSARLO:
 361             s->rsar = (s->rsar & 0xff00) | val;
 362             break;
 363         case EN0_RSARHI:
 364             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 365             break;
 366         case EN0_RCNTLO:
 367             s->rcnt = (s->rcnt & 0xff00) | val;
 368             break;
 369         case EN0_RCNTHI:
 370             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 371             break;
 372         case EN0_RXCR:
 373             s->rxcr = val;
 374             break;
 375         case EN0_DCFG:
 376             s->dcfg = val;
 377             break;
 378         case EN0_ISR:
 379             s->isr &= ~(val & 0x7f);
 380             ne2000_update_irq(s);
 381             break;
 382         case EN1_PHYS ... EN1_PHYS + 5:
 383             s->phys[offset - EN1_PHYS] = val;
 384             break;
 385         case EN1_CURPAG:
 386             s->curpag = val;
 387             break;
 388         case EN1_MULT ... EN1_MULT + 7:
 389             s->mult[offset - EN1_MULT] = val;
 390             break;
 391         }
 392     }
 393 }
 394
 395 uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 396 {
 397     NE2000State *s = opaque;
 398     int offset, page, ret;
 399
 400     addr &= 0xf;
 401     if (addr == E8390_CMD) {
 402         ret = s->cmd;
 403     } else {
 404         page = s->cmd >> 6;
 405         offset = addr | (page << 4);
 406         switch(offset) {
 407         case EN0_TSR:
 408             ret = s->tsr;
 409             break;
 410         case EN0_BOUNDARY:
 411             ret = s->boundary;
 412             break;
 413         case EN0_ISR:
 414             ret = s->isr;
 415             break;
 416         case EN0_RSARLO:
 417             ret = s->rsar & 0x00ff;
 418             break;
 419         case EN0_RSARHI:
 420             ret = s->rsar >> 8;
 421             break;
 422         case EN1_PHYS ... EN1_PHYS + 5:
 423             ret = s->phys[offset - EN1_PHYS];
 424             break;
 425         case EN1_CURPAG:
 426             ret = s->curpag;
 427             break;
 428         case EN1_MULT ... EN1_MULT + 7:
 429             ret = s->mult[offset - EN1_MULT];
 430             break;
 431         case EN0_RSR:
 432             ret = s->rsr;
 433             break;
 434         case EN2_STARTPG:
 435             ret = s->start >> 8;
 436             break;
 437         case EN2_STOPPG:
 438             ret = s->stop >> 8;
 439             break;
 440         case EN0_RTL8029ID0:
 441             ret = 0x50;
 442             break;
 443         case EN0_RTL8029ID1:
 444             ret = 0x43;
 445             break;
 446         case EN3_CONFIG0:
 447             ret = 0;            /* 10baseT media */
 448             break;
 449         case EN3_CONFIG2:
 450             ret = 0x40;         /* 10baseT active */
 451             break;
 452         case EN3_CONFIG3:
 453             ret = 0x40;         /* Full duplex */
 454             break;
 455         default:
 456             ret = 0x00;
 457             break;
 458         }
 459     }
 460 #ifdef DEBUG_NE2000
 461     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 462 #endif
 463     return ret;
 464 }
 465
 466 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 467                                      uint32_t val)
 468 {
 469     if (addr < 32 ||
 470         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 471         s->mem[addr] = val;
 472     }
 473 }
 474
 475 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 476                                      uint32_t val)
 477 {
 478     addr &= ~1; /* XXX: check exact behaviour if not even */
 479     if (addr < 32 ||
 480         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 481         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 482     }
 483 }
 484
 485 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 486                                      uint32_t val)
 487 {
 488     addr &= ~1; /* XXX: check exact behaviour if not even */
 489     if (addr < 32 ||
 490         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 491         cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
 492     }
 493 }
 494
 495 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 496 {
 497     if (addr < 32 ||
 498         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 499         return s->mem[addr];
 500     } else {
 501         return 0xff;
 502     }
 503 }
 504
 505 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 506 {
 507     addr &= ~1; /* XXX: check exact behaviour if not even */
 508     if (addr < 32 ||
 509         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 510         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 511     } else {
 512         return 0xffff;
 513     }
 514 }
 515
 516 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 517 {
 518     addr &= ~1; /* XXX: check exact behaviour if not even */
 519     if (addr < 32 ||
 520         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 521         return le32_to_cpupu((uint32_t *)(s->mem + addr));
 522     } else {
 523         return 0xffffffff;
 524     }
 525 }
 526
 527 static inline void ne2000_dma_update(NE2000State *s, int len)
 528 {
 529     s->rsar += len;
 530     /* wrap */
 531     /* XXX: check what to do if rsar > stop */
 532     if (s->rsar == s->stop)
 533         s->rsar = s->start;
 534
 535     if (s->rcnt <= len) {
 536         s->rcnt = 0;
 537         /* signal end of transfer */
 538         s->isr |= ENISR_RDC;
 539         ne2000_update_irq(s);
 540     } else {
 541         s->rcnt -= len;
 542     }
 543 }
 544
 545 void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 546 {
 547     NE2000State *s = opaque;
 548
 549 #ifdef DEBUG_NE2000
 550     printf("NE2000: asic write val=0x%04x\n", val);
 551 #endif
 552     if (s->rcnt == 0)
 553         return;
 554     if (s->dcfg & 0x01) {
 555         /* 16 bit access */
 556         ne2000_mem_writew(s, s->rsar, val);
 557         ne2000_dma_update(s, 2);
 558     } else {
 559         /* 8 bit access */
 560         ne2000_mem_writeb(s, s->rsar, val);
 561         ne2000_dma_update(s, 1);
 562     }
 563 }
 564
 565 uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 566 {
 567     NE2000State *s = opaque;
 568     int ret;
 569
 570     if (s->dcfg & 0x01) {
 571         /* 16 bit access */
 572         ret = ne2000_mem_readw(s, s->rsar);
 573         ne2000_dma_update(s, 2);
 574     } else {
 575         /* 8 bit access */
 576         ret = ne2000_mem_readb(s, s->rsar);
 577         ne2000_dma_update(s, 1);
 578     }
 579 #ifdef DEBUG_NE2000
 580     printf("NE2000: asic read val=0x%04x\n", ret);
 581 #endif
 582     return ret;
 583 }
 584
 585 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 586 {
 587     NE2000State *s = opaque;
 588
 589 #ifdef DEBUG_NE2000
 590     printf("NE2000: asic writel val=0x%04x\n", val);
 591 #endif
 592     if (s->rcnt == 0)
 593         return;
 594     /* 32 bit access */
 595     ne2000_mem_writel(s, s->rsar, val);
 596     ne2000_dma_update(s, 4);
 597 }
 598
 599 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 600 {
 601     NE2000State *s = opaque;
 602     int ret;
 603
 604     /* 32 bit access */
 605     ret = ne2000_mem_readl(s, s->rsar);
 606     ne2000_dma_update(s, 4);
 607 #ifdef DEBUG_NE2000
 608     printf("NE2000: asic readl val=0x%04x\n", ret);
 609 #endif
 610     return ret;
 611 }
 612
 613 void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 614 {
 615     /* nothing to do (end of reset pulse) */
 616 }
 617
 618 uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 619 {
 620     NE2000State *s = opaque;
 621     ne2000_reset(s);
 622     return 0;
 623 }
 624
 625 void ne2000_save(QEMUFile* f, void* opaque)
 626 {
 627         NE2000State* s = opaque;
 628         uint32_t tmp;
 629
 630         qemu_put_8s(f, &s->rxcr);
 631
 632         qemu_put_8s(f, &s->cmd);
 633         qemu_put_be32s(f, &s->start);
 634         qemu_put_be32s(f, &s->stop);
 635         qemu_put_8s(f, &s->boundary);
 636         qemu_put_8s(f, &s->tsr);
 637         qemu_put_8s(f, &s->tpsr);
 638         qemu_put_be16s(f, &s->tcnt);
 639         qemu_put_be16s(f, &s->rcnt);
 640         qemu_put_be32s(f, &s->rsar);
 641         qemu_put_8s(f, &s->rsr);
 642         qemu_put_8s(f, &s->isr);
 643         qemu_put_8s(f, &s->dcfg);
 644         qemu_put_8s(f, &s->imr);
 645         qemu_put_buffer(f, s->phys, 6);
 646         qemu_put_8s(f, &s->curpag);
 647         qemu_put_buffer(f, s->mult, 8);
 648         tmp = 0;
 649         qemu_put_be32s(f, &tmp); /* ignored, was irq */
 650         qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
 651 }
 652
 653 int ne2000_load(QEMUFile* f, void* opaque, int version_id)
 654 {
 655         NE2000State* s = opaque;
 656         uint32_t tmp;
 657
 658         if (version_id > 3)
 659             return -EINVAL;
 660
 661         if (version_id >= 2) {
 662             qemu_get_8s(f, &s->rxcr);
 663         } else {
 664             s->rxcr = 0x0c;
 665         }
 666
 667         qemu_get_8s(f, &s->cmd);
 668         qemu_get_be32s(f, &s->start);
 669         qemu_get_be32s(f, &s->stop);
 670         qemu_get_8s(f, &s->boundary);
 671         qemu_get_8s(f, &s->tsr);
 672         qemu_get_8s(f, &s->tpsr);
 673         qemu_get_be16s(f, &s->tcnt);
 674         qemu_get_be16s(f, &s->rcnt);
 675         qemu_get_be32s(f, &s->rsar);
 676         qemu_get_8s(f, &s->rsr);
 677         qemu_get_8s(f, &s->isr);
 678         qemu_get_8s(f, &s->dcfg);
 679         qemu_get_8s(f, &s->imr);
 680         qemu_get_buffer(f, s->phys, 6);
 681         qemu_get_8s(f, &s->curpag);
 682         qemu_get_buffer(f, s->mult, 8);
 683         qemu_get_be32s(f, &tmp); /* ignored */
 684         qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
 685
 686         return 0;
 687 }
 688
 689 static void pci_ne2000_save(QEMUFile* f, void* opaque)
 690 {
 691         PCINE2000State* s = opaque;
 692
 693         pci_device_save(&s->dev, f);
 694         ne2000_save(f, &s->ne2000);
 695 }
 696
 697 static int pci_ne2000_load(QEMUFile* f, void* opaque, int version_id)
 698 {
 699         PCINE2000State* s = opaque;
 700         int ret;
 701
 702         if (version_id > 3)
 703             return -EINVAL;
 704
 705         if (version_id >= 3) {
 706             ret = pci_device_load(&s->dev, f);
 707             if (ret < 0)
 708                 return ret;
 709         }
 710
 711         return ne2000_load(f, &s->ne2000, version_id);
 712 }
 713
 714 /***********************************************************/
 715 /* PCI NE2000 definitions */
 716
 717 static void ne2000_map(PCIDevice *pci_dev, int region_num,
 718                        uint32_t addr, uint32_t size, int type)
 719 {
 720     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 721     NE2000State *s = &d->ne2000;
 722
 723     register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
 724     register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
 725
 726     register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 727     register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 728     register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 729     register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 730     register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
 731     register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
 732
 733     register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 734     register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 735 }
 736
 737 static void ne2000_cleanup(VLANClientState *vc)
 738 {
 739     NE2000State *s = vc->opaque;
 740
 741     unregister_savevm("ne2000", s);
 742 }
 743
 744 static int pci_ne2000_init(PCIDevice *pci_dev)
 745 {
 746     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 747     NE2000State *s;
 748     uint8_t *pci_conf;
 749
 750     pci_conf = d->dev.config;
 751     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
 752     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
 753     pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
 754     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 755     pci_conf[0x3d] = 1; // interrupt pin 0
 756
 757     pci_register_bar(&d->dev, 0, 0x100,
 758                            PCI_ADDRESS_SPACE_IO, ne2000_map);
 759     s = &d->ne2000;
 760     s->irq = d->dev.irq[0];
 761     qdev_get_macaddr(&d->dev.qdev, s->macaddr);
 762     ne2000_reset(s);
 763     s->vc = qdev_get_vlan_client(&d->dev.qdev,
 764                                  ne2000_can_receive, ne2000_receive, NULL,
 765                                  ne2000_cleanup, s);
 766
 767     qemu_format_nic_info_str(s->vc, s->macaddr);
 768
 769     register_savevm("ne2000", -1, 3, pci_ne2000_save, pci_ne2000_load, d);
 770     return 0;
 771 }
 772
 773 static PCIDeviceInfo ne2000_info = {
 774     .qdev.name = "ne2k_pci",
 775     .qdev.size = sizeof(PCINE2000State),
 776     .init      = pci_ne2000_init,
 777 };
 778
 779 static void ne2000_register_devices(void)
 780 {
 781     pci_qdev_register(&ne2000_info);
 782 }
 783
 784 device_init(ne2000_register_devices)