2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "hw/usb/uhci-regs.h"
31 #include "hw/pci/pci.h"
32 #include "qemu/timer.h"
34 #include "sysemu/dma.h"
36 #include "qemu/main-loop.h"
38 #define FRAME_TIMER_FREQ 1000
40 #define FRAME_MAX_LOOPS 256
42 /* Must be large enough to handle 10 frame delay for initial isoc requests */
45 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
50 TD_RESULT_STOP_FRAME
= 10,
53 TD_RESULT_ASYNC_START
,
57 typedef struct UHCIState UHCIState
;
58 typedef struct UHCIAsync UHCIAsync
;
59 typedef struct UHCIQueue UHCIQueue
;
60 typedef struct UHCIInfo UHCIInfo
;
61 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass
;
69 int (*initfn
)(PCIDevice
*dev
);
73 struct UHCIPCIDeviceClass
{
74 PCIDeviceClass parent_class
;
79 * Pending async transaction.
80 * 'packet' must be the first field because completion
81 * handler does "(UHCIAsync *) pkt" cast.
86 uint8_t static_buf
[64]; /* 64 bytes is enough, except for isoc packets */
89 QTAILQ_ENTRY(UHCIAsync
) next
;
99 QTAILQ_ENTRY(UHCIQueue
) next
;
100 QTAILQ_HEAD(asyncs_head
, UHCIAsync
) asyncs
;
104 typedef struct UHCIPort
{
112 USBBus bus
; /* Note unused when we're a companion controller */
113 uint16_t cmd
; /* cmd register */
115 uint16_t intr
; /* interrupt enable register */
116 uint16_t frnum
; /* frame number */
117 uint32_t fl_base_addr
; /* frame list base address */
119 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
121 QEMUTimer
*frame_timer
;
123 uint32_t frame_bytes
;
124 uint32_t frame_bandwidth
;
125 bool completions_only
;
126 UHCIPort ports
[NB_PORTS
];
128 /* Interrupts that should be raised at the end of the current frame. */
129 uint32_t pending_int_mask
;
132 QTAILQ_HEAD(, UHCIQueue
) queues
;
133 uint8_t num_ports_vmstate
;
141 typedef struct UHCI_TD
{
143 uint32_t ctrl
; /* see TD_CTRL_xxx */
148 typedef struct UHCI_QH
{
153 static void uhci_async_cancel(UHCIAsync
*async
);
154 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
);
155 static void uhci_resume(void *opaque
);
157 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
159 if ((td
->token
& (0xf << 15)) == 0) {
160 /* ctrl ep, cover ep and dev, not pid! */
161 return td
->token
& 0x7ff00;
163 /* covers ep, dev, pid -> identifies the endpoint */
164 return td
->token
& 0x7ffff;
168 static UHCIQueue
*uhci_queue_new(UHCIState
*s
, uint32_t qh_addr
, UHCI_TD
*td
,
173 queue
= g_new0(UHCIQueue
, 1);
175 queue
->qh_addr
= qh_addr
;
176 queue
->token
= uhci_queue_token(td
);
178 QTAILQ_INIT(&queue
->asyncs
);
179 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
180 queue
->valid
= QH_VALID
;
181 trace_usb_uhci_queue_add(queue
->token
);
185 static void uhci_queue_free(UHCIQueue
*queue
, const char *reason
)
187 UHCIState
*s
= queue
->uhci
;
190 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
191 async
= QTAILQ_FIRST(&queue
->asyncs
);
192 uhci_async_cancel(async
);
194 usb_device_ep_stopped(queue
->ep
->dev
, queue
->ep
);
196 trace_usb_uhci_queue_del(queue
->token
, reason
);
197 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
201 static UHCIQueue
*uhci_queue_find(UHCIState
*s
, UHCI_TD
*td
)
203 uint32_t token
= uhci_queue_token(td
);
206 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
207 if (queue
->token
== token
) {
214 static bool uhci_queue_verify(UHCIQueue
*queue
, uint32_t qh_addr
, UHCI_TD
*td
,
215 uint32_t td_addr
, bool queuing
)
217 UHCIAsync
*first
= QTAILQ_FIRST(&queue
->asyncs
);
218 uint32_t queue_token_addr
= (queue
->token
>> 8) & 0x7f;
220 return queue
->qh_addr
== qh_addr
&&
221 queue
->token
== uhci_queue_token(td
) &&
222 queue_token_addr
== queue
->ep
->dev
->addr
&&
223 (queuing
|| !(td
->ctrl
& TD_CTRL_ACTIVE
) || first
== NULL
||
224 first
->td_addr
== td_addr
);
227 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t td_addr
)
229 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
231 async
->queue
= queue
;
232 async
->td_addr
= td_addr
;
233 usb_packet_init(&async
->packet
);
234 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td_addr
);
239 static void uhci_async_free(UHCIAsync
*async
)
241 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td_addr
);
242 usb_packet_cleanup(&async
->packet
);
243 if (async
->buf
!= async
->static_buf
) {
249 static void uhci_async_link(UHCIAsync
*async
)
251 UHCIQueue
*queue
= async
->queue
;
252 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
253 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td_addr
);
256 static void uhci_async_unlink(UHCIAsync
*async
)
258 UHCIQueue
*queue
= async
->queue
;
259 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
260 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td_addr
);
263 static void uhci_async_cancel(UHCIAsync
*async
)
265 uhci_async_unlink(async
);
266 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td_addr
,
269 usb_cancel_packet(&async
->packet
);
270 uhci_async_free(async
);
274 * Mark all outstanding async packets as invalid.
275 * This is used for canceling them when TDs are removed by the HCD.
277 static void uhci_async_validate_begin(UHCIState
*s
)
281 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
287 * Cancel async packets that are no longer valid
289 static void uhci_async_validate_end(UHCIState
*s
)
291 UHCIQueue
*queue
, *n
;
293 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
295 uhci_queue_free(queue
, "validate-end");
300 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
302 UHCIQueue
*queue
, *n
;
304 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
305 if (queue
->ep
->dev
== dev
) {
306 uhci_queue_free(queue
, "cancel-device");
311 static void uhci_async_cancel_all(UHCIState
*s
)
313 UHCIQueue
*queue
, *nq
;
315 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
316 uhci_queue_free(queue
, "cancel-all");
320 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t td_addr
)
325 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
326 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
327 if (async
->td_addr
== td_addr
) {
335 static void uhci_update_irq(UHCIState
*s
)
338 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
339 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
340 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
341 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
342 (s
->status
& UHCI_STS_HSERR
) ||
343 (s
->status
& UHCI_STS_HCPERR
)) {
348 pci_set_irq(&s
->dev
, level
);
351 static void uhci_reset(void *opaque
)
353 UHCIState
*s
= opaque
;
358 trace_usb_uhci_reset();
360 pci_conf
= s
->dev
.config
;
362 pci_conf
[0x6a] = 0x01; /* usb clock */
363 pci_conf
[0x6b] = 0x00;
371 for(i
= 0; i
< NB_PORTS
; i
++) {
374 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
375 usb_port_reset(&port
->port
);
379 uhci_async_cancel_all(s
);
380 qemu_bh_cancel(s
->bh
);
384 static const VMStateDescription vmstate_uhci_port
= {
387 .minimum_version_id
= 1,
388 .fields
= (VMStateField
[]) {
389 VMSTATE_UINT16(ctrl
, UHCIPort
),
390 VMSTATE_END_OF_LIST()
394 static int uhci_post_load(void *opaque
, int version_id
)
396 UHCIState
*s
= opaque
;
398 if (version_id
< 2) {
399 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
400 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
405 static const VMStateDescription vmstate_uhci
= {
408 .minimum_version_id
= 1,
409 .post_load
= uhci_post_load
,
410 .fields
= (VMStateField
[]) {
411 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
412 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
413 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
414 vmstate_uhci_port
, UHCIPort
),
415 VMSTATE_UINT16(cmd
, UHCIState
),
416 VMSTATE_UINT16(status
, UHCIState
),
417 VMSTATE_UINT16(intr
, UHCIState
),
418 VMSTATE_UINT16(frnum
, UHCIState
),
419 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
420 VMSTATE_UINT8(sof_timing
, UHCIState
),
421 VMSTATE_UINT8(status2
, UHCIState
),
422 VMSTATE_TIMER_PTR(frame_timer
, UHCIState
),
423 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
424 VMSTATE_UINT32_V(pending_int_mask
, UHCIState
, 3),
425 VMSTATE_END_OF_LIST()
429 static void uhci_port_write(void *opaque
, hwaddr addr
,
430 uint64_t val
, unsigned size
)
432 UHCIState
*s
= opaque
;
434 trace_usb_uhci_mmio_writew(addr
, val
);
438 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
439 /* start frame processing */
440 trace_usb_uhci_schedule_start();
441 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
442 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
443 timer_mod(s
->frame_timer
, s
->expire_time
);
444 s
->status
&= ~UHCI_STS_HCHALTED
;
445 } else if (!(val
& UHCI_CMD_RS
)) {
446 s
->status
|= UHCI_STS_HCHALTED
;
448 if (val
& UHCI_CMD_GRESET
) {
452 /* send reset on the USB bus */
453 for(i
= 0; i
< NB_PORTS
; i
++) {
455 usb_device_reset(port
->port
.dev
);
460 if (val
& UHCI_CMD_HCRESET
) {
465 if (val
& UHCI_CMD_EGSM
) {
466 if ((s
->ports
[0].ctrl
& UHCI_PORT_RD
) ||
467 (s
->ports
[1].ctrl
& UHCI_PORT_RD
)) {
474 /* XXX: the chip spec is not coherent, so we add a hidden
475 register to distinguish between IOC and SPD */
476 if (val
& UHCI_STS_USBINT
)
485 if (s
->status
& UHCI_STS_HCHALTED
)
486 s
->frnum
= val
& 0x7ff;
489 s
->fl_base_addr
&= 0xffff0000;
490 s
->fl_base_addr
|= val
& ~0xfff;
493 s
->fl_base_addr
&= 0x0000ffff;
494 s
->fl_base_addr
|= (val
<< 16);
497 s
->sof_timing
= val
& 0xff;
509 dev
= port
->port
.dev
;
510 if (dev
&& dev
->attached
) {
512 if ( (val
& UHCI_PORT_RESET
) &&
513 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
514 usb_device_reset(dev
);
517 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
518 /* enabled may only be set if a device is connected */
519 if (!(port
->ctrl
& UHCI_PORT_CCS
)) {
520 val
&= ~UHCI_PORT_EN
;
522 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
523 /* some bits are reset when a '1' is written to them */
524 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
530 static uint64_t uhci_port_read(void *opaque
, hwaddr addr
, unsigned size
)
532 UHCIState
*s
= opaque
;
549 val
= s
->fl_base_addr
& 0xffff;
552 val
= (s
->fl_base_addr
>> 16) & 0xffff;
570 val
= 0xff7f; /* disabled port */
574 trace_usb_uhci_mmio_readw(addr
, val
);
579 /* signal resume if controller suspended */
580 static void uhci_resume (void *opaque
)
582 UHCIState
*s
= (UHCIState
*)opaque
;
587 if (s
->cmd
& UHCI_CMD_EGSM
) {
588 s
->cmd
|= UHCI_CMD_FGR
;
589 s
->status
|= UHCI_STS_RD
;
594 static void uhci_attach(USBPort
*port1
)
596 UHCIState
*s
= port1
->opaque
;
597 UHCIPort
*port
= &s
->ports
[port1
->index
];
599 /* set connect status */
600 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
603 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
604 port
->ctrl
|= UHCI_PORT_LSDA
;
606 port
->ctrl
&= ~UHCI_PORT_LSDA
;
612 static void uhci_detach(USBPort
*port1
)
614 UHCIState
*s
= port1
->opaque
;
615 UHCIPort
*port
= &s
->ports
[port1
->index
];
617 uhci_async_cancel_device(s
, port1
->dev
);
619 /* set connect status */
620 if (port
->ctrl
& UHCI_PORT_CCS
) {
621 port
->ctrl
&= ~UHCI_PORT_CCS
;
622 port
->ctrl
|= UHCI_PORT_CSC
;
625 if (port
->ctrl
& UHCI_PORT_EN
) {
626 port
->ctrl
&= ~UHCI_PORT_EN
;
627 port
->ctrl
|= UHCI_PORT_ENC
;
633 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
635 UHCIState
*s
= port1
->opaque
;
637 uhci_async_cancel_device(s
, child
);
640 static void uhci_wakeup(USBPort
*port1
)
642 UHCIState
*s
= port1
->opaque
;
643 UHCIPort
*port
= &s
->ports
[port1
->index
];
645 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
646 port
->ctrl
|= UHCI_PORT_RD
;
651 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
656 for (i
= 0; i
< NB_PORTS
; i
++) {
657 UHCIPort
*port
= &s
->ports
[i
];
658 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
661 dev
= usb_find_device(&port
->port
, addr
);
669 static void uhci_read_td(UHCIState
*s
, UHCI_TD
*td
, uint32_t link
)
671 pci_dma_read(&s
->dev
, link
& ~0xf, td
, sizeof(*td
));
672 le32_to_cpus(&td
->link
);
673 le32_to_cpus(&td
->ctrl
);
674 le32_to_cpus(&td
->token
);
675 le32_to_cpus(&td
->buffer
);
678 static int uhci_handle_td_error(UHCIState
*s
, UHCI_TD
*td
, uint32_t td_addr
,
679 int status
, uint32_t *int_mask
)
681 uint32_t queue_token
= uhci_queue_token(td
);
686 td
->ctrl
|= TD_CTRL_NAK
;
687 return TD_RESULT_NEXT_QH
;
690 td
->ctrl
|= TD_CTRL_STALL
;
691 trace_usb_uhci_packet_complete_stall(queue_token
, td_addr
);
692 ret
= TD_RESULT_NEXT_QH
;
696 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
697 /* frame interrupted */
698 trace_usb_uhci_packet_complete_babble(queue_token
, td_addr
);
699 ret
= TD_RESULT_STOP_FRAME
;
702 case USB_RET_IOERROR
:
705 td
->ctrl
|= TD_CTRL_TIMEOUT
;
706 td
->ctrl
&= ~(3 << TD_CTRL_ERROR_SHIFT
);
707 trace_usb_uhci_packet_complete_error(queue_token
, td_addr
);
708 ret
= TD_RESULT_NEXT_QH
;
712 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
713 s
->status
|= UHCI_STS_USBERR
;
714 if (td
->ctrl
& TD_CTRL_IOC
) {
721 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
723 int len
= 0, max_len
;
726 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
727 pid
= td
->token
& 0xff;
729 if (td
->ctrl
& TD_CTRL_IOS
)
730 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
732 if (async
->packet
.status
!= USB_RET_SUCCESS
) {
733 return uhci_handle_td_error(s
, td
, async
->td_addr
,
734 async
->packet
.status
, int_mask
);
737 len
= async
->packet
.actual_length
;
738 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
740 /* The NAK bit may have been set by a previous frame, so clear it
741 here. The docs are somewhat unclear, but win2k relies on this
743 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
744 if (td
->ctrl
& TD_CTRL_IOC
)
747 if (pid
== USB_TOKEN_IN
) {
748 pci_dma_write(&s
->dev
, td
->buffer
, async
->buf
, len
);
749 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
751 /* short packet: do not update QH */
752 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
754 return TD_RESULT_NEXT_QH
;
759 trace_usb_uhci_packet_complete_success(async
->queue
->token
,
761 return TD_RESULT_COMPLETE
;
764 static int uhci_handle_td(UHCIState
*s
, UHCIQueue
*q
, uint32_t qh_addr
,
765 UHCI_TD
*td
, uint32_t td_addr
, uint32_t *int_mask
)
769 bool queuing
= (q
!= NULL
);
770 uint8_t pid
= td
->token
& 0xff;
771 UHCIAsync
*async
= uhci_async_find_td(s
, td_addr
);
774 if (uhci_queue_verify(async
->queue
, qh_addr
, td
, td_addr
, queuing
)) {
775 assert(q
== NULL
|| q
== async
->queue
);
778 uhci_queue_free(async
->queue
, "guest re-used pending td");
784 q
= uhci_queue_find(s
, td
);
785 if (q
&& !uhci_queue_verify(q
, qh_addr
, td
, td_addr
, queuing
)) {
786 uhci_queue_free(q
, "guest re-used qh");
796 if (!(td
->ctrl
& TD_CTRL_ACTIVE
)) {
798 /* Guest marked a pending td non-active, cancel the queue */
799 uhci_queue_free(async
->queue
, "pending td non-active");
802 * ehci11d spec page 22: "Even if the Active bit in the TD is already
803 * cleared when the TD is fetched ... an IOC interrupt is generated"
805 if (td
->ctrl
& TD_CTRL_IOC
) {
808 return TD_RESULT_NEXT_QH
;
813 /* we are busy filling the queue, we are not prepared
814 to consume completed packages then, just leave them
816 return TD_RESULT_ASYNC_CONT
;
820 UHCIAsync
*last
= QTAILQ_LAST(&async
->queue
->asyncs
, asyncs_head
);
822 * While we are waiting for the current td to complete, the guest
823 * may have added more tds to the queue. Note we re-read the td
824 * rather then caching it, as we want to see guest made changes!
826 uhci_read_td(s
, &last_td
, last
->td_addr
);
827 uhci_queue_fill(async
->queue
, &last_td
);
829 return TD_RESULT_ASYNC_CONT
;
831 uhci_async_unlink(async
);
835 if (s
->completions_only
) {
836 return TD_RESULT_ASYNC_CONT
;
839 /* Allocate new packet */
841 USBDevice
*dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
842 USBEndpoint
*ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
845 return uhci_handle_td_error(s
, td
, td_addr
, USB_RET_NODEV
,
848 q
= uhci_queue_new(s
, qh_addr
, td
, ep
);
850 async
= uhci_async_alloc(q
, td_addr
);
852 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
853 spd
= (pid
== USB_TOKEN_IN
&& (td
->ctrl
& TD_CTRL_SPD
) != 0);
854 usb_packet_setup(&async
->packet
, pid
, q
->ep
, 0, td_addr
, spd
,
855 (td
->ctrl
& TD_CTRL_IOC
) != 0);
856 if (max_len
<= sizeof(async
->static_buf
)) {
857 async
->buf
= async
->static_buf
;
859 async
->buf
= g_malloc(max_len
);
861 usb_packet_addbuf(&async
->packet
, async
->buf
, max_len
);
865 case USB_TOKEN_SETUP
:
866 pci_dma_read(&s
->dev
, td
->buffer
, async
->buf
, max_len
);
867 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
868 if (async
->packet
.status
== USB_RET_SUCCESS
) {
869 async
->packet
.actual_length
= max_len
;
874 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
878 /* invalid pid : frame interrupted */
879 uhci_async_free(async
);
880 s
->status
|= UHCI_STS_HCPERR
;
882 return TD_RESULT_STOP_FRAME
;
885 if (async
->packet
.status
== USB_RET_ASYNC
) {
886 uhci_async_link(async
);
888 uhci_queue_fill(q
, td
);
890 return TD_RESULT_ASYNC_START
;
894 ret
= uhci_complete_td(s
, td
, async
, int_mask
);
895 uhci_async_free(async
);
899 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
901 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
902 UHCIState
*s
= async
->queue
->uhci
;
904 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
905 uhci_async_cancel(async
);
910 /* Force processing of this packet *now*, needed for migration */
911 s
->completions_only
= true;
912 qemu_bh_schedule(s
->bh
);
915 static int is_valid(uint32_t link
)
917 return (link
& 1) == 0;
920 static int is_qh(uint32_t link
)
922 return (link
& 2) != 0;
925 static int depth_first(uint32_t link
)
927 return (link
& 4) != 0;
930 /* QH DB used for detecting QH loops */
931 #define UHCI_MAX_QUEUES 128
933 uint32_t addr
[UHCI_MAX_QUEUES
];
937 static void qhdb_reset(QhDb
*db
)
942 /* Add QH to DB. Returns 1 if already present or DB is full. */
943 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
946 for (i
= 0; i
< db
->count
; i
++)
947 if (db
->addr
[i
] == addr
)
950 if (db
->count
>= UHCI_MAX_QUEUES
)
953 db
->addr
[db
->count
++] = addr
;
957 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
)
959 uint32_t int_mask
= 0;
960 uint32_t plink
= td
->link
;
964 while (is_valid(plink
)) {
965 uhci_read_td(q
->uhci
, &ptd
, plink
);
966 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
969 if (uhci_queue_token(&ptd
) != q
->token
) {
972 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
973 ret
= uhci_handle_td(q
->uhci
, q
, q
->qh_addr
, &ptd
, plink
, &int_mask
);
974 if (ret
== TD_RESULT_ASYNC_CONT
) {
977 assert(ret
== TD_RESULT_ASYNC_START
);
978 assert(int_mask
== 0);
981 usb_device_flush_ep_queue(q
->ep
->dev
, q
->ep
);
984 static void uhci_process_frame(UHCIState
*s
)
986 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
987 uint32_t curr_qh
, td_count
= 0;
993 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
995 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
1003 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
1004 if (!s
->completions_only
&& s
->frame_bytes
>= s
->frame_bandwidth
) {
1005 /* We've reached the usb 1.1 bandwidth, which is
1006 1280 bytes/frame, stop processing */
1007 trace_usb_uhci_frame_stop_bandwidth();
1012 trace_usb_uhci_qh_load(link
& ~0xf);
1014 if (qhdb_insert(&qhdb
, link
)) {
1016 * We're going in circles. Which is not a bug because
1017 * HCD is allowed to do that as part of the BW management.
1019 * Stop processing here if no transaction has been done
1020 * since we've been here last time.
1022 if (td_count
== 0) {
1023 trace_usb_uhci_frame_loop_stop_idle();
1026 trace_usb_uhci_frame_loop_continue();
1029 qhdb_insert(&qhdb
, link
);
1033 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1034 le32_to_cpus(&qh
.link
);
1035 le32_to_cpus(&qh
.el_link
);
1037 if (!is_valid(qh
.el_link
)) {
1038 /* QH w/o elements */
1042 /* QH with elements */
1050 uhci_read_td(s
, &td
, link
);
1051 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1053 old_td_ctrl
= td
.ctrl
;
1054 ret
= uhci_handle_td(s
, NULL
, curr_qh
, &td
, link
, &int_mask
);
1055 if (old_td_ctrl
!= td
.ctrl
) {
1056 /* update the status bits of the TD */
1057 val
= cpu_to_le32(td
.ctrl
);
1058 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1062 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1065 case TD_RESULT_NEXT_QH
:
1066 case TD_RESULT_ASYNC_CONT
:
1067 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1068 link
= curr_qh
? qh
.link
: td
.link
;
1071 case TD_RESULT_ASYNC_START
:
1072 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1073 link
= curr_qh
? qh
.link
: td
.link
;
1076 case TD_RESULT_COMPLETE
:
1077 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1080 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1083 /* update QH element link */
1085 val
= cpu_to_le32(qh
.el_link
);
1086 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1088 if (!depth_first(link
)) {
1089 /* done with this QH */
1097 assert(!"unknown return code");
1100 /* go to the next entry */
1104 s
->pending_int_mask
|= int_mask
;
1107 static void uhci_bh(void *opaque
)
1109 UHCIState
*s
= opaque
;
1110 uhci_process_frame(s
);
1113 static void uhci_frame_timer(void *opaque
)
1115 UHCIState
*s
= opaque
;
1116 uint64_t t_now
, t_last_run
;
1118 const uint64_t frame_t
= get_ticks_per_sec() / FRAME_TIMER_FREQ
;
1120 s
->completions_only
= false;
1121 qemu_bh_cancel(s
->bh
);
1123 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1125 trace_usb_uhci_schedule_stop();
1126 timer_del(s
->frame_timer
);
1127 uhci_async_cancel_all(s
);
1128 /* set hchalted bit in status - UHCI11D 2.1.2 */
1129 s
->status
|= UHCI_STS_HCHALTED
;
1133 /* We still store expire_time in our state, for migration */
1134 t_last_run
= s
->expire_time
- frame_t
;
1135 t_now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1137 /* Process up to MAX_FRAMES_PER_TICK frames */
1138 frames
= (t_now
- t_last_run
) / frame_t
;
1139 if (frames
> s
->maxframes
) {
1140 int skipped
= frames
- s
->maxframes
;
1141 s
->expire_time
+= skipped
* frame_t
;
1142 s
->frnum
= (s
->frnum
+ skipped
) & 0x7ff;
1145 if (frames
> MAX_FRAMES_PER_TICK
) {
1146 frames
= MAX_FRAMES_PER_TICK
;
1149 for (i
= 0; i
< frames
; i
++) {
1151 trace_usb_uhci_frame_start(s
->frnum
);
1152 uhci_async_validate_begin(s
);
1153 uhci_process_frame(s
);
1154 uhci_async_validate_end(s
);
1155 /* The spec says frnum is the frame currently being processed, and
1156 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1157 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1158 s
->expire_time
+= frame_t
;
1161 /* Complete the previous frame(s) */
1162 if (s
->pending_int_mask
) {
1163 s
->status2
|= s
->pending_int_mask
;
1164 s
->status
|= UHCI_STS_USBINT
;
1167 s
->pending_int_mask
= 0;
1169 timer_mod(s
->frame_timer
, t_now
+ frame_t
);
1172 static const MemoryRegionOps uhci_ioport_ops
= {
1173 .read
= uhci_port_read
,
1174 .write
= uhci_port_write
,
1175 .valid
.min_access_size
= 1,
1176 .valid
.max_access_size
= 4,
1177 .impl
.min_access_size
= 2,
1178 .impl
.max_access_size
= 2,
1179 .endianness
= DEVICE_LITTLE_ENDIAN
,
1182 static USBPortOps uhci_port_ops
= {
1183 .attach
= uhci_attach
,
1184 .detach
= uhci_detach
,
1185 .child_detach
= uhci_child_detach
,
1186 .wakeup
= uhci_wakeup
,
1187 .complete
= uhci_async_complete
,
1190 static USBBusOps uhci_bus_ops
= {
1193 static int usb_uhci_common_initfn(PCIDevice
*dev
)
1195 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1196 UHCIPCIDeviceClass
*u
= container_of(pc
, UHCIPCIDeviceClass
, parent_class
);
1197 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1198 uint8_t *pci_conf
= s
->dev
.config
;
1201 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1202 /* TODO: reset value should be 0. */
1203 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1205 pci_config_set_interrupt_pin(pci_conf
, u
->info
.irq_pin
+ 1);
1208 USBPort
*ports
[NB_PORTS
];
1209 for(i
= 0; i
< NB_PORTS
; i
++) {
1210 ports
[i
] = &s
->ports
[i
].port
;
1212 if (usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1213 s
->firstport
, s
, &uhci_port_ops
,
1214 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1218 usb_bus_new(&s
->bus
, sizeof(s
->bus
), &uhci_bus_ops
, DEVICE(dev
));
1219 for (i
= 0; i
< NB_PORTS
; i
++) {
1220 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1221 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1224 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1225 s
->frame_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, uhci_frame_timer
, s
);
1226 s
->num_ports_vmstate
= NB_PORTS
;
1227 QTAILQ_INIT(&s
->queues
);
1229 qemu_register_reset(uhci_reset
, s
);
1231 memory_region_init_io(&s
->io_bar
, OBJECT(s
), &uhci_ioport_ops
, s
,
1234 /* Use region 4 for consistency with real hardware. BSD guests seem
1236 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1241 static int usb_uhci_vt82c686b_initfn(PCIDevice
*dev
)
1243 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1244 uint8_t *pci_conf
= s
->dev
.config
;
1246 /* USB misc control 1/2 */
1247 pci_set_long(pci_conf
+ 0x40,0x00001000);
1249 pci_set_long(pci_conf
+ 0x80,0x00020001);
1250 /* USB legacy support */
1251 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1253 return usb_uhci_common_initfn(dev
);
1256 static void usb_uhci_exit(PCIDevice
*dev
)
1258 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1260 trace_usb_uhci_exit();
1262 if (s
->frame_timer
) {
1263 timer_del(s
->frame_timer
);
1264 timer_free(s
->frame_timer
);
1265 s
->frame_timer
= NULL
;
1269 qemu_bh_delete(s
->bh
);
1272 uhci_async_cancel_all(s
);
1274 if (!s
->masterbus
) {
1275 usb_bus_release(&s
->bus
);
1279 static Property uhci_properties_companion
[] = {
1280 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1281 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1282 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1283 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1284 DEFINE_PROP_END_OF_LIST(),
1286 static Property uhci_properties_standalone
[] = {
1287 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1288 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1289 DEFINE_PROP_END_OF_LIST(),
1292 static void uhci_class_init(ObjectClass
*klass
, void *data
)
1294 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1295 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1296 UHCIPCIDeviceClass
*u
= container_of(k
, UHCIPCIDeviceClass
, parent_class
);
1297 UHCIInfo
*info
= data
;
1299 k
->init
= info
->initfn
? info
->initfn
: usb_uhci_common_initfn
;
1300 k
->exit
= info
->unplug
? usb_uhci_exit
: NULL
;
1301 k
->vendor_id
= info
->vendor_id
;
1302 k
->device_id
= info
->device_id
;
1303 k
->revision
= info
->revision
;
1304 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1305 dc
->vmsd
= &vmstate_uhci
;
1306 if (!info
->unplug
) {
1307 /* uhci controllers in companion setups can't be hotplugged */
1308 dc
->hotpluggable
= false;
1309 dc
->props
= uhci_properties_companion
;
1311 dc
->props
= uhci_properties_standalone
;
1313 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
1317 static UHCIInfo uhci_info
[] = {
1319 .name
= "piix3-usb-uhci",
1320 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1321 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
,
1326 .name
= "piix4-usb-uhci",
1327 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1328 .device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
,
1333 .name
= "vt82c686b-usb-uhci",
1334 .vendor_id
= PCI_VENDOR_ID_VIA
,
1335 .device_id
= PCI_DEVICE_ID_VIA_UHCI
,
1338 .initfn
= usb_uhci_vt82c686b_initfn
,
1341 .name
= "ich9-usb-uhci1", /* 00:1d.0 */
1342 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1343 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
,
1348 .name
= "ich9-usb-uhci2", /* 00:1d.1 */
1349 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1350 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
,
1355 .name
= "ich9-usb-uhci3", /* 00:1d.2 */
1356 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1357 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
,
1362 .name
= "ich9-usb-uhci4", /* 00:1a.0 */
1363 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1364 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI4
,
1369 .name
= "ich9-usb-uhci5", /* 00:1a.1 */
1370 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1371 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI5
,
1376 .name
= "ich9-usb-uhci6", /* 00:1a.2 */
1377 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1378 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI6
,
1385 static void uhci_register_types(void)
1387 TypeInfo uhci_type_info
= {
1388 .parent
= TYPE_PCI_DEVICE
,
1389 .instance_size
= sizeof(UHCIState
),
1390 .class_size
= sizeof(UHCIPCIDeviceClass
),
1391 .class_init
= uhci_class_init
,
1395 for (i
= 0; i
< ARRAY_SIZE(uhci_info
); i
++) {
1396 uhci_type_info
.name
= uhci_info
[i
].name
;
1397 uhci_type_info
.class_data
= uhci_info
+ i
;
1398 type_register(&uhci_type_info
);
1402 type_init(uhci_register_types
)