hw/intc/arm_gicv2m.c

   1 /*
   2  *  GICv2m extension for MSI/MSI-x support with a GICv2-based system
   3  *
   4  * Copyright (C) 2015 Linaro, All rights reserved.
   5  *
   6  * Author: Christoffer Dall <christoffer.dall@linaro.org>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /* This file implements an emulated GICv2m widget as described in the ARM
  23  * Server Base System Architecture (SBSA) specification Version 2.2
  24  * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
  25  * identification registers and with a single non-secure MSI register frame.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/pci/msi.h"
  31
  32 #define TYPE_ARM_GICV2M "arm-gicv2m"
  33 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M)
  34
  35 #define GICV2M_NUM_SPI_MAX 128
  36
  37 #define V2M_MSI_TYPER           0x008
  38 #define V2M_MSI_SETSPI_NS       0x040
  39 #define V2M_MSI_IIDR            0xFCC
  40 #define V2M_IIDR0               0xFD0
  41 #define V2M_IIDR11              0xFFC
  42
  43 #define PRODUCT_ID_QEMU         0x51 /* ASCII code Q */
  44
  45 typedef struct ARMGICv2mState {
  46     SysBusDevice parent_obj;
  47
  48     MemoryRegion iomem;
  49     qemu_irq spi[GICV2M_NUM_SPI_MAX];
  50
  51     uint32_t base_spi;
  52     uint32_t num_spi;
  53 } ARMGICv2mState;
  54
  55 static void gicv2m_set_irq(void *opaque, int irq)
  56 {
  57     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  58
  59     qemu_irq_pulse(s->spi[irq]);
  60 }
  61
  62 static uint64_t gicv2m_read(void *opaque, hwaddr offset,
  63                             unsigned size)
  64 {
  65     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  66     uint32_t val;
  67
  68     if (size != 4) {
  69         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size);
  70         return 0;
  71     }
  72
  73     switch (offset) {
  74     case V2M_MSI_TYPER:
  75         val = (s->base_spi + 32) << 16;
  76         val |= s->num_spi;
  77         return val;
  78     case V2M_MSI_IIDR:
  79         /* We don't have any valid implementor so we leave that field as zero
  80          * and we return 0 in the arch revision as per the spec.
  81          */
  82         return (PRODUCT_ID_QEMU << 20);
  83     case V2M_IIDR0 ... V2M_IIDR11:
  84         /* We do not implement any optional identification registers and the
  85          * mandatory MSI_PIDR2 register reads as 0x0, so we capture all
  86          * implementation defined registers here.
  87          */
  88         return 0;
  89     default:
  90         qemu_log_mask(LOG_GUEST_ERROR,
  91                       "gicv2m_read: Bad offset %x\n", (int)offset);
  92         return 0;
  93     }
  94 }
  95
  96 static void gicv2m_write(void *opaque, hwaddr offset,
  97                         uint64_t value, unsigned size)
  98 {
  99     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
 100
 101     if (size != 2 && size != 4) {
 102         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size);
 103         return;
 104     }
 105
 106     switch (offset) {
 107     case V2M_MSI_SETSPI_NS: {
 108         int spi;
 109
 110         spi = (value & 0x3ff) - (s->base_spi + 32);
 111         if (spi >= 0 && spi < s->num_spi) {
 112             gicv2m_set_irq(s, spi);
 113         }
 114         return;
 115     }
 116     default:
 117         qemu_log_mask(LOG_GUEST_ERROR,
 118                       "gicv2m_write: Bad offset %x\n", (int)offset);
 119     }
 120 }
 121
 122 static const MemoryRegionOps gicv2m_ops = {
 123     .read = gicv2m_read,
 124     .write = gicv2m_write,
 125     .endianness = DEVICE_LITTLE_ENDIAN,
 126 };
 127
 128 static void gicv2m_realize(DeviceState *dev, Error **errp)
 129 {
 130     ARMGICv2mState *s = ARM_GICV2M(dev);
 131     int i;
 132
 133     if (s->num_spi > GICV2M_NUM_SPI_MAX) {
 134         error_setg(errp,
 135                    "requested %u SPIs exceeds GICv2m frame maximum %d",
 136                    s->num_spi, GICV2M_NUM_SPI_MAX);
 137         return;
 138     }
 139
 140     if (s->base_spi + 32 > 1020 - s->num_spi) {
 141         error_setg(errp,
 142                    "requested base SPI %u+%u exceeds max. number 1020",
 143                    s->base_spi + 32, s->num_spi);
 144         return;
 145     }
 146
 147     for (i = 0; i < s->num_spi; i++) {
 148         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]);
 149     }
 150
 151     msi_nonbroken = true;
 152     kvm_gsi_direct_mapping = true;
 153     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 154 }
 155
 156 static void gicv2m_init(Object *obj)
 157 {
 158     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 159     ARMGICv2mState *s = ARM_GICV2M(obj);
 160
 161     memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s,
 162                           "gicv2m", 0x1000);
 163     sysbus_init_mmio(sbd, &s->iomem);
 164 }
 165
 166 static Property gicv2m_properties[] = {
 167     DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
 168     DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
 169     DEFINE_PROP_END_OF_LIST(),
 170 };
 171
 172 static void gicv2m_class_init(ObjectClass *klass, void *data)
 173 {
 174     DeviceClass *dc = DEVICE_CLASS(klass);
 175
 176     dc->props = gicv2m_properties;
 177     dc->realize = gicv2m_realize;
 178 }
 179
 180 static const TypeInfo gicv2m_info = {
 181     .name          = TYPE_ARM_GICV2M,
 182     .parent        = TYPE_SYS_BUS_DEVICE,
 183     .instance_size = sizeof(ARMGICv2mState),
 184     .instance_init = gicv2m_init,
 185     .class_init    = gicv2m_class_init,
 186 };
 187
 188 static void gicv2m_register_types(void)
 189 {
 190     type_register_static(&gicv2m_info);
 191 }
 192
 193 type_init(gicv2m_register_types)