include/hw/ppc/spapr.h

   1 #if !defined(__HW_SPAPR_H__)
   2 #define __HW_SPAPR_H__
   3
   4 #include "sysemu/dma.h"
   5 #include "hw/ppc/xics.h"
   6
   7 struct VIOsPAPRBus;
   8 struct sPAPRPHBState;
   9 struct sPAPRNVRAM;
  10
  11 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  12
  13 typedef struct sPAPREnvironment {
  14     struct VIOsPAPRBus *vio_bus;
  15     QLIST_HEAD(, sPAPRPHBState) phbs;
  16     struct sPAPRNVRAM *nvram;
  17     XICSState *icp;
  18
  19     hwaddr ram_limit;
  20     void *htab;
  21     uint32_t htab_shift;
  22     hwaddr rma_size;
  23     int vrma_adjust;
  24     hwaddr fdt_addr, rtas_addr;
  25     ssize_t rtas_size;
  26     void *rtas_blob;
  27     void *fdt_skel;
  28     target_ulong entry_point;
  29     uint64_t rtc_offset;
  30     struct PPCTimebase tb;
  31     bool has_graphics;
  32
  33     uint32_t epow_irq;
  34     Notifier epow_notifier;
  35
  36     /* Migration state */
  37     int htab_save_index;
  38     bool htab_first_pass;
  39     int htab_fd;
  40 } sPAPREnvironment;
  41
  42 #define H_SUCCESS         0
  43 #define H_BUSY            1        /* Hardware busy -- retry later */
  44 #define H_CLOSED          2        /* Resource closed */
  45 #define H_NOT_AVAILABLE   3
  46 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
  47 #define H_PARTIAL         5
  48 #define H_IN_PROGRESS     14       /* Kind of like busy */
  49 #define H_PAGE_REGISTERED 15
  50 #define H_PARTIAL_STORE   16
  51 #define H_PENDING         17       /* returned from H_POLL_PENDING */
  52 #define H_CONTINUE        18       /* Returned from H_Join on success */
  53 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
  54 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
  55                                                  is a good time to retry */
  56 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
  57                                                  is a good time to retry */
  58 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
  59                                                  is a good time to retry */
  60 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
  61                                                  is a good time to retry */
  62 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
  63                                                  is a good time to retry */
  64 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
  65                                                  is a good time to retry */
  66 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
  67 #define H_HARDWARE        -1       /* Hardware error */
  68 #define H_FUNCTION        -2       /* Function not supported */
  69 #define H_PRIVILEGE       -3       /* Caller not privileged */
  70 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
  71 #define H_BAD_MODE        -5       /* Illegal msr value */
  72 #define H_PTEG_FULL       -6       /* PTEG is full */
  73 #define H_NOT_FOUND       -7       /* PTE was not found" */
  74 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
  75 #define H_NO_MEM          -9
  76 #define H_AUTHORITY       -10
  77 #define H_PERMISSION      -11
  78 #define H_DROPPED         -12
  79 #define H_SOURCE_PARM     -13
  80 #define H_DEST_PARM       -14
  81 #define H_REMOTE_PARM     -15
  82 #define H_RESOURCE        -16
  83 #define H_ADAPTER_PARM    -17
  84 #define H_RH_PARM         -18
  85 #define H_RCQ_PARM        -19
  86 #define H_SCQ_PARM        -20
  87 #define H_EQ_PARM         -21
  88 #define H_RT_PARM         -22
  89 #define H_ST_PARM         -23
  90 #define H_SIGT_PARM       -24
  91 #define H_TOKEN_PARM      -25
  92 #define H_MLENGTH_PARM    -27
  93 #define H_MEM_PARM        -28
  94 #define H_MEM_ACCESS_PARM -29
  95 #define H_ATTR_PARM       -30
  96 #define H_PORT_PARM       -31
  97 #define H_MCG_PARM        -32
  98 #define H_VL_PARM         -33
  99 #define H_TSIZE_PARM      -34
 100 #define H_TRACE_PARM      -35
 101
 102 #define H_MASK_PARM       -37
 103 #define H_MCG_FULL        -38
 104 #define H_ALIAS_EXIST     -39
 105 #define H_P_COUNTER       -40
 106 #define H_TABLE_FULL      -41
 107 #define H_ALT_TABLE       -42
 108 #define H_MR_CONDITION    -43
 109 #define H_NOT_ENOUGH_RESOURCES -44
 110 #define H_R_STATE         -45
 111 #define H_RESCINDEND      -46
 112 #define H_P2              -55
 113 #define H_P3              -56
 114 #define H_P4              -57
 115 #define H_P5              -58
 116 #define H_P6              -59
 117 #define H_P7              -60
 118 #define H_P8              -61
 119 #define H_P9              -62
 120 #define H_UNSUPPORTED_FLAG -256
 121 #define H_MULTI_THREADS_ACTIVE -9005
 122
 123
 124 /* Long Busy is a condition that can be returned by the firmware
 125  * when a call cannot be completed now, but the identical call
 126  * should be retried later.  This prevents calls blocking in the
 127  * firmware for long periods of time.  Annoyingly the firmware can return
 128  * a range of return codes, hinting at how long we should wait before
 129  * retrying.  If you don't care for the hint, the macro below is a good
 130  * way to check for the long_busy return codes
 131  */
 132 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 133                             && (x <= H_LONG_BUSY_END_RANGE))
 134
 135 /* Flags */
 136 #define H_LARGE_PAGE      (1ULL<<(63-16))
 137 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 138 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 139 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 140 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 141 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 142 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 143 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 144 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 145 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 146 #define H_ANDCOND         (1ULL<<(63-33))
 147 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 148 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 149 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 150 #define H_COPY_PAGE       (1ULL<<(63-49))
 151 #define H_N               (1ULL<<(63-61))
 152 #define H_PP1             (1ULL<<(63-62))
 153 #define H_PP2             (1ULL<<(63-63))
 154
 155 /* Values for 2nd argument to H_SET_MODE */
 156 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 157 #define H_SET_MODE_RESOURCE_SET_DAWR            2
 158 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 159 #define H_SET_MODE_RESOURCE_LE                  4
 160
 161 /* Flags for H_SET_MODE_RESOURCE_LE */
 162 #define H_SET_MODE_ENDIAN_BIG    0
 163 #define H_SET_MODE_ENDIAN_LITTLE 1
 164
 165 /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
 166 #define H_SET_MODE_ADDR_TRANS_NONE                  0
 167 #define H_SET_MODE_ADDR_TRANS_0001_8000             2
 168 #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000   3
 169
 170 /* VASI States */
 171 #define H_VASI_INVALID    0
 172 #define H_VASI_ENABLED    1
 173 #define H_VASI_ABORTED    2
 174 #define H_VASI_SUSPENDING 3
 175 #define H_VASI_SUSPENDED  4
 176 #define H_VASI_RESUMED    5
 177 #define H_VASI_COMPLETED  6
 178
 179 /* DABRX flags */
 180 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 181 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 182 #define H_DABRX_USER       (1ULL<<(63-63))
 183
 184 /* Each control block has to be on a 4K boundary */
 185 #define H_CB_ALIGNMENT     4096
 186
 187 /* pSeries hypervisor opcodes */
 188 #define H_REMOVE                0x04
 189 #define H_ENTER                 0x08
 190 #define H_READ                  0x0c
 191 #define H_CLEAR_MOD             0x10
 192 #define H_CLEAR_REF             0x14
 193 #define H_PROTECT               0x18
 194 #define H_GET_TCE               0x1c
 195 #define H_PUT_TCE               0x20
 196 #define H_SET_SPRG0             0x24
 197 #define H_SET_DABR              0x28
 198 #define H_PAGE_INIT             0x2c
 199 #define H_SET_ASR               0x30
 200 #define H_ASR_ON                0x34
 201 #define H_ASR_OFF               0x38
 202 #define H_LOGICAL_CI_LOAD       0x3c
 203 #define H_LOGICAL_CI_STORE      0x40
 204 #define H_LOGICAL_CACHE_LOAD    0x44
 205 #define H_LOGICAL_CACHE_STORE   0x48
 206 #define H_LOGICAL_ICBI          0x4c
 207 #define H_LOGICAL_DCBF          0x50
 208 #define H_GET_TERM_CHAR         0x54
 209 #define H_PUT_TERM_CHAR         0x58
 210 #define H_REAL_TO_LOGICAL       0x5c
 211 #define H_HYPERVISOR_DATA       0x60
 212 #define H_EOI                   0x64
 213 #define H_CPPR                  0x68
 214 #define H_IPI                   0x6c
 215 #define H_IPOLL                 0x70
 216 #define H_XIRR                  0x74
 217 #define H_PERFMON               0x7c
 218 #define H_MIGRATE_DMA           0x78
 219 #define H_REGISTER_VPA          0xDC
 220 #define H_CEDE                  0xE0
 221 #define H_CONFER                0xE4
 222 #define H_PROD                  0xE8
 223 #define H_GET_PPP               0xEC
 224 #define H_SET_PPP               0xF0
 225 #define H_PURR                  0xF4
 226 #define H_PIC                   0xF8
 227 #define H_REG_CRQ               0xFC
 228 #define H_FREE_CRQ              0x100
 229 #define H_VIO_SIGNAL            0x104
 230 #define H_SEND_CRQ              0x108
 231 #define H_COPY_RDMA             0x110
 232 #define H_REGISTER_LOGICAL_LAN  0x114
 233 #define H_FREE_LOGICAL_LAN      0x118
 234 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 235 #define H_SEND_LOGICAL_LAN      0x120
 236 #define H_BULK_REMOVE           0x124
 237 #define H_MULTICAST_CTRL        0x130
 238 #define H_SET_XDABR             0x134
 239 #define H_STUFF_TCE             0x138
 240 #define H_PUT_TCE_INDIRECT      0x13C
 241 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 242 #define H_VTERM_PARTNER_INFO    0x150
 243 #define H_REGISTER_VTERM        0x154
 244 #define H_FREE_VTERM            0x158
 245 #define H_RESET_EVENTS          0x15C
 246 #define H_ALLOC_RESOURCE        0x160
 247 #define H_FREE_RESOURCE         0x164
 248 #define H_MODIFY_QP             0x168
 249 #define H_QUERY_QP              0x16C
 250 #define H_REREGISTER_PMR        0x170
 251 #define H_REGISTER_SMR          0x174
 252 #define H_QUERY_MR              0x178
 253 #define H_QUERY_MW              0x17C
 254 #define H_QUERY_HCA             0x180
 255 #define H_QUERY_PORT            0x184
 256 #define H_MODIFY_PORT           0x188
 257 #define H_DEFINE_AQP1           0x18C
 258 #define H_GET_TRACE_BUFFER      0x190
 259 #define H_DEFINE_AQP0           0x194
 260 #define H_RESIZE_MR             0x198
 261 #define H_ATTACH_MCQP           0x19C
 262 #define H_DETACH_MCQP           0x1A0
 263 #define H_CREATE_RPT            0x1A4
 264 #define H_REMOVE_RPT            0x1A8
 265 #define H_REGISTER_RPAGES       0x1AC
 266 #define H_DISABLE_AND_GETC      0x1B0
 267 #define H_ERROR_DATA            0x1B4
 268 #define H_GET_HCA_INFO          0x1B8
 269 #define H_GET_PERF_COUNT        0x1BC
 270 #define H_MANAGE_TRACE          0x1C0
 271 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 272 #define H_QUERY_INT_STATE       0x1E4
 273 #define H_POLL_PENDING          0x1D8
 274 #define H_ILLAN_ATTRIBUTES      0x244
 275 #define H_MODIFY_HEA_QP         0x250
 276 #define H_QUERY_HEA_QP          0x254
 277 #define H_QUERY_HEA             0x258
 278 #define H_QUERY_HEA_PORT        0x25C
 279 #define H_MODIFY_HEA_PORT       0x260
 280 #define H_REG_BCMC              0x264
 281 #define H_DEREG_BCMC            0x268
 282 #define H_REGISTER_HEA_RPAGES   0x26C
 283 #define H_DISABLE_AND_GET_HEA   0x270
 284 #define H_GET_HEA_INFO          0x274
 285 #define H_ALLOC_HEA_RESOURCE    0x278
 286 #define H_ADD_CONN              0x284
 287 #define H_DEL_CONN              0x288
 288 #define H_JOIN                  0x298
 289 #define H_VASI_STATE            0x2A4
 290 #define H_ENABLE_CRQ            0x2B0
 291 #define H_GET_EM_PARMS          0x2B8
 292 #define H_SET_MPP               0x2D0
 293 #define H_GET_MPP               0x2D4
 294 #define H_XIRR_X                0x2FC
 295 #define H_SET_MODE              0x31C
 296 #define MAX_HCALL_OPCODE        H_SET_MODE
 297
 298 /* The hcalls above are standardized in PAPR and implemented by pHyp
 299  * as well.
 300  *
 301  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 302  * So far we just need one for H_RTAS, but in future we'll need more
 303  * for extensions like virtio.  We put those into the 0xf000-0xfffc
 304  * range which is reserved by PAPR for "platform-specific" hcalls.
 305  */
 306 #define KVMPPC_HCALL_BASE       0xf000
 307 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 308 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 309 /* Client Architecture support */
 310 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 311 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
 312
 313 extern sPAPREnvironment *spapr;
 314
 315 typedef struct sPAPRDeviceTreeUpdateHeader {
 316     uint32_t version_id;
 317 } sPAPRDeviceTreeUpdateHeader;
 318
 319 /*#define DEBUG_SPAPR_HCALLS*/
 320
 321 #ifdef DEBUG_SPAPR_HCALLS
 322 #define hcall_dprintf(fmt, ...) \
 323     do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0)
 324 #else
 325 #define hcall_dprintf(fmt, ...) \
 326     do { } while (0)
 327 #endif
 328
 329 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 330                                        target_ulong opcode,
 331                                        target_ulong *args);
 332
 333 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 334 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 335                              target_ulong *args);
 336
 337 int spapr_allocate_irq(int hint, bool lsi);
 338 int spapr_allocate_irq_block(int num, bool lsi, bool msi);
 339
 340 /* RTAS return codes */
 341 #define RTAS_OUT_SUCCESS            0
 342 #define RTAS_OUT_NO_ERRORS_FOUND    1
 343 #define RTAS_OUT_HW_ERROR           -1
 344 #define RTAS_OUT_BUSY               -2
 345 #define RTAS_OUT_PARAM_ERROR        -3
 346 #define RTAS_OUT_NOT_SUPPORTED      -3
 347 #define RTAS_OUT_NOT_AUTHORIZED     -9002
 348
 349 /* RTAS tokens */
 350 #define RTAS_TOKEN_BASE      0x2000
 351
 352 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 353 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 354 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 355 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 356 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 357 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 358 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 359 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 360 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 361 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 362 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 363 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 364 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 365 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 366 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 367 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 368 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 369 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 370 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 371 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 372 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 373 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 374 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 375 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 376 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 377 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 378 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 379 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 380 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 381 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 382 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 383 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 384
 385 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x20)
 386
 387 /* RTAS ibm,get-system-parameter token values */
 388 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 389 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 390 #define RTAS_SYSPARM_UUID                        48
 391
 392 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 393  * of the RTAS ibm,get-system-parameter call.
 394  */
 395 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 396 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 397 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 398 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 399
 400 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 401 {
 402     return addr & ~0xF000000000000000ULL;
 403 }
 404
 405 static inline uint32_t rtas_ld(target_ulong phys, int n)
 406 {
 407     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 408 }
 409
 410 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 411 {
 412     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 413 }
 414
 415
 416 static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len,
 417                                   uint8_t *buffer, uint16_t buffer_len)
 418 {
 419     if (phys_len < 2) {
 420         return;
 421     }
 422     stw_be_phys(&address_space_memory,
 423                 ppc64_phys_to_real(phys), buffer_len);
 424     cpu_physical_memory_write(ppc64_phys_to_real(phys + 2),
 425                               buffer, MIN(buffer_len, phys_len - 2));
 426 }
 427
 428 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 429                               uint32_t token,
 430                               uint32_t nargs, target_ulong args,
 431                               uint32_t nret, target_ulong rets);
 432 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 433 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 434                              uint32_t token, uint32_t nargs, target_ulong args,
 435                              uint32_t nret, target_ulong rets);
 436 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
 437                                  hwaddr rtas_size);
 438
 439 #define SPAPR_TCE_PAGE_SHIFT   12
 440 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 441 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 442
 443 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 444 #define SPAPR_PCI_BASE_LIOBN    0x80000000
 445
 446 #define RTAS_ERROR_LOG_MAX      2048
 447
 448 typedef struct sPAPRTCETable sPAPRTCETable;
 449
 450 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 451 #define SPAPR_TCE_TABLE(obj) \
 452     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
 453
 454 struct sPAPRTCETable {
 455     DeviceState parent;
 456     uint32_t liobn;
 457     uint32_t nb_table;
 458     uint64_t bus_offset;
 459     uint32_t page_shift;
 460     uint64_t *table;
 461     bool bypass;
 462     bool vfio_accel;
 463     int fd;
 464     MemoryRegion iommu;
 465     QLIST_ENTRY(sPAPRTCETable) list;
 466 };
 467
 468 void spapr_events_init(sPAPREnvironment *spapr);
 469 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
 470 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size);
 471 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
 472                                    uint64_t bus_offset,
 473                                    uint32_t page_shift,
 474                                    uint32_t nb_table,
 475                                    bool vfio_accel);
 476 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
 477 void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass);
 478 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 479                  uint32_t liobn, uint64_t window, uint32_t size);
 480 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 481                       sPAPRTCETable *tcet);
 482
 483 #endif /* !defined (__HW_SPAPR_H__) */