hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  */
  13
  14 #include "hw.h"
  15 #include "msix.h"
  16 #include "pci.h"
  17 #include "range.h"
  18
  19 #define MSIX_CAP_LENGTH 12
  20
  21 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  22 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  23 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  24 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  25
  26 /* How much space does an MSIX table need. */
  27 /* The spec requires giving the table structure
  28  * a 4K aligned region all by itself. */
  29 #define MSIX_PAGE_SIZE 0x1000
  30 /* Reserve second half of the page for pending bits */
  31 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
  32 #define MSIX_MAX_ENTRIES 32
  33
  34
  35 /* Flag for interrupt controller to declare MSI-X support */
  36 int msix_supported;
  37
  38 /* Add MSI-X capability to the config space for the device. */
  39 /* Given a bar and its size, add MSI-X table on top of it
  40  * and fill MSI-X capability in the config space.
  41  * Original bar size must be a power of 2 or 0.
  42  * New bar size is returned. */
  43 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
  44                            unsigned bar_nr, unsigned bar_size)
  45 {
  46     int config_offset;
  47     uint8_t *config;
  48     uint32_t new_size;
  49
  50     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
  51         return -EINVAL;
  52     if (bar_size > 0x80000000)
  53         return -ENOSPC;
  54
  55     /* Add space for MSI-X structures */
  56     if (!bar_size) {
  57         new_size = MSIX_PAGE_SIZE;
  58     } else if (bar_size < MSIX_PAGE_SIZE) {
  59         bar_size = MSIX_PAGE_SIZE;
  60         new_size = MSIX_PAGE_SIZE * 2;
  61     } else {
  62         new_size = bar_size * 2;
  63     }
  64
  65     pdev->msix_bar_size = new_size;
  66     config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
  67                                        0, MSIX_CAP_LENGTH);
  68     if (config_offset < 0)
  69         return config_offset;
  70     config = pdev->config + config_offset;
  71
  72     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
  73     /* Table on top of BAR */
  74     pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
  75     /* Pending bits on top of that */
  76     pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
  77                  bar_nr);
  78     pdev->msix_cap = config_offset;
  79     /* Make flags bit writable. */
  80     pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
  81             MSIX_MASKALL_MASK;
  82     return 0;
  83 }
  84
  85 static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
  86                                unsigned size)
  87 {
  88     PCIDevice *dev = opaque;
  89     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
  90     void *page = dev->msix_table_page;
  91
  92     return pci_get_long(page + offset);
  93 }
  94
  95 static uint8_t msix_pending_mask(int vector)
  96 {
  97     return 1 << (vector % 8);
  98 }
  99
 100 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 101 {
 102     return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
 103 }
 104
 105 static int msix_is_pending(PCIDevice *dev, int vector)
 106 {
 107     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 108 }
 109
 110 static void msix_set_pending(PCIDevice *dev, int vector)
 111 {
 112     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 113 }
 114
 115 static void msix_clr_pending(PCIDevice *dev, int vector)
 116 {
 117     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 118 }
 119
 120 static int msix_function_masked(PCIDevice *dev)
 121 {
 122     return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
 123 }
 124
 125 static int msix_is_masked(PCIDevice *dev, int vector)
 126 {
 127     unsigned offset =
 128         vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 129     return msix_function_masked(dev) ||
 130            dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
 131 }
 132
 133 static void msix_handle_mask_update(PCIDevice *dev, int vector)
 134 {
 135     if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
 136         msix_clr_pending(dev, vector);
 137         msix_notify(dev, vector);
 138     }
 139 }
 140
 141 /* Handle MSI-X capability config write. */
 142 void msix_write_config(PCIDevice *dev, uint32_t addr,
 143                        uint32_t val, int len)
 144 {
 145     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 146     int vector;
 147
 148     if (!range_covers_byte(addr, len, enable_pos)) {
 149         return;
 150     }
 151
 152     if (!msix_enabled(dev)) {
 153         return;
 154     }
 155
 156     pci_device_deassert_intx(dev);
 157
 158     if (msix_function_masked(dev)) {
 159         return;
 160     }
 161
 162     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 163         msix_handle_mask_update(dev, vector);
 164     }
 165 }
 166
 167 static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
 168                             uint64_t val, unsigned size)
 169 {
 170     PCIDevice *dev = opaque;
 171     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 172     int vector = offset / PCI_MSIX_ENTRY_SIZE;
 173     pci_set_long(dev->msix_table_page + offset, val);
 174     msix_handle_mask_update(dev, vector);
 175 }
 176
 177 static const MemoryRegionOps msix_mmio_ops = {
 178     .read = msix_mmio_read,
 179     .write = msix_mmio_write,
 180     .endianness = DEVICE_NATIVE_ENDIAN,
 181     .valid = {
 182         .min_access_size = 4,
 183         .max_access_size = 4,
 184     },
 185 };
 186
 187 static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
 188 {
 189     uint8_t *config = d->config + d->msix_cap;
 190     uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
 191     uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
 192     /* TODO: for assigned devices, we'll want to make it possible to map
 193      * pending bits separately in case they are in a separate bar. */
 194
 195     memory_region_add_subregion(bar, offset, &d->msix_mmio);
 196 }
 197
 198 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 199 {
 200     int vector;
 201     for (vector = 0; vector < nentries; ++vector) {
 202         unsigned offset =
 203             vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 204         dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 205     }
 206 }
 207
 208 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 209  * modified, it should be retrieved with msix_bar_size. */
 210 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 211               MemoryRegion *bar,
 212               unsigned bar_nr, unsigned bar_size)
 213 {
 214     int ret;
 215     /* Nothing to do if MSI is not supported by interrupt controller */
 216     if (!msix_supported)
 217         return -ENOTSUP;
 218
 219     if (nentries > MSIX_MAX_ENTRIES)
 220         return -EINVAL;
 221
 222     dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
 223                                         sizeof *dev->msix_entry_used);
 224
 225     dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
 226     msix_mask_all(dev, nentries);
 227
 228     memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
 229                           "msix", MSIX_PAGE_SIZE);
 230
 231     dev->msix_entries_nr = nentries;
 232     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 233     if (ret)
 234         goto err_config;
 235
 236     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 237     msix_mmio_setup(dev, bar);
 238     return 0;
 239
 240 err_config:
 241     dev->msix_entries_nr = 0;
 242     memory_region_destroy(&dev->msix_mmio);
 243     g_free(dev->msix_table_page);
 244     dev->msix_table_page = NULL;
 245     g_free(dev->msix_entry_used);
 246     dev->msix_entry_used = NULL;
 247     return ret;
 248 }
 249
 250 static void msix_free_irq_entries(PCIDevice *dev)
 251 {
 252     int vector;
 253
 254     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 255         dev->msix_entry_used[vector] = 0;
 256         msix_clr_pending(dev, vector);
 257     }
 258 }
 259
 260 /* Clean up resources for the device. */
 261 int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
 262 {
 263     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 264         return 0;
 265     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 266     dev->msix_cap = 0;
 267     msix_free_irq_entries(dev);
 268     dev->msix_entries_nr = 0;
 269     memory_region_del_subregion(bar, &dev->msix_mmio);
 270     memory_region_destroy(&dev->msix_mmio);
 271     g_free(dev->msix_table_page);
 272     dev->msix_table_page = NULL;
 273     g_free(dev->msix_entry_used);
 274     dev->msix_entry_used = NULL;
 275     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 276     return 0;
 277 }
 278
 279 void msix_save(PCIDevice *dev, QEMUFile *f)
 280 {
 281     unsigned n = dev->msix_entries_nr;
 282
 283     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 284         return;
 285     }
 286
 287     qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 288     qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 289 }
 290
 291 /* Should be called after restoring the config space. */
 292 void msix_load(PCIDevice *dev, QEMUFile *f)
 293 {
 294     unsigned n = dev->msix_entries_nr;
 295
 296     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 297         return;
 298     }
 299
 300     msix_free_irq_entries(dev);
 301     qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 302     qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 303 }
 304
 305 /* Does device support MSI-X? */
 306 int msix_present(PCIDevice *dev)
 307 {
 308     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 309 }
 310
 311 /* Is MSI-X enabled? */
 312 int msix_enabled(PCIDevice *dev)
 313 {
 314     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 315         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 316          MSIX_ENABLE_MASK);
 317 }
 318
 319 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 320 uint32_t msix_bar_size(PCIDevice *dev)
 321 {
 322     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 323         dev->msix_bar_size : 0;
 324 }
 325
 326 /* Send an MSI-X message */
 327 void msix_notify(PCIDevice *dev, unsigned vector)
 328 {
 329     uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
 330     uint64_t address;
 331     uint32_t data;
 332
 333     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 334         return;
 335     if (msix_is_masked(dev, vector)) {
 336         msix_set_pending(dev, vector);
 337         return;
 338     }
 339
 340     address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
 341     data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
 342     stl_le_phys(address, data);
 343 }
 344
 345 void msix_reset(PCIDevice *dev)
 346 {
 347     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 348         return;
 349     msix_free_irq_entries(dev);
 350     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 351             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 352     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
 353     msix_mask_all(dev, dev->msix_entries_nr);
 354 }
 355
 356 /* PCI spec suggests that devices make it possible for software to configure
 357  * less vectors than supported by the device, but does not specify a standard
 358  * mechanism for devices to do so.
 359  *
 360  * We support this by asking devices to declare vectors software is going to
 361  * actually use, and checking this on the notification path. Devices that
 362  * don't want to follow the spec suggestion can declare all vectors as used. */
 363
 364 /* Mark vector as used. */
 365 int msix_vector_use(PCIDevice *dev, unsigned vector)
 366 {
 367     if (vector >= dev->msix_entries_nr)
 368         return -EINVAL;
 369     dev->msix_entry_used[vector]++;
 370     return 0;
 371 }
 372
 373 /* Mark vector as unused. */
 374 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 375 {
 376     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 377         return;
 378     }
 379     if (--dev->msix_entry_used[vector]) {
 380         return;
 381     }
 382     msix_clr_pending(dev, vector);
 383 }
 384
 385 void msix_unuse_all_vectors(PCIDevice *dev)
 386 {
 387     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 388         return;
 389     msix_free_irq_entries(dev);
 390 }