2 * Calxeda Highbank SoC emulation
4 * Copyright (c) 2010-2012 Calxeda
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "hw/sysbus.h"
21 #include "hw/arm/arm.h"
22 #include "hw/devices.h"
23 #include "hw/loader.h"
25 #include "sysemu/sysemu.h"
26 #include "hw/boards.h"
27 #include "sysemu/blockdev.h"
28 #include "exec/address-spaces.h"
29 #include "qemu/error-report.h"
31 #define SMP_BOOT_ADDR 0x100
32 #define SMP_BOOT_REG 0x40
33 #define MPCORE_PERIPHBASE 0xfff10000
39 static void hb_write_secondary(ARMCPU
*cpu
, const struct arm_boot_info
*info
)
42 uint32_t smpboot
[] = {
43 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
44 0xe210000f, /* ands r0, r0, #0x0f */
45 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
46 0xe0830200, /* add r0, r3, r0, lsl #4 */
47 0xe59f2024, /* ldr r2, privbase */
48 0xe3a01001, /* mov r1, #1 */
49 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
50 0xe3a010ff, /* mov r1, #0xff */
51 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
54 0xe5901000, /* ldr r1, [r0] */
55 0xe1110001, /* tst r1, r1 */
56 0x0afffffb, /* beq <wfi> */
57 0xe12fff11, /* bx r1 */
58 MPCORE_PERIPHBASE
/* privbase: MPCore peripheral base address. */
60 for (n
= 0; n
< ARRAY_SIZE(smpboot
); n
++) {
61 smpboot
[n
] = tswap32(smpboot
[n
]);
63 rom_add_blob_fixed("smpboot", smpboot
, sizeof(smpboot
), SMP_BOOT_ADDR
);
66 static void hb_reset_secondary(ARMCPU
*cpu
, const struct arm_boot_info
*info
)
68 CPUARMState
*env
= &cpu
->env
;
70 switch (info
->nb_cpus
) {
72 stl_phys_notdirty(&address_space_memory
, SMP_BOOT_REG
+ 0x30, 0);
74 stl_phys_notdirty(&address_space_memory
, SMP_BOOT_REG
+ 0x20, 0);
76 stl_phys_notdirty(&address_space_memory
, SMP_BOOT_REG
+ 0x10, 0);
77 env
->regs
[15] = SMP_BOOT_ADDR
;
84 #define NUM_REGS 0x200
85 static void hb_regs_write(void *opaque
, hwaddr offset
,
86 uint64_t value
, unsigned size
)
88 uint32_t *regs
= opaque
;
90 if (offset
== 0xf00) {
91 if (value
== 1 || value
== 2) {
92 qemu_system_reset_request();
93 } else if (value
== 3) {
94 qemu_system_shutdown_request();
98 regs
[offset
/4] = value
;
101 static uint64_t hb_regs_read(void *opaque
, hwaddr offset
,
104 uint32_t *regs
= opaque
;
105 uint32_t value
= regs
[offset
/4];
107 if ((offset
== 0x100) || (offset
== 0x108) || (offset
== 0x10C)) {
114 static const MemoryRegionOps hb_mem_ops
= {
115 .read
= hb_regs_read
,
116 .write
= hb_regs_write
,
117 .endianness
= DEVICE_NATIVE_ENDIAN
,
120 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
121 #define HIGHBANK_REGISTERS(obj) \
122 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
126 SysBusDevice parent_obj
;
130 uint32_t regs
[NUM_REGS
];
133 static VMStateDescription vmstate_highbank_regs
= {
134 .name
= "highbank-regs",
136 .minimum_version_id
= 0,
137 .minimum_version_id_old
= 0,
138 .fields
= (VMStateField
[]) {
139 VMSTATE_UINT32_ARRAY(regs
, HighbankRegsState
, NUM_REGS
),
140 VMSTATE_END_OF_LIST(),
144 static void highbank_regs_reset(DeviceState
*dev
)
146 HighbankRegsState
*s
= HIGHBANK_REGISTERS(dev
);
148 s
->regs
[0x40] = 0x05F20121;
150 s
->regs
[0x42] = 0x05F30121;
151 s
->regs
[0x43] = 0x05F40121;
154 static int highbank_regs_init(SysBusDevice
*dev
)
156 HighbankRegsState
*s
= HIGHBANK_REGISTERS(dev
);
158 memory_region_init_io(&s
->iomem
, OBJECT(s
), &hb_mem_ops
, s
->regs
,
159 "highbank_regs", 0x1000);
160 sysbus_init_mmio(dev
, &s
->iomem
);
165 static void highbank_regs_class_init(ObjectClass
*klass
, void *data
)
167 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
168 DeviceClass
*dc
= DEVICE_CLASS(klass
);
170 sbc
->init
= highbank_regs_init
;
171 dc
->desc
= "Calxeda Highbank registers";
172 dc
->vmsd
= &vmstate_highbank_regs
;
173 dc
->reset
= highbank_regs_reset
;
176 static const TypeInfo highbank_regs_info
= {
177 .name
= TYPE_HIGHBANK_REGISTERS
,
178 .parent
= TYPE_SYS_BUS_DEVICE
,
179 .instance_size
= sizeof(HighbankRegsState
),
180 .class_init
= highbank_regs_class_init
,
183 static void highbank_regs_register_types(void)
185 type_register_static(&highbank_regs_info
);
188 type_init(highbank_regs_register_types
)
190 static struct arm_boot_info highbank_binfo
;
197 /* ram_size must be set to match the upper bound of memory in the
198 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
199 * normally 0xff900000 or -m 4089. When running this board on a
200 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
201 * device tree and pass -m 2047 to QEMU.
203 static void calxeda_init(QEMUMachineInitArgs
*args
, enum cxmachines machine
)
205 ram_addr_t ram_size
= args
->ram_size
;
206 const char *cpu_model
= args
->cpu_model
;
207 const char *kernel_filename
= args
->kernel_filename
;
208 const char *kernel_cmdline
= args
->kernel_cmdline
;
209 const char *initrd_filename
= args
->initrd_filename
;
210 DeviceState
*dev
= NULL
;
211 SysBusDevice
*busdev
;
215 MemoryRegion
*sysram
;
217 MemoryRegion
*sysmem
;
218 char *sysboot_filename
;
222 case CALXEDA_HIGHBANK
:
223 cpu_model
= "cortex-a9";
226 cpu_model
= "cortex-a15";
231 for (n
= 0; n
< smp_cpus
; n
++) {
232 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
236 cpu
= ARM_CPU(object_new(object_class_get_name(oc
)));
238 object_property_set_int(OBJECT(cpu
), MPCORE_PERIPHBASE
, "reset-cbar",
241 error_report("%s", error_get_pretty(err
));
244 object_property_set_bool(OBJECT(cpu
), true, "realized", &err
);
246 error_report("%s", error_get_pretty(err
));
249 cpu_irq
[n
] = qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
);
252 sysmem
= get_system_memory();
253 dram
= g_new(MemoryRegion
, 1);
254 memory_region_init_ram(dram
, NULL
, "highbank.dram", ram_size
);
255 /* SDRAM at address zero. */
256 memory_region_add_subregion(sysmem
, 0, dram
);
258 sysram
= g_new(MemoryRegion
, 1);
259 memory_region_init_ram(sysram
, NULL
, "highbank.sysram", 0x8000);
260 memory_region_add_subregion(sysmem
, 0xfff88000, sysram
);
261 if (bios_name
!= NULL
) {
262 sysboot_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
263 if (sysboot_filename
!= NULL
) {
264 uint32_t filesize
= get_image_size(sysboot_filename
);
265 if (load_image_targphys("sysram.bin", 0xfff88000, filesize
) < 0) {
266 hw_error("Unable to load %s\n", bios_name
);
269 hw_error("Unable to find %s\n", bios_name
);
274 case CALXEDA_HIGHBANK
:
275 dev
= qdev_create(NULL
, "l2x0");
276 qdev_init_nofail(dev
);
277 busdev
= SYS_BUS_DEVICE(dev
);
278 sysbus_mmio_map(busdev
, 0, 0xfff12000);
280 dev
= qdev_create(NULL
, "a9mpcore_priv");
283 dev
= qdev_create(NULL
, "a15mpcore_priv");
286 qdev_prop_set_uint32(dev
, "num-cpu", smp_cpus
);
287 qdev_prop_set_uint32(dev
, "num-irq", NIRQ_GIC
);
288 qdev_init_nofail(dev
);
289 busdev
= SYS_BUS_DEVICE(dev
);
290 sysbus_mmio_map(busdev
, 0, MPCORE_PERIPHBASE
);
291 for (n
= 0; n
< smp_cpus
; n
++) {
292 sysbus_connect_irq(busdev
, n
, cpu_irq
[n
]);
295 for (n
= 0; n
< 128; n
++) {
296 pic
[n
] = qdev_get_gpio_in(dev
, n
);
299 dev
= qdev_create(NULL
, "sp804");
300 qdev_prop_set_uint32(dev
, "freq0", 150000000);
301 qdev_prop_set_uint32(dev
, "freq1", 150000000);
302 qdev_init_nofail(dev
);
303 busdev
= SYS_BUS_DEVICE(dev
);
304 sysbus_mmio_map(busdev
, 0, 0xfff34000);
305 sysbus_connect_irq(busdev
, 0, pic
[18]);
306 sysbus_create_simple("pl011", 0xfff36000, pic
[20]);
308 dev
= qdev_create(NULL
, "highbank-regs");
309 qdev_init_nofail(dev
);
310 busdev
= SYS_BUS_DEVICE(dev
);
311 sysbus_mmio_map(busdev
, 0, 0xfff3c000);
313 sysbus_create_simple("pl061", 0xfff30000, pic
[14]);
314 sysbus_create_simple("pl061", 0xfff31000, pic
[15]);
315 sysbus_create_simple("pl061", 0xfff32000, pic
[16]);
316 sysbus_create_simple("pl061", 0xfff33000, pic
[17]);
317 sysbus_create_simple("pl031", 0xfff35000, pic
[19]);
318 sysbus_create_simple("pl022", 0xfff39000, pic
[23]);
320 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic
[83]);
322 if (nd_table
[0].used
) {
323 qemu_check_nic_model(&nd_table
[0], "xgmac");
324 dev
= qdev_create(NULL
, "xgmac");
325 qdev_set_nic_properties(dev
, &nd_table
[0]);
326 qdev_init_nofail(dev
);
327 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xfff50000);
328 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[77]);
329 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1, pic
[78]);
330 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2, pic
[79]);
332 qemu_check_nic_model(&nd_table
[1], "xgmac");
333 dev
= qdev_create(NULL
, "xgmac");
334 qdev_set_nic_properties(dev
, &nd_table
[1]);
335 qdev_init_nofail(dev
);
336 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xfff51000);
337 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[80]);
338 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1, pic
[81]);
339 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2, pic
[82]);
342 highbank_binfo
.ram_size
= ram_size
;
343 highbank_binfo
.kernel_filename
= kernel_filename
;
344 highbank_binfo
.kernel_cmdline
= kernel_cmdline
;
345 highbank_binfo
.initrd_filename
= initrd_filename
;
346 /* highbank requires a dtb in order to boot, and the dtb will override
347 * the board ID. The following value is ignored, so set it to -1 to be
348 * clear that the value is meaningless.
350 highbank_binfo
.board_id
= -1;
351 highbank_binfo
.nb_cpus
= smp_cpus
;
352 highbank_binfo
.loader_start
= 0;
353 highbank_binfo
.write_secondary_boot
= hb_write_secondary
;
354 highbank_binfo
.secondary_cpu_reset_hook
= hb_reset_secondary
;
355 arm_load_kernel(ARM_CPU(first_cpu
), &highbank_binfo
);
358 static void highbank_init(QEMUMachineInitArgs
*args
)
360 calxeda_init(args
, CALXEDA_HIGHBANK
);
363 static void midway_init(QEMUMachineInitArgs
*args
)
365 calxeda_init(args
, CALXEDA_MIDWAY
);
368 static QEMUMachine highbank_machine
= {
370 .desc
= "Calxeda Highbank (ECX-1000)",
371 .init
= highbank_init
,
372 .block_default_type
= IF_SCSI
,
376 static QEMUMachine midway_machine
= {
378 .desc
= "Calxeda Midway (ECX-2000)",
380 .block_default_type
= IF_SCSI
,
384 static void calxeda_machines_init(void)
386 qemu_register_machine(&highbank_machine
);
387 qemu_register_machine(&midway_machine
);
390 machine_init(calxeda_machines_init
);