hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Copyright (c) 2010 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *            M.Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "hw/sysbus.h"
  20 #include "sysemu/char.h"
  21 #include "qemu/timer.h"
  22
  23 #ifdef CADENCE_UART_ERR_DEBUG
  24 #define DB_PRINT(...) do { \
  25     fprintf(stderr,  ": %s: ", __func__); \
  26     fprintf(stderr, ## __VA_ARGS__); \
  27     } while (0);
  28 #else
  29     #define DB_PRINT(...)
  30 #endif
  31
  32 #define UART_SR_INTR_RTRIG     0x00000001
  33 #define UART_SR_INTR_REMPTY    0x00000002
  34 #define UART_SR_INTR_RFUL      0x00000004
  35 #define UART_SR_INTR_TEMPTY    0x00000008
  36 #define UART_SR_INTR_TFUL      0x00000010
  37 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
  38 #define UART_SR_TTRIG          0x00002000
  39 #define UART_INTR_TTRIG        0x00000400
  40 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  41  * SR, then the same bit in CISR is set high too */
  42 #define UART_SR_TO_CISR_MASK   0x0000001F
  43
  44 #define UART_INTR_ROVR         0x00000020
  45 #define UART_INTR_FRAME        0x00000040
  46 #define UART_INTR_PARE         0x00000080
  47 #define UART_INTR_TIMEOUT      0x00000100
  48 #define UART_INTR_DMSI         0x00000200
  49 #define UART_INTR_TOVR         0x00001000
  50
  51 #define UART_SR_RACTIVE    0x00000400
  52 #define UART_SR_TACTIVE    0x00000800
  53 #define UART_SR_FDELT      0x00001000
  54
  55 #define UART_CR_RXRST       0x00000001
  56 #define UART_CR_TXRST       0x00000002
  57 #define UART_CR_RX_EN       0x00000004
  58 #define UART_CR_RX_DIS      0x00000008
  59 #define UART_CR_TX_EN       0x00000010
  60 #define UART_CR_TX_DIS      0x00000020
  61 #define UART_CR_RST_TO      0x00000040
  62 #define UART_CR_STARTBRK    0x00000080
  63 #define UART_CR_STOPBRK     0x00000100
  64
  65 #define UART_MR_CLKS            0x00000001
  66 #define UART_MR_CHRL            0x00000006
  67 #define UART_MR_CHRL_SH         1
  68 #define UART_MR_PAR             0x00000038
  69 #define UART_MR_PAR_SH          3
  70 #define UART_MR_NBSTOP          0x000000C0
  71 #define UART_MR_NBSTOP_SH       6
  72 #define UART_MR_CHMODE          0x00000300
  73 #define UART_MR_CHMODE_SH       8
  74 #define UART_MR_UCLKEN          0x00000400
  75 #define UART_MR_IRMODE          0x00000800
  76
  77 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  78 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  79 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  80 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  81 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  82 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  83 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  84 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  85 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  86 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  87
  88 #define RX_FIFO_SIZE           16
  89 #define TX_FIFO_SIZE           16
  90 #define UART_INPUT_CLK         50000000
  91
  92 #define R_CR       (0x00/4)
  93 #define R_MR       (0x04/4)
  94 #define R_IER      (0x08/4)
  95 #define R_IDR      (0x0C/4)
  96 #define R_IMR      (0x10/4)
  97 #define R_CISR     (0x14/4)
  98 #define R_BRGR     (0x18/4)
  99 #define R_RTOR     (0x1C/4)
 100 #define R_RTRIG    (0x20/4)
 101 #define R_MCR      (0x24/4)
 102 #define R_MSR      (0x28/4)
 103 #define R_SR       (0x2C/4)
 104 #define R_TX_RX    (0x30/4)
 105 #define R_BDIV     (0x34/4)
 106 #define R_FDEL     (0x38/4)
 107 #define R_PMIN     (0x3C/4)
 108 #define R_PWID     (0x40/4)
 109 #define R_TTRIG    (0x44/4)
 110
 111 #define R_MAX (R_TTRIG + 1)
 112
 113 #define TYPE_CADENCE_UART "cadence_uart"
 114 #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
 115
 116 typedef struct {
 117     /*< private >*/
 118     SysBusDevice parent_obj;
 119     /*< public >*/
 120
 121     MemoryRegion iomem;
 122     uint32_t r[R_MAX];
 123     uint8_t rx_fifo[RX_FIFO_SIZE];
 124     uint8_t tx_fifo[TX_FIFO_SIZE];
 125     uint32_t rx_wpos;
 126     uint32_t rx_count;
 127     uint32_t tx_count;
 128     uint64_t char_tx_time;
 129     CharDriverState *chr;
 130     qemu_irq irq;
 131     QEMUTimer *fifo_trigger_handle;
 132 } UartState;
 133
 134 static void uart_update_status(UartState *s)
 135 {
 136     s->r[R_SR] = 0;
 137
 138     s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
 139     s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
 140     s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
 141
 142     s->r[R_SR] |= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0;
 143     s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
 144     s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
 145
 146     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 147     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
 148     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 149 }
 150
 151 static void fifo_trigger_update(void *opaque)
 152 {
 153     UartState *s = (UartState *)opaque;
 154
 155     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 156
 157     uart_update_status(s);
 158 }
 159
 160 static void uart_rx_reset(UartState *s)
 161 {
 162     s->rx_wpos = 0;
 163     s->rx_count = 0;
 164     if (s->chr) {
 165         qemu_chr_accept_input(s->chr);
 166     }
 167 }
 168
 169 static void uart_tx_reset(UartState *s)
 170 {
 171     s->tx_count = 0;
 172 }
 173
 174 static void uart_send_breaks(UartState *s)
 175 {
 176     int break_enabled = 1;
 177
 178     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 179                                &break_enabled);
 180 }
 181
 182 static void uart_parameters_setup(UartState *s)
 183 {
 184     QEMUSerialSetParams ssp;
 185     unsigned int baud_rate, packet_size;
 186
 187     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 188             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 189
 190     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 191     packet_size = 1;
 192
 193     switch (s->r[R_MR] & UART_MR_PAR) {
 194     case UART_PARITY_EVEN:
 195         ssp.parity = 'E';
 196         packet_size++;
 197         break;
 198     case UART_PARITY_ODD:
 199         ssp.parity = 'O';
 200         packet_size++;
 201         break;
 202     default:
 203         ssp.parity = 'N';
 204         break;
 205     }
 206
 207     switch (s->r[R_MR] & UART_MR_CHRL) {
 208     case UART_DATA_BITS_6:
 209         ssp.data_bits = 6;
 210         break;
 211     case UART_DATA_BITS_7:
 212         ssp.data_bits = 7;
 213         break;
 214     default:
 215         ssp.data_bits = 8;
 216         break;
 217     }
 218
 219     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 220     case UART_STOP_BITS_1:
 221         ssp.stop_bits = 1;
 222         break;
 223     default:
 224         ssp.stop_bits = 2;
 225         break;
 226     }
 227
 228     packet_size += ssp.data_bits + ssp.stop_bits;
 229     s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
 230     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 231 }
 232
 233 static int uart_can_receive(void *opaque)
 234 {
 235     UartState *s = (UartState *)opaque;
 236
 237     return RX_FIFO_SIZE - s->rx_count;
 238 }
 239
 240 static void uart_ctrl_update(UartState *s)
 241 {
 242     if (s->r[R_CR] & UART_CR_TXRST) {
 243         uart_tx_reset(s);
 244     }
 245
 246     if (s->r[R_CR] & UART_CR_RXRST) {
 247         uart_rx_reset(s);
 248     }
 249
 250     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 251
 252     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 253         uart_send_breaks(s);
 254     }
 255 }
 256
 257 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 258 {
 259     UartState *s = (UartState *)opaque;
 260     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 261     int i;
 262
 263     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 264         return;
 265     }
 266
 267     if (s->rx_count == RX_FIFO_SIZE) {
 268         s->r[R_CISR] |= UART_INTR_ROVR;
 269     } else {
 270         for (i = 0; i < size; i++) {
 271             s->rx_fifo[s->rx_wpos] = buf[i];
 272             s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
 273             s->rx_count++;
 274         }
 275         timer_mod(s->fifo_trigger_handle, new_rx_time +
 276                                                 (s->char_tx_time * 4));
 277     }
 278     uart_update_status(s);
 279 }
 280
 281 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
 282 {
 283     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 284         return;
 285     }
 286
 287     qemu_chr_fe_write_all(s->chr, buf, size);
 288 }
 289
 290 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 291 {
 292     UartState *s = (UartState *)opaque;
 293     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 294
 295     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 296         uart_write_rx_fifo(opaque, buf, size);
 297     }
 298     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 299         uart_write_tx_fifo(s, buf, size);
 300     }
 301 }
 302
 303 static void uart_event(void *opaque, int event)
 304 {
 305     UartState *s = (UartState *)opaque;
 306     uint8_t buf = '\0';
 307
 308     if (event == CHR_EVENT_BREAK) {
 309         uart_write_rx_fifo(opaque, &buf, 1);
 310     }
 311
 312     uart_update_status(s);
 313 }
 314
 315 static void uart_read_rx_fifo(UartState *s, uint32_t *c)
 316 {
 317     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 318         return;
 319     }
 320
 321     if (s->rx_count) {
 322         uint32_t rx_rpos =
 323                 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
 324         *c = s->rx_fifo[rx_rpos];
 325         s->rx_count--;
 326
 327         qemu_chr_accept_input(s->chr);
 328     } else {
 329         *c = 0;
 330     }
 331
 332     uart_update_status(s);
 333 }
 334
 335 static void uart_write(void *opaque, hwaddr offset,
 336                           uint64_t value, unsigned size)
 337 {
 338     UartState *s = (UartState *)opaque;
 339
 340     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 341     offset >>= 2;
 342     switch (offset) {
 343     case R_IER: /* ier (wts imr) */
 344         s->r[R_IMR] |= value;
 345         break;
 346     case R_IDR: /* idr (wtc imr) */
 347         s->r[R_IMR] &= ~value;
 348         break;
 349     case R_IMR: /* imr (read only) */
 350         break;
 351     case R_CISR: /* cisr (wtc) */
 352         s->r[R_CISR] &= ~value;
 353         break;
 354     case R_TX_RX: /* UARTDR */
 355         switch (s->r[R_MR] & UART_MR_CHMODE) {
 356         case NORMAL_MODE:
 357             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 358             break;
 359         case LOCAL_LOOPBACK:
 360             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 361             break;
 362         }
 363         break;
 364     default:
 365         s->r[offset] = value;
 366     }
 367
 368     switch (offset) {
 369     case R_CR:
 370         uart_ctrl_update(s);
 371         break;
 372     case R_MR:
 373         uart_parameters_setup(s);
 374         break;
 375     }
 376     uart_update_status(s);
 377 }
 378
 379 static uint64_t uart_read(void *opaque, hwaddr offset,
 380         unsigned size)
 381 {
 382     UartState *s = (UartState *)opaque;
 383     uint32_t c = 0;
 384
 385     offset >>= 2;
 386     if (offset >= R_MAX) {
 387         c = 0;
 388     } else if (offset == R_TX_RX) {
 389         uart_read_rx_fifo(s, &c);
 390     } else {
 391        c = s->r[offset];
 392     }
 393
 394     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 395     return c;
 396 }
 397
 398 static const MemoryRegionOps uart_ops = {
 399     .read = uart_read,
 400     .write = uart_write,
 401     .endianness = DEVICE_NATIVE_ENDIAN,
 402 };
 403
 404 static void cadence_uart_reset(DeviceState *dev)
 405 {
 406     UartState *s = CADENCE_UART(dev);
 407
 408     s->r[R_CR] = 0x00000128;
 409     s->r[R_IMR] = 0;
 410     s->r[R_CISR] = 0;
 411     s->r[R_RTRIG] = 0x00000020;
 412     s->r[R_BRGR] = 0x0000000F;
 413     s->r[R_TTRIG] = 0x00000020;
 414
 415     uart_rx_reset(s);
 416     uart_tx_reset(s);
 417
 418     s->rx_count = 0;
 419     s->rx_wpos = 0;
 420     uart_update_status(s);
 421 }
 422
 423 static int cadence_uart_init(SysBusDevice *dev)
 424 {
 425     UartState *s = CADENCE_UART(dev);
 426
 427     memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
 428     sysbus_init_mmio(dev, &s->iomem);
 429     sysbus_init_irq(dev, &s->irq);
 430
 431     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 432             (QEMUTimerCB *)fifo_trigger_update, s);
 433
 434     s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
 435
 436     s->chr = qemu_char_get_next_serial();
 437
 438     if (s->chr) {
 439         qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
 440                               uart_event, s);
 441     }
 442
 443     return 0;
 444 }
 445
 446 static int cadence_uart_post_load(void *opaque, int version_id)
 447 {
 448     UartState *s = opaque;
 449
 450     uart_parameters_setup(s);
 451     uart_update_status(s);
 452     return 0;
 453 }
 454
 455 static const VMStateDescription vmstate_cadence_uart = {
 456     .name = "cadence_uart",
 457     .version_id = 2,
 458     .minimum_version_id = 2,
 459     .minimum_version_id_old = 2,
 460     .post_load = cadence_uart_post_load,
 461     .fields = (VMStateField[]) {
 462         VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
 463         VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
 464         VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
 465         VMSTATE_UINT32(rx_count, UartState),
 466         VMSTATE_UINT32(tx_count, UartState),
 467         VMSTATE_UINT32(rx_wpos, UartState),
 468         VMSTATE_TIMER(fifo_trigger_handle, UartState),
 469         VMSTATE_END_OF_LIST()
 470     }
 471 };
 472
 473 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 474 {
 475     DeviceClass *dc = DEVICE_CLASS(klass);
 476     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 477
 478     sdc->init = cadence_uart_init;
 479     dc->vmsd = &vmstate_cadence_uart;
 480     dc->reset = cadence_uart_reset;
 481 }
 482
 483 static const TypeInfo cadence_uart_info = {
 484     .name          = TYPE_CADENCE_UART,
 485     .parent        = TYPE_SYS_BUS_DEVICE,
 486     .instance_size = sizeof(UartState),
 487     .class_init    = cadence_uart_class_init,
 488 };
 489
 490 static void cadence_uart_register_types(void)
 491 {
 492     type_register_static(&cadence_uart_info);
 493 }
 494
 495 type_init(cadence_uart_register_types)