4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
32 #include "hw/core/tcg-cpu-ops.h"
33 #endif /* CONFIG_TCG */
34 #include "internals.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
41 #include "sysemu/tcg.h"
42 #include "sysemu/qtest.h"
43 #include "sysemu/hw_accel.h"
45 #include "disas/capstone.h"
46 #include "fpu/softfloat.h"
49 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
51 ARMCPU
*cpu
= ARM_CPU(cs
);
52 CPUARMState
*env
= &cpu
->env
;
58 env
->regs
[15] = value
& ~1;
59 env
->thumb
= value
& 1;
64 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
65 const TranslationBlock
*tb
)
67 ARMCPU
*cpu
= ARM_CPU(cs
);
68 CPUARMState
*env
= &cpu
->env
;
71 * It's OK to look at env for the current mode here, because it's
72 * never possible for an AArch64 TB to chain to an AArch32 TB.
77 env
->regs
[15] = tb
->pc
;
80 #endif /* CONFIG_TCG */
82 static bool arm_cpu_has_work(CPUState
*cs
)
84 ARMCPU
*cpu
= ARM_CPU(cs
);
86 return (cpu
->power_state
!= PSCI_OFF
)
87 && cs
->interrupt_request
&
88 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
89 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
| CPU_INTERRUPT_VSERR
90 | CPU_INTERRUPT_EXITTB
);
93 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
96 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
99 entry
->opaque
= opaque
;
101 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
104 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
107 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
110 entry
->opaque
= opaque
;
112 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
115 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
117 /* Reset a single ARMCPRegInfo register */
118 ARMCPRegInfo
*ri
= value
;
119 ARMCPU
*cpu
= opaque
;
121 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
)) {
126 ri
->resetfn(&cpu
->env
, ri
);
130 /* A zero offset is never possible as it would be regs[0]
131 * so we use it to indicate that reset is being handled elsewhere.
132 * This is basically only used for fields in non-core coprocessors
133 * (like the pxa2xx ones).
135 if (!ri
->fieldoffset
) {
139 if (cpreg_field_is_64bit(ri
)) {
140 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
142 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
146 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
148 /* Purely an assertion check: we've already done reset once,
149 * so now check that running the reset for the cpreg doesn't
150 * change its value. This traps bugs where two different cpregs
151 * both try to reset the same state field but to different values.
153 ARMCPRegInfo
*ri
= value
;
154 ARMCPU
*cpu
= opaque
;
155 uint64_t oldvalue
, newvalue
;
157 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
161 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
162 cp_reg_reset(key
, value
, opaque
);
163 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
164 assert(oldvalue
== newvalue
);
167 static void arm_cpu_reset(DeviceState
*dev
)
169 CPUState
*s
= CPU(dev
);
170 ARMCPU
*cpu
= ARM_CPU(s
);
171 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
172 CPUARMState
*env
= &cpu
->env
;
174 acc
->parent_reset(dev
);
176 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
178 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
179 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
181 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
182 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
183 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
184 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
186 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
188 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
189 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
192 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
193 /* 64 bit CPUs always start in 64 bit mode */
195 #if defined(CONFIG_USER_ONLY)
196 env
->pstate
= PSTATE_MODE_EL0t
;
197 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
198 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
199 /* Enable all PAC keys. */
200 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
201 SCTLR_EnDA
| SCTLR_EnDB
);
202 /* Trap on btype=3 for PACIxSP. */
203 env
->cp15
.sctlr_el
[1] |= SCTLR_BT0
;
204 /* and to the FP/Neon instructions */
205 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
207 /* and to the SVE instructions */
208 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
210 /* with reasonable vector length */
211 if (cpu_isar_feature(aa64_sve
, cpu
)) {
212 env
->vfp
.zcr_el
[1] = cpu
->sve_default_vq
- 1;
215 * Enable 48-bit address space (TODO: take reserved_va into account).
216 * Enable TBI0 but not TBI1.
217 * Note that this must match useronly_clean_ptr.
219 env
->cp15
.tcr_el
[1].raw_tcr
= 5 | (1ULL << 37);
222 if (cpu_isar_feature(aa64_mte
, cpu
)) {
223 /* Enable tag access, but leave TCF0 as No Effect (0). */
224 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
226 * Exclude all tags, so that tag 0 is always used.
227 * This corresponds to Linux current->thread.gcr_incl = 0.
229 * Set RRND, so that helper_irg() will generate a seed later.
230 * Here in cpu_reset(), the crypto subsystem has not yet been
233 env
->cp15
.gcr_el1
= 0x1ffff;
236 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
237 * This is not yet exposed from the Linux kernel in any way.
239 env
->cp15
.sctlr_el
[1] |= SCTLR_TSCXT
;
241 /* Reset into the highest available EL */
242 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
243 env
->pstate
= PSTATE_MODE_EL3h
;
244 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
245 env
->pstate
= PSTATE_MODE_EL2h
;
247 env
->pstate
= PSTATE_MODE_EL1h
;
250 /* Sample rvbar at reset. */
251 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
252 env
->pc
= env
->cp15
.rvbar
;
255 #if defined(CONFIG_USER_ONLY)
256 /* Userspace expects access to cp10 and cp11 for FP/Neon */
257 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
259 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
264 #if defined(CONFIG_USER_ONLY)
265 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
266 /* For user mode we must enable access to coprocessors */
267 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
268 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
269 env
->cp15
.c15_cpar
= 3;
270 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
271 env
->cp15
.c15_cpar
= 1;
276 * If the highest available EL is EL2, AArch32 will start in Hyp
277 * mode; otherwise it starts in SVC. Note that if we start in
278 * AArch64 then these values in the uncached_cpsr will be ignored.
280 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
281 !arm_feature(env
, ARM_FEATURE_EL3
)) {
282 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
284 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
286 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
288 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
289 * executing as AArch32 then check if highvecs are enabled and
290 * adjust the PC accordingly.
292 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
293 env
->regs
[15] = 0xFFFF0000;
296 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
299 if (arm_feature(env
, ARM_FEATURE_M
)) {
300 #ifndef CONFIG_USER_ONLY
301 uint32_t initial_msp
; /* Loaded from 0x0 */
302 uint32_t initial_pc
; /* Loaded from 0x4 */
307 if (cpu_isar_feature(aa32_lob
, cpu
)) {
309 * LTPSIZE is constant 4 if MVE not implemented, and resets
310 * to an UNKNOWN value if MVE is implemented. We choose to
313 env
->v7m
.ltpsize
= 4;
314 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
315 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
316 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
319 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
320 env
->v7m
.secure
= true;
322 /* This bit resets to 0 if security is supported, but 1 if
323 * it is not. The bit is not present in v7M, but we set it
324 * here so we can avoid having to make checks on it conditional
325 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
327 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
329 * Set NSACR to indicate "NS access permitted to everything";
330 * this avoids having to have all the tests of it being
331 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
332 * v8.1M the guest-visible value of NSACR in a CPU without the
333 * Security Extension is 0xcff.
335 env
->v7m
.nsacr
= 0xcff;
338 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
339 * that it resets to 1, so QEMU always does that rather than making
340 * it dependent on CPU model. In v8M it is RES1.
342 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
343 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
344 if (arm_feature(env
, ARM_FEATURE_V8
)) {
345 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
346 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
347 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
349 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
350 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
351 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
354 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
355 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
356 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
357 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
360 #ifndef CONFIG_USER_ONLY
361 /* Unlike A/R profile, M profile defines the reset LR value */
362 env
->regs
[14] = 0xffffffff;
364 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
365 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
367 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
368 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
369 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
371 /* Address zero is covered by ROM which hasn't yet been
372 * copied into physical memory.
374 initial_msp
= ldl_p(rom
);
375 initial_pc
= ldl_p(rom
+ 4);
377 /* Address zero not covered by a ROM blob, or the ROM blob
378 * is in non-modifiable memory and this is a second reset after
379 * it got copied into memory. In the latter case, rom_ptr
380 * will return a NULL pointer and we should use ldl_phys instead.
382 initial_msp
= ldl_phys(s
->as
, vecbase
);
383 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
386 qemu_log_mask(CPU_LOG_INT
,
387 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
388 initial_msp
, initial_pc
);
390 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
391 env
->regs
[15] = initial_pc
& ~1;
392 env
->thumb
= initial_pc
& 1;
395 * For user mode we run non-secure and with access to the FPU.
396 * The FPU context is active (ie does not need further setup)
397 * and is owned by non-secure.
399 env
->v7m
.secure
= false;
400 env
->v7m
.nsacr
= 0xcff;
401 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
402 env
->v7m
.fpccr
[M_REG_S
] &=
403 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
404 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
408 /* M profile requires that reset clears the exclusive monitor;
409 * A profile does not, but clearing it makes more sense than having it
410 * set with an exclusive access on address zero.
412 arm_clear_exclusive(env
);
414 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
415 if (cpu
->pmsav7_dregion
> 0) {
416 if (arm_feature(env
, ARM_FEATURE_V8
)) {
417 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
418 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
419 * cpu
->pmsav7_dregion
);
420 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
421 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
422 * cpu
->pmsav7_dregion
);
423 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
424 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
425 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
426 * cpu
->pmsav7_dregion
);
427 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
428 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
429 * cpu
->pmsav7_dregion
);
431 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
432 memset(env
->pmsav7
.drbar
, 0,
433 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
434 memset(env
->pmsav7
.drsr
, 0,
435 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
436 memset(env
->pmsav7
.dracr
, 0,
437 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
440 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
441 env
->pmsav7
.rnr
[M_REG_S
] = 0;
442 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
443 env
->pmsav8
.mair0
[M_REG_S
] = 0;
444 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
445 env
->pmsav8
.mair1
[M_REG_S
] = 0;
448 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
449 if (cpu
->sau_sregion
> 0) {
450 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
451 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
454 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
455 * the Cortex-M33 does.
460 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
461 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
462 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
463 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
464 set_float_detect_tininess(float_tininess_before_rounding
,
465 &env
->vfp
.fp_status
);
466 set_float_detect_tininess(float_tininess_before_rounding
,
467 &env
->vfp
.standard_fp_status
);
468 set_float_detect_tininess(float_tininess_before_rounding
,
469 &env
->vfp
.fp_status_f16
);
470 set_float_detect_tininess(float_tininess_before_rounding
,
471 &env
->vfp
.standard_fp_status_f16
);
472 #ifndef CONFIG_USER_ONLY
474 kvm_arm_reset_vcpu(cpu
);
478 hw_breakpoint_update_all(cpu
);
479 hw_watchpoint_update_all(cpu
);
480 arm_rebuild_hflags(env
);
483 #ifndef CONFIG_USER_ONLY
485 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
486 unsigned int target_el
,
487 unsigned int cur_el
, bool secure
,
490 CPUARMState
*env
= cs
->env_ptr
;
491 bool pstate_unmasked
;
492 bool unmasked
= false;
495 * Don't take exceptions if they target a lower EL.
496 * This check should catch any exceptions that would not be taken
499 if (cur_el
> target_el
) {
505 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
509 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
513 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
514 /* VFIQs are only taken when hypervized. */
517 return !(env
->daif
& PSTATE_F
);
519 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
520 /* VIRQs are only taken when hypervized. */
523 return !(env
->daif
& PSTATE_I
);
525 if (!(hcr_el2
& HCR_AMO
) || (hcr_el2
& HCR_TGE
)) {
526 /* VIRQs are only taken when hypervized. */
529 return !(env
->daif
& PSTATE_A
);
531 g_assert_not_reached();
535 * Use the target EL, current execution state and SCR/HCR settings to
536 * determine whether the corresponding CPSR bit is used to mask the
539 if ((target_el
> cur_el
) && (target_el
!= 1)) {
540 /* Exceptions targeting a higher EL may not be maskable */
541 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
543 * 64-bit masking rules are simple: exceptions to EL3
544 * can't be masked, and exceptions to EL2 can only be
545 * masked from Secure state. The HCR and SCR settings
546 * don't affect the masking logic, only the interrupt routing.
548 if (target_el
== 3 || !secure
|| (env
->cp15
.scr_el3
& SCR_EEL2
)) {
553 * The old 32-bit-only environment has a more complicated
554 * masking setup. HCR and SCR bits not only affect interrupt
555 * routing but also change the behaviour of masking.
562 * If FIQs are routed to EL3 or EL2 then there are cases where
563 * we override the CPSR.F in determining if the exception is
564 * masked or not. If neither of these are set then we fall back
565 * to the CPSR.F setting otherwise we further assess the state
568 hcr
= hcr_el2
& HCR_FMO
;
569 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
572 * When EL3 is 32-bit, the SCR.FW bit controls whether the
573 * CPSR.F bit masks FIQ interrupts when taken in non-secure
574 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
575 * when non-secure but only when FIQs are only routed to EL3.
577 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
581 * When EL3 execution state is 32-bit, if HCR.IMO is set then
582 * we may override the CPSR.I masking when in non-secure state.
583 * The SCR.IRQ setting has already been taken into consideration
584 * when setting the target EL, so it does not have a further
587 hcr
= hcr_el2
& HCR_IMO
;
591 g_assert_not_reached();
594 if ((scr
|| hcr
) && !secure
) {
601 * The PSTATE bits only mask the interrupt if we have not overriden the
604 return unmasked
|| pstate_unmasked
;
607 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
609 CPUClass
*cc
= CPU_GET_CLASS(cs
);
610 CPUARMState
*env
= cs
->env_ptr
;
611 uint32_t cur_el
= arm_current_el(env
);
612 bool secure
= arm_is_secure(env
);
613 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
617 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
619 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
621 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
622 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
623 cur_el
, secure
, hcr_el2
)) {
627 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
629 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
630 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
631 cur_el
, secure
, hcr_el2
)) {
635 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
636 excp_idx
= EXCP_VIRQ
;
638 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
639 cur_el
, secure
, hcr_el2
)) {
643 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
644 excp_idx
= EXCP_VFIQ
;
646 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
647 cur_el
, secure
, hcr_el2
)) {
651 if (interrupt_request
& CPU_INTERRUPT_VSERR
) {
652 excp_idx
= EXCP_VSERR
;
654 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
655 cur_el
, secure
, hcr_el2
)) {
656 /* Taking a virtual abort clears HCR_EL2.VSE */
657 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
658 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
665 cs
->exception_index
= excp_idx
;
666 env
->exception
.target_el
= target_el
;
667 cc
->tcg_ops
->do_interrupt(cs
);
670 #endif /* !CONFIG_USER_ONLY */
672 void arm_cpu_update_virq(ARMCPU
*cpu
)
675 * Update the interrupt level for VIRQ, which is the logical OR of
676 * the HCR_EL2.VI bit and the input line level from the GIC.
678 CPUARMState
*env
= &cpu
->env
;
679 CPUState
*cs
= CPU(cpu
);
681 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
682 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
684 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
686 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
688 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
693 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
696 * Update the interrupt level for VFIQ, which is the logical OR of
697 * the HCR_EL2.VF bit and the input line level from the GIC.
699 CPUARMState
*env
= &cpu
->env
;
700 CPUState
*cs
= CPU(cpu
);
702 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
703 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
705 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
707 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
709 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
714 void arm_cpu_update_vserr(ARMCPU
*cpu
)
717 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
719 CPUARMState
*env
= &cpu
->env
;
720 CPUState
*cs
= CPU(cpu
);
722 bool new_state
= env
->cp15
.hcr_el2
& HCR_VSE
;
724 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) != 0)) {
726 cpu_interrupt(cs
, CPU_INTERRUPT_VSERR
);
728 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
733 #ifndef CONFIG_USER_ONLY
734 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
736 ARMCPU
*cpu
= opaque
;
737 CPUARMState
*env
= &cpu
->env
;
738 CPUState
*cs
= CPU(cpu
);
739 static const int mask
[] = {
740 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
741 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
742 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
743 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
746 if (!arm_feature(env
, ARM_FEATURE_EL2
) &&
747 (irq
== ARM_CPU_VIRQ
|| irq
== ARM_CPU_VFIQ
)) {
749 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
750 * have EL2 support we don't care. (Unless the guest is doing something
751 * silly this will only be calls saying "level is still 0".)
757 env
->irq_line_state
|= mask
[irq
];
759 env
->irq_line_state
&= ~mask
[irq
];
764 arm_cpu_update_virq(cpu
);
767 arm_cpu_update_vfiq(cpu
);
772 cpu_interrupt(cs
, mask
[irq
]);
774 cpu_reset_interrupt(cs
, mask
[irq
]);
778 g_assert_not_reached();
782 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
785 ARMCPU
*cpu
= opaque
;
786 CPUARMState
*env
= &cpu
->env
;
787 CPUState
*cs
= CPU(cpu
);
788 uint32_t linestate_bit
;
793 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
794 linestate_bit
= CPU_INTERRUPT_HARD
;
797 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
798 linestate_bit
= CPU_INTERRUPT_FIQ
;
801 g_assert_not_reached();
805 env
->irq_line_state
|= linestate_bit
;
807 env
->irq_line_state
&= ~linestate_bit
;
809 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
813 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
815 ARMCPU
*cpu
= ARM_CPU(cs
);
816 CPUARMState
*env
= &cpu
->env
;
818 cpu_synchronize_state(cs
);
819 return arm_cpu_data_is_big_endian(env
);
824 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
826 ARMCPU
*ac
= ARM_CPU(cpu
);
827 CPUARMState
*env
= &ac
->env
;
831 info
->cap_arch
= CS_ARCH_ARM64
;
832 info
->cap_insn_unit
= 4;
833 info
->cap_insn_split
= 4;
837 info
->cap_insn_unit
= 2;
838 info
->cap_insn_split
= 4;
839 cap_mode
= CS_MODE_THUMB
;
841 info
->cap_insn_unit
= 4;
842 info
->cap_insn_split
= 4;
843 cap_mode
= CS_MODE_ARM
;
845 if (arm_feature(env
, ARM_FEATURE_V8
)) {
846 cap_mode
|= CS_MODE_V8
;
848 if (arm_feature(env
, ARM_FEATURE_M
)) {
849 cap_mode
|= CS_MODE_MCLASS
;
851 info
->cap_arch
= CS_ARCH_ARM
;
852 info
->cap_mode
= cap_mode
;
855 sctlr_b
= arm_sctlr_b(env
);
856 if (bswap_code(sctlr_b
)) {
857 #if TARGET_BIG_ENDIAN
858 info
->endian
= BFD_ENDIAN_LITTLE
;
860 info
->endian
= BFD_ENDIAN_BIG
;
863 info
->flags
&= ~INSN_ARM_BE32
;
864 #ifndef CONFIG_USER_ONLY
866 info
->flags
|= INSN_ARM_BE32
;
871 #ifdef TARGET_AARCH64
873 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
875 ARMCPU
*cpu
= ARM_CPU(cs
);
876 CPUARMState
*env
= &cpu
->env
;
877 uint32_t psr
= pstate_read(env
);
879 int el
= arm_current_el(env
);
880 const char *ns_status
;
882 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
883 for (i
= 0; i
< 32; i
++) {
885 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
887 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
888 (i
+ 2) % 3 ? " " : "\n");
892 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
893 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
897 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
899 psr
& PSTATE_N
? 'N' : '-',
900 psr
& PSTATE_Z
? 'Z' : '-',
901 psr
& PSTATE_C
? 'C' : '-',
902 psr
& PSTATE_V
? 'V' : '-',
905 psr
& PSTATE_SP
? 'h' : 't');
907 if (cpu_isar_feature(aa64_bti
, cpu
)) {
908 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
910 if (!(flags
& CPU_DUMP_FPU
)) {
911 qemu_fprintf(f
, "\n");
914 if (fp_exception_el(env
, el
) != 0) {
915 qemu_fprintf(f
, " FPU disabled\n");
918 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
919 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
921 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
922 int j
, zcr_len
= sve_vqm1_for_el(env
, el
);
924 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
926 if (i
== FFR_PRED_NUM
) {
927 qemu_fprintf(f
, "FFR=");
928 /* It's last, so end the line. */
931 qemu_fprintf(f
, "P%02d=", i
);
944 /* More than one quadword per predicate. */
949 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
951 if (j
* 4 + 4 <= zcr_len
+ 1) {
954 digits
= (zcr_len
% 4 + 1) * 4;
956 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
957 env
->vfp
.pregs
[i
].p
[j
],
958 j
? ":" : eol
? "\n" : " ");
962 for (i
= 0; i
< 32; i
++) {
964 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
965 i
, env
->vfp
.zregs
[i
].d
[1],
966 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
967 } else if (zcr_len
== 1) {
968 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
969 ":%016" PRIx64
":%016" PRIx64
"\n",
970 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
971 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
973 for (j
= zcr_len
; j
>= 0; j
--) {
974 bool odd
= (zcr_len
- j
) % 2 != 0;
976 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
979 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
981 qemu_fprintf(f
, " [%x]=", j
);
984 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
985 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
986 env
->vfp
.zregs
[i
].d
[j
* 2],
987 odd
|| j
== 0 ? "\n" : ":");
992 for (i
= 0; i
< 32; i
++) {
993 uint64_t *q
= aa64_vfp_qreg(env
, i
);
994 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
995 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
1002 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1004 g_assert_not_reached();
1009 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1011 ARMCPU
*cpu
= ARM_CPU(cs
);
1012 CPUARMState
*env
= &cpu
->env
;
1016 aarch64_cpu_dump_state(cs
, f
, flags
);
1020 for (i
= 0; i
< 16; i
++) {
1021 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
1023 qemu_fprintf(f
, "\n");
1025 qemu_fprintf(f
, " ");
1029 if (arm_feature(env
, ARM_FEATURE_M
)) {
1030 uint32_t xpsr
= xpsr_read(env
);
1032 const char *ns_status
= "";
1034 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1035 ns_status
= env
->v7m
.secure
? "S " : "NS ";
1038 if (xpsr
& XPSR_EXCP
) {
1041 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
1042 mode
= "unpriv-thread";
1044 mode
= "priv-thread";
1048 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
1050 xpsr
& XPSR_N
? 'N' : '-',
1051 xpsr
& XPSR_Z
? 'Z' : '-',
1052 xpsr
& XPSR_C
? 'C' : '-',
1053 xpsr
& XPSR_V
? 'V' : '-',
1054 xpsr
& XPSR_T
? 'T' : 'A',
1058 uint32_t psr
= cpsr_read(env
);
1059 const char *ns_status
= "";
1061 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1062 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1063 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1066 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1068 psr
& CPSR_N
? 'N' : '-',
1069 psr
& CPSR_Z
? 'Z' : '-',
1070 psr
& CPSR_C
? 'C' : '-',
1071 psr
& CPSR_V
? 'V' : '-',
1072 psr
& CPSR_T
? 'T' : 'A',
1074 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1077 if (flags
& CPU_DUMP_FPU
) {
1079 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1081 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1084 for (i
= 0; i
< numvfpregs
; i
++) {
1085 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1086 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1088 i
* 2 + 1, (uint32_t)(v
>> 32),
1091 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1092 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1093 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1098 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1100 uint32_t Aff1
= idx
/ clustersz
;
1101 uint32_t Aff0
= idx
% clustersz
;
1102 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1105 static void arm_cpu_initfn(Object
*obj
)
1107 ARMCPU
*cpu
= ARM_CPU(obj
);
1109 cpu_set_cpustate_pointers(cpu
);
1110 cpu
->cp_regs
= g_hash_table_new_full(g_direct_hash
, g_direct_equal
,
1113 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1114 QLIST_INIT(&cpu
->el_change_hooks
);
1116 #ifdef CONFIG_USER_ONLY
1117 # ifdef TARGET_AARCH64
1119 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1120 * These values were chosen to fit within the default signal frame.
1121 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1122 * and our corresponding cpu property.
1124 cpu
->sve_default_vq
= 4;
1125 cpu
->sme_default_vq
= 2;
1128 /* Our inbound IRQ and FIQ lines */
1129 if (kvm_enabled()) {
1130 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1131 * the same interface as non-KVM CPUs.
1133 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1135 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1138 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1139 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1141 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1142 "gicv3-maintenance-interrupt", 1);
1143 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1144 "pmu-interrupt", 1);
1147 /* DTB consumers generally don't in fact care what the 'compatible'
1148 * string is, so always provide some string and trust that a hypothetical
1149 * picky DTB consumer will also provide a helpful error message.
1151 cpu
->dtb_compatible
= "qemu,unknown";
1152 cpu
->psci_version
= QEMU_PSCI_VERSION_0_1
; /* By default assume PSCI v0.1 */
1153 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1155 if (tcg_enabled() || hvf_enabled()) {
1156 /* TCG and HVF implement PSCI 1.1 */
1157 cpu
->psci_version
= QEMU_PSCI_VERSION_1_1
;
1161 static Property arm_cpu_gt_cntfrq_property
=
1162 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1163 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1165 static Property arm_cpu_reset_cbar_property
=
1166 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1168 static Property arm_cpu_reset_hivecs_property
=
1169 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1171 #ifndef CONFIG_USER_ONLY
1172 static Property arm_cpu_has_el2_property
=
1173 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1175 static Property arm_cpu_has_el3_property
=
1176 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1179 static Property arm_cpu_cfgend_property
=
1180 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1182 static Property arm_cpu_has_vfp_property
=
1183 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1185 static Property arm_cpu_has_neon_property
=
1186 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1188 static Property arm_cpu_has_dsp_property
=
1189 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1191 static Property arm_cpu_has_mpu_property
=
1192 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1194 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1195 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1196 * the right value for that particular CPU type, and we don't want
1197 * to override that with an incorrect constant value.
1199 static Property arm_cpu_pmsav7_dregion_property
=
1200 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1202 qdev_prop_uint32
, uint32_t);
1204 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1206 ARMCPU
*cpu
= ARM_CPU(obj
);
1208 return cpu
->has_pmu
;
1211 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1213 ARMCPU
*cpu
= ARM_CPU(obj
);
1216 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1217 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1220 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1222 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1224 cpu
->has_pmu
= value
;
1227 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1230 * The exact approach to calculating guest ticks is:
1232 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1233 * NANOSECONDS_PER_SECOND);
1235 * We don't do that. Rather we intentionally use integer division
1236 * truncation below and in the caller for the conversion of host monotonic
1237 * time to guest ticks to provide the exact inverse for the semantics of
1238 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1239 * it loses precision when representing frequencies where
1240 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1241 * provide an exact inverse leads to scheduling timers with negative
1242 * periods, which in turn leads to sticky behaviour in the guest.
1244 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1245 * cannot become zero.
1247 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1248 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1251 void arm_cpu_post_init(Object
*obj
)
1253 ARMCPU
*cpu
= ARM_CPU(obj
);
1255 /* M profile implies PMSA. We have to do this here rather than
1256 * in realize with the other feature-implication checks because
1257 * we look at the PMSA bit to see if we should add some properties.
1259 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1260 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1263 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1264 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1265 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1268 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1269 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1272 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1273 object_property_add_uint64_ptr(obj
, "rvbar",
1275 OBJ_PROP_FLAG_READWRITE
);
1278 #ifndef CONFIG_USER_ONLY
1279 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1280 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1281 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1283 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1285 object_property_add_link(obj
, "secure-memory",
1287 (Object
**)&cpu
->secure_memory
,
1288 qdev_prop_allow_set_link_before_realize
,
1289 OBJ_PROP_LINK_STRONG
);
1292 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1293 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1297 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1298 cpu
->has_pmu
= true;
1299 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1303 * Allow user to turn off VFP and Neon support, but only for TCG --
1304 * KVM does not currently allow us to lie to the guest about its
1305 * ID/feature registers, so the guest always sees what the host has.
1307 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1308 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1309 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1310 cpu
->has_vfp
= true;
1311 if (!kvm_enabled()) {
1312 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1316 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1317 cpu
->has_neon
= true;
1318 if (!kvm_enabled()) {
1319 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1323 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1324 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1325 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1328 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1329 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1330 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1331 qdev_property_add_static(DEVICE(obj
),
1332 &arm_cpu_pmsav7_dregion_property
);
1336 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1337 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1338 qdev_prop_allow_set_link_before_realize
,
1339 OBJ_PROP_LINK_STRONG
);
1341 * M profile: initial value of the Secure VTOR. We can't just use
1342 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1343 * the property to be set after realize.
1345 object_property_add_uint32_ptr(obj
, "init-svtor",
1347 OBJ_PROP_FLAG_READWRITE
);
1349 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1351 * Initial value of the NS VTOR (for cores without the Security
1352 * extension, this is the only VTOR)
1354 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1356 OBJ_PROP_FLAG_READWRITE
);
1359 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1360 object_property_add_uint32_ptr(obj
, "psci-conduit",
1362 OBJ_PROP_FLAG_READWRITE
);
1364 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1366 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1367 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1370 if (kvm_enabled()) {
1371 kvm_arm_add_vcpu_properties(obj
);
1374 #ifndef CONFIG_USER_ONLY
1375 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1376 cpu_isar_feature(aa64_mte
, cpu
)) {
1377 object_property_add_link(obj
, "tag-memory",
1379 (Object
**)&cpu
->tag_memory
,
1380 qdev_prop_allow_set_link_before_realize
,
1381 OBJ_PROP_LINK_STRONG
);
1383 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1384 object_property_add_link(obj
, "secure-tag-memory",
1386 (Object
**)&cpu
->secure_tag_memory
,
1387 qdev_prop_allow_set_link_before_realize
,
1388 OBJ_PROP_LINK_STRONG
);
1394 static void arm_cpu_finalizefn(Object
*obj
)
1396 ARMCPU
*cpu
= ARM_CPU(obj
);
1397 ARMELChangeHook
*hook
, *next
;
1399 g_hash_table_destroy(cpu
->cp_regs
);
1401 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1402 QLIST_REMOVE(hook
, node
);
1405 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1406 QLIST_REMOVE(hook
, node
);
1409 #ifndef CONFIG_USER_ONLY
1410 if (cpu
->pmu_timer
) {
1411 timer_free(cpu
->pmu_timer
);
1416 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1418 Error
*local_err
= NULL
;
1420 #ifdef TARGET_AARCH64
1421 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1422 arm_cpu_sve_finalize(cpu
, &local_err
);
1423 if (local_err
!= NULL
) {
1424 error_propagate(errp
, local_err
);
1428 arm_cpu_sme_finalize(cpu
, &local_err
);
1429 if (local_err
!= NULL
) {
1430 error_propagate(errp
, local_err
);
1434 arm_cpu_pauth_finalize(cpu
, &local_err
);
1435 if (local_err
!= NULL
) {
1436 error_propagate(errp
, local_err
);
1440 arm_cpu_lpa2_finalize(cpu
, &local_err
);
1441 if (local_err
!= NULL
) {
1442 error_propagate(errp
, local_err
);
1448 if (kvm_enabled()) {
1449 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1450 if (local_err
!= NULL
) {
1451 error_propagate(errp
, local_err
);
1457 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1459 CPUState
*cs
= CPU(dev
);
1460 ARMCPU
*cpu
= ARM_CPU(dev
);
1461 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1462 CPUARMState
*env
= &cpu
->env
;
1464 Error
*local_err
= NULL
;
1465 bool no_aa32
= false;
1467 /* If we needed to query the host kernel for the CPU features
1468 * then it's possible that might have failed in the initfn, but
1469 * this is the first point where we can report it.
1471 if (cpu
->host_cpu_probe_failed
) {
1472 if (!kvm_enabled() && !hvf_enabled()) {
1473 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1475 error_setg(errp
, "Failed to retrieve host CPU features");
1480 #ifndef CONFIG_USER_ONLY
1481 /* The NVIC and M-profile CPU are two halves of a single piece of
1482 * hardware; trying to use one without the other is a command line
1483 * error and will result in segfaults if not caught here.
1485 if (arm_feature(env
, ARM_FEATURE_M
)) {
1487 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1492 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1497 if (!tcg_enabled() && !qtest_enabled()) {
1499 * We assume that no accelerator except TCG (and the "not really an
1500 * accelerator" qtest) can handle these features, because Arm hardware
1501 * virtualization can't virtualize them.
1503 * Catch all the cases which might cause us to create more than one
1504 * address space for the CPU (otherwise we will assert() later in
1505 * cpu_address_space_init()).
1507 if (arm_feature(env
, ARM_FEATURE_M
)) {
1509 "Cannot enable %s when using an M-profile guest CPU",
1510 current_accel_name());
1515 "Cannot enable %s when guest CPU has EL3 enabled",
1516 current_accel_name());
1519 if (cpu
->tag_memory
) {
1521 "Cannot enable %s when guest CPUs has MTE enabled",
1522 current_accel_name());
1530 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1531 if (!cpu
->gt_cntfrq_hz
) {
1532 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1536 scale
= gt_cntfrq_period_ns(cpu
);
1538 scale
= GTIMER_SCALE
;
1541 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1542 arm_gt_ptimer_cb
, cpu
);
1543 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1544 arm_gt_vtimer_cb
, cpu
);
1545 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1546 arm_gt_htimer_cb
, cpu
);
1547 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1548 arm_gt_stimer_cb
, cpu
);
1549 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1550 arm_gt_hvtimer_cb
, cpu
);
1554 cpu_exec_realizefn(cs
, &local_err
);
1555 if (local_err
!= NULL
) {
1556 error_propagate(errp
, local_err
);
1560 arm_cpu_finalize_features(cpu
, &local_err
);
1561 if (local_err
!= NULL
) {
1562 error_propagate(errp
, local_err
);
1566 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1567 cpu
->has_vfp
!= cpu
->has_neon
) {
1569 * This is an architectural requirement for AArch64; AArch32 is
1570 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1573 "AArch64 CPUs must have both VFP and Neon or neither");
1577 if (!cpu
->has_vfp
) {
1581 t
= cpu
->isar
.id_aa64isar1
;
1582 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1583 cpu
->isar
.id_aa64isar1
= t
;
1585 t
= cpu
->isar
.id_aa64pfr0
;
1586 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1587 cpu
->isar
.id_aa64pfr0
= t
;
1589 u
= cpu
->isar
.id_isar6
;
1590 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1591 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1592 cpu
->isar
.id_isar6
= u
;
1594 u
= cpu
->isar
.mvfr0
;
1595 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1596 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1597 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1598 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1599 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1600 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1601 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1602 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1604 cpu
->isar
.mvfr0
= u
;
1606 u
= cpu
->isar
.mvfr1
;
1607 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1608 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1609 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1610 if (arm_feature(env
, ARM_FEATURE_M
)) {
1611 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1613 cpu
->isar
.mvfr1
= u
;
1615 u
= cpu
->isar
.mvfr2
;
1616 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1617 cpu
->isar
.mvfr2
= u
;
1620 if (!cpu
->has_neon
) {
1624 unset_feature(env
, ARM_FEATURE_NEON
);
1626 t
= cpu
->isar
.id_aa64isar0
;
1627 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 0);
1628 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 0);
1629 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 0);
1630 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 0);
1631 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 0);
1632 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 0);
1633 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1634 cpu
->isar
.id_aa64isar0
= t
;
1636 t
= cpu
->isar
.id_aa64isar1
;
1637 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1638 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
1639 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
1640 cpu
->isar
.id_aa64isar1
= t
;
1642 t
= cpu
->isar
.id_aa64pfr0
;
1643 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1644 cpu
->isar
.id_aa64pfr0
= t
;
1646 u
= cpu
->isar
.id_isar5
;
1647 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 0);
1648 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 0);
1649 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 0);
1650 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1651 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1652 cpu
->isar
.id_isar5
= u
;
1654 u
= cpu
->isar
.id_isar6
;
1655 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1656 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1657 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1658 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
1659 cpu
->isar
.id_isar6
= u
;
1661 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1662 u
= cpu
->isar
.mvfr1
;
1663 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1664 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1665 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1666 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1667 cpu
->isar
.mvfr1
= u
;
1669 u
= cpu
->isar
.mvfr2
;
1670 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1671 cpu
->isar
.mvfr2
= u
;
1675 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1679 t
= cpu
->isar
.id_aa64isar0
;
1680 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1681 cpu
->isar
.id_aa64isar0
= t
;
1683 t
= cpu
->isar
.id_aa64isar1
;
1684 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1685 cpu
->isar
.id_aa64isar1
= t
;
1687 u
= cpu
->isar
.mvfr0
;
1688 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1689 cpu
->isar
.mvfr0
= u
;
1691 /* Despite the name, this field covers both VFP and Neon */
1692 u
= cpu
->isar
.mvfr1
;
1693 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1694 cpu
->isar
.mvfr1
= u
;
1697 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1700 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1702 u
= cpu
->isar
.id_isar1
;
1703 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1704 cpu
->isar
.id_isar1
= u
;
1706 u
= cpu
->isar
.id_isar2
;
1707 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1708 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1709 cpu
->isar
.id_isar2
= u
;
1711 u
= cpu
->isar
.id_isar3
;
1712 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1713 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1714 cpu
->isar
.id_isar3
= u
;
1717 /* Some features automatically imply others: */
1718 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1719 if (arm_feature(env
, ARM_FEATURE_M
)) {
1720 set_feature(env
, ARM_FEATURE_V7
);
1722 set_feature(env
, ARM_FEATURE_V7VE
);
1727 * There exist AArch64 cpus without AArch32 support. When KVM
1728 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1729 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1730 * As a general principle, we also do not make ID register
1731 * consistency checks anywhere unless using TCG, because only
1732 * for TCG would a consistency-check failure be a QEMU bug.
1734 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1735 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1738 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1739 /* v7 Virtualization Extensions. In real hardware this implies
1740 * EL2 and also the presence of the Security Extensions.
1741 * For QEMU, for backwards-compatibility we implement some
1742 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1743 * include the various other features that V7VE implies.
1744 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1745 * Security Extensions is ARM_FEATURE_EL3.
1747 assert(!tcg_enabled() || no_aa32
||
1748 cpu_isar_feature(aa32_arm_div
, cpu
));
1749 set_feature(env
, ARM_FEATURE_LPAE
);
1750 set_feature(env
, ARM_FEATURE_V7
);
1752 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1753 set_feature(env
, ARM_FEATURE_VAPA
);
1754 set_feature(env
, ARM_FEATURE_THUMB2
);
1755 set_feature(env
, ARM_FEATURE_MPIDR
);
1756 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1757 set_feature(env
, ARM_FEATURE_V6K
);
1759 set_feature(env
, ARM_FEATURE_V6
);
1762 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1763 * non-EL3 configs. This is needed by some legacy boards.
1765 set_feature(env
, ARM_FEATURE_VBAR
);
1767 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1768 set_feature(env
, ARM_FEATURE_V6
);
1769 set_feature(env
, ARM_FEATURE_MVFR
);
1771 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1772 set_feature(env
, ARM_FEATURE_V5
);
1773 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1774 assert(!tcg_enabled() || no_aa32
||
1775 cpu_isar_feature(aa32_jazelle
, cpu
));
1776 set_feature(env
, ARM_FEATURE_AUXCR
);
1779 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1780 set_feature(env
, ARM_FEATURE_V4T
);
1782 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1783 set_feature(env
, ARM_FEATURE_V7MP
);
1785 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1786 set_feature(env
, ARM_FEATURE_CBAR
);
1788 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1789 !arm_feature(env
, ARM_FEATURE_M
)) {
1790 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1794 * We rely on no XScale CPU having VFP so we can use the same bits in the
1795 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1797 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1798 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1799 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1801 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1802 !arm_feature(env
, ARM_FEATURE_M
) &&
1803 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1804 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1809 /* For CPUs which might have tiny 1K pages, or which have an
1810 * MPU and might have small region sizes, stick with 1K pages.
1814 if (!set_preferred_target_page_bits(pagebits
)) {
1815 /* This can only ever happen for hotplugging a CPU, or if
1816 * the board code incorrectly creates a CPU which it has
1817 * promised via minimum_page_size that it will not.
1819 error_setg(errp
, "This CPU requires a smaller page size than the "
1824 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1825 * We don't support setting cluster ID ([16..23]) (known as Aff2
1826 * in later ARM ARM versions), or any of the higher affinity level fields,
1827 * so these bits always RAZ.
1829 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1830 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1831 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1834 if (cpu
->reset_hivecs
) {
1835 cpu
->reset_sctlr
|= (1 << 13);
1839 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1840 cpu
->reset_sctlr
|= SCTLR_EE
;
1842 cpu
->reset_sctlr
|= SCTLR_B
;
1846 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
1847 /* If the has_el3 CPU property is disabled then we need to disable the
1850 unset_feature(env
, ARM_FEATURE_EL3
);
1853 * Disable the security extension feature bits in the processor
1854 * feature registers as well.
1856 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
, ID_PFR1
, SECURITY
, 0);
1857 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPSDBG
, 0);
1858 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
1859 ID_AA64PFR0
, EL3
, 0);
1862 if (!cpu
->has_el2
) {
1863 unset_feature(env
, ARM_FEATURE_EL2
);
1866 if (!cpu
->has_pmu
) {
1867 unset_feature(env
, ARM_FEATURE_PMU
);
1869 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1872 if (!kvm_enabled()) {
1873 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1874 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1877 #ifndef CONFIG_USER_ONLY
1878 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1882 cpu
->isar
.id_aa64dfr0
=
1883 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1884 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1889 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1891 * Disable the hypervisor feature bits in the processor feature
1892 * registers if we don't have EL2.
1894 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
1895 ID_AA64PFR0
, EL2
, 0);
1896 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
,
1897 ID_PFR1
, VIRTUALIZATION
, 0);
1900 #ifndef CONFIG_USER_ONLY
1901 if (cpu
->tag_memory
== NULL
&& cpu_isar_feature(aa64_mte
, cpu
)) {
1903 * Disable the MTE feature bits if we do not have tag-memory
1904 * provided by the machine.
1906 cpu
->isar
.id_aa64pfr1
=
1907 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 0);
1911 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1912 * to false or by setting pmsav7-dregion to 0.
1914 if (!cpu
->has_mpu
) {
1915 cpu
->pmsav7_dregion
= 0;
1917 if (cpu
->pmsav7_dregion
== 0) {
1918 cpu
->has_mpu
= false;
1921 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1922 arm_feature(env
, ARM_FEATURE_V7
)) {
1923 uint32_t nr
= cpu
->pmsav7_dregion
;
1926 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1931 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1933 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1934 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1935 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1936 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1937 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1940 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1941 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1942 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1947 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1948 uint32_t nr
= cpu
->sau_sregion
;
1951 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1956 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1957 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1961 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1962 set_feature(env
, ARM_FEATURE_VBAR
);
1965 register_cp_regs_for_features(cpu
);
1966 arm_cpu_register_gdb_regs_for_features(cpu
);
1968 init_cpreg_list(cpu
);
1970 #ifndef CONFIG_USER_ONLY
1971 MachineState
*ms
= MACHINE(qdev_get_machine());
1972 unsigned int smp_cpus
= ms
->smp
.cpus
;
1973 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
1976 * We must set cs->num_ases to the final value before
1977 * the first call to cpu_address_space_init.
1979 if (cpu
->tag_memory
!= NULL
) {
1980 cs
->num_ases
= 3 + has_secure
;
1982 cs
->num_ases
= 1 + has_secure
;
1986 if (!cpu
->secure_memory
) {
1987 cpu
->secure_memory
= cs
->memory
;
1989 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1990 cpu
->secure_memory
);
1993 if (cpu
->tag_memory
!= NULL
) {
1994 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
1997 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
1998 cpu
->secure_tag_memory
);
2002 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
2004 /* No core_count specified, default to smp_cpus. */
2005 if (cpu
->core_count
== -1) {
2006 cpu
->core_count
= smp_cpus
;
2010 if (tcg_enabled()) {
2011 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
2014 * We only support DCZ blocklen that fits on one page.
2016 * Architectually this is always true. However TARGET_PAGE_SIZE
2017 * is variable and, for compatibility with -machine virt-2.7,
2018 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2019 * But even then, while the largest architectural DCZ blocklen
2020 * is 2KiB, no cpu actually uses such a large blocklen.
2022 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
2025 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2026 * both nibbles of each byte storing tag data may be written at once.
2027 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2029 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2030 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
2037 acc
->parent_realize(dev
, errp
);
2040 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
2045 const char *cpunamestr
;
2047 cpuname
= g_strsplit(cpu_model
, ",", 1);
2048 cpunamestr
= cpuname
[0];
2049 #ifdef CONFIG_USER_ONLY
2050 /* For backwards compatibility usermode emulation allows "-cpu any",
2051 * which has the same semantics as "-cpu max".
2053 if (!strcmp(cpunamestr
, "any")) {
2057 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
2058 oc
= object_class_by_name(typename
);
2059 g_strfreev(cpuname
);
2061 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
2062 object_class_is_abstract(oc
)) {
2068 static Property arm_cpu_properties
[] = {
2069 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2070 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2071 mp_affinity
, ARM64_AFFINITY_INVALID
),
2072 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2073 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2074 DEFINE_PROP_END_OF_LIST()
2077 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2079 ARMCPU
*cpu
= ARM_CPU(cs
);
2080 CPUARMState
*env
= &cpu
->env
;
2082 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2083 return g_strdup("iwmmxt");
2085 return g_strdup("arm");
2088 #ifndef CONFIG_USER_ONLY
2089 #include "hw/core/sysemu-cpu-ops.h"
2091 static const struct SysemuCPUOps arm_sysemu_ops
= {
2092 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2093 .asidx_from_attrs
= arm_asidx_from_attrs
,
2094 .write_elf32_note
= arm_cpu_write_elf32_note
,
2095 .write_elf64_note
= arm_cpu_write_elf64_note
,
2096 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2097 .legacy_vmsd
= &vmstate_arm_cpu
,
2102 static const struct TCGCPUOps arm_tcg_ops
= {
2103 .initialize
= arm_translate_init
,
2104 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2105 .debug_excp_handler
= arm_debug_excp_handler
,
2107 #ifdef CONFIG_USER_ONLY
2108 .record_sigsegv
= arm_cpu_record_sigsegv
,
2109 .record_sigbus
= arm_cpu_record_sigbus
,
2111 .tlb_fill
= arm_cpu_tlb_fill
,
2112 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2113 .do_interrupt
= arm_cpu_do_interrupt
,
2114 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2115 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2116 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2117 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2118 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2119 #endif /* !CONFIG_USER_ONLY */
2121 #endif /* CONFIG_TCG */
2123 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2125 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2126 CPUClass
*cc
= CPU_CLASS(acc
);
2127 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2129 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2130 &acc
->parent_realize
);
2132 device_class_set_props(dc
, arm_cpu_properties
);
2133 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2135 cc
->class_by_name
= arm_cpu_class_by_name
;
2136 cc
->has_work
= arm_cpu_has_work
;
2137 cc
->dump_state
= arm_cpu_dump_state
;
2138 cc
->set_pc
= arm_cpu_set_pc
;
2139 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2140 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2141 #ifndef CONFIG_USER_ONLY
2142 cc
->sysemu_ops
= &arm_sysemu_ops
;
2144 cc
->gdb_num_core_regs
= 26;
2145 cc
->gdb_core_xml_file
= "arm-core.xml";
2146 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2147 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2148 cc
->gdb_stop_before_watchpoint
= true;
2149 cc
->disas_set_info
= arm_disas_set_info
;
2152 cc
->tcg_ops
= &arm_tcg_ops
;
2153 #endif /* CONFIG_TCG */
2156 static void arm_cpu_instance_init(Object
*obj
)
2158 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2160 acc
->info
->initfn(obj
);
2161 arm_cpu_post_init(obj
);
2164 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2166 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2171 void arm_cpu_register(const ARMCPUInfo
*info
)
2173 TypeInfo type_info
= {
2174 .parent
= TYPE_ARM_CPU
,
2175 .instance_size
= sizeof(ARMCPU
),
2176 .instance_align
= __alignof__(ARMCPU
),
2177 .instance_init
= arm_cpu_instance_init
,
2178 .class_size
= sizeof(ARMCPUClass
),
2179 .class_init
= info
->class_init
?: cpu_register_class_init
,
2180 .class_data
= (void *)info
,
2183 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2184 type_register(&type_info
);
2185 g_free((void *)type_info
.name
);
2188 static const TypeInfo arm_cpu_type_info
= {
2189 .name
= TYPE_ARM_CPU
,
2191 .instance_size
= sizeof(ARMCPU
),
2192 .instance_align
= __alignof__(ARMCPU
),
2193 .instance_init
= arm_cpu_initfn
,
2194 .instance_finalize
= arm_cpu_finalizefn
,
2196 .class_size
= sizeof(ARMCPUClass
),
2197 .class_init
= arm_cpu_class_init
,
2200 static void arm_cpu_register_types(void)
2202 type_register_static(&arm_cpu_type_info
);
2205 type_init(arm_cpu_register_types
)