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vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-type
[qemu.git] / hw / arm / pxa2xx.c
blob25ec549e7137abe1b4546115d9728a0617122db3
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "hw/sysbus.h"
11 #include "hw/arm/pxa.h"
12 #include "sysemu/sysemu.h"
13 #include "hw/char/serial.h"
14 #include "hw/i2c/i2c.h"
15 #include "hw/ssi.h"
16 #include "sysemu/char.h"
17 #include "sysemu/blockdev.h"
18
19 static struct {
20 hwaddr io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 hwaddr io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 /* Clear the write-one-to-clear bits... */
118 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
119 /* ...and set the plain r/w bits */
120 s->pm_regs[addr >> 2] &= ~0x15;
121 s->pm_regs[addr >> 2] |= value & 0x15;
122 break;
123
124 case PSSR: /* Read-clean registers */
125 case RCSR:
126 case PKSR:
127 s->pm_regs[addr >> 2] &= ~value;
128 break;
129
130 default: /* Read-write registers */
131 if (!(addr & 3)) {
132 s->pm_regs[addr >> 2] = value;
133 break;
134 }
135
136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
137 break;
138 }
139 }
140
141 static const MemoryRegionOps pxa2xx_pm_ops = {
142 .read = pxa2xx_pm_read,
143 .write = pxa2xx_pm_write,
144 .endianness = DEVICE_NATIVE_ENDIAN,
145 };
146
147 static const VMStateDescription vmstate_pxa2xx_pm = {
148 .name = "pxa2xx_pm",
149 .version_id = 0,
150 .minimum_version_id = 0,
151 .minimum_version_id_old = 0,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
154 VMSTATE_END_OF_LIST()
155 }
156 };
157
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
162
163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
164 unsigned size)
165 {
166 PXA2xxState *s = (PXA2xxState *) opaque;
167
168 switch (addr) {
169 case CCCR:
170 case CKEN:
171 case OSCC:
172 return s->cm_regs[addr >> 2];
173
174 case CCSR:
175 return s->cm_regs[CCCR >> 2] | (3 << 28);
176
177 default:
178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
179 break;
180 }
181 return 0;
182 }
183
184 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
185 uint64_t value, unsigned size)
186 {
187 PXA2xxState *s = (PXA2xxState *) opaque;
188
189 switch (addr) {
190 case CCCR:
191 case CKEN:
192 s->cm_regs[addr >> 2] = value;
193 break;
194
195 case OSCC:
196 s->cm_regs[addr >> 2] &= ~0x6c;
197 s->cm_regs[addr >> 2] |= value & 0x6e;
198 if ((value >> 1) & 1) /* OON */
199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
200 break;
201
202 default:
203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
204 break;
205 }
206 }
207
208 static const MemoryRegionOps pxa2xx_cm_ops = {
209 .read = pxa2xx_cm_read,
210 .write = pxa2xx_cm_write,
211 .endianness = DEVICE_NATIVE_ENDIAN,
212 };
213
214 static const VMStateDescription vmstate_pxa2xx_cm = {
215 .name = "pxa2xx_cm",
216 .version_id = 0,
217 .minimum_version_id = 0,
218 .minimum_version_id_old = 0,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
221 VMSTATE_UINT32(clkcfg, PXA2xxState),
222 VMSTATE_UINT32(pmnc, PXA2xxState),
223 VMSTATE_END_OF_LIST()
224 }
225 };
226
227 static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri,
228 uint64_t *value)
229 {
230 PXA2xxState *s = (PXA2xxState *)ri->opaque;
231 *value = s->clkcfg;
232 return 0;
233 }
234
235 static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
236 uint64_t value)
237 {
238 PXA2xxState *s = (PXA2xxState *)ri->opaque;
239 s->clkcfg = value & 0xf;
240 if (value & 2) {
241 printf("%s: CPU frequency change attempt\n", __func__);
242 }
243 return 0;
244 }
245
246 static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
247 uint64_t value)
248 {
249 PXA2xxState *s = (PXA2xxState *)ri->opaque;
250 static const char *pwrmode[8] = {
251 "Normal", "Idle", "Deep-idle", "Standby",
252 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
253 };
254
255 if (value & 8) {
256 printf("%s: CPU voltage change attempt\n", __func__);
257 }
258 switch (value & 7) {
259 case 0:
260 /* Do nothing */
261 break;
262
263 case 1:
264 /* Idle */
265 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
266 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
267 break;
268 }
269 /* Fall through. */
270
271 case 2:
272 /* Deep-Idle */
273 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
274 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
275 goto message;
276
277 case 3:
278 s->cpu->env.uncached_cpsr =
279 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
280 s->cpu->env.cp15.c1_sys = 0;
281 s->cpu->env.cp15.c1_coproc = 0;
282 s->cpu->env.cp15.c2_base0 = 0;
283 s->cpu->env.cp15.c3 = 0;
284 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
285 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
286
287 /*
288 * The scratch-pad register is almost universally used
289 * for storing the return address on suspend. For the
290 * lack of a resuming bootloader, perform a jump
291 * directly to that address.
292 */
293 memset(s->cpu->env.regs, 0, 4 * 15);
294 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
295
296 #if 0
297 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
298 cpu_physical_memory_write(0, &buffer, 4);
299 buffer = s->pm_regs[PSPR >> 2];
300 cpu_physical_memory_write(8, &buffer, 4);
301 #endif
302
303 /* Suspend */
304 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
305
306 goto message;
307
308 default:
309 message:
310 printf("%s: machine entered %s mode\n", __func__,
311 pwrmode[value & 7]);
312 }
313
314 return 0;
315 }
316
317 static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
318 uint64_t *value)
319 {
320 PXA2xxState *s = (PXA2xxState *)ri->opaque;
321 *value = s->pmnc;
322 return 0;
323 }
324
325 static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
326 uint64_t value)
327 {
328 PXA2xxState *s = (PXA2xxState *)ri->opaque;
329 s->pmnc = value;
330 return 0;
331 }
332
333 static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
334 uint64_t *value)
335 {
336 PXA2xxState *s = (PXA2xxState *)ri->opaque;
337 if (s->pmnc & 1) {
338 *value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
339 } else {
340 *value = 0;
341 }
342 return 0;
343 }
344
345 static const ARMCPRegInfo pxa_cp_reginfo[] = {
346 /* cp14 crm==1: perf registers */
347 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
348 .access = PL1_RW,
349 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
350 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
351 .access = PL1_RW,
352 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
353 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
354 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
355 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
357 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
358 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
359 /* cp14 crm==2: performance count registers */
360 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
361 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
362 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
363 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
364 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
366 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
367 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
368 /* cp14 crn==6: CLKCFG */
369 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
370 .access = PL1_RW,
371 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
372 /* cp14 crn==7: PWRMODE */
373 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
374 .access = PL1_RW,
375 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
376 REGINFO_SENTINEL
377 };
378
379 static void pxa2xx_setup_cp14(PXA2xxState *s)
380 {
381 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
382 }
383
384 #define MDCNFG 0x00 /* SDRAM Configuration register */
385 #define MDREFR 0x04 /* SDRAM Refresh Control register */
386 #define MSC0 0x08 /* Static Memory Control register 0 */
387 #define MSC1 0x0c /* Static Memory Control register 1 */
388 #define MSC2 0x10 /* Static Memory Control register 2 */
389 #define MECR 0x14 /* Expansion Memory Bus Config register */
390 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
391 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
392 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
393 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
394 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
395 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
396 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
397 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
398 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
399 #define ARB_CNTL 0x48 /* Arbiter Control register */
400 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
401 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
402 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
403 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
404 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
405 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
406 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
407
408 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
409 unsigned size)
410 {
411 PXA2xxState *s = (PXA2xxState *) opaque;
412
413 switch (addr) {
414 case MDCNFG ... SA1110:
415 if ((addr & 3) == 0)
416 return s->mm_regs[addr >> 2];
417
418 default:
419 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
420 break;
421 }
422 return 0;
423 }
424
425 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
426 uint64_t value, unsigned size)
427 {
428 PXA2xxState *s = (PXA2xxState *) opaque;
429
430 switch (addr) {
431 case MDCNFG ... SA1110:
432 if ((addr & 3) == 0) {
433 s->mm_regs[addr >> 2] = value;
434 break;
435 }
436
437 default:
438 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
439 break;
440 }
441 }
442
443 static const MemoryRegionOps pxa2xx_mm_ops = {
444 .read = pxa2xx_mm_read,
445 .write = pxa2xx_mm_write,
446 .endianness = DEVICE_NATIVE_ENDIAN,
447 };
448
449 static const VMStateDescription vmstate_pxa2xx_mm = {
450 .name = "pxa2xx_mm",
451 .version_id = 0,
452 .minimum_version_id = 0,
453 .minimum_version_id_old = 0,
454 .fields = (VMStateField[]) {
455 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
456 VMSTATE_END_OF_LIST()
457 }
458 };
459
460 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
461 #define PXA2XX_SSP(obj) \
462 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
463
464 /* Synchronous Serial Ports */
465 typedef struct {
466 /*< private >*/
467 SysBusDevice parent_obj;
468 /*< public >*/
469
470 MemoryRegion iomem;
471 qemu_irq irq;
472 int enable;
473 SSIBus *bus;
474
475 uint32_t sscr[2];
476 uint32_t sspsp;
477 uint32_t ssto;
478 uint32_t ssitr;
479 uint32_t sssr;
480 uint8_t sstsa;
481 uint8_t ssrsa;
482 uint8_t ssacd;
483
484 uint32_t rx_fifo[16];
485 int rx_level;
486 int rx_start;
487 } PXA2xxSSPState;
488
489 #define SSCR0 0x00 /* SSP Control register 0 */
490 #define SSCR1 0x04 /* SSP Control register 1 */
491 #define SSSR 0x08 /* SSP Status register */
492 #define SSITR 0x0c /* SSP Interrupt Test register */
493 #define SSDR 0x10 /* SSP Data register */
494 #define SSTO 0x28 /* SSP Time-Out register */
495 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
496 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
497 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
498 #define SSTSS 0x38 /* SSP Time Slot Status register */
499 #define SSACD 0x3c /* SSP Audio Clock Divider register */
500
501 /* Bitfields for above registers */
502 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
503 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
504 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
505 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
506 #define SSCR0_SSE (1 << 7)
507 #define SSCR0_RIM (1 << 22)
508 #define SSCR0_TIM (1 << 23)
509 #define SSCR0_MOD (1 << 31)
510 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
511 #define SSCR1_RIE (1 << 0)
512 #define SSCR1_TIE (1 << 1)
513 #define SSCR1_LBM (1 << 2)
514 #define SSCR1_MWDS (1 << 5)
515 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
516 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
517 #define SSCR1_EFWR (1 << 14)
518 #define SSCR1_PINTE (1 << 18)
519 #define SSCR1_TINTE (1 << 19)
520 #define SSCR1_RSRE (1 << 20)
521 #define SSCR1_TSRE (1 << 21)
522 #define SSCR1_EBCEI (1 << 29)
523 #define SSITR_INT (7 << 5)
524 #define SSSR_TNF (1 << 2)
525 #define SSSR_RNE (1 << 3)
526 #define SSSR_TFS (1 << 5)
527 #define SSSR_RFS (1 << 6)
528 #define SSSR_ROR (1 << 7)
529 #define SSSR_PINT (1 << 18)
530 #define SSSR_TINT (1 << 19)
531 #define SSSR_EOC (1 << 20)
532 #define SSSR_TUR (1 << 21)
533 #define SSSR_BCE (1 << 23)
534 #define SSSR_RW 0x00bc0080
535
536 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
537 {
538 int level = 0;
539
540 level |= s->ssitr & SSITR_INT;
541 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
542 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
543 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
544 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
545 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
546 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
547 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
548 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
549 qemu_set_irq(s->irq, !!level);
550 }
551
552 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
553 {
554 s->sssr &= ~(0xf << 12); /* Clear RFL */
555 s->sssr &= ~(0xf << 8); /* Clear TFL */
556 s->sssr &= ~SSSR_TFS;
557 s->sssr &= ~SSSR_TNF;
558 if (s->enable) {
559 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
560 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
561 s->sssr |= SSSR_RFS;
562 else
563 s->sssr &= ~SSSR_RFS;
564 if (s->rx_level)
565 s->sssr |= SSSR_RNE;
566 else
567 s->sssr &= ~SSSR_RNE;
568 /* TX FIFO is never filled, so it is always in underrun
569 condition if SSP is enabled */
570 s->sssr |= SSSR_TFS;
571 s->sssr |= SSSR_TNF;
572 }
573
574 pxa2xx_ssp_int_update(s);
575 }
576
577 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
578 unsigned size)
579 {
580 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
581 uint32_t retval;
582
583 switch (addr) {
584 case SSCR0:
585 return s->sscr[0];
586 case SSCR1:
587 return s->sscr[1];
588 case SSPSP:
589 return s->sspsp;
590 case SSTO:
591 return s->ssto;
592 case SSITR:
593 return s->ssitr;
594 case SSSR:
595 return s->sssr | s->ssitr;
596 case SSDR:
597 if (!s->enable)
598 return 0xffffffff;
599 if (s->rx_level < 1) {
600 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
601 return 0xffffffff;
602 }
603 s->rx_level --;
604 retval = s->rx_fifo[s->rx_start ++];
605 s->rx_start &= 0xf;
606 pxa2xx_ssp_fifo_update(s);
607 return retval;
608 case SSTSA:
609 return s->sstsa;
610 case SSRSA:
611 return s->ssrsa;
612 case SSTSS:
613 return 0;
614 case SSACD:
615 return s->ssacd;
616 default:
617 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
618 break;
619 }
620 return 0;
621 }
622
623 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
624 uint64_t value64, unsigned size)
625 {
626 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
627 uint32_t value = value64;
628
629 switch (addr) {
630 case SSCR0:
631 s->sscr[0] = value & 0xc7ffffff;
632 s->enable = value & SSCR0_SSE;
633 if (value & SSCR0_MOD)
634 printf("%s: Attempt to use network mode\n", __FUNCTION__);
635 if (s->enable && SSCR0_DSS(value) < 4)
636 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
637 SSCR0_DSS(value));
638 if (!(value & SSCR0_SSE)) {
639 s->sssr = 0;
640 s->ssitr = 0;
641 s->rx_level = 0;
642 }
643 pxa2xx_ssp_fifo_update(s);
644 break;
645
646 case SSCR1:
647 s->sscr[1] = value;
648 if (value & (SSCR1_LBM | SSCR1_EFWR))
649 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
650 pxa2xx_ssp_fifo_update(s);
651 break;
652
653 case SSPSP:
654 s->sspsp = value;
655 break;
656
657 case SSTO:
658 s->ssto = value;
659 break;
660
661 case SSITR:
662 s->ssitr = value & SSITR_INT;
663 pxa2xx_ssp_int_update(s);
664 break;
665
666 case SSSR:
667 s->sssr &= ~(value & SSSR_RW);
668 pxa2xx_ssp_int_update(s);
669 break;
670
671 case SSDR:
672 if (SSCR0_UWIRE(s->sscr[0])) {
673 if (s->sscr[1] & SSCR1_MWDS)
674 value &= 0xffff;
675 else
676 value &= 0xff;
677 } else
678 /* Note how 32bits overflow does no harm here */
679 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
680
681 /* Data goes from here to the Tx FIFO and is shifted out from
682 * there directly to the slave, no need to buffer it.
683 */
684 if (s->enable) {
685 uint32_t readval;
686 readval = ssi_transfer(s->bus, value);
687 if (s->rx_level < 0x10) {
688 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
689 } else {
690 s->sssr |= SSSR_ROR;
691 }
692 }
693 pxa2xx_ssp_fifo_update(s);
694 break;
695
696 case SSTSA:
697 s->sstsa = value;
698 break;
699
700 case SSRSA:
701 s->ssrsa = value;
702 break;
703
704 case SSACD:
705 s->ssacd = value;
706 break;
707
708 default:
709 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
710 break;
711 }
712 }
713
714 static const MemoryRegionOps pxa2xx_ssp_ops = {
715 .read = pxa2xx_ssp_read,
716 .write = pxa2xx_ssp_write,
717 .endianness = DEVICE_NATIVE_ENDIAN,
718 };
719
720 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
721 {
722 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
723 int i;
724
725 qemu_put_be32(f, s->enable);
726
727 qemu_put_be32s(f, &s->sscr[0]);
728 qemu_put_be32s(f, &s->sscr[1]);
729 qemu_put_be32s(f, &s->sspsp);
730 qemu_put_be32s(f, &s->ssto);
731 qemu_put_be32s(f, &s->ssitr);
732 qemu_put_be32s(f, &s->sssr);
733 qemu_put_8s(f, &s->sstsa);
734 qemu_put_8s(f, &s->ssrsa);
735 qemu_put_8s(f, &s->ssacd);
736
737 qemu_put_byte(f, s->rx_level);
738 for (i = 0; i < s->rx_level; i ++)
739 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
740 }
741
742 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
743 {
744 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
745 int i;
746
747 s->enable = qemu_get_be32(f);
748
749 qemu_get_be32s(f, &s->sscr[0]);
750 qemu_get_be32s(f, &s->sscr[1]);
751 qemu_get_be32s(f, &s->sspsp);
752 qemu_get_be32s(f, &s->ssto);
753 qemu_get_be32s(f, &s->ssitr);
754 qemu_get_be32s(f, &s->sssr);
755 qemu_get_8s(f, &s->sstsa);
756 qemu_get_8s(f, &s->ssrsa);
757 qemu_get_8s(f, &s->ssacd);
758
759 s->rx_level = qemu_get_byte(f);
760 s->rx_start = 0;
761 for (i = 0; i < s->rx_level; i ++)
762 s->rx_fifo[i] = qemu_get_byte(f);
763
764 return 0;
765 }
766
767 static int pxa2xx_ssp_init(SysBusDevice *sbd)
768 {
769 DeviceState *dev = DEVICE(sbd);
770 PXA2xxSSPState *s = PXA2XX_SSP(dev);
771
772 sysbus_init_irq(sbd, &s->irq);
773
774 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
775 "pxa2xx-ssp", 0x1000);
776 sysbus_init_mmio(sbd, &s->iomem);
777 register_savevm(dev, "pxa2xx_ssp", -1, 0,
778 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
779
780 s->bus = ssi_create_bus(dev, "ssi");
781 return 0;
782 }
783
784 /* Real-Time Clock */
785 #define RCNR 0x00 /* RTC Counter register */
786 #define RTAR 0x04 /* RTC Alarm register */
787 #define RTSR 0x08 /* RTC Status register */
788 #define RTTR 0x0c /* RTC Timer Trim register */
789 #define RDCR 0x10 /* RTC Day Counter register */
790 #define RYCR 0x14 /* RTC Year Counter register */
791 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
792 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
793 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
794 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
795 #define SWCR 0x28 /* RTC Stopwatch Counter register */
796 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
797 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
798 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
799 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
800
801 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
802 #define PXA2XX_RTC(obj) \
803 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
804
805 typedef struct {
806 /*< private >*/
807 SysBusDevice parent_obj;
808 /*< public >*/
809
810 MemoryRegion iomem;
811 uint32_t rttr;
812 uint32_t rtsr;
813 uint32_t rtar;
814 uint32_t rdar1;
815 uint32_t rdar2;
816 uint32_t ryar1;
817 uint32_t ryar2;
818 uint32_t swar1;
819 uint32_t swar2;
820 uint32_t piar;
821 uint32_t last_rcnr;
822 uint32_t last_rdcr;
823 uint32_t last_rycr;
824 uint32_t last_swcr;
825 uint32_t last_rtcpicr;
826 int64_t last_hz;
827 int64_t last_sw;
828 int64_t last_pi;
829 QEMUTimer *rtc_hz;
830 QEMUTimer *rtc_rdal1;
831 QEMUTimer *rtc_rdal2;
832 QEMUTimer *rtc_swal1;
833 QEMUTimer *rtc_swal2;
834 QEMUTimer *rtc_pi;
835 qemu_irq rtc_irq;
836 } PXA2xxRTCState;
837
838 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
839 {
840 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
841 }
842
843 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
844 {
845 int64_t rt = qemu_clock_get_ms(rtc_clock);
846 s->last_rcnr += ((rt - s->last_hz) << 15) /
847 (1000 * ((s->rttr & 0xffff) + 1));
848 s->last_rdcr += ((rt - s->last_hz) << 15) /
849 (1000 * ((s->rttr & 0xffff) + 1));
850 s->last_hz = rt;
851 }
852
853 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
854 {
855 int64_t rt = qemu_clock_get_ms(rtc_clock);
856 if (s->rtsr & (1 << 12))
857 s->last_swcr += (rt - s->last_sw) / 10;
858 s->last_sw = rt;
859 }
860
861 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
862 {
863 int64_t rt = qemu_clock_get_ms(rtc_clock);
864 if (s->rtsr & (1 << 15))
865 s->last_swcr += rt - s->last_pi;
866 s->last_pi = rt;
867 }
868
869 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
870 uint32_t rtsr)
871 {
872 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
873 timer_mod(s->rtc_hz, s->last_hz +
874 (((s->rtar - s->last_rcnr) * 1000 *
875 ((s->rttr & 0xffff) + 1)) >> 15));
876 else
877 timer_del(s->rtc_hz);
878
879 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
880 timer_mod(s->rtc_rdal1, s->last_hz +
881 (((s->rdar1 - s->last_rdcr) * 1000 *
882 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
883 else
884 timer_del(s->rtc_rdal1);
885
886 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
887 timer_mod(s->rtc_rdal2, s->last_hz +
888 (((s->rdar2 - s->last_rdcr) * 1000 *
889 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
890 else
891 timer_del(s->rtc_rdal2);
892
893 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
894 timer_mod(s->rtc_swal1, s->last_sw +
895 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
896 else
897 timer_del(s->rtc_swal1);
898
899 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
900 timer_mod(s->rtc_swal2, s->last_sw +
901 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
902 else
903 timer_del(s->rtc_swal2);
904
905 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
906 timer_mod(s->rtc_pi, s->last_pi +
907 (s->piar & 0xffff) - s->last_rtcpicr);
908 else
909 timer_del(s->rtc_pi);
910 }
911
912 static inline void pxa2xx_rtc_hz_tick(void *opaque)
913 {
914 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
915 s->rtsr |= (1 << 0);
916 pxa2xx_rtc_alarm_update(s, s->rtsr);
917 pxa2xx_rtc_int_update(s);
918 }
919
920 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
921 {
922 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
923 s->rtsr |= (1 << 4);
924 pxa2xx_rtc_alarm_update(s, s->rtsr);
925 pxa2xx_rtc_int_update(s);
926 }
927
928 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
929 {
930 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
931 s->rtsr |= (1 << 6);
932 pxa2xx_rtc_alarm_update(s, s->rtsr);
933 pxa2xx_rtc_int_update(s);
934 }
935
936 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
937 {
938 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
939 s->rtsr |= (1 << 8);
940 pxa2xx_rtc_alarm_update(s, s->rtsr);
941 pxa2xx_rtc_int_update(s);
942 }
943
944 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
945 {
946 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
947 s->rtsr |= (1 << 10);
948 pxa2xx_rtc_alarm_update(s, s->rtsr);
949 pxa2xx_rtc_int_update(s);
950 }
951
952 static inline void pxa2xx_rtc_pi_tick(void *opaque)
953 {
954 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
955 s->rtsr |= (1 << 13);
956 pxa2xx_rtc_piupdate(s);
957 s->last_rtcpicr = 0;
958 pxa2xx_rtc_alarm_update(s, s->rtsr);
959 pxa2xx_rtc_int_update(s);
960 }
961
962 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
963 unsigned size)
964 {
965 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
966
967 switch (addr) {
968 case RTTR:
969 return s->rttr;
970 case RTSR:
971 return s->rtsr;
972 case RTAR:
973 return s->rtar;
974 case RDAR1:
975 return s->rdar1;
976 case RDAR2:
977 return s->rdar2;
978 case RYAR1:
979 return s->ryar1;
980 case RYAR2:
981 return s->ryar2;
982 case SWAR1:
983 return s->swar1;
984 case SWAR2:
985 return s->swar2;
986 case PIAR:
987 return s->piar;
988 case RCNR:
989 return s->last_rcnr +
990 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
991 (1000 * ((s->rttr & 0xffff) + 1));
992 case RDCR:
993 return s->last_rdcr +
994 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
995 (1000 * ((s->rttr & 0xffff) + 1));
996 case RYCR:
997 return s->last_rycr;
998 case SWCR:
999 if (s->rtsr & (1 << 12))
1000 return s->last_swcr +
1001 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
1002 else
1003 return s->last_swcr;
1004 default:
1005 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1006 break;
1007 }
1008 return 0;
1009 }
1010
1011 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1012 uint64_t value64, unsigned size)
1013 {
1014 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1015 uint32_t value = value64;
1016
1017 switch (addr) {
1018 case RTTR:
1019 if (!(s->rttr & (1 << 31))) {
1020 pxa2xx_rtc_hzupdate(s);
1021 s->rttr = value;
1022 pxa2xx_rtc_alarm_update(s, s->rtsr);
1023 }
1024 break;
1025
1026 case RTSR:
1027 if ((s->rtsr ^ value) & (1 << 15))
1028 pxa2xx_rtc_piupdate(s);
1029
1030 if ((s->rtsr ^ value) & (1 << 12))
1031 pxa2xx_rtc_swupdate(s);
1032
1033 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1034 pxa2xx_rtc_alarm_update(s, value);
1035
1036 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1037 pxa2xx_rtc_int_update(s);
1038 break;
1039
1040 case RTAR:
1041 s->rtar = value;
1042 pxa2xx_rtc_alarm_update(s, s->rtsr);
1043 break;
1044
1045 case RDAR1:
1046 s->rdar1 = value;
1047 pxa2xx_rtc_alarm_update(s, s->rtsr);
1048 break;
1049
1050 case RDAR2:
1051 s->rdar2 = value;
1052 pxa2xx_rtc_alarm_update(s, s->rtsr);
1053 break;
1054
1055 case RYAR1:
1056 s->ryar1 = value;
1057 pxa2xx_rtc_alarm_update(s, s->rtsr);
1058 break;
1059
1060 case RYAR2:
1061 s->ryar2 = value;
1062 pxa2xx_rtc_alarm_update(s, s->rtsr);
1063 break;
1064
1065 case SWAR1:
1066 pxa2xx_rtc_swupdate(s);
1067 s->swar1 = value;
1068 s->last_swcr = 0;
1069 pxa2xx_rtc_alarm_update(s, s->rtsr);
1070 break;
1071
1072 case SWAR2:
1073 s->swar2 = value;
1074 pxa2xx_rtc_alarm_update(s, s->rtsr);
1075 break;
1076
1077 case PIAR:
1078 s->piar = value;
1079 pxa2xx_rtc_alarm_update(s, s->rtsr);
1080 break;
1081
1082 case RCNR:
1083 pxa2xx_rtc_hzupdate(s);
1084 s->last_rcnr = value;
1085 pxa2xx_rtc_alarm_update(s, s->rtsr);
1086 break;
1087
1088 case RDCR:
1089 pxa2xx_rtc_hzupdate(s);
1090 s->last_rdcr = value;
1091 pxa2xx_rtc_alarm_update(s, s->rtsr);
1092 break;
1093
1094 case RYCR:
1095 s->last_rycr = value;
1096 break;
1097
1098 case SWCR:
1099 pxa2xx_rtc_swupdate(s);
1100 s->last_swcr = value;
1101 pxa2xx_rtc_alarm_update(s, s->rtsr);
1102 break;
1103
1104 case RTCPICR:
1105 pxa2xx_rtc_piupdate(s);
1106 s->last_rtcpicr = value & 0xffff;
1107 pxa2xx_rtc_alarm_update(s, s->rtsr);
1108 break;
1109
1110 default:
1111 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1112 }
1113 }
1114
1115 static const MemoryRegionOps pxa2xx_rtc_ops = {
1116 .read = pxa2xx_rtc_read,
1117 .write = pxa2xx_rtc_write,
1118 .endianness = DEVICE_NATIVE_ENDIAN,
1119 };
1120
1121 static int pxa2xx_rtc_init(SysBusDevice *dev)
1122 {
1123 PXA2xxRTCState *s = PXA2XX_RTC(dev);
1124 struct tm tm;
1125 int wom;
1126
1127 s->rttr = 0x7fff;
1128 s->rtsr = 0;
1129
1130 qemu_get_timedate(&tm, 0);
1131 wom = ((tm.tm_mday - 1) / 7) + 1;
1132
1133 s->last_rcnr = (uint32_t) mktimegm(&tm);
1134 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1135 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1136 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1137 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1138 s->last_swcr = (tm.tm_hour << 19) |
1139 (tm.tm_min << 13) | (tm.tm_sec << 7);
1140 s->last_rtcpicr = 0;
1141 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1142
1143 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1144 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1145 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1146 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1147 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1148 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1149
1150 sysbus_init_irq(dev, &s->rtc_irq);
1151
1152 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
1153 "pxa2xx-rtc", 0x10000);
1154 sysbus_init_mmio(dev, &s->iomem);
1155
1156 return 0;
1157 }
1158
1159 static void pxa2xx_rtc_pre_save(void *opaque)
1160 {
1161 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1162
1163 pxa2xx_rtc_hzupdate(s);
1164 pxa2xx_rtc_piupdate(s);
1165 pxa2xx_rtc_swupdate(s);
1166 }
1167
1168 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1169 {
1170 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1171
1172 pxa2xx_rtc_alarm_update(s, s->rtsr);
1173
1174 return 0;
1175 }
1176
1177 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1178 .name = "pxa2xx_rtc",
1179 .version_id = 0,
1180 .minimum_version_id = 0,
1181 .minimum_version_id_old = 0,
1182 .pre_save = pxa2xx_rtc_pre_save,
1183 .post_load = pxa2xx_rtc_post_load,
1184 .fields = (VMStateField[]) {
1185 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1186 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1187 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1188 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1189 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1190 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1191 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1192 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1193 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1194 VMSTATE_UINT32(piar, PXA2xxRTCState),
1195 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1196 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1197 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1198 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1199 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1200 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1201 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1202 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1203 VMSTATE_END_OF_LIST(),
1204 },
1205 };
1206
1207 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1208 {
1209 DeviceClass *dc = DEVICE_CLASS(klass);
1210 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1211
1212 k->init = pxa2xx_rtc_init;
1213 dc->desc = "PXA2xx RTC Controller";
1214 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1215 }
1216
1217 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1218 .name = TYPE_PXA2XX_RTC,
1219 .parent = TYPE_SYS_BUS_DEVICE,
1220 .instance_size = sizeof(PXA2xxRTCState),
1221 .class_init = pxa2xx_rtc_sysbus_class_init,
1222 };
1223
1224 /* I2C Interface */
1225 typedef struct {
1226 I2CSlave i2c;
1227 PXA2xxI2CState *host;
1228 } PXA2xxI2CSlaveState;
1229
1230 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1231 #define PXA2XX_I2C(obj) \
1232 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1233
1234 struct PXA2xxI2CState {
1235 /*< private >*/
1236 SysBusDevice parent_obj;
1237 /*< public >*/
1238
1239 MemoryRegion iomem;
1240 PXA2xxI2CSlaveState *slave;
1241 i2c_bus *bus;
1242 qemu_irq irq;
1243 uint32_t offset;
1244 uint32_t region_size;
1245
1246 uint16_t control;
1247 uint16_t status;
1248 uint8_t ibmr;
1249 uint8_t data;
1250 };
1251
1252 #define IBMR 0x80 /* I2C Bus Monitor register */
1253 #define IDBR 0x88 /* I2C Data Buffer register */
1254 #define ICR 0x90 /* I2C Control register */
1255 #define ISR 0x98 /* I2C Status register */
1256 #define ISAR 0xa0 /* I2C Slave Address register */
1257
1258 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1259 {
1260 uint16_t level = 0;
1261 level |= s->status & s->control & (1 << 10); /* BED */
1262 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1263 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1264 level |= s->status & (1 << 9); /* SAD */
1265 qemu_set_irq(s->irq, !!level);
1266 }
1267
1268 /* These are only stubs now. */
1269 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1270 {
1271 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1272 PXA2xxI2CState *s = slave->host;
1273
1274 switch (event) {
1275 case I2C_START_SEND:
1276 s->status |= (1 << 9); /* set SAD */
1277 s->status &= ~(1 << 0); /* clear RWM */
1278 break;
1279 case I2C_START_RECV:
1280 s->status |= (1 << 9); /* set SAD */
1281 s->status |= 1 << 0; /* set RWM */
1282 break;
1283 case I2C_FINISH:
1284 s->status |= (1 << 4); /* set SSD */
1285 break;
1286 case I2C_NACK:
1287 s->status |= 1 << 1; /* set ACKNAK */
1288 break;
1289 }
1290 pxa2xx_i2c_update(s);
1291 }
1292
1293 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1294 {
1295 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1296 PXA2xxI2CState *s = slave->host;
1297 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1298 return 0;
1299
1300 if (s->status & (1 << 0)) { /* RWM */
1301 s->status |= 1 << 6; /* set ITE */
1302 }
1303 pxa2xx_i2c_update(s);
1304
1305 return s->data;
1306 }
1307
1308 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1309 {
1310 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1311 PXA2xxI2CState *s = slave->host;
1312 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1313 return 1;
1314
1315 if (!(s->status & (1 << 0))) { /* RWM */
1316 s->status |= 1 << 7; /* set IRF */
1317 s->data = data;
1318 }
1319 pxa2xx_i2c_update(s);
1320
1321 return 1;
1322 }
1323
1324 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1325 unsigned size)
1326 {
1327 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1328
1329 addr -= s->offset;
1330 switch (addr) {
1331 case ICR:
1332 return s->control;
1333 case ISR:
1334 return s->status | (i2c_bus_busy(s->bus) << 2);
1335 case ISAR:
1336 return s->slave->i2c.address;
1337 case IDBR:
1338 return s->data;
1339 case IBMR:
1340 if (s->status & (1 << 2))
1341 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1342 else
1343 s->ibmr = 0;
1344 return s->ibmr;
1345 default:
1346 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1347 break;
1348 }
1349 return 0;
1350 }
1351
1352 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1353 uint64_t value64, unsigned size)
1354 {
1355 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1356 uint32_t value = value64;
1357 int ack;
1358
1359 addr -= s->offset;
1360 switch (addr) {
1361 case ICR:
1362 s->control = value & 0xfff7;
1363 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1364 /* TODO: slave mode */
1365 if (value & (1 << 0)) { /* START condition */
1366 if (s->data & 1)
1367 s->status |= 1 << 0; /* set RWM */
1368 else
1369 s->status &= ~(1 << 0); /* clear RWM */
1370 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1371 } else {
1372 if (s->status & (1 << 0)) { /* RWM */
1373 s->data = i2c_recv(s->bus);
1374 if (value & (1 << 2)) /* ACKNAK */
1375 i2c_nack(s->bus);
1376 ack = 1;
1377 } else
1378 ack = !i2c_send(s->bus, s->data);
1379 }
1380
1381 if (value & (1 << 1)) /* STOP condition */
1382 i2c_end_transfer(s->bus);
1383
1384 if (ack) {
1385 if (value & (1 << 0)) /* START condition */
1386 s->status |= 1 << 6; /* set ITE */
1387 else
1388 if (s->status & (1 << 0)) /* RWM */
1389 s->status |= 1 << 7; /* set IRF */
1390 else
1391 s->status |= 1 << 6; /* set ITE */
1392 s->status &= ~(1 << 1); /* clear ACKNAK */
1393 } else {
1394 s->status |= 1 << 6; /* set ITE */
1395 s->status |= 1 << 10; /* set BED */
1396 s->status |= 1 << 1; /* set ACKNAK */
1397 }
1398 }
1399 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1400 if (value & (1 << 4)) /* MA */
1401 i2c_end_transfer(s->bus);
1402 pxa2xx_i2c_update(s);
1403 break;
1404
1405 case ISR:
1406 s->status &= ~(value & 0x07f0);
1407 pxa2xx_i2c_update(s);
1408 break;
1409
1410 case ISAR:
1411 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1412 break;
1413
1414 case IDBR:
1415 s->data = value & 0xff;
1416 break;
1417
1418 default:
1419 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1420 }
1421 }
1422
1423 static const MemoryRegionOps pxa2xx_i2c_ops = {
1424 .read = pxa2xx_i2c_read,
1425 .write = pxa2xx_i2c_write,
1426 .endianness = DEVICE_NATIVE_ENDIAN,
1427 };
1428
1429 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1430 .name = "pxa2xx_i2c_slave",
1431 .version_id = 1,
1432 .minimum_version_id = 1,
1433 .minimum_version_id_old = 1,
1434 .fields = (VMStateField []) {
1435 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1436 VMSTATE_END_OF_LIST()
1437 }
1438 };
1439
1440 static const VMStateDescription vmstate_pxa2xx_i2c = {
1441 .name = "pxa2xx_i2c",
1442 .version_id = 1,
1443 .minimum_version_id = 1,
1444 .minimum_version_id_old = 1,
1445 .fields = (VMStateField []) {
1446 VMSTATE_UINT16(control, PXA2xxI2CState),
1447 VMSTATE_UINT16(status, PXA2xxI2CState),
1448 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1449 VMSTATE_UINT8(data, PXA2xxI2CState),
1450 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1451 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1452 VMSTATE_END_OF_LIST()
1453 }
1454 };
1455
1456 static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1457 {
1458 /* Nothing to do. */
1459 return 0;
1460 }
1461
1462 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1463 {
1464 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1465
1466 k->init = pxa2xx_i2c_slave_init;
1467 k->event = pxa2xx_i2c_event;
1468 k->recv = pxa2xx_i2c_rx;
1469 k->send = pxa2xx_i2c_tx;
1470 }
1471
1472 static const TypeInfo pxa2xx_i2c_slave_info = {
1473 .name = "pxa2xx-i2c-slave",
1474 .parent = TYPE_I2C_SLAVE,
1475 .instance_size = sizeof(PXA2xxI2CSlaveState),
1476 .class_init = pxa2xx_i2c_slave_class_init,
1477 };
1478
1479 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1480 qemu_irq irq, uint32_t region_size)
1481 {
1482 DeviceState *dev;
1483 SysBusDevice *i2c_dev;
1484 PXA2xxI2CState *s;
1485 i2c_bus *i2cbus;
1486
1487 dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1488 qdev_prop_set_uint32(dev, "size", region_size + 1);
1489 qdev_prop_set_uint32(dev, "offset", base & region_size);
1490 qdev_init_nofail(dev);
1491
1492 i2c_dev = SYS_BUS_DEVICE(dev);
1493 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1494 sysbus_connect_irq(i2c_dev, 0, irq);
1495
1496 s = PXA2XX_I2C(i2c_dev);
1497 /* FIXME: Should the slave device really be on a separate bus? */
1498 i2cbus = i2c_init_bus(dev, "dummy");
1499 dev = i2c_create_slave(i2cbus, "pxa2xx-i2c-slave", 0);
1500 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE(dev));
1501 s->slave->host = s;
1502
1503 return s;
1504 }
1505
1506 static int pxa2xx_i2c_initfn(SysBusDevice *sbd)
1507 {
1508 DeviceState *dev = DEVICE(sbd);
1509 PXA2xxI2CState *s = PXA2XX_I2C(dev);
1510
1511 s->bus = i2c_init_bus(dev, "i2c");
1512
1513 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
1514 "pxa2xx-i2c", s->region_size);
1515 sysbus_init_mmio(sbd, &s->iomem);
1516 sysbus_init_irq(sbd, &s->irq);
1517
1518 return 0;
1519 }
1520
1521 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1522 {
1523 return s->bus;
1524 }
1525
1526 static Property pxa2xx_i2c_properties[] = {
1527 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1528 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1529 DEFINE_PROP_END_OF_LIST(),
1530 };
1531
1532 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1533 {
1534 DeviceClass *dc = DEVICE_CLASS(klass);
1535 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1536
1537 k->init = pxa2xx_i2c_initfn;
1538 dc->desc = "PXA2xx I2C Bus Controller";
1539 dc->vmsd = &vmstate_pxa2xx_i2c;
1540 dc->props = pxa2xx_i2c_properties;
1541 }
1542
1543 static const TypeInfo pxa2xx_i2c_info = {
1544 .name = TYPE_PXA2XX_I2C,
1545 .parent = TYPE_SYS_BUS_DEVICE,
1546 .instance_size = sizeof(PXA2xxI2CState),
1547 .class_init = pxa2xx_i2c_class_init,
1548 };
1549
1550 /* PXA Inter-IC Sound Controller */
1551 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1552 {
1553 i2s->rx_len = 0;
1554 i2s->tx_len = 0;
1555 i2s->fifo_len = 0;
1556 i2s->clk = 0x1a;
1557 i2s->control[0] = 0x00;
1558 i2s->control[1] = 0x00;
1559 i2s->status = 0x00;
1560 i2s->mask = 0x00;
1561 }
1562
1563 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1564 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1565 #define SACR_DREC(val) (val & (1 << 3))
1566 #define SACR_DPRL(val) (val & (1 << 4))
1567
1568 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1569 {
1570 int rfs, tfs;
1571 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1572 !SACR_DREC(i2s->control[1]);
1573 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1574 i2s->enable && !SACR_DPRL(i2s->control[1]);
1575
1576 qemu_set_irq(i2s->rx_dma, rfs);
1577 qemu_set_irq(i2s->tx_dma, tfs);
1578
1579 i2s->status &= 0xe0;
1580 if (i2s->fifo_len < 16 || !i2s->enable)
1581 i2s->status |= 1 << 0; /* TNF */
1582 if (i2s->rx_len)
1583 i2s->status |= 1 << 1; /* RNE */
1584 if (i2s->enable)
1585 i2s->status |= 1 << 2; /* BSY */
1586 if (tfs)
1587 i2s->status |= 1 << 3; /* TFS */
1588 if (rfs)
1589 i2s->status |= 1 << 4; /* RFS */
1590 if (!(i2s->tx_len && i2s->enable))
1591 i2s->status |= i2s->fifo_len << 8; /* TFL */
1592 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1593
1594 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1595 }
1596
1597 #define SACR0 0x00 /* Serial Audio Global Control register */
1598 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1599 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1600 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1601 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1602 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1603 #define SADR 0x80 /* Serial Audio Data register */
1604
1605 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1606 unsigned size)
1607 {
1608 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1609
1610 switch (addr) {
1611 case SACR0:
1612 return s->control[0];
1613 case SACR1:
1614 return s->control[1];
1615 case SASR0:
1616 return s->status;
1617 case SAIMR:
1618 return s->mask;
1619 case SAICR:
1620 return 0;
1621 case SADIV:
1622 return s->clk;
1623 case SADR:
1624 if (s->rx_len > 0) {
1625 s->rx_len --;
1626 pxa2xx_i2s_update(s);
1627 return s->codec_in(s->opaque);
1628 }
1629 return 0;
1630 default:
1631 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1632 break;
1633 }
1634 return 0;
1635 }
1636
1637 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1638 uint64_t value, unsigned size)
1639 {
1640 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1641 uint32_t *sample;
1642
1643 switch (addr) {
1644 case SACR0:
1645 if (value & (1 << 3)) /* RST */
1646 pxa2xx_i2s_reset(s);
1647 s->control[0] = value & 0xff3d;
1648 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1649 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1650 s->codec_out(s->opaque, *sample);
1651 s->status &= ~(1 << 7); /* I2SOFF */
1652 }
1653 if (value & (1 << 4)) /* EFWR */
1654 printf("%s: Attempt to use special function\n", __FUNCTION__);
1655 s->enable = (value & 9) == 1; /* ENB && !RST*/
1656 pxa2xx_i2s_update(s);
1657 break;
1658 case SACR1:
1659 s->control[1] = value & 0x0039;
1660 if (value & (1 << 5)) /* ENLBF */
1661 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1662 if (value & (1 << 4)) /* DPRL */
1663 s->fifo_len = 0;
1664 pxa2xx_i2s_update(s);
1665 break;
1666 case SAIMR:
1667 s->mask = value & 0x0078;
1668 pxa2xx_i2s_update(s);
1669 break;
1670 case SAICR:
1671 s->status &= ~(value & (3 << 5));
1672 pxa2xx_i2s_update(s);
1673 break;
1674 case SADIV:
1675 s->clk = value & 0x007f;
1676 break;
1677 case SADR:
1678 if (s->tx_len && s->enable) {
1679 s->tx_len --;
1680 pxa2xx_i2s_update(s);
1681 s->codec_out(s->opaque, value);
1682 } else if (s->fifo_len < 16) {
1683 s->fifo[s->fifo_len ++] = value;
1684 pxa2xx_i2s_update(s);
1685 }
1686 break;
1687 default:
1688 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1689 }
1690 }
1691
1692 static const MemoryRegionOps pxa2xx_i2s_ops = {
1693 .read = pxa2xx_i2s_read,
1694 .write = pxa2xx_i2s_write,
1695 .endianness = DEVICE_NATIVE_ENDIAN,
1696 };
1697
1698 static const VMStateDescription vmstate_pxa2xx_i2s = {
1699 .name = "pxa2xx_i2s",
1700 .version_id = 0,
1701 .minimum_version_id = 0,
1702 .minimum_version_id_old = 0,
1703 .fields = (VMStateField[]) {
1704 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1705 VMSTATE_UINT32(status, PXA2xxI2SState),
1706 VMSTATE_UINT32(mask, PXA2xxI2SState),
1707 VMSTATE_UINT32(clk, PXA2xxI2SState),
1708 VMSTATE_INT32(enable, PXA2xxI2SState),
1709 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1710 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1711 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1712 VMSTATE_END_OF_LIST()
1713 }
1714 };
1715
1716 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1717 {
1718 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1719 uint32_t *sample;
1720
1721 /* Signal FIFO errors */
1722 if (s->enable && s->tx_len)
1723 s->status |= 1 << 5; /* TUR */
1724 if (s->enable && s->rx_len)
1725 s->status |= 1 << 6; /* ROR */
1726
1727 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1728 * handle the cases where it makes a difference. */
1729 s->tx_len = tx - s->fifo_len;
1730 s->rx_len = rx;
1731 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1732 if (s->enable)
1733 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1734 s->codec_out(s->opaque, *sample);
1735 pxa2xx_i2s_update(s);
1736 }
1737
1738 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1739 hwaddr base,
1740 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1741 {
1742 PXA2xxI2SState *s = (PXA2xxI2SState *)
1743 g_malloc0(sizeof(PXA2xxI2SState));
1744
1745 s->irq = irq;
1746 s->rx_dma = rx_dma;
1747 s->tx_dma = tx_dma;
1748 s->data_req = pxa2xx_i2s_data_req;
1749
1750 pxa2xx_i2s_reset(s);
1751
1752 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1753 "pxa2xx-i2s", 0x100000);
1754 memory_region_add_subregion(sysmem, base, &s->iomem);
1755
1756 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1757
1758 return s;
1759 }
1760
1761 /* PXA Fast Infra-red Communications Port */
1762 struct PXA2xxFIrState {
1763 MemoryRegion iomem;
1764 qemu_irq irq;
1765 qemu_irq rx_dma;
1766 qemu_irq tx_dma;
1767 int enable;
1768 CharDriverState *chr;
1769
1770 uint8_t control[3];
1771 uint8_t status[2];
1772
1773 int rx_len;
1774 int rx_start;
1775 uint8_t rx_fifo[64];
1776 };
1777
1778 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1779 {
1780 s->control[0] = 0x00;
1781 s->control[1] = 0x00;
1782 s->control[2] = 0x00;
1783 s->status[0] = 0x00;
1784 s->status[1] = 0x00;
1785 s->enable = 0;
1786 }
1787
1788 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1789 {
1790 static const int tresh[4] = { 8, 16, 32, 0 };
1791 int intr = 0;
1792 if ((s->control[0] & (1 << 4)) && /* RXE */
1793 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1794 s->status[0] |= 1 << 4; /* RFS */
1795 else
1796 s->status[0] &= ~(1 << 4); /* RFS */
1797 if (s->control[0] & (1 << 3)) /* TXE */
1798 s->status[0] |= 1 << 3; /* TFS */
1799 else
1800 s->status[0] &= ~(1 << 3); /* TFS */
1801 if (s->rx_len)
1802 s->status[1] |= 1 << 2; /* RNE */
1803 else
1804 s->status[1] &= ~(1 << 2); /* RNE */
1805 if (s->control[0] & (1 << 4)) /* RXE */
1806 s->status[1] |= 1 << 0; /* RSY */
1807 else
1808 s->status[1] &= ~(1 << 0); /* RSY */
1809
1810 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1811 (s->status[0] & (1 << 4)); /* RFS */
1812 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1813 (s->status[0] & (1 << 3)); /* TFS */
1814 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1815 (s->status[0] & (1 << 6)); /* EOC */
1816 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1817 (s->status[0] & (1 << 1)); /* TUR */
1818 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1819
1820 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1821 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1822
1823 qemu_set_irq(s->irq, intr && s->enable);
1824 }
1825
1826 #define ICCR0 0x00 /* FICP Control register 0 */
1827 #define ICCR1 0x04 /* FICP Control register 1 */
1828 #define ICCR2 0x08 /* FICP Control register 2 */
1829 #define ICDR 0x0c /* FICP Data register */
1830 #define ICSR0 0x14 /* FICP Status register 0 */
1831 #define ICSR1 0x18 /* FICP Status register 1 */
1832 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1833
1834 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1835 unsigned size)
1836 {
1837 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1838 uint8_t ret;
1839
1840 switch (addr) {
1841 case ICCR0:
1842 return s->control[0];
1843 case ICCR1:
1844 return s->control[1];
1845 case ICCR2:
1846 return s->control[2];
1847 case ICDR:
1848 s->status[0] &= ~0x01;
1849 s->status[1] &= ~0x72;
1850 if (s->rx_len) {
1851 s->rx_len --;
1852 ret = s->rx_fifo[s->rx_start ++];
1853 s->rx_start &= 63;
1854 pxa2xx_fir_update(s);
1855 return ret;
1856 }
1857 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1858 break;
1859 case ICSR0:
1860 return s->status[0];
1861 case ICSR1:
1862 return s->status[1] | (1 << 3); /* TNF */
1863 case ICFOR:
1864 return s->rx_len;
1865 default:
1866 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1867 break;
1868 }
1869 return 0;
1870 }
1871
1872 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1873 uint64_t value64, unsigned size)
1874 {
1875 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1876 uint32_t value = value64;
1877 uint8_t ch;
1878
1879 switch (addr) {
1880 case ICCR0:
1881 s->control[0] = value;
1882 if (!(value & (1 << 4))) /* RXE */
1883 s->rx_len = s->rx_start = 0;
1884 if (!(value & (1 << 3))) { /* TXE */
1885 /* Nop */
1886 }
1887 s->enable = value & 1; /* ITR */
1888 if (!s->enable)
1889 s->status[0] = 0;
1890 pxa2xx_fir_update(s);
1891 break;
1892 case ICCR1:
1893 s->control[1] = value;
1894 break;
1895 case ICCR2:
1896 s->control[2] = value & 0x3f;
1897 pxa2xx_fir_update(s);
1898 break;
1899 case ICDR:
1900 if (s->control[2] & (1 << 2)) /* TXP */
1901 ch = value;
1902 else
1903 ch = ~value;
1904 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1905 qemu_chr_fe_write(s->chr, &ch, 1);
1906 break;
1907 case ICSR0:
1908 s->status[0] &= ~(value & 0x66);
1909 pxa2xx_fir_update(s);
1910 break;
1911 case ICFOR:
1912 break;
1913 default:
1914 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1915 }
1916 }
1917
1918 static const MemoryRegionOps pxa2xx_fir_ops = {
1919 .read = pxa2xx_fir_read,
1920 .write = pxa2xx_fir_write,
1921 .endianness = DEVICE_NATIVE_ENDIAN,
1922 };
1923
1924 static int pxa2xx_fir_is_empty(void *opaque)
1925 {
1926 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1927 return (s->rx_len < 64);
1928 }
1929
1930 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1931 {
1932 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1933 if (!(s->control[0] & (1 << 4))) /* RXE */
1934 return;
1935
1936 while (size --) {
1937 s->status[1] |= 1 << 4; /* EOF */
1938 if (s->rx_len >= 64) {
1939 s->status[1] |= 1 << 6; /* ROR */
1940 break;
1941 }
1942
1943 if (s->control[2] & (1 << 3)) /* RXP */
1944 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1945 else
1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1947 }
1948
1949 pxa2xx_fir_update(s);
1950 }
1951
1952 static void pxa2xx_fir_event(void *opaque, int event)
1953 {
1954 }
1955
1956 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1957 {
1958 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1959 int i;
1960
1961 qemu_put_be32(f, s->enable);
1962
1963 qemu_put_8s(f, &s->control[0]);
1964 qemu_put_8s(f, &s->control[1]);
1965 qemu_put_8s(f, &s->control[2]);
1966 qemu_put_8s(f, &s->status[0]);
1967 qemu_put_8s(f, &s->status[1]);
1968
1969 qemu_put_byte(f, s->rx_len);
1970 for (i = 0; i < s->rx_len; i ++)
1971 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1972 }
1973
1974 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1975 {
1976 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1977 int i;
1978
1979 s->enable = qemu_get_be32(f);
1980
1981 qemu_get_8s(f, &s->control[0]);
1982 qemu_get_8s(f, &s->control[1]);
1983 qemu_get_8s(f, &s->control[2]);
1984 qemu_get_8s(f, &s->status[0]);
1985 qemu_get_8s(f, &s->status[1]);
1986
1987 s->rx_len = qemu_get_byte(f);
1988 s->rx_start = 0;
1989 for (i = 0; i < s->rx_len; i ++)
1990 s->rx_fifo[i] = qemu_get_byte(f);
1991
1992 return 0;
1993 }
1994
1995 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
1996 hwaddr base,
1997 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
1998 CharDriverState *chr)
1999 {
2000 PXA2xxFIrState *s = (PXA2xxFIrState *)
2001 g_malloc0(sizeof(PXA2xxFIrState));
2002
2003 s->irq = irq;
2004 s->rx_dma = rx_dma;
2005 s->tx_dma = tx_dma;
2006 s->chr = chr;
2007
2008 pxa2xx_fir_reset(s);
2009
2010 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
2011 memory_region_add_subregion(sysmem, base, &s->iomem);
2012
2013 if (chr) {
2014 qemu_chr_fe_claim_no_fail(chr);
2015 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2016 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2017 }
2018
2019 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2020 pxa2xx_fir_load, s);
2021
2022 return s;
2023 }
2024
2025 static void pxa2xx_reset(void *opaque, int line, int level)
2026 {
2027 PXA2xxState *s = (PXA2xxState *) opaque;
2028
2029 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2030 cpu_reset(CPU(s->cpu));
2031 /* TODO: reset peripherals */
2032 }
2033 }
2034
2035 /* Initialise a PXA270 integrated chip (ARM based core). */
2036 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2037 unsigned int sdram_size, const char *revision)
2038 {
2039 PXA2xxState *s;
2040 int i;
2041 DriveInfo *dinfo;
2042 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2043
2044 if (revision && strncmp(revision, "pxa27", 5)) {
2045 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2046 exit(1);
2047 }
2048 if (!revision)
2049 revision = "pxa270";
2050
2051 s->cpu = cpu_arm_init(revision);
2052 if (s->cpu == NULL) {
2053 fprintf(stderr, "Unable to find CPU definition\n");
2054 exit(1);
2055 }
2056 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2057
2058 /* SDRAM & Internal Memory Storage */
2059 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
2060 vmstate_register_ram_global(&s->sdram);
2061 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2062 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
2063 vmstate_register_ram_global(&s->internal);
2064 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2065 &s->internal);
2066
2067 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2068
2069 s->dma = pxa27x_dma_init(0x40000000,
2070 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2071
2072 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2073 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2074 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2075 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2076 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2077 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2078 NULL);
2079
2080 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2081
2082 dinfo = drive_get(IF_SD, 0, 0);
2083 if (!dinfo) {
2084 fprintf(stderr, "qemu: missing SecureDigital device\n");
2085 exit(1);
2086 }
2087 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2088 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2089 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2090 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2091
2092 for (i = 0; pxa270_serial[i].io_base; i++) {
2093 if (serial_hds[i]) {
2094 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2095 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2096 14857000 / 16, serial_hds[i],
2097 DEVICE_NATIVE_ENDIAN);
2098 } else {
2099 break;
2100 }
2101 }
2102 if (serial_hds[i])
2103 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2104 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2105 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2106 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2107 serial_hds[i]);
2108
2109 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2110 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2111
2112 s->cm_base = 0x41300000;
2113 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2114 s->clkcfg = 0x00000009; /* Turbo mode active */
2115 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2116 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2117 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2118
2119 pxa2xx_setup_cp14(s);
2120
2121 s->mm_base = 0x48000000;
2122 s->mm_regs[MDMRS >> 2] = 0x00020002;
2123 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2124 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2125 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2126 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2127 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2128
2129 s->pm_base = 0x40f00000;
2130 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2131 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2132 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2133
2134 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2135 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2136 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2137 DeviceState *dev;
2138 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2139 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2140 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2141 }
2142
2143 if (usb_enabled(false)) {
2144 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2145 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2146 }
2147
2148 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2149 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2150
2151 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2152 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2153
2154 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2155 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2156 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2157 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2158
2159 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2160 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2161 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2162 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2163
2164 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2165 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2166
2167 /* GPIO1 resets the processor */
2168 /* The handler can be overridden by board-specific code */
2169 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2170 return s;
2171 }
2172
2173 /* Initialise a PXA255 integrated chip (ARM based core). */
2174 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2175 {
2176 PXA2xxState *s;
2177 int i;
2178 DriveInfo *dinfo;
2179
2180 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2181
2182 s->cpu = cpu_arm_init("pxa255");
2183 if (s->cpu == NULL) {
2184 fprintf(stderr, "Unable to find CPU definition\n");
2185 exit(1);
2186 }
2187 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2188
2189 /* SDRAM & Internal Memory Storage */
2190 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
2191 vmstate_register_ram_global(&s->sdram);
2192 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2193 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2194 PXA2XX_INTERNAL_SIZE);
2195 vmstate_register_ram_global(&s->internal);
2196 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2197 &s->internal);
2198
2199 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2200
2201 s->dma = pxa255_dma_init(0x40000000,
2202 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2203
2204 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2205 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2206 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2207 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2209 NULL);
2210
2211 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2212
2213 dinfo = drive_get(IF_SD, 0, 0);
2214 if (!dinfo) {
2215 fprintf(stderr, "qemu: missing SecureDigital device\n");
2216 exit(1);
2217 }
2218 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2219 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2220 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2221 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2222
2223 for (i = 0; pxa255_serial[i].io_base; i++) {
2224 if (serial_hds[i]) {
2225 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2226 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2227 14745600 / 16, serial_hds[i],
2228 DEVICE_NATIVE_ENDIAN);
2229 } else {
2230 break;
2231 }
2232 }
2233 if (serial_hds[i])
2234 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2235 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2236 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2237 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2238 serial_hds[i]);
2239
2240 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2241 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2242
2243 s->cm_base = 0x41300000;
2244 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2245 s->clkcfg = 0x00000009; /* Turbo mode active */
2246 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2247 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2248 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2249
2250 pxa2xx_setup_cp14(s);
2251
2252 s->mm_base = 0x48000000;
2253 s->mm_regs[MDMRS >> 2] = 0x00020002;
2254 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2255 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2256 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2257 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2258 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2259
2260 s->pm_base = 0x40f00000;
2261 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2262 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2263 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2264
2265 for (i = 0; pxa255_ssp[i].io_base; i ++);
2266 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2267 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2268 DeviceState *dev;
2269 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2270 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2271 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2272 }
2273
2274 if (usb_enabled(false)) {
2275 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2276 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2277 }
2278
2279 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2280 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2281
2282 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2283 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2284
2285 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2286 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2287 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2288 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2289
2290 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2291 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2292 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2293 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2294
2295 /* GPIO1 resets the processor */
2296 /* The handler can be overridden by board-specific code */
2297 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2298 return s;
2299 }
2300
2301 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2302 {
2303 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2304
2305 sdc->init = pxa2xx_ssp_init;
2306 }
2307
2308 static const TypeInfo pxa2xx_ssp_info = {
2309 .name = TYPE_PXA2XX_SSP,
2310 .parent = TYPE_SYS_BUS_DEVICE,
2311 .instance_size = sizeof(PXA2xxSSPState),
2312 .class_init = pxa2xx_ssp_class_init,
2313 };
2314
2315 static void pxa2xx_register_types(void)
2316 {
2317 type_register_static(&pxa2xx_i2c_slave_info);
2318 type_register_static(&pxa2xx_ssp_info);
2319 type_register_static(&pxa2xx_i2c_info);
2320 type_register_static(&pxa2xx_rtc_sysbus_info);
2321 }
2322
2323 type_init(pxa2xx_register_types)
QEmu