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arm-semi.c: Use correct check for failure of do_brk()
[qemu.git] / hw / sun4m.c
blobdf3aa321caccd26856ab0aa72e959546cb1ea758
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint32_t ecc_version;
101 uint8_t nvram_machine_id;
102 uint16_t machine_id;
103 uint32_t iommu_version;
104 uint64_t max_mem;
105 const char * const default_cpu_model;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint8_t nvram_machine_id;
119 uint16_t machine_id;
120 uint32_t iounit_version;
121 uint64_t max_mem;
122 const char * const default_cpu_model;
123 };
124
125 struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint8_t nvram_machine_id;
132 uint16_t machine_id;
133 uint32_t iommu_version;
134 uint64_t max_mem;
135 const char * const default_cpu_model;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void pic_info(Monitor *mon)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void irq_info(Monitor *mon)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(CPUState *env)
257 {
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261 }
262
263 static void cpu_set_irq(void *opaque, int irq, int level)
264 {
265 CPUState *env = opaque;
266
267 if (level) {
268 trace_sun4m_cpu_set_irq_raise(irq);
269 env->pil_in |= 1 << irq;
270 cpu_kick_irq(env);
271 } else {
272 trace_sun4m_cpu_set_irq_lower(irq);
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
275 }
276 }
277
278 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279 {
280 }
281
282 static void main_cpu_reset(void *opaque)
283 {
284 CPUState *env = opaque;
285
286 cpu_reset(env);
287 env->halted = 0;
288 }
289
290 static void secondary_cpu_reset(void *opaque)
291 {
292 CPUState *env = opaque;
293
294 cpu_reset(env);
295 env->halted = 1;
296 }
297
298 static void cpu_halt_signal(void *opaque, int irq, int level)
299 {
300 if (level && cpu_single_env)
301 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302 }
303
304 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305 {
306 return addr - 0xf0000000ULL;
307 }
308
309 static unsigned long sun4m_load_kernel(const char *kernel_filename,
310 const char *initrd_filename,
311 ram_addr_t RAM_size)
312 {
313 int linux_boot;
314 unsigned int i;
315 long initrd_size, kernel_size;
316 uint8_t *ptr;
317
318 linux_boot = (kernel_filename != NULL);
319
320 kernel_size = 0;
321 if (linux_boot) {
322 int bswap_needed;
323
324 #ifdef BSWAP_NEEDED
325 bswap_needed = 1;
326 #else
327 bswap_needed = 0;
328 #endif
329 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
331 if (kernel_size < 0)
332 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
333 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334 TARGET_PAGE_SIZE);
335 if (kernel_size < 0)
336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
359 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360 if (ldl_p(ptr) == 0x48647253) { // HdrS
361 stl_p(ptr + 16, INITRD_LOAD_ADDR);
362 stl_p(ptr + 20, initrd_size);
363 break;
364 }
365 }
366 }
367 }
368 return kernel_size;
369 }
370
371 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
372 {
373 DeviceState *dev;
374 SysBusDevice *s;
375
376 dev = qdev_create(NULL, "iommu");
377 qdev_prop_set_uint32(dev, "version", version);
378 qdev_init_nofail(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_connect_irq(s, 0, irq);
381 sysbus_mmio_map(s, 0, addr);
382
383 return s;
384 }
385
386 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
387 void *iommu, qemu_irq *dev_irq, int is_ledma)
388 {
389 DeviceState *dev;
390 SysBusDevice *s;
391
392 dev = qdev_create(NULL, "sparc32_dma");
393 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
394 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
395 qdev_init_nofail(dev);
396 s = sysbus_from_qdev(dev);
397 sysbus_connect_irq(s, 0, parent_irq);
398 *dev_irq = qdev_get_gpio_in(dev, 0);
399 sysbus_mmio_map(s, 0, daddr);
400
401 return s;
402 }
403
404 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
405 void *dma_opaque, qemu_irq irq)
406 {
407 DeviceState *dev;
408 SysBusDevice *s;
409 qemu_irq reset;
410
411 qemu_check_nic_model(&nd_table[0], "lance");
412
413 dev = qdev_create(NULL, "lance");
414 qdev_set_nic_properties(dev, nd);
415 qdev_prop_set_ptr(dev, "dma", dma_opaque);
416 qdev_init_nofail(dev);
417 s = sysbus_from_qdev(dev);
418 sysbus_mmio_map(s, 0, leaddr);
419 sysbus_connect_irq(s, 0, irq);
420 reset = qdev_get_gpio_in(dev, 0);
421 qdev_connect_gpio_out(dma_opaque, 0, reset);
422 }
423
424 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425 target_phys_addr_t addrg,
426 qemu_irq **parent_irq)
427 {
428 DeviceState *dev;
429 SysBusDevice *s;
430 unsigned int i, j;
431
432 dev = qdev_create(NULL, "slavio_intctl");
433 qdev_init_nofail(dev);
434
435 s = sysbus_from_qdev(dev);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440 }
441 }
442 sysbus_mmio_map(s, 0, addrg);
443 for (i = 0; i < MAX_CPUS; i++) {
444 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445 }
446
447 return dev;
448 }
449
450 #define SYS_TIMER_OFFSET 0x10000ULL
451 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452
453 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
454 qemu_irq *cpu_irqs, unsigned int num_cpus)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458 unsigned int i;
459
460 dev = qdev_create(NULL, "slavio_timer");
461 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
462 qdev_init_nofail(dev);
463 s = sysbus_from_qdev(dev);
464 sysbus_connect_irq(s, 0, master_irq);
465 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466
467 for (i = 0; i < MAX_CPUS; i++) {
468 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
469 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470 }
471 }
472
473 #define MISC_LEDS 0x01600000
474 #define MISC_CFG 0x01800000
475 #define MISC_DIAG 0x01a00000
476 #define MISC_MDM 0x01b00000
477 #define MISC_SYS 0x01f00000
478
479 static void slavio_misc_init(target_phys_addr_t base,
480 target_phys_addr_t aux1_base,
481 target_phys_addr_t aux2_base, qemu_irq irq,
482 qemu_irq fdc_tc)
483 {
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "slavio_misc");
488 qdev_init_nofail(dev);
489 s = sysbus_from_qdev(dev);
490 if (base) {
491 /* 8 bit registers */
492 /* Slavio control */
493 sysbus_mmio_map(s, 0, base + MISC_CFG);
494 /* Diagnostics */
495 sysbus_mmio_map(s, 1, base + MISC_DIAG);
496 /* Modem control */
497 sysbus_mmio_map(s, 2, base + MISC_MDM);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s, 3, base + MISC_LEDS);
501 /* 32 bit registers */
502 /* System control */
503 sysbus_mmio_map(s, 4, base + MISC_SYS);
504 }
505 if (aux1_base) {
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s, 5, aux1_base);
508 }
509 if (aux2_base) {
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s, 6, aux2_base);
512 }
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_connect_irq(s, 1, fdc_tc);
515 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
516 }
517
518 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
519 {
520 DeviceState *dev;
521 SysBusDevice *s;
522
523 dev = qdev_create(NULL, "eccmemctl");
524 qdev_prop_set_uint32(dev, "version", version);
525 qdev_init_nofail(dev);
526 s = sysbus_from_qdev(dev);
527 sysbus_connect_irq(s, 0, irq);
528 sysbus_mmio_map(s, 0, base);
529 if (version == 0) { // SS-600MP only
530 sysbus_mmio_map(s, 1, base + 0x1000);
531 }
532 }
533
534 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
535 {
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "apc");
540 qdev_init_nofail(dev);
541 s = sysbus_from_qdev(dev);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s, 0, power_base);
544 sysbus_connect_irq(s, 0, cpu_halt);
545 }
546
547 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
548 int height, int depth)
549 {
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "SUNW,tcx");
554 qdev_prop_set_taddr(dev, "addr", addr);
555 qdev_prop_set_uint32(dev, "vram_size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
559 qdev_init_nofail(dev);
560 s = sysbus_from_qdev(dev);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563 /* DAC */
564 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565 /* TEC (dummy) */
566 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569 if (depth == 24) {
570 /* 24-bit plane */
571 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572 /* Control plane */
573 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574 } else {
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577 }
578 }
579
580 /* NCR89C100/MACIO Internal ID register */
581 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582
583 static void idreg_init(target_phys_addr_t addr)
584 {
585 DeviceState *dev;
586 SysBusDevice *s;
587
588 dev = qdev_create(NULL, "macio_idreg");
589 qdev_init_nofail(dev);
590 s = sysbus_from_qdev(dev);
591
592 sysbus_mmio_map(s, 0, addr);
593 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594 }
595
596 static int idreg_init1(SysBusDevice *dev)
597 {
598 ram_addr_t idreg_offset;
599
600 idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data));
601 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
602 return 0;
603 }
604
605 static SysBusDeviceInfo idreg_info = {
606 .init = idreg_init1,
607 .qdev.name = "macio_idreg",
608 .qdev.size = sizeof(SysBusDevice),
609 };
610
611 static void idreg_register_devices(void)
612 {
613 sysbus_register_withprop(&idreg_info);
614 }
615
616 device_init(idreg_register_devices);
617
618 /* SS-5 TCX AFX register */
619 static void afx_init(target_phys_addr_t addr)
620 {
621 DeviceState *dev;
622 SysBusDevice *s;
623
624 dev = qdev_create(NULL, "tcx_afx");
625 qdev_init_nofail(dev);
626 s = sysbus_from_qdev(dev);
627
628 sysbus_mmio_map(s, 0, addr);
629 }
630
631 static int afx_init1(SysBusDevice *dev)
632 {
633 ram_addr_t afx_offset;
634
635 afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4);
636 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
637 return 0;
638 }
639
640 static SysBusDeviceInfo afx_info = {
641 .init = afx_init1,
642 .qdev.name = "tcx_afx",
643 .qdev.size = sizeof(SysBusDevice),
644 };
645
646 static void afx_register_devices(void)
647 {
648 sysbus_register_withprop(&afx_info);
649 }
650
651 device_init(afx_register_devices);
652
653 /* Boot PROM (OpenBIOS) */
654 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
655 {
656 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
657 return addr + *base_addr - PROM_VADDR;
658 }
659
660 static void prom_init(target_phys_addr_t addr, const char *bios_name)
661 {
662 DeviceState *dev;
663 SysBusDevice *s;
664 char *filename;
665 int ret;
666
667 dev = qdev_create(NULL, "openprom");
668 qdev_init_nofail(dev);
669 s = sysbus_from_qdev(dev);
670
671 sysbus_mmio_map(s, 0, addr);
672
673 /* load boot prom */
674 if (bios_name == NULL) {
675 bios_name = PROM_FILENAME;
676 }
677 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
678 if (filename) {
679 ret = load_elf(filename, translate_prom_address, &addr, NULL,
680 NULL, NULL, 1, ELF_MACHINE, 0);
681 if (ret < 0 || ret > PROM_SIZE_MAX) {
682 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
683 }
684 qemu_free(filename);
685 } else {
686 ret = -1;
687 }
688 if (ret < 0 || ret > PROM_SIZE_MAX) {
689 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
690 exit(1);
691 }
692 }
693
694 static int prom_init1(SysBusDevice *dev)
695 {
696 ram_addr_t prom_offset;
697
698 prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX);
699 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
700 return 0;
701 }
702
703 static SysBusDeviceInfo prom_info = {
704 .init = prom_init1,
705 .qdev.name = "openprom",
706 .qdev.size = sizeof(SysBusDevice),
707 .qdev.props = (Property[]) {
708 {/* end of property list */}
709 }
710 };
711
712 static void prom_register_devices(void)
713 {
714 sysbus_register_withprop(&prom_info);
715 }
716
717 device_init(prom_register_devices);
718
719 typedef struct RamDevice
720 {
721 SysBusDevice busdev;
722 uint64_t size;
723 } RamDevice;
724
725 /* System RAM */
726 static int ram_init1(SysBusDevice *dev)
727 {
728 ram_addr_t RAM_size, ram_offset;
729 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
730
731 RAM_size = d->size;
732
733 ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size);
734 sysbus_init_mmio(dev, RAM_size, ram_offset);
735 return 0;
736 }
737
738 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
739 uint64_t max_mem)
740 {
741 DeviceState *dev;
742 SysBusDevice *s;
743 RamDevice *d;
744
745 /* allocate RAM */
746 if ((uint64_t)RAM_size > max_mem) {
747 fprintf(stderr,
748 "qemu: Too much memory for this machine: %d, maximum %d\n",
749 (unsigned int)(RAM_size / (1024 * 1024)),
750 (unsigned int)(max_mem / (1024 * 1024)));
751 exit(1);
752 }
753 dev = qdev_create(NULL, "memory");
754 s = sysbus_from_qdev(dev);
755
756 d = FROM_SYSBUS(RamDevice, s);
757 d->size = RAM_size;
758 qdev_init_nofail(dev);
759
760 sysbus_mmio_map(s, 0, addr);
761 }
762
763 static SysBusDeviceInfo ram_info = {
764 .init = ram_init1,
765 .qdev.name = "memory",
766 .qdev.size = sizeof(RamDevice),
767 .qdev.props = (Property[]) {
768 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
769 DEFINE_PROP_END_OF_LIST(),
770 }
771 };
772
773 static void ram_register_devices(void)
774 {
775 sysbus_register_withprop(&ram_info);
776 }
777
778 device_init(ram_register_devices);
779
780 static void cpu_devinit(const char *cpu_model, unsigned int id,
781 uint64_t prom_addr, qemu_irq **cpu_irqs)
782 {
783 CPUState *env;
784
785 env = cpu_init(cpu_model);
786 if (!env) {
787 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
788 exit(1);
789 }
790
791 cpu_sparc_set_id(env, id);
792 if (id == 0) {
793 qemu_register_reset(main_cpu_reset, env);
794 } else {
795 qemu_register_reset(secondary_cpu_reset, env);
796 env->halted = 1;
797 }
798 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
799 env->prom_addr = prom_addr;
800 }
801
802 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
803 const char *boot_device,
804 const char *kernel_filename,
805 const char *kernel_cmdline,
806 const char *initrd_filename, const char *cpu_model)
807 {
808 unsigned int i;
809 void *iommu, *espdma, *ledma, *nvram;
810 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
811 espdma_irq, ledma_irq;
812 qemu_irq esp_reset, dma_enable;
813 qemu_irq fdc_tc;
814 qemu_irq *cpu_halt;
815 unsigned long kernel_size;
816 DriveInfo *fd[MAX_FD];
817 void *fw_cfg;
818 unsigned int num_vsimms;
819
820 /* init CPUs */
821 if (!cpu_model)
822 cpu_model = hwdef->default_cpu_model;
823
824 for(i = 0; i < smp_cpus; i++) {
825 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
826 }
827
828 for (i = smp_cpus; i < MAX_CPUS; i++)
829 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
830
831
832 /* set up devices */
833 ram_init(0, RAM_size, hwdef->max_mem);
834 /* models without ECC don't trap when missing ram is accessed */
835 if (!hwdef->ecc_base) {
836 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
837 }
838
839 prom_init(hwdef->slavio_base, bios_name);
840
841 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
842 hwdef->intctl_base + 0x10000ULL,
843 cpu_irqs);
844
845 for (i = 0; i < 32; i++) {
846 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
847 }
848 for (i = 0; i < MAX_CPUS; i++) {
849 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
850 }
851
852 if (hwdef->idreg_base) {
853 idreg_init(hwdef->idreg_base);
854 }
855
856 if (hwdef->afx_base) {
857 afx_init(hwdef->afx_base);
858 }
859
860 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
861 slavio_irq[30]);
862
863 if (hwdef->iommu_pad_base) {
864 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
865 Software shouldn't use aliased addresses, neither should it crash
866 when does. Using empty_slot instead of aliasing can help with
867 debugging such accesses */
868 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
869 }
870
871 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
872 iommu, &espdma_irq, 0);
873
874 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
875 slavio_irq[16], iommu, &ledma_irq, 1);
876
877 if (graphic_depth != 8 && graphic_depth != 24) {
878 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
879 exit (1);
880 }
881 num_vsimms = 0;
882 if (num_vsimms == 0) {
883 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
884 graphic_depth);
885 }
886
887 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
888 /* vsimm registers probed by OBP */
889 if (hwdef->vsimm[i].reg_base) {
890 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
891 }
892 }
893
894 if (hwdef->sx_base) {
895 empty_slot_init(hwdef->sx_base, 0x2000);
896 }
897
898 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
899
900 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
901
902 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
903
904 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
905 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
906 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
907 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
908 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
909 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
910
911 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
912 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
913 slavio_irq[30], fdc_tc);
914
915 if (hwdef->apc_base) {
916 apc_init(hwdef->apc_base, cpu_halt[0]);
917 }
918
919 if (hwdef->fd_base) {
920 /* there is zero or one floppy drive */
921 memset(fd, 0, sizeof(fd));
922 fd[0] = drive_get(IF_FLOPPY, 0, 0);
923 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
924 &fdc_tc);
925 }
926
927 if (drive_get_max_bus(IF_SCSI) > 0) {
928 fprintf(stderr, "qemu: too many SCSI bus\n");
929 exit(1);
930 }
931
932 esp_init(hwdef->esp_base, 2,
933 espdma_memory_read, espdma_memory_write,
934 espdma, espdma_irq, &esp_reset, &dma_enable);
935
936 qdev_connect_gpio_out(espdma, 0, esp_reset);
937 qdev_connect_gpio_out(espdma, 1, dma_enable);
938
939 if (hwdef->cs_base) {
940 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
941 slavio_irq[5]);
942 }
943
944 if (hwdef->dbri_base) {
945 /* ISDN chip with attached CS4215 audio codec */
946 /* prom space */
947 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
948 /* reg space */
949 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
950 }
951
952 if (hwdef->bpp_base) {
953 /* parallel port */
954 empty_slot_init(hwdef->bpp_base, 0x20);
955 }
956
957 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
958 RAM_size);
959
960 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
961 boot_device, RAM_size, kernel_size, graphic_width,
962 graphic_height, graphic_depth, hwdef->nvram_machine_id,
963 "Sun4m");
964
965 if (hwdef->ecc_base)
966 ecc_init(hwdef->ecc_base, slavio_irq[28],
967 hwdef->ecc_version);
968
969 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
970 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
971 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
972 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
973 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
974 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
975 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
976 if (kernel_cmdline) {
977 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
978 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
979 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
980 (uint8_t*)strdup(kernel_cmdline),
981 strlen(kernel_cmdline) + 1);
982 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
983 strlen(kernel_cmdline) + 1);
984 } else {
985 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
986 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
987 }
988 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
989 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
990 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
991 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
992 }
993
994 enum {
995 ss2_id = 0,
996 ss5_id = 32,
997 vger_id,
998 lx_id,
999 ss4_id,
1000 scls_id,
1001 sbook_id,
1002 ss10_id = 64,
1003 ss20_id,
1004 ss600mp_id,
1005 ss1000_id = 96,
1006 ss2000_id,
1007 };
1008
1009 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1010 /* SS-5 */
1011 {
1012 .iommu_base = 0x10000000,
1013 .iommu_pad_base = 0x10004000,
1014 .iommu_pad_len = 0x0fffb000,
1015 .tcx_base = 0x50000000,
1016 .cs_base = 0x6c000000,
1017 .slavio_base = 0x70000000,
1018 .ms_kb_base = 0x71000000,
1019 .serial_base = 0x71100000,
1020 .nvram_base = 0x71200000,
1021 .fd_base = 0x71400000,
1022 .counter_base = 0x71d00000,
1023 .intctl_base = 0x71e00000,
1024 .idreg_base = 0x78000000,
1025 .dma_base = 0x78400000,
1026 .esp_base = 0x78800000,
1027 .le_base = 0x78c00000,
1028 .apc_base = 0x6a000000,
1029 .afx_base = 0x6e000000,
1030 .aux1_base = 0x71900000,
1031 .aux2_base = 0x71910000,
1032 .nvram_machine_id = 0x80,
1033 .machine_id = ss5_id,
1034 .iommu_version = 0x05000000,
1035 .max_mem = 0x10000000,
1036 .default_cpu_model = "Fujitsu MB86904",
1037 },
1038 /* SS-10 */
1039 {
1040 .iommu_base = 0xfe0000000ULL,
1041 .tcx_base = 0xe20000000ULL,
1042 .slavio_base = 0xff0000000ULL,
1043 .ms_kb_base = 0xff1000000ULL,
1044 .serial_base = 0xff1100000ULL,
1045 .nvram_base = 0xff1200000ULL,
1046 .fd_base = 0xff1700000ULL,
1047 .counter_base = 0xff1300000ULL,
1048 .intctl_base = 0xff1400000ULL,
1049 .idreg_base = 0xef0000000ULL,
1050 .dma_base = 0xef0400000ULL,
1051 .esp_base = 0xef0800000ULL,
1052 .le_base = 0xef0c00000ULL,
1053 .apc_base = 0xefa000000ULL, // XXX should not exist
1054 .aux1_base = 0xff1800000ULL,
1055 .aux2_base = 0xff1a01000ULL,
1056 .ecc_base = 0xf00000000ULL,
1057 .ecc_version = 0x10000000, // version 0, implementation 1
1058 .nvram_machine_id = 0x72,
1059 .machine_id = ss10_id,
1060 .iommu_version = 0x03000000,
1061 .max_mem = 0xf00000000ULL,
1062 .default_cpu_model = "TI SuperSparc II",
1063 },
1064 /* SS-600MP */
1065 {
1066 .iommu_base = 0xfe0000000ULL,
1067 .tcx_base = 0xe20000000ULL,
1068 .slavio_base = 0xff0000000ULL,
1069 .ms_kb_base = 0xff1000000ULL,
1070 .serial_base = 0xff1100000ULL,
1071 .nvram_base = 0xff1200000ULL,
1072 .counter_base = 0xff1300000ULL,
1073 .intctl_base = 0xff1400000ULL,
1074 .dma_base = 0xef0081000ULL,
1075 .esp_base = 0xef0080000ULL,
1076 .le_base = 0xef0060000ULL,
1077 .apc_base = 0xefa000000ULL, // XXX should not exist
1078 .aux1_base = 0xff1800000ULL,
1079 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1080 .ecc_base = 0xf00000000ULL,
1081 .ecc_version = 0x00000000, // version 0, implementation 0
1082 .nvram_machine_id = 0x71,
1083 .machine_id = ss600mp_id,
1084 .iommu_version = 0x01000000,
1085 .max_mem = 0xf00000000ULL,
1086 .default_cpu_model = "TI SuperSparc II",
1087 },
1088 /* SS-20 */
1089 {
1090 .iommu_base = 0xfe0000000ULL,
1091 .tcx_base = 0xe20000000ULL,
1092 .slavio_base = 0xff0000000ULL,
1093 .ms_kb_base = 0xff1000000ULL,
1094 .serial_base = 0xff1100000ULL,
1095 .nvram_base = 0xff1200000ULL,
1096 .fd_base = 0xff1700000ULL,
1097 .counter_base = 0xff1300000ULL,
1098 .intctl_base = 0xff1400000ULL,
1099 .idreg_base = 0xef0000000ULL,
1100 .dma_base = 0xef0400000ULL,
1101 .esp_base = 0xef0800000ULL,
1102 .le_base = 0xef0c00000ULL,
1103 .bpp_base = 0xef4800000ULL,
1104 .apc_base = 0xefa000000ULL, // XXX should not exist
1105 .aux1_base = 0xff1800000ULL,
1106 .aux2_base = 0xff1a01000ULL,
1107 .dbri_base = 0xee0000000ULL,
1108 .sx_base = 0xf80000000ULL,
1109 .vsimm = {
1110 {
1111 .reg_base = 0x9c000000ULL,
1112 .vram_base = 0xfc000000ULL
1113 }, {
1114 .reg_base = 0x90000000ULL,
1115 .vram_base = 0xf0000000ULL
1116 }, {
1117 .reg_base = 0x94000000ULL
1118 }, {
1119 .reg_base = 0x98000000ULL
1120 }
1121 },
1122 .ecc_base = 0xf00000000ULL,
1123 .ecc_version = 0x20000000, // version 0, implementation 2
1124 .nvram_machine_id = 0x72,
1125 .machine_id = ss20_id,
1126 .iommu_version = 0x13000000,
1127 .max_mem = 0xf00000000ULL,
1128 .default_cpu_model = "TI SuperSparc II",
1129 },
1130 /* Voyager */
1131 {
1132 .iommu_base = 0x10000000,
1133 .tcx_base = 0x50000000,
1134 .slavio_base = 0x70000000,
1135 .ms_kb_base = 0x71000000,
1136 .serial_base = 0x71100000,
1137 .nvram_base = 0x71200000,
1138 .fd_base = 0x71400000,
1139 .counter_base = 0x71d00000,
1140 .intctl_base = 0x71e00000,
1141 .idreg_base = 0x78000000,
1142 .dma_base = 0x78400000,
1143 .esp_base = 0x78800000,
1144 .le_base = 0x78c00000,
1145 .apc_base = 0x71300000, // pmc
1146 .aux1_base = 0x71900000,
1147 .aux2_base = 0x71910000,
1148 .nvram_machine_id = 0x80,
1149 .machine_id = vger_id,
1150 .iommu_version = 0x05000000,
1151 .max_mem = 0x10000000,
1152 .default_cpu_model = "Fujitsu MB86904",
1153 },
1154 /* LX */
1155 {
1156 .iommu_base = 0x10000000,
1157 .iommu_pad_base = 0x10004000,
1158 .iommu_pad_len = 0x0fffb000,
1159 .tcx_base = 0x50000000,
1160 .slavio_base = 0x70000000,
1161 .ms_kb_base = 0x71000000,
1162 .serial_base = 0x71100000,
1163 .nvram_base = 0x71200000,
1164 .fd_base = 0x71400000,
1165 .counter_base = 0x71d00000,
1166 .intctl_base = 0x71e00000,
1167 .idreg_base = 0x78000000,
1168 .dma_base = 0x78400000,
1169 .esp_base = 0x78800000,
1170 .le_base = 0x78c00000,
1171 .aux1_base = 0x71900000,
1172 .aux2_base = 0x71910000,
1173 .nvram_machine_id = 0x80,
1174 .machine_id = lx_id,
1175 .iommu_version = 0x04000000,
1176 .max_mem = 0x10000000,
1177 .default_cpu_model = "TI MicroSparc I",
1178 },
1179 /* SS-4 */
1180 {
1181 .iommu_base = 0x10000000,
1182 .tcx_base = 0x50000000,
1183 .cs_base = 0x6c000000,
1184 .slavio_base = 0x70000000,
1185 .ms_kb_base = 0x71000000,
1186 .serial_base = 0x71100000,
1187 .nvram_base = 0x71200000,
1188 .fd_base = 0x71400000,
1189 .counter_base = 0x71d00000,
1190 .intctl_base = 0x71e00000,
1191 .idreg_base = 0x78000000,
1192 .dma_base = 0x78400000,
1193 .esp_base = 0x78800000,
1194 .le_base = 0x78c00000,
1195 .apc_base = 0x6a000000,
1196 .aux1_base = 0x71900000,
1197 .aux2_base = 0x71910000,
1198 .nvram_machine_id = 0x80,
1199 .machine_id = ss4_id,
1200 .iommu_version = 0x05000000,
1201 .max_mem = 0x10000000,
1202 .default_cpu_model = "Fujitsu MB86904",
1203 },
1204 /* SPARCClassic */
1205 {
1206 .iommu_base = 0x10000000,
1207 .tcx_base = 0x50000000,
1208 .slavio_base = 0x70000000,
1209 .ms_kb_base = 0x71000000,
1210 .serial_base = 0x71100000,
1211 .nvram_base = 0x71200000,
1212 .fd_base = 0x71400000,
1213 .counter_base = 0x71d00000,
1214 .intctl_base = 0x71e00000,
1215 .idreg_base = 0x78000000,
1216 .dma_base = 0x78400000,
1217 .esp_base = 0x78800000,
1218 .le_base = 0x78c00000,
1219 .apc_base = 0x6a000000,
1220 .aux1_base = 0x71900000,
1221 .aux2_base = 0x71910000,
1222 .nvram_machine_id = 0x80,
1223 .machine_id = scls_id,
1224 .iommu_version = 0x05000000,
1225 .max_mem = 0x10000000,
1226 .default_cpu_model = "TI MicroSparc I",
1227 },
1228 /* SPARCbook */
1229 {
1230 .iommu_base = 0x10000000,
1231 .tcx_base = 0x50000000, // XXX
1232 .slavio_base = 0x70000000,
1233 .ms_kb_base = 0x71000000,
1234 .serial_base = 0x71100000,
1235 .nvram_base = 0x71200000,
1236 .fd_base = 0x71400000,
1237 .counter_base = 0x71d00000,
1238 .intctl_base = 0x71e00000,
1239 .idreg_base = 0x78000000,
1240 .dma_base = 0x78400000,
1241 .esp_base = 0x78800000,
1242 .le_base = 0x78c00000,
1243 .apc_base = 0x6a000000,
1244 .aux1_base = 0x71900000,
1245 .aux2_base = 0x71910000,
1246 .nvram_machine_id = 0x80,
1247 .machine_id = sbook_id,
1248 .iommu_version = 0x05000000,
1249 .max_mem = 0x10000000,
1250 .default_cpu_model = "TI MicroSparc I",
1251 },
1252 };
1253
1254 /* SPARCstation 5 hardware initialisation */
1255 static void ss5_init(ram_addr_t RAM_size,
1256 const char *boot_device,
1257 const char *kernel_filename, const char *kernel_cmdline,
1258 const char *initrd_filename, const char *cpu_model)
1259 {
1260 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1261 kernel_cmdline, initrd_filename, cpu_model);
1262 }
1263
1264 /* SPARCstation 10 hardware initialisation */
1265 static void ss10_init(ram_addr_t RAM_size,
1266 const char *boot_device,
1267 const char *kernel_filename, const char *kernel_cmdline,
1268 const char *initrd_filename, const char *cpu_model)
1269 {
1270 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1271 kernel_cmdline, initrd_filename, cpu_model);
1272 }
1273
1274 /* SPARCserver 600MP hardware initialisation */
1275 static void ss600mp_init(ram_addr_t RAM_size,
1276 const char *boot_device,
1277 const char *kernel_filename,
1278 const char *kernel_cmdline,
1279 const char *initrd_filename, const char *cpu_model)
1280 {
1281 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1282 kernel_cmdline, initrd_filename, cpu_model);
1283 }
1284
1285 /* SPARCstation 20 hardware initialisation */
1286 static void ss20_init(ram_addr_t RAM_size,
1287 const char *boot_device,
1288 const char *kernel_filename, const char *kernel_cmdline,
1289 const char *initrd_filename, const char *cpu_model)
1290 {
1291 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1292 kernel_cmdline, initrd_filename, cpu_model);
1293 }
1294
1295 /* SPARCstation Voyager hardware initialisation */
1296 static void vger_init(ram_addr_t RAM_size,
1297 const char *boot_device,
1298 const char *kernel_filename, const char *kernel_cmdline,
1299 const char *initrd_filename, const char *cpu_model)
1300 {
1301 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1302 kernel_cmdline, initrd_filename, cpu_model);
1303 }
1304
1305 /* SPARCstation LX hardware initialisation */
1306 static void ss_lx_init(ram_addr_t RAM_size,
1307 const char *boot_device,
1308 const char *kernel_filename, const char *kernel_cmdline,
1309 const char *initrd_filename, const char *cpu_model)
1310 {
1311 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1312 kernel_cmdline, initrd_filename, cpu_model);
1313 }
1314
1315 /* SPARCstation 4 hardware initialisation */
1316 static void ss4_init(ram_addr_t RAM_size,
1317 const char *boot_device,
1318 const char *kernel_filename, const char *kernel_cmdline,
1319 const char *initrd_filename, const char *cpu_model)
1320 {
1321 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1322 kernel_cmdline, initrd_filename, cpu_model);
1323 }
1324
1325 /* SPARCClassic hardware initialisation */
1326 static void scls_init(ram_addr_t RAM_size,
1327 const char *boot_device,
1328 const char *kernel_filename, const char *kernel_cmdline,
1329 const char *initrd_filename, const char *cpu_model)
1330 {
1331 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1332 kernel_cmdline, initrd_filename, cpu_model);
1333 }
1334
1335 /* SPARCbook hardware initialisation */
1336 static void sbook_init(ram_addr_t RAM_size,
1337 const char *boot_device,
1338 const char *kernel_filename, const char *kernel_cmdline,
1339 const char *initrd_filename, const char *cpu_model)
1340 {
1341 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1342 kernel_cmdline, initrd_filename, cpu_model);
1343 }
1344
1345 static QEMUMachine ss5_machine = {
1346 .name = "SS-5",
1347 .desc = "Sun4m platform, SPARCstation 5",
1348 .init = ss5_init,
1349 .use_scsi = 1,
1350 .is_default = 1,
1351 };
1352
1353 static QEMUMachine ss10_machine = {
1354 .name = "SS-10",
1355 .desc = "Sun4m platform, SPARCstation 10",
1356 .init = ss10_init,
1357 .use_scsi = 1,
1358 .max_cpus = 4,
1359 };
1360
1361 static QEMUMachine ss600mp_machine = {
1362 .name = "SS-600MP",
1363 .desc = "Sun4m platform, SPARCserver 600MP",
1364 .init = ss600mp_init,
1365 .use_scsi = 1,
1366 .max_cpus = 4,
1367 };
1368
1369 static QEMUMachine ss20_machine = {
1370 .name = "SS-20",
1371 .desc = "Sun4m platform, SPARCstation 20",
1372 .init = ss20_init,
1373 .use_scsi = 1,
1374 .max_cpus = 4,
1375 };
1376
1377 static QEMUMachine voyager_machine = {
1378 .name = "Voyager",
1379 .desc = "Sun4m platform, SPARCstation Voyager",
1380 .init = vger_init,
1381 .use_scsi = 1,
1382 };
1383
1384 static QEMUMachine ss_lx_machine = {
1385 .name = "LX",
1386 .desc = "Sun4m platform, SPARCstation LX",
1387 .init = ss_lx_init,
1388 .use_scsi = 1,
1389 };
1390
1391 static QEMUMachine ss4_machine = {
1392 .name = "SS-4",
1393 .desc = "Sun4m platform, SPARCstation 4",
1394 .init = ss4_init,
1395 .use_scsi = 1,
1396 };
1397
1398 static QEMUMachine scls_machine = {
1399 .name = "SPARCClassic",
1400 .desc = "Sun4m platform, SPARCClassic",
1401 .init = scls_init,
1402 .use_scsi = 1,
1403 };
1404
1405 static QEMUMachine sbook_machine = {
1406 .name = "SPARCbook",
1407 .desc = "Sun4m platform, SPARCbook",
1408 .init = sbook_init,
1409 .use_scsi = 1,
1410 };
1411
1412 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1413 /* SS-1000 */
1414 {
1415 .iounit_bases = {
1416 0xfe0200000ULL,
1417 0xfe1200000ULL,
1418 0xfe2200000ULL,
1419 0xfe3200000ULL,
1420 -1,
1421 },
1422 .tcx_base = 0x820000000ULL,
1423 .slavio_base = 0xf00000000ULL,
1424 .ms_kb_base = 0xf00240000ULL,
1425 .serial_base = 0xf00200000ULL,
1426 .nvram_base = 0xf00280000ULL,
1427 .counter_base = 0xf00300000ULL,
1428 .espdma_base = 0x800081000ULL,
1429 .esp_base = 0x800080000ULL,
1430 .ledma_base = 0x800040000ULL,
1431 .le_base = 0x800060000ULL,
1432 .sbi_base = 0xf02800000ULL,
1433 .nvram_machine_id = 0x80,
1434 .machine_id = ss1000_id,
1435 .iounit_version = 0x03000000,
1436 .max_mem = 0xf00000000ULL,
1437 .default_cpu_model = "TI SuperSparc II",
1438 },
1439 /* SS-2000 */
1440 {
1441 .iounit_bases = {
1442 0xfe0200000ULL,
1443 0xfe1200000ULL,
1444 0xfe2200000ULL,
1445 0xfe3200000ULL,
1446 0xfe4200000ULL,
1447 },
1448 .tcx_base = 0x820000000ULL,
1449 .slavio_base = 0xf00000000ULL,
1450 .ms_kb_base = 0xf00240000ULL,
1451 .serial_base = 0xf00200000ULL,
1452 .nvram_base = 0xf00280000ULL,
1453 .counter_base = 0xf00300000ULL,
1454 .espdma_base = 0x800081000ULL,
1455 .esp_base = 0x800080000ULL,
1456 .ledma_base = 0x800040000ULL,
1457 .le_base = 0x800060000ULL,
1458 .sbi_base = 0xf02800000ULL,
1459 .nvram_machine_id = 0x80,
1460 .machine_id = ss2000_id,
1461 .iounit_version = 0x03000000,
1462 .max_mem = 0xf00000000ULL,
1463 .default_cpu_model = "TI SuperSparc II",
1464 },
1465 };
1466
1467 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1468 {
1469 DeviceState *dev;
1470 SysBusDevice *s;
1471 unsigned int i;
1472
1473 dev = qdev_create(NULL, "sbi");
1474 qdev_init_nofail(dev);
1475
1476 s = sysbus_from_qdev(dev);
1477
1478 for (i = 0; i < MAX_CPUS; i++) {
1479 sysbus_connect_irq(s, i, *parent_irq[i]);
1480 }
1481
1482 sysbus_mmio_map(s, 0, addr);
1483
1484 return dev;
1485 }
1486
1487 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1488 const char *boot_device,
1489 const char *kernel_filename,
1490 const char *kernel_cmdline,
1491 const char *initrd_filename, const char *cpu_model)
1492 {
1493 unsigned int i;
1494 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1495 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1496 espdma_irq, ledma_irq;
1497 qemu_irq esp_reset, dma_enable;
1498 unsigned long kernel_size;
1499 void *fw_cfg;
1500 DeviceState *dev;
1501
1502 /* init CPUs */
1503 if (!cpu_model)
1504 cpu_model = hwdef->default_cpu_model;
1505
1506 for(i = 0; i < smp_cpus; i++) {
1507 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1508 }
1509
1510 for (i = smp_cpus; i < MAX_CPUS; i++)
1511 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1512
1513 /* set up devices */
1514 ram_init(0, RAM_size, hwdef->max_mem);
1515
1516 prom_init(hwdef->slavio_base, bios_name);
1517
1518 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1519
1520 for (i = 0; i < 32; i++) {
1521 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1522 }
1523 for (i = 0; i < MAX_CPUS; i++) {
1524 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1525 }
1526
1527 for (i = 0; i < MAX_IOUNITS; i++)
1528 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1529 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1530 hwdef->iounit_version,
1531 sbi_irq[0]);
1532
1533 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1534 iounits[0], &espdma_irq, 0);
1535
1536 /* should be lebuffer instead */
1537 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1538 iounits[0], &ledma_irq, 0);
1539
1540 if (graphic_depth != 8 && graphic_depth != 24) {
1541 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1542 exit (1);
1543 }
1544 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1545 graphic_depth);
1546
1547 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1548
1549 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1550
1551 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1552
1553 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1554 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1555 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1556 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1557 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1558 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1559
1560 if (drive_get_max_bus(IF_SCSI) > 0) {
1561 fprintf(stderr, "qemu: too many SCSI bus\n");
1562 exit(1);
1563 }
1564
1565 esp_init(hwdef->esp_base, 2,
1566 espdma_memory_read, espdma_memory_write,
1567 espdma, espdma_irq, &esp_reset, &dma_enable);
1568
1569 qdev_connect_gpio_out(espdma, 0, esp_reset);
1570 qdev_connect_gpio_out(espdma, 1, dma_enable);
1571
1572 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1573 RAM_size);
1574
1575 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1576 boot_device, RAM_size, kernel_size, graphic_width,
1577 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1578 "Sun4d");
1579
1580 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1581 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1582 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1583 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1584 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1585 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1586 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1587 if (kernel_cmdline) {
1588 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1589 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1590 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1591 (uint8_t*)strdup(kernel_cmdline),
1592 strlen(kernel_cmdline) + 1);
1593 } else {
1594 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1595 }
1596 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1597 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1598 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1599 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1600 }
1601
1602 /* SPARCserver 1000 hardware initialisation */
1603 static void ss1000_init(ram_addr_t RAM_size,
1604 const char *boot_device,
1605 const char *kernel_filename, const char *kernel_cmdline,
1606 const char *initrd_filename, const char *cpu_model)
1607 {
1608 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1609 kernel_cmdline, initrd_filename, cpu_model);
1610 }
1611
1612 /* SPARCcenter 2000 hardware initialisation */
1613 static void ss2000_init(ram_addr_t RAM_size,
1614 const char *boot_device,
1615 const char *kernel_filename, const char *kernel_cmdline,
1616 const char *initrd_filename, const char *cpu_model)
1617 {
1618 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1619 kernel_cmdline, initrd_filename, cpu_model);
1620 }
1621
1622 static QEMUMachine ss1000_machine = {
1623 .name = "SS-1000",
1624 .desc = "Sun4d platform, SPARCserver 1000",
1625 .init = ss1000_init,
1626 .use_scsi = 1,
1627 .max_cpus = 8,
1628 };
1629
1630 static QEMUMachine ss2000_machine = {
1631 .name = "SS-2000",
1632 .desc = "Sun4d platform, SPARCcenter 2000",
1633 .init = ss2000_init,
1634 .use_scsi = 1,
1635 .max_cpus = 20,
1636 };
1637
1638 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1639 /* SS-2 */
1640 {
1641 .iommu_base = 0xf8000000,
1642 .tcx_base = 0xfe000000,
1643 .slavio_base = 0xf6000000,
1644 .intctl_base = 0xf5000000,
1645 .counter_base = 0xf3000000,
1646 .ms_kb_base = 0xf0000000,
1647 .serial_base = 0xf1000000,
1648 .nvram_base = 0xf2000000,
1649 .fd_base = 0xf7200000,
1650 .dma_base = 0xf8400000,
1651 .esp_base = 0xf8800000,
1652 .le_base = 0xf8c00000,
1653 .aux1_base = 0xf7400003,
1654 .nvram_machine_id = 0x55,
1655 .machine_id = ss2_id,
1656 .max_mem = 0x10000000,
1657 .default_cpu_model = "Cypress CY7C601",
1658 },
1659 };
1660
1661 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1662 qemu_irq *parent_irq)
1663 {
1664 DeviceState *dev;
1665 SysBusDevice *s;
1666 unsigned int i;
1667
1668 dev = qdev_create(NULL, "sun4c_intctl");
1669 qdev_init_nofail(dev);
1670
1671 s = sysbus_from_qdev(dev);
1672
1673 for (i = 0; i < MAX_PILS; i++) {
1674 sysbus_connect_irq(s, i, parent_irq[i]);
1675 }
1676 sysbus_mmio_map(s, 0, addr);
1677
1678 return dev;
1679 }
1680
1681 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1682 const char *boot_device,
1683 const char *kernel_filename,
1684 const char *kernel_cmdline,
1685 const char *initrd_filename, const char *cpu_model)
1686 {
1687 void *iommu, *espdma, *ledma, *nvram;
1688 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1689 qemu_irq esp_reset, dma_enable;
1690 qemu_irq fdc_tc;
1691 unsigned long kernel_size;
1692 DriveInfo *fd[MAX_FD];
1693 void *fw_cfg;
1694 DeviceState *dev;
1695 unsigned int i;
1696
1697 /* init CPU */
1698 if (!cpu_model)
1699 cpu_model = hwdef->default_cpu_model;
1700
1701 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1702
1703 /* set up devices */
1704 ram_init(0, RAM_size, hwdef->max_mem);
1705
1706 prom_init(hwdef->slavio_base, bios_name);
1707
1708 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1709
1710 for (i = 0; i < 8; i++) {
1711 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1712 }
1713
1714 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1715 slavio_irq[1]);
1716
1717 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1718 iommu, &espdma_irq, 0);
1719
1720 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1721 slavio_irq[3], iommu, &ledma_irq, 1);
1722
1723 if (graphic_depth != 8 && graphic_depth != 24) {
1724 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1725 exit (1);
1726 }
1727 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1728 graphic_depth);
1729
1730 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1731
1732 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1733
1734 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1735 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1736 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1737 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1738 escc_init(hwdef->serial_base, slavio_irq[1],
1739 slavio_irq[1], serial_hds[0], serial_hds[1],
1740 ESCC_CLOCK, 1);
1741
1742 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1743
1744 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1745 /* there is zero or one floppy drive */
1746 memset(fd, 0, sizeof(fd));
1747 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1748 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1749 &fdc_tc);
1750 }
1751
1752 if (drive_get_max_bus(IF_SCSI) > 0) {
1753 fprintf(stderr, "qemu: too many SCSI bus\n");
1754 exit(1);
1755 }
1756
1757 esp_init(hwdef->esp_base, 2,
1758 espdma_memory_read, espdma_memory_write,
1759 espdma, espdma_irq, &esp_reset, &dma_enable);
1760
1761 qdev_connect_gpio_out(espdma, 0, esp_reset);
1762 qdev_connect_gpio_out(espdma, 1, dma_enable);
1763
1764 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1765 RAM_size);
1766
1767 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1768 boot_device, RAM_size, kernel_size, graphic_width,
1769 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1770 "Sun4c");
1771
1772 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1773 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1774 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1775 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1776 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1777 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1778 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1779 if (kernel_cmdline) {
1780 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1781 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1782 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1783 (uint8_t*)strdup(kernel_cmdline),
1784 strlen(kernel_cmdline) + 1);
1785 } else {
1786 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1787 }
1788 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1789 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1790 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1791 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1792 }
1793
1794 /* SPARCstation 2 hardware initialisation */
1795 static void ss2_init(ram_addr_t RAM_size,
1796 const char *boot_device,
1797 const char *kernel_filename, const char *kernel_cmdline,
1798 const char *initrd_filename, const char *cpu_model)
1799 {
1800 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1801 kernel_cmdline, initrd_filename, cpu_model);
1802 }
1803
1804 static QEMUMachine ss2_machine = {
1805 .name = "SS-2",
1806 .desc = "Sun4c platform, SPARCstation 2",
1807 .init = ss2_init,
1808 .use_scsi = 1,
1809 };
1810
1811 static void ss2_machine_init(void)
1812 {
1813 qemu_register_machine(&ss5_machine);
1814 qemu_register_machine(&ss10_machine);
1815 qemu_register_machine(&ss600mp_machine);
1816 qemu_register_machine(&ss20_machine);
1817 qemu_register_machine(&voyager_machine);
1818 qemu_register_machine(&ss_lx_machine);
1819 qemu_register_machine(&ss4_machine);
1820 qemu_register_machine(&scls_machine);
1821 qemu_register_machine(&sbook_machine);
1822 qemu_register_machine(&ss1000_machine);
1823 qemu_register_machine(&ss2000_machine);
1824 qemu_register_machine(&ss2_machine);
1825 }
1826
1827 machine_init(ss2_machine_init);
QEmu