target/arm/translate-a32.h

   1 /*
   2  *  AArch32 translation, common definitions.
   3  *
   4  * Copyright (c) 2021 Linaro, Ltd.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TARGET_ARM_TRANSLATE_A64_H
  21 #define TARGET_ARM_TRANSLATE_A64_H
  22
  23 /* Prototypes for autogenerated disassembler functions */
  24 bool disas_m_nocp(DisasContext *dc, uint32_t insn);
  25 bool disas_mve(DisasContext *dc, uint32_t insn);
  26 bool disas_vfp(DisasContext *s, uint32_t insn);
  27 bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
  28 bool disas_neon_dp(DisasContext *s, uint32_t insn);
  29 bool disas_neon_ls(DisasContext *s, uint32_t insn);
  30 bool disas_neon_shared(DisasContext *s, uint32_t insn);
  31
  32 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
  33 void arm_gen_condlabel(DisasContext *s);
  34 bool vfp_access_check(DisasContext *s);
  35 bool vfp_access_check_m(DisasContext *s, bool skip_context_update);
  36 void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
  37 void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
  38 void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
  39 void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
  40 TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
  41 void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
  42 void gen_set_condexec(DisasContext *s);
  43 void gen_set_pc_im(DisasContext *s, target_ulong val);
  44 void gen_lookup_tb(DisasContext *s);
  45 long vfp_reg_offset(bool dp, unsigned reg);
  46 long neon_full_reg_offset(unsigned reg);
  47 long neon_element_offset(int reg, int element, MemOp memop);
  48 void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
  49 void clear_eci_state(DisasContext *s);
  50 bool mve_eci_check(DisasContext *s);
  51 void mve_update_and_store_eci(DisasContext *s);
  52
  53 static inline TCGv_i32 load_cpu_offset(int offset)
  54 {
  55     TCGv_i32 tmp = tcg_temp_new_i32();
  56     tcg_gen_ld_i32(tmp, cpu_env, offset);
  57     return tmp;
  58 }
  59
  60 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
  61
  62 static inline void store_cpu_offset(TCGv_i32 var, int offset)
  63 {
  64     tcg_gen_st_i32(var, cpu_env, offset);
  65     tcg_temp_free_i32(var);
  66 }
  67
  68 #define store_cpu_field(var, name) \
  69     store_cpu_offset(var, offsetof(CPUARMState, name))
  70
  71 /* Create a new temporary and set it to the value of a CPU register.  */
  72 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
  73 {
  74     TCGv_i32 tmp = tcg_temp_new_i32();
  75     load_reg_var(s, tmp, reg);
  76     return tmp;
  77 }
  78
  79 void store_reg(DisasContext *s, int reg, TCGv_i32 var);
  80
  81 void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
  82                               TCGv_i32 a32, int index, MemOp opc);
  83 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
  84                               TCGv_i32 a32, int index, MemOp opc);
  85 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
  86                               TCGv_i32 a32, int index, MemOp opc);
  87 void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
  88                               TCGv_i32 a32, int index, MemOp opc);
  89 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  90                      int index, MemOp opc);
  91 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  92                      int index, MemOp opc);
  93 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
  94                      int index, MemOp opc);
  95 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
  96                      int index, MemOp opc);
  97
  98 #define DO_GEN_LD(SUFF, OPC)                                            \
  99     static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
 100                                          TCGv_i32 a32, int index)       \
 101     {                                                                   \
 102         gen_aa32_ld_i32(s, val, a32, index, OPC);                       \
 103     }
 104
 105 #define DO_GEN_ST(SUFF, OPC)                                            \
 106     static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
 107                                          TCGv_i32 a32, int index)       \
 108     {                                                                   \
 109         gen_aa32_st_i32(s, val, a32, index, OPC);                       \
 110     }
 111
 112 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
 113                                  TCGv_i32 a32, int index)
 114 {
 115     gen_aa32_ld_i64(s, val, a32, index, MO_Q);
 116 }
 117
 118 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
 119                                  TCGv_i32 a32, int index)
 120 {
 121     gen_aa32_st_i64(s, val, a32, index, MO_Q);
 122 }
 123
 124 DO_GEN_LD(8u, MO_UB)
 125 DO_GEN_LD(16u, MO_UW)
 126 DO_GEN_LD(32u, MO_UL)
 127 DO_GEN_ST(8, MO_UB)
 128 DO_GEN_ST(16, MO_UW)
 129 DO_GEN_ST(32, MO_UL)
 130
 131 #undef DO_GEN_LD
 132 #undef DO_GEN_ST
 133
 134 #if defined(CONFIG_USER_ONLY)
 135 #define IS_USER(s) 1
 136 #else
 137 #define IS_USER(s) (s->user)
 138 #endif
 139
 140 /* Set NZCV flags from the high 4 bits of var.  */
 141 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
 142
 143 /* Swap low and high halfwords.  */
 144 static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
 145 {
 146     tcg_gen_rotri_i32(dest, var, 16);
 147 }
 148
 149 #endif