hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/hw.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci-host/apb.h"
  31 #include "hw/i386/pc.h"
  32 #include "hw/char/serial.h"
  33 #include "hw/timer/m48t59.h"
  34 #include "hw/block/fdc.h"
  35 #include "net/net.h"
  36 #include "qemu/timer.h"
  37 #include "sysemu/sysemu.h"
  38 #include "hw/boards.h"
  39 #include "hw/nvram/openbios_firmware_abi.h"
  40 #include "hw/nvram/chrp_nvram.h"
  41 #include "hw/nvram/fw_cfg.h"
  42 #include "hw/sysbus.h"
  43 #include "hw/ide.h"
  44 #include "hw/loader.h"
  45 #include "elf.h"
  46 #include "sysemu/block-backend.h"
  47 #include "exec/address-spaces.h"
  48 #include "qemu/cutils.h"
  49
  50 //#define DEBUG_IRQ
  51 //#define DEBUG_EBUS
  52 //#define DEBUG_TIMER
  53
  54 #ifdef DEBUG_IRQ
  55 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  56     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  57 #else
  58 #define CPUIRQ_DPRINTF(fmt, ...)
  59 #endif
  60
  61 #ifdef DEBUG_EBUS
  62 #define EBUS_DPRINTF(fmt, ...)                                  \
  63     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  64 #else
  65 #define EBUS_DPRINTF(fmt, ...)
  66 #endif
  67
  68 #ifdef DEBUG_TIMER
  69 #define TIMER_DPRINTF(fmt, ...)                                  \
  70     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  71 #else
  72 #define TIMER_DPRINTF(fmt, ...)
  73 #endif
  74
  75 #define KERNEL_LOAD_ADDR     0x00404000
  76 #define CMDLINE_ADDR         0x003ff000
  77 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  78 #define PROM_VADDR           0x000ffd00000ULL
  79 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  80 #define APB_MEM_BASE         0x1ff00000000ULL
  81 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  82 #define PROM_FILENAME        "openbios-sparc64"
  83 #define NVRAM_SIZE           0x2000
  84 #define MAX_IDE_BUS          2
  85 #define BIOS_CFG_IOPORT      0x510
  86 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  87 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  88 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  89
  90 #define IVEC_MAX             0x40
  91
  92 #define TICK_MAX             0x7fffffffffffffffULL
  93
  94 struct hwdef {
  95     const char * const default_cpu_model;
  96     uint16_t machine_id;
  97     uint64_t prom_addr;
  98     uint64_t console_serial_base;
  99 };
 100
 101 typedef struct EbusState {
 102     PCIDevice pci_dev;
 103     MemoryRegion bar0;
 104     MemoryRegion bar1;
 105 } EbusState;
 106
 107 void DMA_init(ISABus *bus, int high_page_enable)
 108 {
 109 }
 110
 111 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 112                             Error **errp)
 113 {
 114     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 115 }
 116
 117 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 118                                   const char *arch, ram_addr_t RAM_size,
 119                                   const char *boot_devices,
 120                                   uint32_t kernel_image, uint32_t kernel_size,
 121                                   const char *cmdline,
 122                                   uint32_t initrd_image, uint32_t initrd_size,
 123                                   uint32_t NVRAM_image,
 124                                   int width, int height, int depth,
 125                                   const uint8_t *macaddr)
 126 {
 127     unsigned int i;
 128     int sysp_end;
 129     uint8_t image[0x1ff0];
 130     NvramClass *k = NVRAM_GET_CLASS(nvram);
 131
 132     memset(image, '\0', sizeof(image));
 133
 134     /* OpenBIOS nvram variables partition */
 135     sysp_end = chrp_nvram_create_system_partition(image, 0);
 136
 137     /* Free space partition */
 138     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 139
 140     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 141
 142     for (i = 0; i < sizeof(image); i++) {
 143         (k->write)(nvram, i, image[i]);
 144     }
 145
 146     return 0;
 147 }
 148
 149 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 150                                   const char *initrd_filename,
 151                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 152                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 153                                   uint64_t *kernel_entry)
 154 {
 155     int linux_boot;
 156     unsigned int i;
 157     long kernel_size;
 158     uint8_t *ptr;
 159     uint64_t kernel_top;
 160
 161     linux_boot = (kernel_filename != NULL);
 162
 163     kernel_size = 0;
 164     if (linux_boot) {
 165         int bswap_needed;
 166
 167 #ifdef BSWAP_NEEDED
 168         bswap_needed = 1;
 169 #else
 170         bswap_needed = 0;
 171 #endif
 172         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 173                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 174         if (kernel_size < 0) {
 175             *kernel_addr = KERNEL_LOAD_ADDR;
 176             *kernel_entry = KERNEL_LOAD_ADDR;
 177             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 178                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 179                                     TARGET_PAGE_SIZE);
 180         }
 181         if (kernel_size < 0) {
 182             kernel_size = load_image_targphys(kernel_filename,
 183                                               KERNEL_LOAD_ADDR,
 184                                               RAM_size - KERNEL_LOAD_ADDR);
 185         }
 186         if (kernel_size < 0) {
 187             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 188                     kernel_filename);
 189             exit(1);
 190         }
 191         /* load initrd above kernel */
 192         *initrd_size = 0;
 193         if (initrd_filename) {
 194             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 195
 196             *initrd_size = load_image_targphys(initrd_filename,
 197                                                *initrd_addr,
 198                                                RAM_size - *initrd_addr);
 199             if ((int)*initrd_size < 0) {
 200                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 201                         initrd_filename);
 202                 exit(1);
 203             }
 204         }
 205         if (*initrd_size > 0) {
 206             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 207                 ptr = rom_ptr(*kernel_addr + i);
 208                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 209                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 210                     stl_p(ptr + 28, *initrd_size);
 211                     break;
 212                 }
 213             }
 214         }
 215     }
 216     return kernel_size;
 217 }
 218
 219 void cpu_check_irqs(CPUSPARCState *env)
 220 {
 221     CPUState *cs;
 222     uint32_t pil = env->pil_in |
 223                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 224
 225     /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
 226     if (env->ivec_status & 0x20) {
 227         return;
 228     }
 229     cs = CPU(sparc_env_get_cpu(env));
 230     /* check if TM or SM in SOFTINT are set
 231        setting these also causes interrupt 14 */
 232     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 233         pil |= 1 << 14;
 234     }
 235
 236     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 237        is (2 << psrpil). */
 238     if (pil < (2 << env->psrpil)){
 239         if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 240             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 241                            env->interrupt_index);
 242             env->interrupt_index = 0;
 243             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 244         }
 245         return;
 246     }
 247
 248     if (cpu_interrupts_enabled(env)) {
 249
 250         unsigned int i;
 251
 252         for (i = 15; i > env->psrpil; i--) {
 253             if (pil & (1 << i)) {
 254                 int old_interrupt = env->interrupt_index;
 255                 int new_interrupt = TT_EXTINT | i;
 256
 257                 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
 258                   && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
 259                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 260                                    "current %x >= pending %x\n",
 261                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 262                 } else if (old_interrupt != new_interrupt) {
 263                     env->interrupt_index = new_interrupt;
 264                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 265                                    old_interrupt, new_interrupt);
 266                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 267                 }
 268                 break;
 269             }
 270         }
 271     } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 272         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 273                        "current interrupt %x\n",
 274                        pil, env->pil_in, env->softint, env->interrupt_index);
 275         env->interrupt_index = 0;
 276         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 277     }
 278 }
 279
 280 static void cpu_kick_irq(SPARCCPU *cpu)
 281 {
 282     CPUState *cs = CPU(cpu);
 283     CPUSPARCState *env = &cpu->env;
 284
 285     cs->halted = 0;
 286     cpu_check_irqs(env);
 287     qemu_cpu_kick(cs);
 288 }
 289
 290 static void cpu_set_ivec_irq(void *opaque, int irq, int level)
 291 {
 292     SPARCCPU *cpu = opaque;
 293     CPUSPARCState *env = &cpu->env;
 294     CPUState *cs;
 295
 296     if (level) {
 297         if (!(env->ivec_status & 0x20)) {
 298             CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
 299             cs = CPU(cpu);
 300             cs->halted = 0;
 301             env->interrupt_index = TT_IVEC;
 302             env->ivec_status |= 0x20;
 303             env->ivec_data[0] = (0x1f << 6) | irq;
 304             env->ivec_data[1] = 0;
 305             env->ivec_data[2] = 0;
 306             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 307         }
 308     } else {
 309         if (env->ivec_status & 0x20) {
 310             CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
 311             cs = CPU(cpu);
 312             env->ivec_status &= ~0x20;
 313             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 314         }
 315     }
 316 }
 317
 318 typedef struct ResetData {
 319     SPARCCPU *cpu;
 320     uint64_t prom_addr;
 321 } ResetData;
 322
 323 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
 324                                   QEMUBHFunc *cb, uint32_t frequency,
 325                                   uint64_t disabled_mask, uint64_t npt_mask)
 326 {
 327     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 328
 329     timer->name = name;
 330     timer->frequency = frequency;
 331     timer->disabled_mask = disabled_mask;
 332     timer->npt_mask = npt_mask;
 333
 334     timer->disabled = 1;
 335     timer->npt = 1;
 336     timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 337
 338     timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
 339
 340     return timer;
 341 }
 342
 343 static void cpu_timer_reset(CPUTimer *timer)
 344 {
 345     timer->disabled = 1;
 346     timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 347
 348     timer_del(timer->qtimer);
 349 }
 350
 351 static void main_cpu_reset(void *opaque)
 352 {
 353     ResetData *s = (ResetData *)opaque;
 354     CPUSPARCState *env = &s->cpu->env;
 355     static unsigned int nr_resets;
 356
 357     cpu_reset(CPU(s->cpu));
 358
 359     cpu_timer_reset(env->tick);
 360     cpu_timer_reset(env->stick);
 361     cpu_timer_reset(env->hstick);
 362
 363     env->gregs[1] = 0; // Memory start
 364     env->gregs[2] = ram_size; // Memory size
 365     env->gregs[3] = 0; // Machine description XXX
 366     if (nr_resets++ == 0) {
 367         /* Power on reset */
 368         env->pc = s->prom_addr + 0x20ULL;
 369     } else {
 370         env->pc = s->prom_addr + 0x40ULL;
 371     }
 372     env->npc = env->pc + 4;
 373 }
 374
 375 static void tick_irq(void *opaque)
 376 {
 377     SPARCCPU *cpu = opaque;
 378     CPUSPARCState *env = &cpu->env;
 379
 380     CPUTimer* timer = env->tick;
 381
 382     if (timer->disabled) {
 383         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 384         return;
 385     } else {
 386         CPUIRQ_DPRINTF("tick: fire\n");
 387     }
 388
 389     env->softint |= SOFTINT_TIMER;
 390     cpu_kick_irq(cpu);
 391 }
 392
 393 static void stick_irq(void *opaque)
 394 {
 395     SPARCCPU *cpu = opaque;
 396     CPUSPARCState *env = &cpu->env;
 397
 398     CPUTimer* timer = env->stick;
 399
 400     if (timer->disabled) {
 401         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 402         return;
 403     } else {
 404         CPUIRQ_DPRINTF("stick: fire\n");
 405     }
 406
 407     env->softint |= SOFTINT_STIMER;
 408     cpu_kick_irq(cpu);
 409 }
 410
 411 static void hstick_irq(void *opaque)
 412 {
 413     SPARCCPU *cpu = opaque;
 414     CPUSPARCState *env = &cpu->env;
 415
 416     CPUTimer* timer = env->hstick;
 417
 418     if (timer->disabled) {
 419         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 420         return;
 421     } else {
 422         CPUIRQ_DPRINTF("hstick: fire\n");
 423     }
 424
 425     env->softint |= SOFTINT_STIMER;
 426     cpu_kick_irq(cpu);
 427 }
 428
 429 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 430 {
 431     return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
 432 }
 433
 434 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 435 {
 436     return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
 437 }
 438
 439 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 440 {
 441     uint64_t real_count = count & ~timer->npt_mask;
 442     uint64_t npt_bit = count & timer->npt_mask;
 443
 444     int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 445                     cpu_to_timer_ticks(real_count, timer->frequency);
 446
 447     TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
 448                   timer->name, real_count,
 449                   timer->npt ? "disabled" : "enabled", timer);
 450
 451     timer->npt = npt_bit ? 1 : 0;
 452     timer->clock_offset = vm_clock_offset;
 453 }
 454
 455 uint64_t cpu_tick_get_count(CPUTimer *timer)
 456 {
 457     uint64_t real_count = timer_to_cpu_ticks(
 458                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
 459                     timer->frequency);
 460
 461     TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
 462            timer->name, real_count,
 463            timer->npt ? "disabled" : "enabled", timer);
 464
 465     if (timer->npt) {
 466         real_count |= timer->npt_mask;
 467     }
 468
 469     return real_count;
 470 }
 471
 472 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 473 {
 474     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 475
 476     uint64_t real_limit = limit & ~timer->disabled_mask;
 477     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 478
 479     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 480                     timer->clock_offset;
 481
 482     if (expires < now) {
 483         expires = now + 1;
 484     }
 485
 486     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 487                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 488                   timer->name, real_limit,
 489                   timer->disabled?"disabled":"enabled",
 490                   timer, limit,
 491                   timer_to_cpu_ticks(now - timer->clock_offset,
 492                                      timer->frequency),
 493                   timer_to_cpu_ticks(expires - now, timer->frequency));
 494
 495     if (!real_limit) {
 496         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 497                 timer->name);
 498         timer_del(timer->qtimer);
 499     } else if (timer->disabled) {
 500         timer_del(timer->qtimer);
 501     } else {
 502         timer_mod(timer->qtimer, expires);
 503     }
 504 }
 505
 506 static void isa_irq_handler(void *opaque, int n, int level)
 507 {
 508     static const int isa_irq_to_ivec[16] = {
 509         [1] = 0x29, /* keyboard */
 510         [4] = 0x2b, /* serial */
 511         [6] = 0x27, /* floppy */
 512         [7] = 0x22, /* parallel */
 513         [12] = 0x2a, /* mouse */
 514     };
 515     qemu_irq *irqs = opaque;
 516     int ivec;
 517
 518     assert(n < 16);
 519     ivec = isa_irq_to_ivec[n];
 520     EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
 521     if (ivec) {
 522         qemu_set_irq(irqs[ivec], level);
 523     }
 524 }
 525
 526 /* EBUS (Eight bit bus) bridge */
 527 static ISABus *
 528 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
 529 {
 530     qemu_irq *isa_irq;
 531     PCIDevice *pci_dev;
 532     ISABus *isa_bus;
 533
 534     pci_dev = pci_create_simple(bus, devfn, "ebus");
 535     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
 536     isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
 537     isa_bus_irqs(isa_bus, isa_irq);
 538     return isa_bus;
 539 }
 540
 541 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp)
 542 {
 543     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 544
 545     if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 546                      pci_address_space_io(pci_dev), errp)) {
 547         return;
 548     }
 549
 550     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 551     pci_dev->config[0x05] = 0x00;
 552     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 553     pci_dev->config[0x07] = 0x03; // status = medium devsel
 554     pci_dev->config[0x09] = 0x00; // programming i/f
 555     pci_dev->config[0x0D] = 0x0a; // latency_timer
 556
 557     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 558                              0, 0x1000000);
 559     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 560     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 561                              0, 0x4000);
 562     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 563 }
 564
 565 static void ebus_class_init(ObjectClass *klass, void *data)
 566 {
 567     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 568
 569     k->realize = pci_ebus_realize;
 570     k->vendor_id = PCI_VENDOR_ID_SUN;
 571     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 572     k->revision = 0x01;
 573     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 574 }
 575
 576 static const TypeInfo ebus_info = {
 577     .name          = "ebus",
 578     .parent        = TYPE_PCI_DEVICE,
 579     .instance_size = sizeof(EbusState),
 580     .class_init    = ebus_class_init,
 581 };
 582
 583 #define TYPE_OPENPROM "openprom"
 584 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 585
 586 typedef struct PROMState {
 587     SysBusDevice parent_obj;
 588
 589     MemoryRegion prom;
 590 } PROMState;
 591
 592 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 593 {
 594     hwaddr *base_addr = (hwaddr *)opaque;
 595     return addr + *base_addr - PROM_VADDR;
 596 }
 597
 598 /* Boot PROM (OpenBIOS) */
 599 static void prom_init(hwaddr addr, const char *bios_name)
 600 {
 601     DeviceState *dev;
 602     SysBusDevice *s;
 603     char *filename;
 604     int ret;
 605
 606     dev = qdev_create(NULL, TYPE_OPENPROM);
 607     qdev_init_nofail(dev);
 608     s = SYS_BUS_DEVICE(dev);
 609
 610     sysbus_mmio_map(s, 0, addr);
 611
 612     /* load boot prom */
 613     if (bios_name == NULL) {
 614         bios_name = PROM_FILENAME;
 615     }
 616     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 617     if (filename) {
 618         ret = load_elf(filename, translate_prom_address, &addr,
 619                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 620         if (ret < 0 || ret > PROM_SIZE_MAX) {
 621             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 622         }
 623         g_free(filename);
 624     } else {
 625         ret = -1;
 626     }
 627     if (ret < 0 || ret > PROM_SIZE_MAX) {
 628         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 629         exit(1);
 630     }
 631 }
 632
 633 static int prom_init1(SysBusDevice *dev)
 634 {
 635     PROMState *s = OPENPROM(dev);
 636
 637     memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX,
 638                            &error_fatal);
 639     vmstate_register_ram_global(&s->prom);
 640     memory_region_set_readonly(&s->prom, true);
 641     sysbus_init_mmio(dev, &s->prom);
 642     return 0;
 643 }
 644
 645 static Property prom_properties[] = {
 646     {/* end of property list */},
 647 };
 648
 649 static void prom_class_init(ObjectClass *klass, void *data)
 650 {
 651     DeviceClass *dc = DEVICE_CLASS(klass);
 652     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 653
 654     k->init = prom_init1;
 655     dc->props = prom_properties;
 656 }
 657
 658 static const TypeInfo prom_info = {
 659     .name          = TYPE_OPENPROM,
 660     .parent        = TYPE_SYS_BUS_DEVICE,
 661     .instance_size = sizeof(PROMState),
 662     .class_init    = prom_class_init,
 663 };
 664
 665
 666 #define TYPE_SUN4U_MEMORY "memory"
 667 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 668
 669 typedef struct RamDevice {
 670     SysBusDevice parent_obj;
 671
 672     MemoryRegion ram;
 673     uint64_t size;
 674 } RamDevice;
 675
 676 /* System RAM */
 677 static int ram_init1(SysBusDevice *dev)
 678 {
 679     RamDevice *d = SUN4U_RAM(dev);
 680
 681     memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 682                            &error_fatal);
 683     vmstate_register_ram_global(&d->ram);
 684     sysbus_init_mmio(dev, &d->ram);
 685     return 0;
 686 }
 687
 688 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 689 {
 690     DeviceState *dev;
 691     SysBusDevice *s;
 692     RamDevice *d;
 693
 694     /* allocate RAM */
 695     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 696     s = SYS_BUS_DEVICE(dev);
 697
 698     d = SUN4U_RAM(dev);
 699     d->size = RAM_size;
 700     qdev_init_nofail(dev);
 701
 702     sysbus_mmio_map(s, 0, addr);
 703 }
 704
 705 static Property ram_properties[] = {
 706     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 707     DEFINE_PROP_END_OF_LIST(),
 708 };
 709
 710 static void ram_class_init(ObjectClass *klass, void *data)
 711 {
 712     DeviceClass *dc = DEVICE_CLASS(klass);
 713     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 714
 715     k->init = ram_init1;
 716     dc->props = ram_properties;
 717 }
 718
 719 static const TypeInfo ram_info = {
 720     .name          = TYPE_SUN4U_MEMORY,
 721     .parent        = TYPE_SYS_BUS_DEVICE,
 722     .instance_size = sizeof(RamDevice),
 723     .class_init    = ram_class_init,
 724 };
 725
 726 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 727 {
 728     SPARCCPU *cpu;
 729     CPUSPARCState *env;
 730     ResetData *reset_info;
 731
 732     uint32_t   tick_frequency = 100*1000000;
 733     uint32_t  stick_frequency = 100*1000000;
 734     uint32_t hstick_frequency = 100*1000000;
 735
 736     if (cpu_model == NULL) {
 737         cpu_model = hwdef->default_cpu_model;
 738     }
 739     cpu = cpu_sparc_init(cpu_model);
 740     if (cpu == NULL) {
 741         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 742         exit(1);
 743     }
 744     env = &cpu->env;
 745
 746     env->tick = cpu_timer_create("tick", cpu, tick_irq,
 747                                   tick_frequency, TICK_INT_DIS,
 748                                   TICK_NPT_MASK);
 749
 750     env->stick = cpu_timer_create("stick", cpu, stick_irq,
 751                                    stick_frequency, TICK_INT_DIS,
 752                                    TICK_NPT_MASK);
 753
 754     env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
 755                                     hstick_frequency, TICK_INT_DIS,
 756                                     TICK_NPT_MASK);
 757
 758     reset_info = g_malloc0(sizeof(ResetData));
 759     reset_info->cpu = cpu;
 760     reset_info->prom_addr = hwdef->prom_addr;
 761     qemu_register_reset(main_cpu_reset, reset_info);
 762
 763     return cpu;
 764 }
 765
 766 static void sun4uv_init(MemoryRegion *address_space_mem,
 767                         MachineState *machine,
 768                         const struct hwdef *hwdef)
 769 {
 770     SPARCCPU *cpu;
 771     Nvram *nvram;
 772     unsigned int i;
 773     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 774     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 775     ISABus *isa_bus;
 776     SysBusDevice *s;
 777     qemu_irq *ivec_irqs, *pbm_irqs;
 778     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 779     DriveInfo *fd[MAX_FD];
 780     DeviceState *dev;
 781     FWCfgState *fw_cfg;
 782
 783     /* init CPUs */
 784     cpu = cpu_devinit(machine->cpu_model, hwdef);
 785
 786     /* set up devices */
 787     ram_init(0, machine->ram_size);
 788
 789     prom_init(hwdef->prom_addr, bios_name);
 790
 791     ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
 792     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
 793                            &pci_bus3, &pbm_irqs);
 794     pci_vga_init(pci_bus);
 795
 796     // XXX Should be pci_bus3
 797     isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
 798
 799     i = 0;
 800     if (hwdef->console_serial_base) {
 801         serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
 802                        NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 803         i++;
 804     }
 805
 806     serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS);
 807     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
 808
 809     for(i = 0; i < nb_nics; i++)
 810         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 811
 812     ide_drive_get(hd, ARRAY_SIZE(hd));
 813
 814     pci_cmd646_ide_init(pci_bus, hd, 1);
 815
 816     isa_create_simple(isa_bus, "i8042");
 817
 818     /* Floppy */
 819     for(i = 0; i < MAX_FD; i++) {
 820         fd[i] = drive_get(IF_FLOPPY, 0, i);
 821     }
 822     dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC));
 823     if (fd[0]) {
 824         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 825                             &error_abort);
 826     }
 827     if (fd[1]) {
 828         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 829                             &error_abort);
 830     }
 831     qdev_prop_set_uint32(dev, "dma", -1);
 832     qdev_init_nofail(dev);
 833
 834     /* Map NVRAM into I/O (ebus) space */
 835     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 836     s = SYS_BUS_DEVICE(nvram);
 837     memory_region_add_subregion(get_system_io(), 0x2000,
 838                                 sysbus_mmio_get_region(s, 0));
 839
 840     initrd_size = 0;
 841     initrd_addr = 0;
 842     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 843                                     machine->initrd_filename,
 844                                     ram_size, &initrd_size, &initrd_addr,
 845                                     &kernel_addr, &kernel_entry);
 846
 847     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 848                            machine->boot_order,
 849                            kernel_addr, kernel_size,
 850                            machine->kernel_cmdline,
 851                            initrd_addr, initrd_size,
 852                            /* XXX: need an option to load a NVRAM image */
 853                            0,
 854                            graphic_width, graphic_height, graphic_depth,
 855                            (uint8_t *)&nd_table[0].macaddr);
 856
 857     fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
 858     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 859     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 860     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 861     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 862     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 863     if (machine->kernel_cmdline) {
 864         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 865                        strlen(machine->kernel_cmdline) + 1);
 866         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 867     } else {
 868         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 869     }
 870     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 871     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 872     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 873
 874     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 875     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 876     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 877
 878     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 879 }
 880
 881 enum {
 882     sun4u_id = 0,
 883     sun4v_id = 64,
 884     niagara_id,
 885 };
 886
 887 static const struct hwdef hwdefs[] = {
 888     /* Sun4u generic PC-like machine */
 889     {
 890         .default_cpu_model = "TI UltraSparc IIi",
 891         .machine_id = sun4u_id,
 892         .prom_addr = 0x1fff0000000ULL,
 893         .console_serial_base = 0,
 894     },
 895     /* Sun4v generic PC-like machine */
 896     {
 897         .default_cpu_model = "Sun UltraSparc T1",
 898         .machine_id = sun4v_id,
 899         .prom_addr = 0x1fff0000000ULL,
 900         .console_serial_base = 0,
 901     },
 902     /* Sun4v generic Niagara machine */
 903     {
 904         .default_cpu_model = "Sun UltraSparc T1",
 905         .machine_id = niagara_id,
 906         .prom_addr = 0xfff0000000ULL,
 907         .console_serial_base = 0xfff0c2c000ULL,
 908     },
 909 };
 910
 911 /* Sun4u hardware initialisation */
 912 static void sun4u_init(MachineState *machine)
 913 {
 914     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 915 }
 916
 917 /* Sun4v hardware initialisation */
 918 static void sun4v_init(MachineState *machine)
 919 {
 920     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 921 }
 922
 923 /* Niagara hardware initialisation */
 924 static void niagara_init(MachineState *machine)
 925 {
 926     sun4uv_init(get_system_memory(), machine, &hwdefs[2]);
 927 }
 928
 929 static void sun4u_class_init(ObjectClass *oc, void *data)
 930 {
 931     MachineClass *mc = MACHINE_CLASS(oc);
 932
 933     mc->desc = "Sun4u platform";
 934     mc->init = sun4u_init;
 935     mc->max_cpus = 1; /* XXX for now */
 936     mc->is_default = 1;
 937     mc->default_boot_order = "c";
 938 }
 939
 940 static const TypeInfo sun4u_type = {
 941     .name = MACHINE_TYPE_NAME("sun4u"),
 942     .parent = TYPE_MACHINE,
 943     .class_init = sun4u_class_init,
 944 };
 945
 946 static void sun4v_class_init(ObjectClass *oc, void *data)
 947 {
 948     MachineClass *mc = MACHINE_CLASS(oc);
 949
 950     mc->desc = "Sun4v platform";
 951     mc->init = sun4v_init;
 952     mc->max_cpus = 1; /* XXX for now */
 953     mc->default_boot_order = "c";
 954 }
 955
 956 static const TypeInfo sun4v_type = {
 957     .name = MACHINE_TYPE_NAME("sun4v"),
 958     .parent = TYPE_MACHINE,
 959     .class_init = sun4v_class_init,
 960 };
 961
 962 static void niagara_class_init(ObjectClass *oc, void *data)
 963 {
 964     MachineClass *mc = MACHINE_CLASS(oc);
 965
 966     mc->desc = "Sun4v platform, Niagara";
 967     mc->init = niagara_init;
 968     mc->max_cpus = 1; /* XXX for now */
 969     mc->default_boot_order = "c";
 970 }
 971
 972 static const TypeInfo niagara_type = {
 973     .name = MACHINE_TYPE_NAME("Niagara"),
 974     .parent = TYPE_MACHINE,
 975     .class_init = niagara_class_init,
 976 };
 977
 978 static void sun4u_register_types(void)
 979 {
 980     type_register_static(&ebus_info);
 981     type_register_static(&prom_info);
 982     type_register_static(&ram_info);
 983
 984     type_register_static(&sun4u_type);
 985     type_register_static(&sun4v_type);
 986     type_register_static(&niagara_type);
 987 }
 988
 989 type_init(sun4u_register_types)