hw/block/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "hw/hw.h"
  40 #include "hw/block/flash.h"
  41 #include "block/block.h"
  42 #include "qemu/timer.h"
  43 #include "qemu/bitops.h"
  44 #include "exec/address-spaces.h"
  45 #include "qemu/host-utils.h"
  46 #include "hw/sysbus.h"
  47
  48 #define PFLASH_BUG(fmt, ...) \
  49 do { \
  50     fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  51     exit(1); \
  52 } while(0)
  53
  54 /* #define PFLASH_DEBUG */
  55 #ifdef PFLASH_DEBUG
  56 #define DPRINTF(fmt, ...)                                   \
  57 do {                                                        \
  58     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  59 } while (0)
  60 #else
  61 #define DPRINTF(fmt, ...) do { } while (0)
  62 #endif
  63
  64 #define TYPE_CFI_PFLASH01 "cfi.pflash01"
  65 #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
  66
  67 struct pflash_t {
  68     /*< private >*/
  69     SysBusDevice parent_obj;
  70     /*< public >*/
  71
  72     BlockDriverState *bs;
  73     uint32_t nb_blocs;
  74     uint64_t sector_len;
  75     uint8_t bank_width;
  76     uint8_t device_width; /* If 0, device width not specified. */
  77     uint8_t be;
  78     uint8_t wcycle; /* if 0, the flash is read normally */
  79     int ro;
  80     uint8_t cmd;
  81     uint8_t status;
  82     uint16_t ident0;
  83     uint16_t ident1;
  84     uint16_t ident2;
  85     uint16_t ident3;
  86     uint8_t cfi_len;
  87     uint8_t cfi_table[0x52];
  88     uint64_t counter;
  89     unsigned int writeblock_size;
  90     QEMUTimer *timer;
  91     MemoryRegion mem;
  92     char *name;
  93     void *storage;
  94 };
  95
  96 static const VMStateDescription vmstate_pflash = {
  97     .name = "pflash_cfi01",
  98     .version_id = 1,
  99     .minimum_version_id = 1,
 100     .fields = (VMStateField[]) {
 101         VMSTATE_UINT8(wcycle, pflash_t),
 102         VMSTATE_UINT8(cmd, pflash_t),
 103         VMSTATE_UINT8(status, pflash_t),
 104         VMSTATE_UINT64(counter, pflash_t),
 105         VMSTATE_END_OF_LIST()
 106     }
 107 };
 108
 109 static void pflash_timer (void *opaque)
 110 {
 111     pflash_t *pfl = opaque;
 112
 113     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
 114     /* Reset flash */
 115     pfl->status ^= 0x80;
 116     memory_region_rom_device_set_romd(&pfl->mem, true);
 117     pfl->wcycle = 0;
 118     pfl->cmd = 0;
 119 }
 120
 121 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
 122                              int width, int be)
 123 {
 124     hwaddr boff;
 125     uint32_t ret;
 126     uint8_t *p;
 127
 128     ret = -1;
 129     boff = offset & 0xFF; /* why this here ?? */
 130
 131     if (pfl->bank_width == 2) {
 132         boff = boff >> 1;
 133     } else if (pfl->bank_width == 4) {
 134         boff = boff >> 2;
 135     }
 136
 137 #if 0
 138     DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
 139             __func__, offset, pfl->cmd, width);
 140 #endif
 141     switch (pfl->cmd) {
 142     default:
 143         /* This should never happen : reset state & treat it as a read */
 144         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 145         pfl->wcycle = 0;
 146         pfl->cmd = 0;
 147         /* fall through to read code */
 148     case 0x00:
 149         /* Flash area read */
 150         p = pfl->storage;
 151         switch (width) {
 152         case 1:
 153             ret = p[offset];
 154             DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
 155                     __func__, offset, ret);
 156             break;
 157         case 2:
 158             if (be) {
 159                 ret = p[offset] << 8;
 160                 ret |= p[offset + 1];
 161             } else {
 162                 ret = p[offset];
 163                 ret |= p[offset + 1] << 8;
 164             }
 165             DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
 166                     __func__, offset, ret);
 167             break;
 168         case 4:
 169             if (be) {
 170                 ret = p[offset] << 24;
 171                 ret |= p[offset + 1] << 16;
 172                 ret |= p[offset + 2] << 8;
 173                 ret |= p[offset + 3];
 174             } else {
 175                 ret = p[offset];
 176                 ret |= p[offset + 1] << 8;
 177                 ret |= p[offset + 2] << 16;
 178                 ret |= p[offset + 3] << 24;
 179             }
 180             DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
 181                     __func__, offset, ret);
 182             break;
 183         default:
 184             DPRINTF("BUG in %s\n", __func__);
 185         }
 186
 187         break;
 188     case 0x10: /* Single byte program */
 189     case 0x20: /* Block erase */
 190     case 0x28: /* Block erase */
 191     case 0x40: /* single byte program */
 192     case 0x50: /* Clear status register */
 193     case 0x60: /* Block /un)lock */
 194     case 0x70: /* Status Register */
 195     case 0xe8: /* Write block */
 196         /* Status register read.  Return status from each device in
 197          * bank.
 198          */
 199         ret = pfl->status;
 200         if (pfl->device_width && width > pfl->device_width) {
 201             int shift = pfl->device_width * 8;
 202             while (shift + pfl->device_width * 8 <= width * 8) {
 203                 ret |= pfl->status << shift;
 204                 shift += pfl->device_width * 8;
 205             }
 206         } else if (!pfl->device_width && width > 2) {
 207             /* Handle 32 bit flash cases where device width is not
 208              * set. (Existing behavior before device width added.)
 209              */
 210             ret |= pfl->status << 16;
 211         }
 212         DPRINTF("%s: status %x\n", __func__, ret);
 213         break;
 214     case 0x90:
 215         switch (boff) {
 216         case 0:
 217             ret = pfl->ident0 << 8 | pfl->ident1;
 218             DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
 219             break;
 220         case 1:
 221             ret = pfl->ident2 << 8 | pfl->ident3;
 222             DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
 223             break;
 224         default:
 225             DPRINTF("%s: Read Device Information boff=%x\n", __func__,
 226                     (unsigned)boff);
 227             ret = 0;
 228             break;
 229         }
 230         break;
 231     case 0x98: /* Query mode */
 232         if (boff > pfl->cfi_len)
 233             ret = 0;
 234         else
 235             ret = pfl->cfi_table[boff];
 236         break;
 237     }
 238     return ret;
 239 }
 240
 241 /* update flash content on disk */
 242 static void pflash_update(pflash_t *pfl, int offset,
 243                           int size)
 244 {
 245     int offset_end;
 246     if (pfl->bs) {
 247         offset_end = offset + size;
 248         /* round to sectors */
 249         offset = offset >> 9;
 250         offset_end = (offset_end + 511) >> 9;
 251         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 252                    offset_end - offset);
 253     }
 254 }
 255
 256 static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
 257                                      uint32_t value, int width, int be)
 258 {
 259     uint8_t *p = pfl->storage;
 260
 261     DPRINTF("%s: block write offset " TARGET_FMT_plx
 262             " value %x counter %016" PRIx64 "\n",
 263             __func__, offset, value, pfl->counter);
 264     switch (width) {
 265     case 1:
 266         p[offset] = value;
 267         break;
 268     case 2:
 269         if (be) {
 270             p[offset] = value >> 8;
 271             p[offset + 1] = value;
 272         } else {
 273             p[offset] = value;
 274             p[offset + 1] = value >> 8;
 275         }
 276         break;
 277     case 4:
 278         if (be) {
 279             p[offset] = value >> 24;
 280             p[offset + 1] = value >> 16;
 281             p[offset + 2] = value >> 8;
 282             p[offset + 3] = value;
 283         } else {
 284             p[offset] = value;
 285             p[offset + 1] = value >> 8;
 286             p[offset + 2] = value >> 16;
 287             p[offset + 3] = value >> 24;
 288         }
 289         break;
 290     }
 291
 292 }
 293
 294 static void pflash_write(pflash_t *pfl, hwaddr offset,
 295                          uint32_t value, int width, int be)
 296 {
 297     uint8_t *p;
 298     uint8_t cmd;
 299
 300     cmd = value;
 301
 302     DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
 303             __func__, offset, value, width, pfl->wcycle);
 304
 305     if (!pfl->wcycle) {
 306         /* Set the device in I/O access mode */
 307         memory_region_rom_device_set_romd(&pfl->mem, false);
 308     }
 309
 310     switch (pfl->wcycle) {
 311     case 0:
 312         /* read mode */
 313         switch (cmd) {
 314         case 0x00: /* ??? */
 315             goto reset_flash;
 316         case 0x10: /* Single Byte Program */
 317         case 0x40: /* Single Byte Program */
 318             DPRINTF("%s: Single Byte Program\n", __func__);
 319             break;
 320         case 0x20: /* Block erase */
 321             p = pfl->storage;
 322             offset &= ~(pfl->sector_len - 1);
 323
 324             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
 325                     __func__, offset, (unsigned)pfl->sector_len);
 326
 327             if (!pfl->ro) {
 328                 memset(p + offset, 0xff, pfl->sector_len);
 329                 pflash_update(pfl, offset, pfl->sector_len);
 330             } else {
 331                 pfl->status |= 0x20; /* Block erase error */
 332             }
 333             pfl->status |= 0x80; /* Ready! */
 334             break;
 335         case 0x50: /* Clear status bits */
 336             DPRINTF("%s: Clear status bits\n", __func__);
 337             pfl->status = 0x0;
 338             goto reset_flash;
 339         case 0x60: /* Block (un)lock */
 340             DPRINTF("%s: Block unlock\n", __func__);
 341             break;
 342         case 0x70: /* Status Register */
 343             DPRINTF("%s: Read status register\n", __func__);
 344             pfl->cmd = cmd;
 345             return;
 346         case 0x90: /* Read Device ID */
 347             DPRINTF("%s: Read Device information\n", __func__);
 348             pfl->cmd = cmd;
 349             return;
 350         case 0x98: /* CFI query */
 351             DPRINTF("%s: CFI query\n", __func__);
 352             break;
 353         case 0xe8: /* Write to buffer */
 354             DPRINTF("%s: Write to buffer\n", __func__);
 355             pfl->status |= 0x80; /* Ready! */
 356             break;
 357         case 0xf0: /* Probe for AMD flash */
 358             DPRINTF("%s: Probe for AMD flash\n", __func__);
 359             goto reset_flash;
 360         case 0xff: /* Read array mode */
 361             DPRINTF("%s: Read array mode\n", __func__);
 362             goto reset_flash;
 363         default:
 364             goto error_flash;
 365         }
 366         pfl->wcycle++;
 367         pfl->cmd = cmd;
 368         break;
 369     case 1:
 370         switch (pfl->cmd) {
 371         case 0x10: /* Single Byte Program */
 372         case 0x40: /* Single Byte Program */
 373             DPRINTF("%s: Single Byte Program\n", __func__);
 374             if (!pfl->ro) {
 375                 pflash_data_write(pfl, offset, value, width, be);
 376                 pflash_update(pfl, offset, width);
 377             } else {
 378                 pfl->status |= 0x10; /* Programming error */
 379             }
 380             pfl->status |= 0x80; /* Ready! */
 381             pfl->wcycle = 0;
 382         break;
 383         case 0x20: /* Block erase */
 384         case 0x28:
 385             if (cmd == 0xd0) { /* confirm */
 386                 pfl->wcycle = 0;
 387                 pfl->status |= 0x80;
 388             } else if (cmd == 0xff) { /* read array mode */
 389                 goto reset_flash;
 390             } else
 391                 goto error_flash;
 392
 393             break;
 394         case 0xe8:
 395             /* Mask writeblock size based on device width, or bank width if
 396              * device width not specified.
 397              */
 398             if (pfl->device_width) {
 399                 value = extract32(value, 0, pfl->device_width * 8);
 400             } else {
 401                 value = extract32(value, 0, pfl->bank_width * 8);
 402             }
 403             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 404             pfl->counter = value;
 405             pfl->wcycle++;
 406             break;
 407         case 0x60:
 408             if (cmd == 0xd0) {
 409                 pfl->wcycle = 0;
 410                 pfl->status |= 0x80;
 411             } else if (cmd == 0x01) {
 412                 pfl->wcycle = 0;
 413                 pfl->status |= 0x80;
 414             } else if (cmd == 0xff) {
 415                 goto reset_flash;
 416             } else {
 417                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 418                 goto reset_flash;
 419             }
 420             break;
 421         case 0x98:
 422             if (cmd == 0xff) {
 423                 goto reset_flash;
 424             } else {
 425                 DPRINTF("%s: leaving query mode\n", __func__);
 426             }
 427             break;
 428         default:
 429             goto error_flash;
 430         }
 431         break;
 432     case 2:
 433         switch (pfl->cmd) {
 434         case 0xe8: /* Block write */
 435             if (!pfl->ro) {
 436                 pflash_data_write(pfl, offset, value, width, be);
 437             } else {
 438                 pfl->status |= 0x10; /* Programming error */
 439             }
 440
 441             pfl->status |= 0x80;
 442
 443             if (!pfl->counter) {
 444                 hwaddr mask = pfl->writeblock_size - 1;
 445                 mask = ~mask;
 446
 447                 DPRINTF("%s: block write finished\n", __func__);
 448                 pfl->wcycle++;
 449                 if (!pfl->ro) {
 450                     /* Flush the entire write buffer onto backing storage.  */
 451                     pflash_update(pfl, offset & mask, pfl->writeblock_size);
 452                 } else {
 453                     pfl->status |= 0x10; /* Programming error */
 454                 }
 455             }
 456
 457             pfl->counter--;
 458             break;
 459         default:
 460             goto error_flash;
 461         }
 462         break;
 463     case 3: /* Confirm mode */
 464         switch (pfl->cmd) {
 465         case 0xe8: /* Block write */
 466             if (cmd == 0xd0) {
 467                 pfl->wcycle = 0;
 468                 pfl->status |= 0x80;
 469             } else {
 470                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 471                 PFLASH_BUG("Write block confirm");
 472                 goto reset_flash;
 473             }
 474             break;
 475         default:
 476             goto error_flash;
 477         }
 478         break;
 479     default:
 480         /* Should never happen */
 481         DPRINTF("%s: invalid write state\n",  __func__);
 482         goto reset_flash;
 483     }
 484     return;
 485
 486  error_flash:
 487     qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
 488                   "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
 489                   "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
 490
 491  reset_flash:
 492     memory_region_rom_device_set_romd(&pfl->mem, true);
 493
 494     pfl->wcycle = 0;
 495     pfl->cmd = 0;
 496 }
 497
 498
 499 static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
 500 {
 501     return pflash_read(opaque, addr, 1, 1);
 502 }
 503
 504 static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
 505 {
 506     return pflash_read(opaque, addr, 1, 0);
 507 }
 508
 509 static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
 510 {
 511     pflash_t *pfl = opaque;
 512
 513     return pflash_read(pfl, addr, 2, 1);
 514 }
 515
 516 static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
 517 {
 518     pflash_t *pfl = opaque;
 519
 520     return pflash_read(pfl, addr, 2, 0);
 521 }
 522
 523 static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
 524 {
 525     pflash_t *pfl = opaque;
 526
 527     return pflash_read(pfl, addr, 4, 1);
 528 }
 529
 530 static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
 531 {
 532     pflash_t *pfl = opaque;
 533
 534     return pflash_read(pfl, addr, 4, 0);
 535 }
 536
 537 static void pflash_writeb_be(void *opaque, hwaddr addr,
 538                              uint32_t value)
 539 {
 540     pflash_write(opaque, addr, value, 1, 1);
 541 }
 542
 543 static void pflash_writeb_le(void *opaque, hwaddr addr,
 544                              uint32_t value)
 545 {
 546     pflash_write(opaque, addr, value, 1, 0);
 547 }
 548
 549 static void pflash_writew_be(void *opaque, hwaddr addr,
 550                              uint32_t value)
 551 {
 552     pflash_t *pfl = opaque;
 553
 554     pflash_write(pfl, addr, value, 2, 1);
 555 }
 556
 557 static void pflash_writew_le(void *opaque, hwaddr addr,
 558                              uint32_t value)
 559 {
 560     pflash_t *pfl = opaque;
 561
 562     pflash_write(pfl, addr, value, 2, 0);
 563 }
 564
 565 static void pflash_writel_be(void *opaque, hwaddr addr,
 566                              uint32_t value)
 567 {
 568     pflash_t *pfl = opaque;
 569
 570     pflash_write(pfl, addr, value, 4, 1);
 571 }
 572
 573 static void pflash_writel_le(void *opaque, hwaddr addr,
 574                              uint32_t value)
 575 {
 576     pflash_t *pfl = opaque;
 577
 578     pflash_write(pfl, addr, value, 4, 0);
 579 }
 580
 581 static const MemoryRegionOps pflash_cfi01_ops_be = {
 582     .old_mmio = {
 583         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 584         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 585     },
 586     .endianness = DEVICE_NATIVE_ENDIAN,
 587 };
 588
 589 static const MemoryRegionOps pflash_cfi01_ops_le = {
 590     .old_mmio = {
 591         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 592         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 593     },
 594     .endianness = DEVICE_NATIVE_ENDIAN,
 595 };
 596
 597 static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
 598 {
 599     pflash_t *pfl = CFI_PFLASH01(dev);
 600     uint64_t total_len;
 601     int ret;
 602
 603     total_len = pfl->sector_len * pfl->nb_blocs;
 604
 605     /* XXX: to be fixed */
 606 #if 0
 607     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 608         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 609         return NULL;
 610 #endif
 611
 612     memory_region_init_rom_device(
 613         &pfl->mem, OBJECT(dev),
 614         pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
 615         pfl->name, total_len);
 616     vmstate_register_ram(&pfl->mem, DEVICE(pfl));
 617     pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
 618     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 619
 620     if (pfl->bs) {
 621         /* read the initial flash content */
 622         ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 623
 624         if (ret < 0) {
 625             vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
 626             memory_region_destroy(&pfl->mem);
 627             error_setg(errp, "failed to read the initial flash content");
 628             return;
 629         }
 630     }
 631
 632     if (pfl->bs) {
 633         pfl->ro = bdrv_is_read_only(pfl->bs);
 634     } else {
 635         pfl->ro = 0;
 636     }
 637
 638     pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 639     pfl->wcycle = 0;
 640     pfl->cmd = 0;
 641     pfl->status = 0;
 642     /* Hardcoded CFI table */
 643     pfl->cfi_len = 0x52;
 644     /* Standard "QRY" string */
 645     pfl->cfi_table[0x10] = 'Q';
 646     pfl->cfi_table[0x11] = 'R';
 647     pfl->cfi_table[0x12] = 'Y';
 648     /* Command set (Intel) */
 649     pfl->cfi_table[0x13] = 0x01;
 650     pfl->cfi_table[0x14] = 0x00;
 651     /* Primary extended table address (none) */
 652     pfl->cfi_table[0x15] = 0x31;
 653     pfl->cfi_table[0x16] = 0x00;
 654     /* Alternate command set (none) */
 655     pfl->cfi_table[0x17] = 0x00;
 656     pfl->cfi_table[0x18] = 0x00;
 657     /* Alternate extended table (none) */
 658     pfl->cfi_table[0x19] = 0x00;
 659     pfl->cfi_table[0x1A] = 0x00;
 660     /* Vcc min */
 661     pfl->cfi_table[0x1B] = 0x45;
 662     /* Vcc max */
 663     pfl->cfi_table[0x1C] = 0x55;
 664     /* Vpp min (no Vpp pin) */
 665     pfl->cfi_table[0x1D] = 0x00;
 666     /* Vpp max (no Vpp pin) */
 667     pfl->cfi_table[0x1E] = 0x00;
 668     /* Reserved */
 669     pfl->cfi_table[0x1F] = 0x07;
 670     /* Timeout for min size buffer write */
 671     pfl->cfi_table[0x20] = 0x07;
 672     /* Typical timeout for block erase */
 673     pfl->cfi_table[0x21] = 0x0a;
 674     /* Typical timeout for full chip erase (4096 ms) */
 675     pfl->cfi_table[0x22] = 0x00;
 676     /* Reserved */
 677     pfl->cfi_table[0x23] = 0x04;
 678     /* Max timeout for buffer write */
 679     pfl->cfi_table[0x24] = 0x04;
 680     /* Max timeout for block erase */
 681     pfl->cfi_table[0x25] = 0x04;
 682     /* Max timeout for chip erase */
 683     pfl->cfi_table[0x26] = 0x00;
 684     /* Device size */
 685     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 686     /* Flash device interface (8 & 16 bits) */
 687     pfl->cfi_table[0x28] = 0x02;
 688     pfl->cfi_table[0x29] = 0x00;
 689     /* Max number of bytes in multi-bytes write */
 690     if (pfl->bank_width == 1) {
 691         pfl->cfi_table[0x2A] = 0x08;
 692     } else {
 693         pfl->cfi_table[0x2A] = 0x0B;
 694     }
 695     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 696
 697     pfl->cfi_table[0x2B] = 0x00;
 698     /* Number of erase block regions (uniform) */
 699     pfl->cfi_table[0x2C] = 0x01;
 700     /* Erase block region 1 */
 701     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 702     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 703     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 704     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 705
 706     /* Extended */
 707     pfl->cfi_table[0x31] = 'P';
 708     pfl->cfi_table[0x32] = 'R';
 709     pfl->cfi_table[0x33] = 'I';
 710
 711     pfl->cfi_table[0x34] = '1';
 712     pfl->cfi_table[0x35] = '0';
 713
 714     pfl->cfi_table[0x36] = 0x00;
 715     pfl->cfi_table[0x37] = 0x00;
 716     pfl->cfi_table[0x38] = 0x00;
 717     pfl->cfi_table[0x39] = 0x00;
 718
 719     pfl->cfi_table[0x3a] = 0x00;
 720
 721     pfl->cfi_table[0x3b] = 0x00;
 722     pfl->cfi_table[0x3c] = 0x00;
 723
 724     pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
 725 }
 726
 727 static Property pflash_cfi01_properties[] = {
 728     DEFINE_PROP_DRIVE("drive", struct pflash_t, bs),
 729     DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
 730     DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0),
 731     DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0),
 732     DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0),
 733     DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
 734     DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
 735     DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
 736     DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
 737     DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
 738     DEFINE_PROP_STRING("name", struct pflash_t, name),
 739     DEFINE_PROP_END_OF_LIST(),
 740 };
 741
 742 static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
 743 {
 744     DeviceClass *dc = DEVICE_CLASS(klass);
 745
 746     dc->realize = pflash_cfi01_realize;
 747     dc->props = pflash_cfi01_properties;
 748     dc->vmsd = &vmstate_pflash;
 749     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 750 }
 751
 752
 753 static const TypeInfo pflash_cfi01_info = {
 754     .name           = TYPE_CFI_PFLASH01,
 755     .parent         = TYPE_SYS_BUS_DEVICE,
 756     .instance_size  = sizeof(struct pflash_t),
 757     .class_init     = pflash_cfi01_class_init,
 758 };
 759
 760 static void pflash_cfi01_register_types(void)
 761 {
 762     type_register_static(&pflash_cfi01_info);
 763 }
 764
 765 type_init(pflash_cfi01_register_types)
 766
 767 pflash_t *pflash_cfi01_register(hwaddr base,
 768                                 DeviceState *qdev, const char *name,
 769                                 hwaddr size,
 770                                 BlockDriverState *bs,
 771                                 uint32_t sector_len, int nb_blocs,
 772                                 int bank_width, uint16_t id0, uint16_t id1,
 773                                 uint16_t id2, uint16_t id3, int be)
 774 {
 775     DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01);
 776
 777     if (bs && qdev_prop_set_drive(dev, "drive", bs)) {
 778         abort();
 779     }
 780     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
 781     qdev_prop_set_uint64(dev, "sector-length", sector_len);
 782     qdev_prop_set_uint8(dev, "width", bank_width);
 783     qdev_prop_set_uint8(dev, "big-endian", !!be);
 784     qdev_prop_set_uint16(dev, "id0", id0);
 785     qdev_prop_set_uint16(dev, "id1", id1);
 786     qdev_prop_set_uint16(dev, "id2", id2);
 787     qdev_prop_set_uint16(dev, "id3", id3);
 788     qdev_prop_set_string(dev, "name", name);
 789     qdev_init_nofail(dev);
 790
 791     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 792     return CFI_PFLASH01(dev);
 793 }
 794
 795 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
 796 {
 797     return &fl->mem;
 798 }