4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "disas/disas.h"
26 #include "qemu-common.h"
28 #include "qemu/bitops.h"
29 #include "exec/cpu_ldst.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
34 #include "trace-tcg.h"
38 #define OPENRISC_DISAS
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 # define LOG_DIS(...) do { } while (0)
46 typedef struct DisasContext
{
48 target_ulong pc
, ppc
, npc
;
49 uint32_t tb_flags
, synced_flags
, flags
;
52 int singlestep_enabled
;
53 uint32_t delayed_branch
;
56 static TCGv_env cpu_env
;
58 static TCGv cpu_R
[32];
60 static TCGv jmp_pc
; /* l.jr/l.jalr temp pc */
63 static TCGv_i32 env_btaken
; /* bf/bnf , F flag taken */
64 static TCGv_i32 fpcsr
;
65 static TCGv machi
, maclo
;
66 static TCGv fpmaddhi
, fpmaddlo
;
67 static TCGv_i32 env_flags
;
68 #include "exec/gen-icount.h"
70 void openrisc_translate_init(void)
72 static const char * const regnames
[] = {
73 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
74 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
75 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
76 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
80 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
81 tcg_ctx
.tcg_env
= cpu_env
;
82 cpu_sr
= tcg_global_mem_new(cpu_env
,
83 offsetof(CPUOpenRISCState
, sr
), "sr");
84 env_flags
= tcg_global_mem_new_i32(cpu_env
,
85 offsetof(CPUOpenRISCState
, flags
),
87 cpu_pc
= tcg_global_mem_new(cpu_env
,
88 offsetof(CPUOpenRISCState
, pc
), "pc");
89 cpu_npc
= tcg_global_mem_new(cpu_env
,
90 offsetof(CPUOpenRISCState
, npc
), "npc");
91 cpu_ppc
= tcg_global_mem_new(cpu_env
,
92 offsetof(CPUOpenRISCState
, ppc
), "ppc");
93 jmp_pc
= tcg_global_mem_new(cpu_env
,
94 offsetof(CPUOpenRISCState
, jmp_pc
), "jmp_pc");
95 env_btaken
= tcg_global_mem_new_i32(cpu_env
,
96 offsetof(CPUOpenRISCState
, btaken
),
98 fpcsr
= tcg_global_mem_new_i32(cpu_env
,
99 offsetof(CPUOpenRISCState
, fpcsr
),
101 machi
= tcg_global_mem_new(cpu_env
,
102 offsetof(CPUOpenRISCState
, machi
),
104 maclo
= tcg_global_mem_new(cpu_env
,
105 offsetof(CPUOpenRISCState
, maclo
),
107 fpmaddhi
= tcg_global_mem_new(cpu_env
,
108 offsetof(CPUOpenRISCState
, fpmaddhi
),
110 fpmaddlo
= tcg_global_mem_new(cpu_env
,
111 offsetof(CPUOpenRISCState
, fpmaddlo
),
113 for (i
= 0; i
< 32; i
++) {
114 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
115 offsetof(CPUOpenRISCState
, gpr
[i
]),
120 /* Writeback SR_F translation space to execution space. */
121 static inline void wb_SR_F(void)
123 TCGLabel
*label
= gen_new_label();
124 tcg_gen_andi_tl(cpu_sr
, cpu_sr
, ~SR_F
);
125 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, label
);
126 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, SR_F
);
127 gen_set_label(label
);
130 static inline int zero_extend(unsigned int val
, int width
)
132 return val
& ((1 << width
) - 1);
135 static inline int sign_extend(unsigned int val
, int width
)
140 val
<<= TARGET_LONG_BITS
- width
;
143 sval
>>= TARGET_LONG_BITS
- width
;
147 static inline void gen_sync_flags(DisasContext
*dc
)
149 /* Sync the tb dependent flag between translate and runtime. */
150 if (dc
->tb_flags
!= dc
->synced_flags
) {
151 tcg_gen_movi_tl(env_flags
, dc
->tb_flags
);
152 dc
->synced_flags
= dc
->tb_flags
;
156 static void gen_exception(DisasContext
*dc
, unsigned int excp
)
158 TCGv_i32 tmp
= tcg_const_i32(excp
);
159 gen_helper_exception(cpu_env
, tmp
);
160 tcg_temp_free_i32(tmp
);
163 static void gen_illegal_exception(DisasContext
*dc
)
165 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
166 gen_exception(dc
, EXCP_ILLEGAL
);
167 dc
->is_jmp
= DISAS_UPDATE
;
170 /* not used yet, open it when we need or64. */
171 /*#ifdef TARGET_OPENRISC64
172 static void check_ob64s(DisasContext *dc)
174 if (!(dc->flags & CPUCFGR_OB64S)) {
175 gen_illegal_exception(dc);
179 static void check_of64s(DisasContext *dc)
181 if (!(dc->flags & CPUCFGR_OF64S)) {
182 gen_illegal_exception(dc);
186 static void check_ov64s(DisasContext *dc)
188 if (!(dc->flags & CPUCFGR_OV64S)) {
189 gen_illegal_exception(dc);
194 static inline bool use_goto_tb(DisasContext
*dc
, target_ulong dest
)
196 if (unlikely(dc
->singlestep_enabled
)) {
200 #ifndef CONFIG_USER_ONLY
201 return (dc
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
207 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
209 if (use_goto_tb(dc
, dest
)) {
210 tcg_gen_movi_tl(cpu_pc
, dest
);
212 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ n
);
214 tcg_gen_movi_tl(cpu_pc
, dest
);
215 if (dc
->singlestep_enabled
) {
216 gen_exception(dc
, EXCP_DEBUG
);
222 static void gen_jump(DisasContext
*dc
, uint32_t imm
, uint32_t reg
, uint32_t op0
)
225 /* N26, 26bits imm */
226 tmp_pc
= sign_extend((imm
<<2), 26) + dc
->pc
;
230 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
232 case 0x01: /* l.jal */
233 tcg_gen_movi_tl(cpu_R
[9], (dc
->pc
+ 8));
234 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
236 case 0x03: /* l.bnf */
237 case 0x04: /* l.bf */
239 TCGLabel
*lab
= gen_new_label();
240 TCGv sr_f
= tcg_temp_new();
241 tcg_gen_movi_tl(jmp_pc
, dc
->pc
+8);
242 tcg_gen_andi_tl(sr_f
, cpu_sr
, SR_F
);
243 tcg_gen_brcondi_i32(op0
== 0x03 ? TCG_COND_EQ
: TCG_COND_NE
,
245 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
250 case 0x11: /* l.jr */
251 tcg_gen_mov_tl(jmp_pc
, cpu_R
[reg
]);
253 case 0x12: /* l.jalr */
254 tcg_gen_movi_tl(cpu_R
[9], (dc
->pc
+ 8));
255 tcg_gen_mov_tl(jmp_pc
, cpu_R
[reg
]);
258 gen_illegal_exception(dc
);
262 dc
->delayed_branch
= 2;
263 dc
->tb_flags
|= D_FLAG
;
268 static void dec_calc(DisasContext
*dc
, uint32_t insn
)
270 uint32_t op0
, op1
, op2
;
272 op0
= extract32(insn
, 0, 4);
273 op1
= extract32(insn
, 8, 2);
274 op2
= extract32(insn
, 6, 2);
275 ra
= extract32(insn
, 16, 5);
276 rb
= extract32(insn
, 11, 5);
277 rd
= extract32(insn
, 21, 5);
282 case 0x00: /* l.add */
283 LOG_DIS("l.add r%d, r%d, r%d\n", rd
, ra
, rb
);
285 TCGLabel
*lab
= gen_new_label();
286 TCGv_i64 ta
= tcg_temp_new_i64();
287 TCGv_i64 tb
= tcg_temp_new_i64();
288 TCGv_i64 td
= tcg_temp_local_new_i64();
289 TCGv_i32 res
= tcg_temp_local_new_i32();
290 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
291 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
292 tcg_gen_extu_i32_i64(tb
, cpu_R
[rb
]);
293 tcg_gen_add_i64(td
, ta
, tb
);
294 tcg_gen_extrl_i64_i32(res
, td
);
295 tcg_gen_shri_i64(td
, td
, 31);
296 tcg_gen_andi_i64(td
, td
, 0x3);
297 /* Jump to lab when no overflow. */
298 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
299 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
300 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
301 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
302 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
303 gen_exception(dc
, EXCP_RANGE
);
305 tcg_gen_mov_i32(cpu_R
[rd
], res
);
306 tcg_temp_free_i64(ta
);
307 tcg_temp_free_i64(tb
);
308 tcg_temp_free_i64(td
);
309 tcg_temp_free_i32(res
);
310 tcg_temp_free_i32(sr_ove
);
314 gen_illegal_exception(dc
);
319 case 0x0001: /* l.addc */
322 LOG_DIS("l.addc r%d, r%d, r%d\n", rd
, ra
, rb
);
324 TCGLabel
*lab
= gen_new_label();
325 TCGv_i64 ta
= tcg_temp_new_i64();
326 TCGv_i64 tb
= tcg_temp_new_i64();
327 TCGv_i64 tcy
= tcg_temp_local_new_i64();
328 TCGv_i64 td
= tcg_temp_local_new_i64();
329 TCGv_i32 res
= tcg_temp_local_new_i32();
330 TCGv_i32 sr_cy
= tcg_temp_local_new_i32();
331 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
332 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
333 tcg_gen_extu_i32_i64(tb
, cpu_R
[rb
]);
334 tcg_gen_andi_i32(sr_cy
, cpu_sr
, SR_CY
);
335 tcg_gen_extu_i32_i64(tcy
, sr_cy
);
336 tcg_gen_shri_i64(tcy
, tcy
, 10);
337 tcg_gen_add_i64(td
, ta
, tb
);
338 tcg_gen_add_i64(td
, td
, tcy
);
339 tcg_gen_extrl_i64_i32(res
, td
);
340 tcg_gen_shri_i64(td
, td
, 32);
341 tcg_gen_andi_i64(td
, td
, 0x3);
342 /* Jump to lab when no overflow. */
343 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
344 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
345 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
346 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
347 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
348 gen_exception(dc
, EXCP_RANGE
);
350 tcg_gen_mov_i32(cpu_R
[rd
], res
);
351 tcg_temp_free_i64(ta
);
352 tcg_temp_free_i64(tb
);
353 tcg_temp_free_i64(tcy
);
354 tcg_temp_free_i64(td
);
355 tcg_temp_free_i32(res
);
356 tcg_temp_free_i32(sr_cy
);
357 tcg_temp_free_i32(sr_ove
);
361 gen_illegal_exception(dc
);
366 case 0x0002: /* l.sub */
369 LOG_DIS("l.sub r%d, r%d, r%d\n", rd
, ra
, rb
);
371 TCGLabel
*lab
= gen_new_label();
372 TCGv_i64 ta
= tcg_temp_new_i64();
373 TCGv_i64 tb
= tcg_temp_new_i64();
374 TCGv_i64 td
= tcg_temp_local_new_i64();
375 TCGv_i32 res
= tcg_temp_local_new_i32();
376 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
378 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
379 tcg_gen_extu_i32_i64(tb
, cpu_R
[rb
]);
380 tcg_gen_sub_i64(td
, ta
, tb
);
381 tcg_gen_extrl_i64_i32(res
, td
);
382 tcg_gen_shri_i64(td
, td
, 31);
383 tcg_gen_andi_i64(td
, td
, 0x3);
384 /* Jump to lab when no overflow. */
385 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
386 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
387 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
388 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
389 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
390 gen_exception(dc
, EXCP_RANGE
);
392 tcg_gen_mov_i32(cpu_R
[rd
], res
);
393 tcg_temp_free_i64(ta
);
394 tcg_temp_free_i64(tb
);
395 tcg_temp_free_i64(td
);
396 tcg_temp_free_i32(res
);
397 tcg_temp_free_i32(sr_ove
);
401 gen_illegal_exception(dc
);
406 case 0x0003: /* l.and */
409 LOG_DIS("l.and r%d, r%d, r%d\n", rd
, ra
, rb
);
410 tcg_gen_and_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
413 gen_illegal_exception(dc
);
418 case 0x0004: /* l.or */
421 LOG_DIS("l.or r%d, r%d, r%d\n", rd
, ra
, rb
);
422 tcg_gen_or_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
425 gen_illegal_exception(dc
);
432 case 0x00: /* l.xor */
433 LOG_DIS("l.xor r%d, r%d, r%d\n", rd
, ra
, rb
);
434 tcg_gen_xor_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
437 gen_illegal_exception(dc
);
444 case 0x03: /* l.mul */
445 LOG_DIS("l.mul r%d, r%d, r%d\n", rd
, ra
, rb
);
446 if (ra
!= 0 && rb
!= 0) {
447 gen_helper_mul32(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
449 tcg_gen_movi_tl(cpu_R
[rd
], 0x0);
453 gen_illegal_exception(dc
);
460 case 0x03: /* l.div */
461 LOG_DIS("l.div r%d, r%d, r%d\n", rd
, ra
, rb
);
463 TCGLabel
*lab0
= gen_new_label();
464 TCGLabel
*lab1
= gen_new_label();
465 TCGLabel
*lab2
= gen_new_label();
466 TCGLabel
*lab3
= gen_new_label();
467 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
469 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
470 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
471 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab0
);
472 gen_exception(dc
, EXCP_RANGE
);
475 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_R
[rb
],
477 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[ra
],
479 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[rb
],
482 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
483 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
484 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab3
);
485 gen_exception(dc
, EXCP_RANGE
);
487 tcg_gen_div_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
490 tcg_temp_free_i32(sr_ove
);
495 gen_illegal_exception(dc
);
502 case 0x03: /* l.divu */
503 LOG_DIS("l.divu r%d, r%d, r%d\n", rd
, ra
, rb
);
505 TCGLabel
*lab0
= gen_new_label();
506 TCGLabel
*lab1
= gen_new_label();
507 TCGLabel
*lab2
= gen_new_label();
508 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
510 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
511 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
512 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab0
);
513 gen_exception(dc
, EXCP_RANGE
);
516 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[rb
],
518 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
519 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
520 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab2
);
521 gen_exception(dc
, EXCP_RANGE
);
523 tcg_gen_divu_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
526 tcg_temp_free_i32(sr_ove
);
531 gen_illegal_exception(dc
);
538 case 0x03: /* l.mulu */
539 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd
, ra
, rb
);
540 if (rb
!= 0 && ra
!= 0) {
541 TCGv_i64 result
= tcg_temp_local_new_i64();
542 TCGv_i64 tra
= tcg_temp_local_new_i64();
543 TCGv_i64 trb
= tcg_temp_local_new_i64();
544 TCGv_i64 high
= tcg_temp_new_i64();
545 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
546 TCGLabel
*lab
= gen_new_label();
547 /* Calculate each result. */
548 tcg_gen_extu_i32_i64(tra
, cpu_R
[ra
]);
549 tcg_gen_extu_i32_i64(trb
, cpu_R
[rb
]);
550 tcg_gen_mul_i64(result
, tra
, trb
);
551 tcg_temp_free_i64(tra
);
552 tcg_temp_free_i64(trb
);
553 tcg_gen_shri_i64(high
, result
, TARGET_LONG_BITS
);
554 /* Overflow or not. */
555 tcg_gen_brcondi_i64(TCG_COND_EQ
, high
, 0x00000000, lab
);
556 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
557 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
558 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
559 gen_exception(dc
, EXCP_RANGE
);
561 tcg_temp_free_i64(high
);
562 tcg_gen_trunc_i64_tl(cpu_R
[rd
], result
);
563 tcg_temp_free_i64(result
);
564 tcg_temp_free_i32(sr_ove
);
566 tcg_gen_movi_tl(cpu_R
[rd
], 0);
571 gen_illegal_exception(dc
);
578 case 0x00: /* l.cmov */
579 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd
, ra
, rb
);
581 TCGLabel
*lab
= gen_new_label();
582 TCGv res
= tcg_temp_local_new();
583 TCGv sr_f
= tcg_temp_new();
584 tcg_gen_andi_tl(sr_f
, cpu_sr
, SR_F
);
585 tcg_gen_mov_tl(res
, cpu_R
[rb
]);
586 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_f
, SR_F
, lab
);
587 tcg_gen_mov_tl(res
, cpu_R
[ra
]);
589 tcg_gen_mov_tl(cpu_R
[rd
], res
);
596 gen_illegal_exception(dc
);
603 case 0x00: /* l.ff1 */
604 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd
, ra
, rb
);
605 gen_helper_ff1(cpu_R
[rd
], cpu_R
[ra
]);
607 case 0x01: /* l.fl1 */
608 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd
, ra
, rb
);
609 gen_helper_fl1(cpu_R
[rd
], cpu_R
[ra
]);
613 gen_illegal_exception(dc
);
622 case 0x00: /* l.sll */
623 LOG_DIS("l.sll r%d, r%d, r%d\n", rd
, ra
, rb
);
624 tcg_gen_shl_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
626 case 0x01: /* l.srl */
627 LOG_DIS("l.srl r%d, r%d, r%d\n", rd
, ra
, rb
);
628 tcg_gen_shr_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
630 case 0x02: /* l.sra */
631 LOG_DIS("l.sra r%d, r%d, r%d\n", rd
, ra
, rb
);
632 tcg_gen_sar_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
634 case 0x03: /* l.ror */
635 LOG_DIS("l.ror r%d, r%d, r%d\n", rd
, ra
, rb
);
636 tcg_gen_rotr_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
640 gen_illegal_exception(dc
);
646 gen_illegal_exception(dc
);
655 case 0x00: /* l.exths */
656 LOG_DIS("l.exths r%d, r%d\n", rd
, ra
);
657 tcg_gen_ext16s_tl(cpu_R
[rd
], cpu_R
[ra
]);
659 case 0x01: /* l.extbs */
660 LOG_DIS("l.extbs r%d, r%d\n", rd
, ra
);
661 tcg_gen_ext8s_tl(cpu_R
[rd
], cpu_R
[ra
]);
663 case 0x02: /* l.exthz */
664 LOG_DIS("l.exthz r%d, r%d\n", rd
, ra
);
665 tcg_gen_ext16u_tl(cpu_R
[rd
], cpu_R
[ra
]);
667 case 0x03: /* l.extbz */
668 LOG_DIS("l.extbz r%d, r%d\n", rd
, ra
);
669 tcg_gen_ext8u_tl(cpu_R
[rd
], cpu_R
[ra
]);
673 gen_illegal_exception(dc
);
679 gen_illegal_exception(dc
);
688 case 0x00: /* l.extws */
689 LOG_DIS("l.extws r%d, r%d\n", rd
, ra
);
690 tcg_gen_ext32s_tl(cpu_R
[rd
], cpu_R
[ra
]);
692 case 0x01: /* l.extwz */
693 LOG_DIS("l.extwz r%d, r%d\n", rd
, ra
);
694 tcg_gen_ext32u_tl(cpu_R
[rd
], cpu_R
[ra
]);
698 gen_illegal_exception(dc
);
704 gen_illegal_exception(dc
);
710 gen_illegal_exception(dc
);
715 static void dec_misc(DisasContext
*dc
, uint32_t insn
)
719 #ifdef OPENRISC_DISAS
722 uint32_t I16
, I5
, I11
, N26
, tmp
;
725 op0
= extract32(insn
, 26, 6);
726 op1
= extract32(insn
, 24, 2);
727 ra
= extract32(insn
, 16, 5);
728 rb
= extract32(insn
, 11, 5);
729 rd
= extract32(insn
, 21, 5);
730 #ifdef OPENRISC_DISAS
731 L6
= extract32(insn
, 5, 6);
732 K5
= extract32(insn
, 0, 5);
734 I16
= extract32(insn
, 0, 16);
735 I5
= extract32(insn
, 21, 5);
736 I11
= extract32(insn
, 0, 11);
737 N26
= extract32(insn
, 0, 26);
738 tmp
= (I5
<<11) + I11
;
742 LOG_DIS("l.j %d\n", N26
);
743 gen_jump(dc
, N26
, 0, op0
);
746 case 0x01: /* l.jal */
747 LOG_DIS("l.jal %d\n", N26
);
748 gen_jump(dc
, N26
, 0, op0
);
751 case 0x03: /* l.bnf */
752 LOG_DIS("l.bnf %d\n", N26
);
753 gen_jump(dc
, N26
, 0, op0
);
756 case 0x04: /* l.bf */
757 LOG_DIS("l.bf %d\n", N26
);
758 gen_jump(dc
, N26
, 0, op0
);
763 case 0x01: /* l.nop */
764 LOG_DIS("l.nop %d\n", I16
);
768 gen_illegal_exception(dc
);
773 case 0x11: /* l.jr */
774 LOG_DIS("l.jr r%d\n", rb
);
775 gen_jump(dc
, 0, rb
, op0
);
778 case 0x12: /* l.jalr */
779 LOG_DIS("l.jalr r%d\n", rb
);
780 gen_jump(dc
, 0, rb
, op0
);
783 case 0x13: /* l.maci */
784 LOG_DIS("l.maci %d, r%d, %d\n", I5
, ra
, I11
);
786 TCGv_i64 t1
= tcg_temp_new_i64();
787 TCGv_i64 t2
= tcg_temp_new_i64();
788 TCGv_i32 dst
= tcg_temp_new_i32();
789 TCGv ttmp
= tcg_const_tl(tmp
);
790 tcg_gen_mul_tl(dst
, cpu_R
[ra
], ttmp
);
791 tcg_gen_ext_i32_i64(t1
, dst
);
792 tcg_gen_concat_i32_i64(t2
, maclo
, machi
);
793 tcg_gen_add_i64(t2
, t2
, t1
);
794 tcg_gen_extrl_i64_i32(maclo
, t2
);
795 tcg_gen_shri_i64(t2
, t2
, 32);
796 tcg_gen_extrl_i64_i32(machi
, t2
);
797 tcg_temp_free_i32(dst
);
799 tcg_temp_free_i64(t1
);
800 tcg_temp_free_i64(t2
);
804 case 0x09: /* l.rfe */
807 #if defined(CONFIG_USER_ONLY)
810 if (dc
->mem_idx
== MMU_USER_IDX
) {
811 gen_illegal_exception(dc
);
814 gen_helper_rfe(cpu_env
);
815 dc
->is_jmp
= DISAS_UPDATE
;
820 case 0x1c: /* l.cust1 */
821 LOG_DIS("l.cust1\n");
824 case 0x1d: /* l.cust2 */
825 LOG_DIS("l.cust2\n");
828 case 0x1e: /* l.cust3 */
829 LOG_DIS("l.cust3\n");
832 case 0x1f: /* l.cust4 */
833 LOG_DIS("l.cust4\n");
836 case 0x3c: /* l.cust5 */
837 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd
, ra
, rb
, L6
, K5
);
840 case 0x3d: /* l.cust6 */
841 LOG_DIS("l.cust6\n");
844 case 0x3e: /* l.cust7 */
845 LOG_DIS("l.cust7\n");
848 case 0x3f: /* l.cust8 */
849 LOG_DIS("l.cust8\n");
852 /* not used yet, open it when we need or64. */
853 /*#ifdef TARGET_OPENRISC64
855 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
861 case 0x21: /* l.lwz */
862 LOG_DIS("l.lwz r%d, r%d, %d\n", rd
, ra
, I16
);
866 case 0x22: /* l.lws */
867 LOG_DIS("l.lws r%d, r%d, %d\n", rd
, ra
, I16
);
871 case 0x23: /* l.lbz */
872 LOG_DIS("l.lbz r%d, r%d, %d\n", rd
, ra
, I16
);
876 case 0x24: /* l.lbs */
877 LOG_DIS("l.lbs r%d, r%d, %d\n", rd
, ra
, I16
);
881 case 0x25: /* l.lhz */
882 LOG_DIS("l.lhz r%d, r%d, %d\n", rd
, ra
, I16
);
886 case 0x26: /* l.lhs */
887 LOG_DIS("l.lhs r%d, r%d, %d\n", rd
, ra
, I16
);
893 TCGv t0
= tcg_temp_new();
894 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
895 tcg_gen_qemu_ld_tl(cpu_R
[rd
], t0
, dc
->mem_idx
, mop
);
900 case 0x27: /* l.addi */
901 LOG_DIS("l.addi r%d, r%d, %d\n", rd
, ra
, I16
);
904 tcg_gen_mov_tl(cpu_R
[rd
], cpu_R
[ra
]);
906 TCGLabel
*lab
= gen_new_label();
907 TCGv_i64 ta
= tcg_temp_new_i64();
908 TCGv_i64 td
= tcg_temp_local_new_i64();
909 TCGv_i32 res
= tcg_temp_local_new_i32();
910 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
911 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
912 tcg_gen_addi_i64(td
, ta
, sign_extend(I16
, 16));
913 tcg_gen_extrl_i64_i32(res
, td
);
914 tcg_gen_shri_i64(td
, td
, 32);
915 tcg_gen_andi_i64(td
, td
, 0x3);
916 /* Jump to lab when no overflow. */
917 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
918 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
919 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
920 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
921 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
922 gen_exception(dc
, EXCP_RANGE
);
924 tcg_gen_mov_i32(cpu_R
[rd
], res
);
925 tcg_temp_free_i64(ta
);
926 tcg_temp_free_i64(td
);
927 tcg_temp_free_i32(res
);
928 tcg_temp_free_i32(sr_ove
);
933 case 0x28: /* l.addic */
934 LOG_DIS("l.addic r%d, r%d, %d\n", rd
, ra
, I16
);
936 TCGLabel
*lab
= gen_new_label();
937 TCGv_i64 ta
= tcg_temp_new_i64();
938 TCGv_i64 td
= tcg_temp_local_new_i64();
939 TCGv_i64 tcy
= tcg_temp_local_new_i64();
940 TCGv_i32 res
= tcg_temp_local_new_i32();
941 TCGv_i32 sr_cy
= tcg_temp_local_new_i32();
942 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
943 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
944 tcg_gen_andi_i32(sr_cy
, cpu_sr
, SR_CY
);
945 tcg_gen_shri_i32(sr_cy
, sr_cy
, 10);
946 tcg_gen_extu_i32_i64(tcy
, sr_cy
);
947 tcg_gen_addi_i64(td
, ta
, sign_extend(I16
, 16));
948 tcg_gen_add_i64(td
, td
, tcy
);
949 tcg_gen_extrl_i64_i32(res
, td
);
950 tcg_gen_shri_i64(td
, td
, 32);
951 tcg_gen_andi_i64(td
, td
, 0x3);
952 /* Jump to lab when no overflow. */
953 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
954 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
955 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
956 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
957 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
958 gen_exception(dc
, EXCP_RANGE
);
960 tcg_gen_mov_i32(cpu_R
[rd
], res
);
961 tcg_temp_free_i64(ta
);
962 tcg_temp_free_i64(td
);
963 tcg_temp_free_i64(tcy
);
964 tcg_temp_free_i32(res
);
965 tcg_temp_free_i32(sr_cy
);
966 tcg_temp_free_i32(sr_ove
);
970 case 0x29: /* l.andi */
971 LOG_DIS("l.andi r%d, r%d, %d\n", rd
, ra
, I16
);
972 tcg_gen_andi_tl(cpu_R
[rd
], cpu_R
[ra
], zero_extend(I16
, 16));
975 case 0x2a: /* l.ori */
976 LOG_DIS("l.ori r%d, r%d, %d\n", rd
, ra
, I16
);
977 tcg_gen_ori_tl(cpu_R
[rd
], cpu_R
[ra
], zero_extend(I16
, 16));
980 case 0x2b: /* l.xori */
981 LOG_DIS("l.xori r%d, r%d, %d\n", rd
, ra
, I16
);
982 tcg_gen_xori_tl(cpu_R
[rd
], cpu_R
[ra
], sign_extend(I16
, 16));
985 case 0x2c: /* l.muli */
986 LOG_DIS("l.muli r%d, r%d, %d\n", rd
, ra
, I16
);
987 if (ra
!= 0 && I16
!= 0) {
988 TCGv_i32 im
= tcg_const_i32(I16
);
989 gen_helper_mul32(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], im
);
990 tcg_temp_free_i32(im
);
992 tcg_gen_movi_tl(cpu_R
[rd
], 0x0);
996 case 0x2d: /* l.mfspr */
997 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd
, ra
, I16
);
999 #if defined(CONFIG_USER_ONLY)
1002 TCGv_i32 ti
= tcg_const_i32(I16
);
1003 if (dc
->mem_idx
== MMU_USER_IDX
) {
1004 gen_illegal_exception(dc
);
1007 gen_helper_mfspr(cpu_R
[rd
], cpu_env
, cpu_R
[rd
], cpu_R
[ra
], ti
);
1008 tcg_temp_free_i32(ti
);
1013 case 0x30: /* l.mtspr */
1014 LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1016 #if defined(CONFIG_USER_ONLY)
1019 TCGv_i32 im
= tcg_const_i32(tmp
);
1020 if (dc
->mem_idx
== MMU_USER_IDX
) {
1021 gen_illegal_exception(dc
);
1024 gen_helper_mtspr(cpu_env
, cpu_R
[ra
], cpu_R
[rb
], im
);
1025 tcg_temp_free_i32(im
);
1030 /* not used yet, open it when we need or64. */
1031 /*#ifdef TARGET_OPENRISC64
1033 LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1039 case 0x35: /* l.sw */
1040 LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1044 case 0x36: /* l.sb */
1045 LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1049 case 0x37: /* l.sh */
1050 LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1056 TCGv t0
= tcg_temp_new();
1057 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(tmp
, 16));
1058 tcg_gen_qemu_st_tl(cpu_R
[rb
], t0
, dc
->mem_idx
, mop
);
1064 gen_illegal_exception(dc
);
1069 static void dec_mac(DisasContext
*dc
, uint32_t insn
)
1073 op0
= extract32(insn
, 0, 4);
1074 ra
= extract32(insn
, 16, 5);
1075 rb
= extract32(insn
, 11, 5);
1078 case 0x0001: /* l.mac */
1079 LOG_DIS("l.mac r%d, r%d\n", ra
, rb
);
1081 TCGv_i32 t0
= tcg_temp_new_i32();
1082 TCGv_i64 t1
= tcg_temp_new_i64();
1083 TCGv_i64 t2
= tcg_temp_new_i64();
1084 tcg_gen_mul_tl(t0
, cpu_R
[ra
], cpu_R
[rb
]);
1085 tcg_gen_ext_i32_i64(t1
, t0
);
1086 tcg_gen_concat_i32_i64(t2
, maclo
, machi
);
1087 tcg_gen_add_i64(t2
, t2
, t1
);
1088 tcg_gen_extrl_i64_i32(maclo
, t2
);
1089 tcg_gen_shri_i64(t2
, t2
, 32);
1090 tcg_gen_extrl_i64_i32(machi
, t2
);
1091 tcg_temp_free_i32(t0
);
1092 tcg_temp_free_i64(t1
);
1093 tcg_temp_free_i64(t2
);
1097 case 0x0002: /* l.msb */
1098 LOG_DIS("l.msb r%d, r%d\n", ra
, rb
);
1100 TCGv_i32 t0
= tcg_temp_new_i32();
1101 TCGv_i64 t1
= tcg_temp_new_i64();
1102 TCGv_i64 t2
= tcg_temp_new_i64();
1103 tcg_gen_mul_tl(t0
, cpu_R
[ra
], cpu_R
[rb
]);
1104 tcg_gen_ext_i32_i64(t1
, t0
);
1105 tcg_gen_concat_i32_i64(t2
, maclo
, machi
);
1106 tcg_gen_sub_i64(t2
, t2
, t1
);
1107 tcg_gen_extrl_i64_i32(maclo
, t2
);
1108 tcg_gen_shri_i64(t2
, t2
, 32);
1109 tcg_gen_extrl_i64_i32(machi
, t2
);
1110 tcg_temp_free_i32(t0
);
1111 tcg_temp_free_i64(t1
);
1112 tcg_temp_free_i64(t2
);
1117 gen_illegal_exception(dc
);
1122 static void dec_logic(DisasContext
*dc
, uint32_t insn
)
1125 uint32_t rd
, ra
, L6
;
1126 op0
= extract32(insn
, 6, 2);
1127 rd
= extract32(insn
, 21, 5);
1128 ra
= extract32(insn
, 16, 5);
1129 L6
= extract32(insn
, 0, 6);
1132 case 0x00: /* l.slli */
1133 LOG_DIS("l.slli r%d, r%d, %d\n", rd
, ra
, L6
);
1134 tcg_gen_shli_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f));
1137 case 0x01: /* l.srli */
1138 LOG_DIS("l.srli r%d, r%d, %d\n", rd
, ra
, L6
);
1139 tcg_gen_shri_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f));
1142 case 0x02: /* l.srai */
1143 LOG_DIS("l.srai r%d, r%d, %d\n", rd
, ra
, L6
);
1144 tcg_gen_sari_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f)); break;
1146 case 0x03: /* l.rori */
1147 LOG_DIS("l.rori r%d, r%d, %d\n", rd
, ra
, L6
);
1148 tcg_gen_rotri_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f));
1152 gen_illegal_exception(dc
);
1157 static void dec_M(DisasContext
*dc
, uint32_t insn
)
1162 op0
= extract32(insn
, 16, 1);
1163 rd
= extract32(insn
, 21, 5);
1164 K16
= extract32(insn
, 0, 16);
1167 case 0x0: /* l.movhi */
1168 LOG_DIS("l.movhi r%d, %d\n", rd
, K16
);
1169 tcg_gen_movi_tl(cpu_R
[rd
], (K16
<< 16));
1172 case 0x1: /* l.macrc */
1173 LOG_DIS("l.macrc r%d\n", rd
);
1174 tcg_gen_mov_tl(cpu_R
[rd
], maclo
);
1175 tcg_gen_movi_tl(maclo
, 0x0);
1176 tcg_gen_movi_tl(machi
, 0x0);
1180 gen_illegal_exception(dc
);
1185 static void dec_comp(DisasContext
*dc
, uint32_t insn
)
1190 op0
= extract32(insn
, 21, 5);
1191 ra
= extract32(insn
, 16, 5);
1192 rb
= extract32(insn
, 11, 5);
1194 tcg_gen_movi_i32(env_btaken
, 0x0);
1195 /* unsigned integers */
1196 tcg_gen_ext32u_tl(cpu_R
[ra
], cpu_R
[ra
]);
1197 tcg_gen_ext32u_tl(cpu_R
[rb
], cpu_R
[rb
]);
1200 case 0x0: /* l.sfeq */
1201 LOG_DIS("l.sfeq r%d, r%d\n", ra
, rb
);
1202 tcg_gen_setcond_tl(TCG_COND_EQ
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1205 case 0x1: /* l.sfne */
1206 LOG_DIS("l.sfne r%d, r%d\n", ra
, rb
);
1207 tcg_gen_setcond_tl(TCG_COND_NE
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1210 case 0x2: /* l.sfgtu */
1211 LOG_DIS("l.sfgtu r%d, r%d\n", ra
, rb
);
1212 tcg_gen_setcond_tl(TCG_COND_GTU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1215 case 0x3: /* l.sfgeu */
1216 LOG_DIS("l.sfgeu r%d, r%d\n", ra
, rb
);
1217 tcg_gen_setcond_tl(TCG_COND_GEU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1220 case 0x4: /* l.sfltu */
1221 LOG_DIS("l.sfltu r%d, r%d\n", ra
, rb
);
1222 tcg_gen_setcond_tl(TCG_COND_LTU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1225 case 0x5: /* l.sfleu */
1226 LOG_DIS("l.sfleu r%d, r%d\n", ra
, rb
);
1227 tcg_gen_setcond_tl(TCG_COND_LEU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1230 case 0xa: /* l.sfgts */
1231 LOG_DIS("l.sfgts r%d, r%d\n", ra
, rb
);
1232 tcg_gen_setcond_tl(TCG_COND_GT
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1235 case 0xb: /* l.sfges */
1236 LOG_DIS("l.sfges r%d, r%d\n", ra
, rb
);
1237 tcg_gen_setcond_tl(TCG_COND_GE
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1240 case 0xc: /* l.sflts */
1241 LOG_DIS("l.sflts r%d, r%d\n", ra
, rb
);
1242 tcg_gen_setcond_tl(TCG_COND_LT
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1245 case 0xd: /* l.sfles */
1246 LOG_DIS("l.sfles r%d, r%d\n", ra
, rb
);
1247 tcg_gen_setcond_tl(TCG_COND_LE
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1251 gen_illegal_exception(dc
);
1257 static void dec_compi(DisasContext
*dc
, uint32_t insn
)
1262 op0
= extract32(insn
, 21, 5);
1263 ra
= extract32(insn
, 16, 5);
1264 I16
= extract32(insn
, 0, 16);
1266 tcg_gen_movi_i32(env_btaken
, 0x0);
1267 I16
= sign_extend(I16
, 16);
1270 case 0x0: /* l.sfeqi */
1271 LOG_DIS("l.sfeqi r%d, %d\n", ra
, I16
);
1272 tcg_gen_setcondi_tl(TCG_COND_EQ
, env_btaken
, cpu_R
[ra
], I16
);
1275 case 0x1: /* l.sfnei */
1276 LOG_DIS("l.sfnei r%d, %d\n", ra
, I16
);
1277 tcg_gen_setcondi_tl(TCG_COND_NE
, env_btaken
, cpu_R
[ra
], I16
);
1280 case 0x2: /* l.sfgtui */
1281 LOG_DIS("l.sfgtui r%d, %d\n", ra
, I16
);
1282 tcg_gen_setcondi_tl(TCG_COND_GTU
, env_btaken
, cpu_R
[ra
], I16
);
1285 case 0x3: /* l.sfgeui */
1286 LOG_DIS("l.sfgeui r%d, %d\n", ra
, I16
);
1287 tcg_gen_setcondi_tl(TCG_COND_GEU
, env_btaken
, cpu_R
[ra
], I16
);
1290 case 0x4: /* l.sfltui */
1291 LOG_DIS("l.sfltui r%d, %d\n", ra
, I16
);
1292 tcg_gen_setcondi_tl(TCG_COND_LTU
, env_btaken
, cpu_R
[ra
], I16
);
1295 case 0x5: /* l.sfleui */
1296 LOG_DIS("l.sfleui r%d, %d\n", ra
, I16
);
1297 tcg_gen_setcondi_tl(TCG_COND_LEU
, env_btaken
, cpu_R
[ra
], I16
);
1300 case 0xa: /* l.sfgtsi */
1301 LOG_DIS("l.sfgtsi r%d, %d\n", ra
, I16
);
1302 tcg_gen_setcondi_tl(TCG_COND_GT
, env_btaken
, cpu_R
[ra
], I16
);
1305 case 0xb: /* l.sfgesi */
1306 LOG_DIS("l.sfgesi r%d, %d\n", ra
, I16
);
1307 tcg_gen_setcondi_tl(TCG_COND_GE
, env_btaken
, cpu_R
[ra
], I16
);
1310 case 0xc: /* l.sfltsi */
1311 LOG_DIS("l.sfltsi r%d, %d\n", ra
, I16
);
1312 tcg_gen_setcondi_tl(TCG_COND_LT
, env_btaken
, cpu_R
[ra
], I16
);
1315 case 0xd: /* l.sflesi */
1316 LOG_DIS("l.sflesi r%d, %d\n", ra
, I16
);
1317 tcg_gen_setcondi_tl(TCG_COND_LE
, env_btaken
, cpu_R
[ra
], I16
);
1321 gen_illegal_exception(dc
);
1327 static void dec_sys(DisasContext
*dc
, uint32_t insn
)
1330 #ifdef OPENRISC_DISAS
1333 op0
= extract32(insn
, 16, 10);
1334 #ifdef OPENRISC_DISAS
1335 K16
= extract32(insn
, 0, 16);
1339 case 0x000: /* l.sys */
1340 LOG_DIS("l.sys %d\n", K16
);
1341 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1342 gen_exception(dc
, EXCP_SYSCALL
);
1343 dc
->is_jmp
= DISAS_UPDATE
;
1346 case 0x100: /* l.trap */
1347 LOG_DIS("l.trap %d\n", K16
);
1348 #if defined(CONFIG_USER_ONLY)
1351 if (dc
->mem_idx
== MMU_USER_IDX
) {
1352 gen_illegal_exception(dc
);
1355 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1356 gen_exception(dc
, EXCP_TRAP
);
1360 case 0x300: /* l.csync */
1361 LOG_DIS("l.csync\n");
1362 #if defined(CONFIG_USER_ONLY)
1365 if (dc
->mem_idx
== MMU_USER_IDX
) {
1366 gen_illegal_exception(dc
);
1372 case 0x200: /* l.msync */
1373 LOG_DIS("l.msync\n");
1374 #if defined(CONFIG_USER_ONLY)
1377 if (dc
->mem_idx
== MMU_USER_IDX
) {
1378 gen_illegal_exception(dc
);
1384 case 0x270: /* l.psync */
1385 LOG_DIS("l.psync\n");
1386 #if defined(CONFIG_USER_ONLY)
1389 if (dc
->mem_idx
== MMU_USER_IDX
) {
1390 gen_illegal_exception(dc
);
1397 gen_illegal_exception(dc
);
1402 static void dec_float(DisasContext
*dc
, uint32_t insn
)
1405 uint32_t ra
, rb
, rd
;
1406 op0
= extract32(insn
, 0, 8);
1407 ra
= extract32(insn
, 16, 5);
1408 rb
= extract32(insn
, 11, 5);
1409 rd
= extract32(insn
, 21, 5);
1412 case 0x00: /* lf.add.s */
1413 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1414 gen_helper_float_add_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1417 case 0x01: /* lf.sub.s */
1418 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1419 gen_helper_float_sub_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1423 case 0x02: /* lf.mul.s */
1424 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1425 if (ra
!= 0 && rb
!= 0) {
1426 gen_helper_float_mul_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1428 tcg_gen_ori_tl(fpcsr
, fpcsr
, FPCSR_ZF
);
1429 tcg_gen_movi_i32(cpu_R
[rd
], 0x0);
1433 case 0x03: /* lf.div.s */
1434 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1435 gen_helper_float_div_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1438 case 0x04: /* lf.itof.s */
1439 LOG_DIS("lf.itof r%d, r%d\n", rd
, ra
);
1440 gen_helper_itofs(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1443 case 0x05: /* lf.ftoi.s */
1444 LOG_DIS("lf.ftoi r%d, r%d\n", rd
, ra
);
1445 gen_helper_ftois(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1448 case 0x06: /* lf.rem.s */
1449 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1450 gen_helper_float_rem_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1453 case 0x07: /* lf.madd.s */
1454 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1455 gen_helper_float_muladd_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1458 case 0x08: /* lf.sfeq.s */
1459 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra
, rb
);
1460 gen_helper_float_eq_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1463 case 0x09: /* lf.sfne.s */
1464 LOG_DIS("lf.sfne.s r%d, r%d\n", ra
, rb
);
1465 gen_helper_float_ne_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1468 case 0x0a: /* lf.sfgt.s */
1469 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra
, rb
);
1470 gen_helper_float_gt_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1473 case 0x0b: /* lf.sfge.s */
1474 LOG_DIS("lf.sfge.s r%d, r%d\n", ra
, rb
);
1475 gen_helper_float_ge_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1478 case 0x0c: /* lf.sflt.s */
1479 LOG_DIS("lf.sflt.s r%d, r%d\n", ra
, rb
);
1480 gen_helper_float_lt_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1483 case 0x0d: /* lf.sfle.s */
1484 LOG_DIS("lf.sfle.s r%d, r%d\n", ra
, rb
);
1485 gen_helper_float_le_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1488 /* not used yet, open it when we need or64. */
1489 /*#ifdef TARGET_OPENRISC64
1491 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
1493 gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1497 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
1499 gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1503 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
1505 if (ra != 0 && rb != 0) {
1506 gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1508 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1509 tcg_gen_movi_i64(cpu_R[rd], 0x0);
1514 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
1516 gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1519 case 0x14: lf.itof.d
1520 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1522 gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
1525 case 0x15: lf.ftoi.d
1526 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1528 gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
1532 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
1534 gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1537 case 0x17: lf.madd.d
1538 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
1540 gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1543 case 0x18: lf.sfeq.d
1544 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
1546 gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1549 case 0x1a: lf.sfgt.d
1550 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
1552 gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1555 case 0x1b: lf.sfge.d
1556 LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
1558 gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1561 case 0x19: lf.sfne.d
1562 LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
1564 gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1567 case 0x1c: lf.sflt.d
1568 LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
1570 gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1573 case 0x1d: lf.sfle.d
1574 LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
1576 gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1581 gen_illegal_exception(dc
);
1587 static void disas_openrisc_insn(DisasContext
*dc
, OpenRISCCPU
*cpu
)
1591 insn
= cpu_ldl_code(&cpu
->env
, dc
->pc
);
1592 op0
= extract32(insn
, 26, 6);
1604 dec_logic(dc
, insn
);
1608 dec_compi(dc
, insn
);
1616 dec_float(dc
, insn
);
1633 void gen_intermediate_code(CPUOpenRISCState
*env
, struct TranslationBlock
*tb
)
1635 OpenRISCCPU
*cpu
= openrisc_env_get_cpu(env
);
1636 CPUState
*cs
= CPU(cpu
);
1637 struct DisasContext ctx
, *dc
= &ctx
;
1639 uint32_t next_page_start
;
1646 dc
->is_jmp
= DISAS_NEXT
;
1649 dc
->flags
= cpu
->env
.cpucfgr
;
1650 dc
->mem_idx
= cpu_mmu_index(&cpu
->env
, false);
1651 dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1652 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1653 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1654 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1655 qemu_log("-----------------------------------------\n");
1656 log_cpu_state(CPU(cpu
), 0);
1659 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1661 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1663 if (max_insns
== 0) {
1664 max_insns
= CF_COUNT_MASK
;
1666 if (max_insns
> TCG_MAX_INSNS
) {
1667 max_insns
= TCG_MAX_INSNS
;
1673 tcg_gen_insn_start(dc
->pc
);
1676 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
1677 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1678 gen_exception(dc
, EXCP_DEBUG
);
1679 dc
->is_jmp
= DISAS_UPDATE
;
1680 /* The address covered by the breakpoint must be included in
1681 [tb->pc, tb->pc + tb->size) in order to for it to be
1682 properly cleared -- thus we increment the PC here so that
1683 the logic setting tb->size below does the right thing. */
1688 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
1691 dc
->ppc
= dc
->pc
- 4;
1692 dc
->npc
= dc
->pc
+ 4;
1693 tcg_gen_movi_tl(cpu_ppc
, dc
->ppc
);
1694 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
1695 disas_openrisc_insn(dc
, cpu
);
1698 if (dc
->delayed_branch
) {
1699 dc
->delayed_branch
--;
1700 if (!dc
->delayed_branch
) {
1701 dc
->tb_flags
&= ~D_FLAG
;
1703 tcg_gen_mov_tl(cpu_pc
, jmp_pc
);
1704 tcg_gen_mov_tl(cpu_npc
, jmp_pc
);
1705 tcg_gen_movi_tl(jmp_pc
, 0);
1707 dc
->is_jmp
= DISAS_JUMP
;
1711 } while (!dc
->is_jmp
1712 && !tcg_op_buf_full()
1713 && !cs
->singlestep_enabled
1715 && (dc
->pc
< next_page_start
)
1716 && num_insns
< max_insns
);
1718 if (tb
->cflags
& CF_LAST_IO
) {
1721 if (dc
->is_jmp
== DISAS_NEXT
) {
1722 dc
->is_jmp
= DISAS_UPDATE
;
1723 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1725 if (unlikely(cs
->singlestep_enabled
)) {
1726 if (dc
->is_jmp
== DISAS_NEXT
) {
1727 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1729 gen_exception(dc
, EXCP_DEBUG
);
1731 switch (dc
->is_jmp
) {
1733 gen_goto_tb(dc
, 0, dc
->pc
);
1739 /* indicate that the hash table must be used
1740 to find the next TB */
1744 /* nothing more to generate */
1749 gen_tb_end(tb
, num_insns
);
1751 tb
->size
= dc
->pc
- pc_start
;
1752 tb
->icount
= num_insns
;
1755 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
1756 && qemu_log_in_addr_range(pc_start
)) {
1758 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
1759 qemu_log("\nisize=%d osize=%d\n",
1760 dc
->pc
- pc_start
, tcg_op_buf_count());
1765 void openrisc_cpu_dump_state(CPUState
*cs
, FILE *f
,
1766 fprintf_function cpu_fprintf
,
1769 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1770 CPUOpenRISCState
*env
= &cpu
->env
;
1773 cpu_fprintf(f
, "PC=%08x\n", env
->pc
);
1774 for (i
= 0; i
< 32; ++i
) {
1775 cpu_fprintf(f
, "R%02d=%08x%c", i
, env
->gpr
[i
],
1776 (i
% 4) == 3 ? '\n' : ' ');
1780 void restore_state_to_opc(CPUOpenRISCState
*env
, TranslationBlock
*tb
,